TP65H070G4PS TRANSPHORM | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 12

Technical content

Features

  • Gen IV technology
  • JEDEC-qualified GaN technology
  • Dynamic RDS(on)eff production tested
  • Robust design, defined by — Wide gate safety margin — Transient over-voltage capability
  • Very low QRR
  • Reduced crossover loss
  • RoHS compliant and Halogen-free packaging Benefits
  • Achieves increased efficiency in both hard- and soft- switched circuits — Increased power density — Reduced system size and weight — Overall lower system cost
  • Easy to drive with commonly-used gate drivers
  • GSD pin layout improves high speed design

Applications

  • Datacom
  • Broad industrial
  • PV inverter
  • Servo motor
  • Computing
  • Consumer

Description

The TP65H070G4PS 650V, 72mΩ Gallium Nitride (GaN) FET is a normally-off device. It combines state-of-the-art high voltage GaN HEMT and low voltage silicon MOSFET technologies—offering superior reliability and performance. The Gen IV SuperGaN® platform uses advanced epi and patented design technologies to simplify manufacturability while improving efficiency over silicon via lower gate charge, output capacitance, crossover loss, and reverse recovery charge Related Literature

  • AN0009: Recommended External Circuitry for GaN FETs
  • AN0003: Printed Circuit Board Layout and Probing
  • AN0010: Paralleling GaN FETs
  • AN0014: Low cost driver solution

Ordering Information

Part Number Package Package Configuration TP65H070G4PS 3 lead TO-220 Source Key Specifications VDSS (V) 650 VDSS(TR) (V) 800 RDS(on)eff (mΩ) max* 85 Qoss (nC) typ 78 QG (nC) typ 9 * Dynamic on-resistance; see Figures 18 and 19 Cascode Device Structure Cascode Schematic Symbol S G D S TP65H070G4PS TO-220 (top view)

Dec. 4, 2023 transphormusa.com tp65h070g4ps.2v1 2 TP65H070G4PS Thermal Resistance Symbol Parameter Maximum Unit RΘJC Junction-to-case 1 °C/W RΘJA Junction-to-ambient 62 °C/W Absolute Maximum Ratings (Tc=25°C unless otherwise stated.) Symbol Parameter Limit Value Unit VDSS Drain to source voltage (TJ = -55°C to 150°C) 650 V VDSS(TR) Transient drain to source voltage (a) 800 VGSS Gate to source voltage ±20 PD Maximum power dissipation @TC=25°C 96 W ID Continuous drain current @TC=25°C (b) 29 A Continuous drain current @TC=100°C (b) 18.4 A IDM Pulsed drain current (pulse width: 10µs) 120 A TC Operating temperature Case -55 to +150 °C TJ Junction -55 to +150 °C TS Storage temperature -55 to +150 °C TSOLD Soldering peak temperature (c) 260 °C Notes: a. In off-state, spike duration < 30µs, non-repetitive b. For increased stability at high current operation, see Circuit Implementation on page 3 c. For 10 sec., 1.6mm from the case

Dec. 4, 2023 transphormusa.com tp65h070g4ps.2v1 3 TP65H070G4PS Circuit Implementation Recommended gate drive: (0V, 12V) with RG= 50Ω Simplified Half-bridge Schematic ( See also on Figure 13 ) Required DC Link RC Snubber (RCDCL) (d) Recommended Switching Node RC Snubber (RCSN) (e) Gate Ferrite Bead (FB1) 10nF + 5Ω Not necessary (e) 200 — 300Ω at 100MHz Notes: d. RCDCL should be placed as close as possible to the drain pin e. RCSN (68pF + 15Ω) is needed only if RG is smaller than recommendations For additional gate driver options/configurations, please see Layout Recommendations Gate Loop:

  • Gate Driver: SiLab Si823x/Si827x
  • Keep gate loop compact
  • Minimize coupling with power loop Power loop: ( For reference see page 13 )
  • Minimize power loop path inductance
  • Minimize switching node coupling with high and low power plane
  • Add DC bus snubber to reduce to voltage ringing
  • Add Switching node snubber for high current operation

Dec. 4, 2023 transphormusa.com tp65h070g4ps.2v1 4 TP65H070G4PS Electrical Parameter (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Forward Device Characteristics V(BL)DSS Drain-source voltage 650 — — V VGS=0V, ID=1mA VGS(th) Gate threshold voltage 3.3 4 4.8 V VDS=VGS, ID=0.7mA RDS(on)eff Drain-source on-resistance (f) — 72 85 mΩ VGS=10V, ID=18A,TJ=25°C — 148 — VGS=10V, ID=18A, TJ=150°C IDSS Drain-to-source leakage current — 1.2 12 µA VDS=650V, VGS=0V, TJ=25°C — 8 — VDS=650V, VGS=0V, TJ=150°C IGSS Gate-to-source forward leakage current — — 100 nA VGS=20V Gate-to-source reverse leakage current — — -100 VGS=-20V CISS Input capacitance — 638 — pF VGS=0V, VDS=400V, f=1MHz COSS Output capacitance — 72 — CRSS Reverse transfer capacitance — 2 — CO(er) Output capacitance, energy related (g) — 105 — pF VGS=0V, VDS=0V to 400V CO(tr) Output capacitance, time related (h) — 194 — QG Total gate charge — 9 — nC VDS=400V, VGS=0V to 10V, ID=18A QGS Gate-source charge — 3.7 — QGD Gate-drain charge — 2.4 — QOSS Output charge — 80 — nC VGS=0V, VDS=0V to 400V tD(on) Turn-on delay — 43.4 — ns VDS=400V, VGS=0V to 12V, ID=18A, RG=50Ω tR Rise time — 6.2 — tD(off) Turn-off delay — 56 — tF Fall time — 7.2 — Notes: f. Dynamic on-resistance; see Figures 19 and 20 for test circuit and conditions g. Equivalent capacitance to give same stored energy as VDS rises from 0V to 400V h. Equivalent capacitance to give same charging time as VDS rises from 0V to 400V

Dec. 4, 2023 transphormusa.com tp65h070g4ps.2v1 5 TP65H070G4PS Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Reverse Device Characteristics IS Reverse current — — 18 A VGS=0V, TC=100°C, ≤25% duty cycle VSD Reverse voltage (i) — 2.4 — V VGS=0V, IS=18A — 1.7 — VGS=0V, IS=9A tRR Reverse recovery time — 80 — ns IS=18A, VDD=400V, di/dt=1000A/ms QRR Reverse recovery charge(j) — 0 — nC Notes: i. Includes dynamic RDS(on) effect j. Excludes Qoss

Figure 13. Safe Operating Area TC=25°C Figure 14. Inductive Switching Loss TC=25°C

Dec. 4, 2023 transphormusa.com tp65h070g4ps.2v1 11 TP65H070G4PS Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switche s requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The table below provides some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Minimize lead length of TO-220 and TO-247 package when mounting to the PCB Use long traces in drive circuit, long lead length of the devices Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points Use differential mode probe or probe ground clip with long wire See AN0003: Printed Circuit Board Layout and Probing GaN Design Resources The complete technical library of GaN design tools can be found at transphormusa.com/design:

  • Reference designs
  • Evaluation kits
  • Application notes
  • Design guides
  • Simulation models
  • Technical papers and presentations

Dec. 4, 2023 transphormusa.com tp65h070g4ps.2v1 12 TP65H070G4PS Mechanical 8x8 PQFN Package