TP65H035G4QS TRANSPHORM | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 13

Technical content

Features

  • JEDEC qualified GaN technology
  • Dynamic RDS(on)eff production tested
  • Robust design, defined by — Wide gate safety margin — Transient over-voltage capability
  • Enhanced inrush current capability
  • Very low QRR
  • Reduced crossover loss
  • Kelvin source for low inductance gate return path Benefits
  • Enables AC-DC bridgeless totem-pole PFC designs — Increased power density — Reduced system size and weight — Overall lower system cost
  • Achieves increased efficiency in both hard- and soft- switched circuits
  • Easy to drive with commonly-used gate drivers
  • GSD pin layout improves high speed design
  • Pin-to-pin drop-in with e-mode GaN

Applications

  • Datacom
  • Broad industrial
  • PV inverter
  • Servo motor

Description

The TP65H035G4QS 650V, 35 mΩ gallium nitride (GaN) FET is a normally-off device using Transphorm’s Gen IV platform. It combines a state-of-the-art high voltage GaN HEMT with a low voltage silicon MOSFET to offer superior reliability and performance. The Gen IV SuperGaN® platform uses advanced epi and patented design technologies to simplify manufacturability while improving efficiency over silicon via lower gate charge, output capacitance, crossover loss, and reverse recovery charge. Related Literature

  • AN0009: Recommended External Circuitry for GaN FETs
  • AN0003: Printed Circuit Board Layout and Probing
  • AN0014: Low cost driver solution TP65H035G4QS TOLL (bottom view)

Ordering Information

Part Number Package Package Configuration TP65H035G4QS-TR 10x12mm TOLL Source Key Specifications VDSS (V) 650 V(TR)DSS (V) 800 RDS(on)eff (mΩ) max* 41 QRR (nC) typ 150 QG (nC) typ 22 * Dynamic on-resistance; ; see Figures 20 and 21 Cascode Device Structure Cascode Schematic Symbol * “-TR” suffix refers to tape and reel. Refer to AN0012 for details. D G S KS

Dec. 5, 2023 transphormusa.com tp65h035G4qs.1v1 2 TP65H035G4QS Absolute Maximum Ratings (Tc=25°C unless otherwise stated.) Symbol Parameter Limit Value Unit VDSS Drain to source voltage (TJ = -55°C to 150°C) 650 V V(TR)DSS Transient drain to source voltage (a) 800 VGSS Gate to source voltage ±20 PD Maximum power dissipation @TC=25°C 156 W ID Continuous drain current @TC=25°C (b) 46.5 A Continuous drain current @TC=100°C (b) 29.5 A IDM Pulsed drain current (pulse width: 10µs) 240 A TC Operating temperature Case -55 to +150 °C TJ Junction -55 to +150 °C TS Storage temperature -55 to +150 °C TSOLD Reflow soldering temperature (c) 260 °C Notes: a. In off-state, spike duty cycle D<0.01, spike duration <30µs, none repetitive b. For increased stability at high current operation, see Circuit Implementation on page 3 c. Reflow MSL3 Thermal Resistance Symbol Parameter Max Unit RΘJC Junction-to-case 0.8 °C/W RΘJA Junction-to-ambient 45 °C/W

Dec. 5, 2023 transphormusa.com tp65h035G4qs.1v1 3 TP65H035G4QS Circuit Implementation Simplified half-bridge hard switching schematic ( See also on Figure 16 ) For additional gate driver options/configurations, please see Layout Recommendations for hard switching Gate Loop:

  • Gate Driver: SiLab Si823x/Si827x
  • Keep gate loop compact (using Kelvin source)
  • Minimize coupling with power loop Power loop: ( For reference see page 12 )
  • Minimize power loop path inductance
  • Minimize switching node coupling with high and low power plane
  • Add DC bus noise filter (RCDCL) to reduce to voltage ringing
  • Add Switching node snubber for high current operation Parameter Symbol Value Single Gate Resistor RG (RG(OFF) only) 30 Ω ( D1/D2/RG(ON): NS) Dual Gate Resistor RG(ON) / RG(OFF) 15 Ω / 30 Ω Dual Gate Resistor Effective RG(ON) / RG(OFF) 10 Ω / 30 Ω Operating frequency Fsw 60~100 kHz Steering Diode D1/D2 1N4001 or B0540WS-7 Gate Ferrite Bead FB 180 — 270 Ω at 100MHz(d) Gate-to-source Resistor R1/R2 10 kΩ DC Link RC Noise Filter RCDCL [4.7nF + 5Ω] x 2 or [10nF+ 2.3Ω] Switching Node RC Snub- RCSN Not Necessary (e) Gate Driver Driver Si8230/Si8274 Note: d. For every design and layout, a range of ferrite beads (FB) should be evaluated to help suppress any high frequency ringing e. RCSN (100pF + 10Ω) is needed if
  • RG is smaller than recommendations
  • Layout is not optimized
  • Requires high current operation

Dec. 5, 2023 transphormusa.com tp65h035G4qs.1v1 4 TP65H035G4QS Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Forward Device Characteristics VDSS(BL) Drain-source voltage 650 — — V VGS=0V VGS(th) Gate threshold voltage 3.3 4 4.8 V VDS=VGS, ID=1mA ΔVGS(th)/TJ Gate threshold voltage temperature co- efficient — -6.5 — mV/°C RDS(on)eff Drain-source on-resistance (f) — 35 41 mΩ VGS=10V, ID=30A — 72 — VGS=10V, ID=30A, TJ=150°C IDSS Drain-to-source leakage current — 3 30 µA VDS=650V, VGS=0V — 20 — VDS=650V, VGS=0V, TJ=150°C IGSS Gate-to-source forward leakage current — — 400 nA VGS=20V Gate-to-source reverse leakage current — — -400 VGS=-20V CISS Input capacitance — 1500 — pF VGS=0V, VDS=400V, f=1MHz COSS Output capacitance — 147 — CRSS Reverse transfer capacitance — 5 — CO(er) Output capacitance, energy related (g) — 220 — pF VGS=0V, VDS=0V to 400V CO(tr) Output capacitance, time related (h) — 380 — QG Total gate charge — 22 — nC VDS=400V, VGS=0V to 10V, ID=32A QGS Gate-source charge — 8.4 — QGD Gate-drain charge — 6.6 — QOSS Output charge — 150 — nC VGS=0V, VDS=0V to 400V tD(on) Turn-on delay — 60 — ns VDS=400V, VGS=0V to 12V, RG=30, ID=32A, ZFB=240Ω at 100MHz (See Figure 15) tR Rise time — 10 — tD(off) Turn-off delay — 94 — tF Fall time — 10 — Eoff Turn off Energy — 53 — J VDS=400V, VGS=0V to 12V, RG(on) =10 RG(off)=30, ID=30A, ZFB=180Ω at 100MHz Eon Turn on Energy — 66 — J Notes: f. Dynamic on-resistance; see Figures 20 and 21 for test circuit and conditions g. Equivalent capacitance to give same stored energy as VDS rises from 0V to 400V h. Equivalent capacitance to give same charging time as VDS rises from 0V to 400V

Dec. 5, 2023 transphormusa.com tp65h035G4qs.1v1 5 TP65H035G4QS Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Reverse Device Characteristics IS Reverse current — — 29.5 A VGS=0V, TC=100°C ≤25% duty cycle VSD Reverse voltage (i) — 1.8 — V VGS=0V, IS=32A — 1.3 — VGS=0V, IS=16A tRR Reverse recovery time — 59 — ns IS=32A, VDD=400V, di/dt=1000A/ms QRR Reverse recovery charge (j) — 0 — nC Notes: i. Includes dynamic RDS(on) effect j. Excludes Qoss k. Reverse conduction di/dt will not exceed this max value with recommended RG

Dec. 5, 2023 transphormusa.com tp65h035G4qs.1v1 11 TP65H035G4QS

Dec. 5, 2023 transphormusa.com tp65h035G4qs.1v1 12 TP65H035G4QS Half-bridge Reference Schematic

Dec. 5, 2023 transphormusa.com tp65h035G4qs.1v1 13 TP65H035G4QS Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switche s requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The table below provides some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Minimize lead length of TO-220 and TO-247 package when mounting to the PCB Use long traces in drive circuit, long lead length of the devices Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points Use differential mode probe or probe ground clip with long wire See AN0003: Printed Circuit Board Layout and Probing GaN Design Resources The complete technical library of GaN design tools can be found at transphormusa.com/design:

  • Evaluation kits
  • Application notes
  • Design guides
  • Simulation models
  • Technical papers and presentations