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Document overview
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Technical content
Features
JEDEC qualified GaN technology Dynamic RDS(on)eff production tested Robust design, defined by — Intrinsic lifetime tests — Wide gate safety margin — Transient over-voltage capability Very low Q RR Reduced crossover loss Benefits Enables AC-DC bridgeless totem-pole PFC designs — Increased power density — Reduced system size and weight — Overall lower system cost Achieves increased efficiency in both hard- and soft- switched circuits Easy to drive with commonly-used gate drivers GSD pin layout improves high speed design
Applications
Datacom Broad industrial PV inverter Servo motor
Description
The TP65H015G5WS 650V, 15 mΩ gallium nitride GaN FET is a normally-off device using Transphorm’s Gen V platform. It combines a state-of-the-art high voltage GaN HEMT with a low voltage silicon MOSFET to offer superior reliability and performance. The Gen V SuperGaN™ platform uses advanced epi and patented design technologies to simplify manufacturability while improving efficiency over silicon via lower gate charge, output capacitance, crossover loss, and reverse recovery charge. Related Literature AN0009: Recommended External Circuitry for GaN FETs AN0003: Printed Circuit Board Layout and Probing AN0010: Paralleling GaN FETs S G D S TP65H015G5WS TO-247 (top view)
Ordering Information
Part Number Package Package Configuration TP65H015G5WS 3 lead TO-247 Source Key Specifications VDSS (V) 650 V(TR)DSS (V) 725 RDS(on)eff (mΩ) max* 18 QRR (nC) typ 430 * Dynamic on-resistance QG (nC) typ 68 Cascode Device Structure Cascode Schematic Symbol
May 25, 2020 transphormusa.com tp65h015G5ws.1 2 TP65H015G5WS-Preliminary Thermal Resistance Symbol Parameter Typical Unit RΘJC Junction-to-case 0.45 °C/W RΘJA Junction-to-ambient 40 °C/W Absolute Maximum Ratings (Tc=25°C unless otherwise stated.) Symbol Parameter Limit Value Unit VDSS Drain to source voltage (T J = -55°C to 150°C) 650 V V(TR)DSS Transient drain to source voltage a 725 VGSS Gate to source voltage ±20 PD Maximum power dissipation @T C=25°C 276 W ID Continuous drain current @TC=25°C b 95 A Continuous drain current @TC=100°C b 60 A IDM Pulsed drain current (pulse width: 10µs) 600 A TC Operating temperature Case -55 to +150 °C TJ Junction -55 to +150 °C TS Storage temperature -55 to +150 °C TSOLD Soldering peak temperature c 260 °C Notes: a. In off-state, spike duty cycle D<0.01, spike duration <1µs b. For increased stability at high current operation, see Circuit Implementation on page 3 c. For 10 sec., 1.6mm from the case
May 25, 2020 transphormusa.com tp65h015G5ws.1 3 TP65H015G5WS-Preliminary Circuit Implementation Recommended gate drive: (0V, 12V) with RG=15Ω Simplified Half-bridge Schematic Required DC Link RC Snubber (RCDCL) a Recommended Switching Node RC Snubber (RCSN) b, c [10nF + 3.3 Ω] x 3 Not necessary Notes: a. RCDCL should be placed as close as possible to the drain pin b. RCSN is needed only if RG is smaller than recommendations or operational current exceeds 100C rated IDMAX c. If required, please use [10 Ω + 100pF] x 3 in parallel Gate Ferrite Bead (FB1) 80-120 Ω at 100MHz
May 25, 2020 transphormusa.com tp65h015G5ws.1 4 TP65H015G5WS-Preliminary Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Forward Device Characteristics V(BL)DSS Drain-source voltage 650 — — V V GS=0V VGS(th) Gate threshold voltage 3.3 4 4.8 V V DS=VGS, ID=2mA RDS(on)eff Drain-source on-resistance a — 15 18 mΩ VGS=10V, ID=60A — 31 — V GS=10V, ID=60A, TJ=150°C IDSS Drain-to-source leakage current — 7 70 µA VDS=650V, VGS=0V — 50 — V DS=650V, VGS=0V, TJ=150°C IGSS Gate-to-source forward leakage current — — 400 nA VGS=20V Gate-to-source reverse leakage current — — -400 V GS=-20V CISS Input capacitance — 4670 — pF V GS=0V, VDS=400V, f=1MHz COSS Output capacitance — 312 — CRSS Reverse transfer capacitance — 8 — CO(er) Output capacitance, energy related b — 497 — pF V GS=0V, VDS=0V to 400V CO(tr) Output capacitance, time related c — 1020 — QG Total gate charge — 68 100 nC VDS=400V, VGS=0V to 10V, ID=60A QGS Gate-source charge — 30 — QGD Gate-drain charge — 18 — QOSS Output charge — 430 — nC VGS=0V, VDS=0V to 400V tD(on) Turn-on delay — 78 — ns VDS=400V, VGS=0V to 12V, RG=15, ZFB=120 at 100MHz, ID=60A tR Rise time — 20 — tD(off) Turn-off delay — 132 — tF Fall time — 10 — Notes: a. Dynamic on-resistance; see Figures 19 and 20 for test circuit and conditions b. Equivalent capacitance to give same stored energy as V DS rises from 0V to 400V c. Equivalent capacitance to gi ve same charging time as VDS rises from 0V to 400V
May 25, 2020 transphormusa.com tp65h015G5ws.1 5 TP65H015G5WS-Preliminary Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Reverse Device Characteristics IS Reverse current — — 60 A VGS=0V, TC=100°C ≤15% duty cycle VSD Reverse voltage a — 1.5 — V VGS=0V, IS=60A — 1.1 — V GS=0V, IS=30A tRR Reverse recovery time — 100 — ns IS=60A, VDD=400V, di/dt=1000A/ms QRR Reverse recovery charge — 430 — nC (di/dt)RM Reverse diode di/dt b — — 3500 A/µs Circuit implementation and parameters on page 3 Notes: a. Includes dynamic R DS(on) effect b. Reverse conduction di/dt will not exc eed this max value with recommended RG.
May 25, 2020 transphormusa.com tp65h015G5ws.1 6 TP65H015G5WS-Preliminary Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switches requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The table below provides some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Minimize lead length of TO-220 and TO-247 package when mounting to the PCB Use long traces in drive circuit, long lead length of the devices Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points Use differential mode probe or probe ground clip with long wire See AN0003: Printed Circuit Board Layout and Probing GaN Design Resources The complete technical library of GaN design tools can be found at transphormusa.com/design: Evaluation kits Application notes Design guides Simulation models Technical papers and presentations
May 25, 2020 transphormusa.com tp65h015G5ws.1 7 TP65H015G5WS-Preliminary Mechanical 3 Lead TO-247 Package