TC8750 TELEDYNE | Alldatasheet
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TELEDYNE COMPONENTS 3bE D MM 8917602 0007134 7 MBTSC om T-S1-10-0S # TELEDYNE COMPONENTS TC8750 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL BDC OUTPUT
FEATURES
High Accuracy, 3-1/2 Digit Resolution With 1 High Stability Over Full Temperature Range <10.025% Error — Gain Temperature Coetficient ...<25 ppmv°C Typ i Military Temperature Range Devices = ZOTO Dit eeeerernrninsnsnsetn £30 HVPPC TYP 1 Monotonic Performance — Differential Nonlinearity Drift ...<2.5 ppm/"C Typ —No Missing Codes @ Latched Parallel BDC Outputs
1 Monolithic CMOS Construction Gives Low Power LPTTL and CMOS Compatible Outputs and
Dissipation .nrecosnessnseseesvecesne20 MW TYP Control inputs | Contains All Required Active Elements 1 Strobed or Free-Running Conversion — Needs Only Passive Support Components, 1 Infinite Input Range Reference Voltage, and Dual Power Supplies — Any Positive Voltage Can Be Applied via a Scaling Resistor TEST CIRCUIT 0.4 pF ae Hosv TC8750 pep INTIATE = __|19 2 OUTPUTS CONVERSION 21 Mi OA 1000S R s HS 3 3| 10'S imo: NT COMPARATOR | reANAL| » » an A oat TT PS ia | ft | ees 3 2
1000 H OA
+sv } rie——8 | = °) [Tit OB 's 100 ka. og [ [2 BiTo A 20ka: =? 23__o Tal is 7 pro ~2 val ind Rois Vaer 301 ka. Rage =e 20 pA sex. 7 rr" Fr For example, with Vpe¢ = SV, Rpg = 250 ka. O VREF . 17g a-13 1208
TELEDYNE COMPONENTS 3bE D MM 8917602 0007135 9 MMTSC T-51-10-05 . 3-1/2 DIGIT ADC WITH PARALLEL BDC OUTPUT TC8750 GENERAL DESCRIPTION PIN CONFIGURATION The TC8750 is a 3-1/2 digit, monolithic CMOS analog- to-digital converter. Fully self-contained in a single 24-pin dual-in-line package, the converter requires only passive support components, voltage or current references, and om Leg 1000's ora power supplies, Conversion is performed by an incremental charge- soos J C22] [23] DATA VALID balancing technique which has inherently high accuracy, DIGIT ) pfs] [22] Busy linearity, and noise immunity. An amplifier integrates the ag fa] INTIATE. sum of the unknown analog current and pulses of a refer- oe =e ence current. The number of pulses (charge increments) a needed to maintain the amplifier summing junction near aos J SLE] tes7s0 19 ¥D0 Zero are counted. At the end of conversion, the total count olelr ) Lz] [19 Vss is latched into the digital outputs in a 3-1/2 digit, parallel Cal Fleas BDC digit format. ois liajzeno anvust ORDERING INFORMATION rs ) C84 [1s] up our —— SSSSsSsSSSSSSSSSSSSS DIGIT ) Bf my ‘Temperature 1 Part No. Package Range ale psiner TC8750CPG 24-Pin Plastic DIP. 0°C to +70°C TC8750EHG 24-Pin CerDIP_ 40°C to +85°C TC8750MHG __—_24-Pin CerDIP. 55°C to +125°C HANDLING PRECAUTIONS CMOS devices must be handled correctly to prevent damage. Package and store only in conductive foam, anti- ‘static tubes or other conductive material. Use proper anti- static handling procedures. Do not connect in circuits under “power-on” conditions, ashigh transients may cause perma- nent damage.
1783 Am14 “me
TELEDYNE COMPONENTS 3bE D MM 8917602 0007136 O METSC T-51-10-05 3-1/2 DIGIT ADC WITH PARALLEL BDC OUTPUT TC8750 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, Von = +5V, Vss = -5V, Vano = OV, Vrer =-6.4V, Reus = 100 kQ, test circuit shown. Ta = +25°C unless full temperature range is specified (-55°C to +125°C for MH package, 40°C to +85°C for EH package, 0° to +70°C for CP package). Parametar —__Dfiriton conan | atm | yp | t’| er |e Accuracy Resolution BCD Word Length 34/2 Digits ‘Accuracy __ of Digital Output 7 ___|(1999 Counts) _ Relative Output Deviation From % Accuracy Straight Line Between Normalized Zero and a Full-Scale Input _ Differential Deviation From 1 LSB % Nonlinearity Between Transition Points Differential Variation in Differential Full Temperature 25 | ppmec Nonlinearity Nonlinearity Due to Range Temperature Drit_ Temperature Change Gain Variance Variation From Exact #2 %of (Compensate By Trimming Norninal River res) Gain Temperature Variation In A Due to Full Temperature #25 | 475 | 480 | ppc Dritt Temperature Change Range Zero Offset Correction at Zero Adjust Iiw= 0 #0 | 260 mv to Give Zero Output When InputisZero Zero Temperature Variation in Zero Offset Full Temperature as | a8 | ppc Drift Due to Temperatura Range Change Analoginput (See Note) - iy Full Scale Full-Scale Analog Input HA Current to Achieve Specified Activity ine Reference Current Input to = [HA Achieve Specified Accuracy Digital Input Vint Logical "1" Input Threshold pA Current to Achieve Specified Activity os Vint Logical “O" Input Threshold Full Temperature 16 [Vv for Intiate Conversion input Range Digital Output _ _ Vourl# Logical “1” Output Vohiage Full Temperature Range Vv : for Digits Out, Busy, and lout =-10 1A Data Valid Outputs lour = -500 pA Vour® Logical “O" Output Voliage Full Temperature Range o4 | 04 | V for Digits Out, Busy, and Vp = 4.75V Data Valid Outputs tour = 500 HA Dynamig Conversion Time Time Requiredto Perform Full Temperature 12 | ms ‘One Complete A/D Range . Conversion 1207
1784 B-01
TELEDYNE COMPONENTS 3bE D MM@ 8917602 0007137 2 METSC T-51-10-05 tout 3-1/2 DIGIT ADC WITH PARALLEL BDC OUTPUT TC8750 ELECTRICAL CHARACTERISTICS (Cont.) Dynamic (Gontp Conversion Vint conv = +5V Conv Rate in per Free-Run Mode sec Minimum Pulse Full Temperature ns Width for Range Initiate Conversion Supply Current Ipp Quiescent (H Package) Current Required From Full Temperature 14 mA Postve Supply During «Range (P Package) Operation Vint conv = OV. 14 mA ig Quiescent (H Package) Current Required From Full Temperature -25 | -35 | mA Negative Supply During Range (P Package) a Operation a Vint conv = OV 5 mA Supply Sensitivity | Change in Full-Scale Gain Voo + 1V, Vgs #1V. 20.5 cal WN vs Supply Voltage Change — [Vop! = |Vssi__ “Change in Full-Scale Gain 40.05 | 40.4 %N =5VHIV vs Supply Voltage Chango for Tracking Supplies NOTE: Ix and Iner pins connect to the summing junction of an operational amplifier, Voltage sources cannot be attached directly but must be bufisred by extemal resistors. See Test Circuit. CIRCUIT DESCRIPTION The other counter is a data counter, which is reset During conversion, the sumof accontinuous.current (In) S¥nChronously with the clock counter and counts the num and pulses of a retorance current ine) are integrated {orn ero mes ler is svitched into the suming input ofthe fixed number of clock periods. Im is proportional to the 2”Plifier during the period defined by the clock counter. analog input voltage; Iner is switched in for exactly one clock When the Initiate Conversion input is strobed with a period just frequently enough to maintain the summing input POStive signal, the busy line latches high and a 10 ps (times of the integrator near zero. Thus, the charge from the _ 9'v@nare appropriate) start-up cycle begins. The integrating continuous Iiy current is balanced against the pulses of Iner tae ane is cischarged and both counters tet reset curing current. The total number of Iner pulses needed during the M's startup Period, © persion begins ot ote ace conversion period to maintain the charge is countedandthe tore © and e' ow a ei i ehecinta by the Thi result (in BCD) is latched into the outputs at the end of Counteror by anoverflow condition in counter. This conversion, pulse disables further inputs into both counters and triggers The conversion contains two counters and a clock, in 310.8 shutdown cycle. During the shutdown cycle, Data addition fo'an operational anpliion comparator latching, Valid goes low for5 ys. Thisbinary sequenceis shown inthe tier, : latching, timing diagrams. Busy is true high, and when the circuit is output buffers, and housekeeping logic. One counter is a ia y ¢ , S @ busy, Initiate Conversion has no effect and may be high or clock counter which (after a reset pulse) starts counting < a , clock pulses; when the required counts reached, the clock OW. Data Valid ctnoes oworie date from a conversion cl ok ris applied to the circuit or counter generates @ pulse to start the end-of-conversion ti Data Valid falls at the end of a subsequent conversion, at which time the output data are updatedto reflect the latest conversion, 1208
1785 B-02
TELEDYNE COMPONENTS 3bE D MM 8917602 0007138 4 MBTSC 7-51-10-05 3-1/2 DIGIT ADC WITH PARALLEL BDC OUTPUT TC8750 TIMING DIAGRAMS Clocked Mode Free-Run Mode mate “iH-- commen Y, GS Vou--4-y eusy yr sone ve pata OH picts YOH ouT Vou ~6 ys-bl | ¢— $008 CONVERSION TIME RECYCLE ‘CONVERSION TIME ——?! TIME ~25 ys NOTE: Rise and fall tmes = 200 ns typical, C, = 50 pF. PIN FUNCTIONS Initiate Conversion Input output at the Data Valid pin indicates that the Digits Out pins _ . latched with the result of the last conversion cycle. The Accepts CMOS and most 5V logic inputs. Applying ae laten rine! " logic “1” to the Initiate Conversion pin initiates the A/D Pata Valid output goes tologic Spproximately Sjisbefore conversion cycle. Once conversion has been initiated, the jh? CO" evcatat pecanversion cycle. During the § ve cycle cannot be interrupted, and the Initiate Conversion pin Pa. Tiny Out ng Nati PIS: is disabled until conversion is complete. Two modes of ie Digits Out are not valid. operation the Initiate Conversion input isheld at logic "0" for Digits Output (1's, 10's, 10's, 1000's) standby and taken to logic “1” when a conversion is desired. The BDC digit outputs which are the result of the A/D For free-running operation the Initiate Conversion pin is conversion. These outputs are CMOS logic and low power connected to Vpp or similar permanent logic “1" voltage. TTL compatible. Busy Output APPLICATIONS INFORMATION A digital status output which is compatible with CMOS logic and low power TTL (can sink and source 500 pA). A ‘Nput/Output Relationships logic “1” output on the Busy pin indicates a conversion cycle The analog input voltage (Vin) is related tothe output by is in process. A logic “1” to logic “0” transition indicates that the transfer equation: conversion is complete and the result has been latched at the Digits Out pins. A logic “O" to logic “1” transition indicates Digital Counts = VN? A* Rrer a new conversion cycle has been initiated. If the device is. i S= Ene VaEF operating in the free-running mode, the Busy output will remain low for approximately 2.5 us, markingthe completion A=4128 and initiation of consecutive conversion cycles. where digital counts is the value of the BCD output word Data Valid Output presented at Digits Out pins in response to Viv. A digital status whichis compatible with CMOS logicand low power TTL (can sink and source 50 JA). A logic “1” 1-200
1786 B-03
TELEDYNE COMPONENTS 3bE D MM 8917602 0007239 b MTSC T-51-10-05 3-1/2 DIGIT ADC.WITH PARALLEL BDC OUTPUT C8750 ‘The digital output code format is as follows: the conversion time will be six times longer, and the supply ne current is now reduced to 0.5 mA), Analog Input Digital Output Fordetails of this relationship, refer tothe typical perfor Vin < Full Scale 1100110011001 mance curves in Application Note 9. ~~" = Full Scale 1 LSB 1100110011001 20 0.000.110 Exact value not critical, but should have a nominal value oso Of 1002 +10%. Locate close to pin 14. Conue External Component Selection Exact value not ofiticl, but should have a nominal value Obtaining high-accuracy conversion systemdepends of 270 pF +20%. Locate close to pin 14. onthe voltage regulation of Ver, and thermal stability of Rin and Raer. The exact dependence is given by the transfer Cyr function. Systemaccuracy also depends, toa lesser degree, Exact value not critical, but should have a nominal value ‘on the voltage regulation of Vpp and Vss. Supply connec- —_of 68 pF +10%. Low leakage types are recommended, tions Vop and Vss should have bypass capacitors of 0.1 F although mica or ceramic devices can be used in applica- or larger value right at the device pins. tions where their temperature limits are not exceeded, Locate as close as possible to pins 14 and 15. Rin, Rrer Values of these components are chosen to give a full: Vag scale input current of approximately 10 A and a reference ‘A negative reference voltage must be supplied. This current of approximately -20 pA. may be obtained from a constant current source circuit or from the negative supply. Vww Full Scale Veer Rw 0A Rrer~ =o HA Voo, Ves Power supplies of +5V are recommended with 0.05% Examples: line and load regulation and 0.1 uF decoupling capacitors. Rw= 2 -4MQ Race~ 3a =320ka Adjustment Procedure 1OHA ~20nA The test circuit diagram shows optional circuits for imation: trimming the zero location and full-scale gain. Because the Note that these values are approximations; the exact - . ri relationships are defined by the transfer equation. In prac- “gital outputs romain constant outside of epee oper- tice, the value of Rin typically would be trimmed using the ting range Ge. Foro ane Stove ft scale), vs optional gain adjust circuit to obtain full-scale output at Vin recommended t bie) Points in setting full scale (see adjustment procedure). Metal film resistors iol nd full-scale values. Recommended procedure is as with 1% tolerance or better are recommended for high jollowa: Accuracy applications because oftheirthermalstabilty and 5 she initiate conversion control high o provide free- generation. tun operation, and verify that converter is operating FS ci ations for the TC8750 are based on Reus = 2. Set Viny to +1/2 LSB and trim the zero adjust circuit to 100 kQ.#10%, unless otherwise noted. However, there are ao oct the esa Ot wanstion. This instances when the designer may want to change this correctly locate the zero end. resistor By aoe to rae. oT een cUPPY 3. For fullscaleadjustment, set Vintothe full scale value faster andthe supply current willbe much higher (e.g., when less 1-1/2 LSB, and trim the gain acjust circuit for a Reis =20kO, the conversion timeis reduced by 1/3, andthe 1100110011000 to 1100110011001 transition. Ra lsincreasedneconversiontine wilbetongerenatveadutmens are performed in this order, tore shouldbe supblycurrent wilbemuch lower. (e.g, when Rong Ma, "© interaction and they should not have to be repeated. 1-210
1787 B-04
TELEDYNE COMPONENTS 3bE D MM 8917602 0007140 2 mETSC T-51-10-05 3-1/2 DIGIT ADC WITH PARALLEL BDC OUTPUT T8750 APPLICATION/DESIGN CIRCUITS 3-1/2 ADC With LCD (SHELLY Wo. 484-01 OR EQUVALENT) LL Tions ‘Oh . - "és PoP 1] S lolalelslela delelalelalal sel wal el sla AAA =, || =, | [aieaeaba! D A " Yoo LD 4 p81 YssPh} iG 7 PTT OEE ee Te v0 AS as a NS SS ae lle LTT IU a 7 rea7s0 BT 1s aves oes eke JR ai] ter tus Yer so ebrhort Bipolar Operation (+ and - Inputs) ABSOLUTE VALUE CIRCUIT WITH SIGN +5V Wy ac pr 16. ane
3002 S Roamp mn ial
LN | ° 5aleoureur ‘Te8760 Vin © 24kQ (1=4,0=-) > won 7410R OR EQUIVALENT = EQUIVALENT = *Optional visual indication of negative input. NOTE: Values for R should be between 10 kQ and 100 kQ.
1788 B-05 m
TELEDYNE COMPONENTS 3bE D MM 8517602 0007141 4 mmeETSsSc T-51-10-05 3-1/2 DIGIT ADC WITH PARALLEL BDC OUTPUT TC8750 APPLICATION/DESIGN CIRCUITS (Cont.) Microprocessor-Based ADC System Az Ay Ag sv! 18 use =e +5VO0 24 14) oc | = > 33] K oe ° co i] INPUTS ANALOG. 370 pF. ic a OR O— MULTIPLEXER ee (a —_ ° 1000 resrs9 5 > —# aa on 2 [1 >] . 1k TEE sng 2 sora 10kQ 4 ae 8 0.4 pF TC9491 Nv iv