T1022

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Teledyne e2v Semiconductors SAS 2018 T1042/T1022 QorIQ Integrated Multicore Communications Processor Preliminary Datasheet DS1176 Whilst Teledyne e2v Semiconductors SAS ha s taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also rese rves the right to change t he specification of goods wi thout notice. Teledyne e2v S emiconductors SAS accepts no liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with information contained herein. Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 Saint- Egrève, France Holding Company: Teledyne e2v Semiconductors SAS Telephone: +33 (0)4 76 58 30 00 Contact Teledyne e2v by e-mail: hotline-std@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations cent res

FEATURES

• e5500 cores built on Power Architecture® technology, – T1042 has four cores and T1022 has two cores –E a c h core with a private 256KB L2 cache  256 KB shared L3 CoreNet platform cache (CPC)  Hierarchical interconnect fabric –C o r e N e t Coherency manager supporting coherent and non‐coherent transactions with prioritization and bandwidth allocation amongst CoreNet end‐points –1 5 0 G b p s coherent read bandwidth  One 32‐/6 4‐bit DDR3L/DDR4 SDRAM memory controllers –E C C and interleaving support  Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: –P a c k e t parsing, classification, and distribution –Q u e u e management for scheduling, packet sequencing, and congestion management –H a r d w a r e buffer management for buffer allocation and de‐allocation – Cryptography Acceleration –R e g E x Pattern Matching Acceleration – IEEE Std 1588™ support  Parallel Ethernet interfaces –U p to two RGMII interface –O n e MII interface  Eight SerDes lanes for high‐speed peripheral interfaces –F o u r PCI Express 2.0 controllers –T w o Serial ATA (SATA 3Gb/s) controllers –U p to five SGMII interface supporting 1000 Mbps –U p to two SGMII interface with maximum speed of 2500 Mbps – Supports 1000Base‐KX  Additional peripheral interfaces –T w o high‐speed USB 2.0 controllers with integrated PHY –E n h a n c e d secure digital host controller with support for high capacity memory card(SD/eSDHC/eMMC) –E n h a n c e d Serial peripheral interface (eSPI) –F o u r I2C controllers –T w o DUARTs –I n t e g r a t e d flash controller supporting NAND and NOR flash –D i s p l a y interface unit (DIU) with 12‐bit dual data rate –T D M Interface –F o u r GPIO controllers supporting up to 109 general purpose I/O signals –T w o 8‐channel DMA engines –M u l t i c o r e programmable interrupt controller (MPIC)  QUICC Engine block –3 2‐bit RISC controller for flexible support of the communications peripherals –S e r i a l DMA channel for receive and transmit on all serial channels –T w o universal communication controllers, supporting TDM, HDLC and UART  780 FC‐PBGA package, 23 mm x 23 mm 1176B–HIREL–10/18

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 1. OVERVIEW The T1042 QorIQ advanced multicore processor combines with high‐performance data path accelera‐ tion and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, gateways, and general‐purpose embedded computing systems. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also simplifying board design. This figure shows the block diagram of the chip. Figure 1‐1. T1042 Block diagram (P eripheral access management unit) Co reNet TM C oherency Manager Secur ity Monitor Po wer managment eSDHC 2x DU AR T IFC eSPI, 4x GPIO 32/64-bit DDR3L/4 memory controller R eal-time debug Watchpoint cross trigger Perf Monitor2 x USB2.0 w/PHY 4x I2C Po wer Ar chitecture e5500 32 KB D-C ache 32 KB I-C ache 256 KB backside L2 cache 256 KB platform cache Secur ity fuse pr ocessor DIU Secur ity 5.4 (XoR, CRC) Pa tter n match engine 2.2 Queue Mgr. Buffer Mgr. 1G 1G 1G Pa rs e, classify , distribute 2xDMAPCle PCle PCle PCle S A T A 2.0 S A T A 2.0 TDM/HDLC TDM/HDLC QUICC Engine Co reNet trace 8-lane , 5 GHz SerDes 2.5G PAMU 2.5G Aurora

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 1‐2. T1022 Block diagram 2. PIN ASSIGNMENTS 2.1 780 ball layout diagrams This figure shows the complete view of the T1040 ball map diagram. Figure 2‐2, Figure 2‐3, Figure 2‐4, and Figure 2‐5 show quadrant views. (P eripheral access management unit) Co reNet TM C oherency Manager Secur ity Monitor Po wer managment eSDHC 2x DU AR T IFC eSPI, 4x GPIO 32/64-bit DDR3L/4 memory controller R eal-time debug Watchpoint cross trigger Perf Monitor2 x USB2.0 w/PHY 4x I2C Po wer Ar chitecture e5500 32 KB D-C ache 32 KB I-C ache 256 KB backside L2 cache 256 KB platform cache Secur ity fuse pr ocessor DIU Secur ity 5.4 (XoR, CRC) Pa tter n match engine 2.2 Queue Mgr. Buffer Mgr. 1G 1G 1G Pa rs e, classify , distribute 2xDMAPCle PCle PCle PCle S A T A 2.0 S A T A 2.0 TDM/HDLC TDM/HDLC QUICC Engine Co reNet trace 8-lane , 5 GHz SerDes 1G2.5G PAMU 2.5G Aurora

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 2‐1. Complete BGA Map for the T1040 1234567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 1234567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH DDR Interface 1 IFC DUART I2C eSPI MPI C Trust System Control ASLEEP SYSCL K DDR Clocking RT C Debug DF T JTA G Analog Signals Serdes 1 USB PHY 1 and 2 IEEE1 588 Ethernet MI 1 Ethernet Cont. 1 Ethernet Cont. 2 DIFF_SYSCL K USB CL K DMA Starlite TD M QE TD M eSDHC Powe r Ground No Connects SEE DETAIL A SEE DETAIL B SEE DETAIL C SEE DETAIL D

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 2‐2. Detail A 1234567891 0 1 1 1 2 1 3 1 4 1234567891 0 1 1 1 2 1 3 1 4 A B C D E F G H J K L M N P A B C D E F G H J K L M N P IFC _ AD0 0 IFC _ AD01 IFC _ AD0 2 IFC _ AD0 3 IFC _ AD0 4 IFC _ AD0 5 IFC _ AD0 6 IFC _ AD0 7 IFC _ AD0 8 IFC _ AD0 9 IFC _ AD10 IFC _ AD11 IFC _ AD1 2 IFC _ AD1 3 IFC _ AD1 4 IFC _ AD1 5 IFC _ A16 IFC _ A17 IFC _ A18 IFC _ A19 IFC _ A20 IFC _ A21 IFC _ A22 IFC _ A23 IFC _ A24 IFC _ A25 IFC _ A26 IFC _ A27 IFC _ A28 IFC _ A29 IFC _ A30 IFC _ A31 IFC _ PAR1 IFC _ CS_B0 IFC _ WE0_B IFC_BCT L IFC _ TE IFC _ PERR_ B IFC _ NDDDR_ CL K SPI _ MOSI SPI _ MISO SPI _ CL K SPI _ CS_B0 SPI _ CS_B1 SPI _ CS_B2 SPI _ CS_B3 SDHC_ CMD SDHC_ DAT0 SDHC_ DAT1 SDHC_ DAT2 SDHC_ DAT3 SDHC_ CL K IRQ0 0 IRQ0 1 IRQ0 2 IRQ0 3 IRQ0 4 IRQ0 5 IRQ1 0 IRQ_ OUT_B PORESET _ B HRESET _ B RESET _ REQ_ BASLEEP EVT0_B EVT1_BEVT2_B EVT3_B EVT4_B CLK_ OUT SC AN_ MODE_ B TE ST _ SEL_B USB1 _ UDP USB1 _ UDM USB1 _ VBUS CLMP USB1 _ UI D USB1 _ DR V VBUS USB1 _ PWR FA ULT USB2 _ UDP USB2 _ UDM USB2 _ VBUS CLMP USB2 _ UI D USB2 _ DR V VBUS USB2 _ PWR FA ULT USB_ IBIA S_ REXT DIFF_ SY SCLK DIFF_ SY SCLK_BUSBCL K DMA1 _ DREQ0 _ B CLK0 9CLK1 0 CLK1 1 CLK1 2 SDHC_ CD_ B SDHC_ WP TH _ TP A SP ARE1 SP ARE2 SP ARE3 NC0 2 NC0 3 NC0 4 NC0 5 NC0 6 NC0 7 DDR Interface 1 IFC DUART I2C eSPI MPI C Trust System Control ASLEEP SYSCL K DDR Clocking RT C Debug DF T JTA G Analog Signals Serdes 1 USB PHY 1 and 2 IEEE1 588 Ethernet MI 1 Ethernet Cont. 1 Ethernet Cont. 2 DIFF_SYSCL K USB CL K DMA Starlite TD M QE TD M eSDHC GND0 01 GND004 GND005 GND006 GND007 GND008 GND0 16 GND020 GND021 GND022 GND023 GND030 GND031 GND035 GND036 GND037 GND038 GND039 GND040 GND041 GND042 GND050 GND053 GND054 GND055 GND056 GND057 GND058 GND063 GND064 GND065 GND066 GND072 GND073 GND0 74 GND075 GND080 GND081 GND082 GND083 GND084 GND085 GND091 GND092 GND093 GND094 USB_ AGND0 1 USB_ AGND02 USB_ AGND03 USB_ AGND04 USB_ AGND05 USB_ AGND06 USB_ AGND07 USB_ AGND08 USB_ AGND09 USB_ AGND1 0 USB_ AGND1 1 USB_ AGND1 2 O1VDD1 O1VDD2 O1VDD3 OVDD1 DVDD1 DVDD2 CVDD EVDD PR OG_ SF P PR OG_ MT R TH _ VDD VDD0 4 VDD0 5 VDD0 9 VDD1 3 VDD1 4 VDD1 8 VDD1 9 VDDC0 1 VDDC0 2 VDDC0 3 VDDC0 4 VDDC0 5 AVDD_ CG A1 AVDD_ CG A2 AVDD_ PL A T USB_ HVDD1 USB_ HVDD2 USB_ OVDD1 USB_ OVDD2 USB_ S VDD1 USB_ S VDD2 Powe r Ground No Connects

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 2‐3. Detail B 15 16 17 18 19 20 21 22 23 24 25 26 27 28 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A B C D E F G H J K L M N P A B C D E F G H J K L M N P D1_ MDQ0 0 D1_ MDQ0 1 D1_ MDQ0 2 D1_ MDQ0 3 D1_ MDQ0 4 D1_ MDQ0 5 D1_ MDQ0 6 D1_ MDQ0 7 D1_ MDQ0 8 D1_ MDQ0 9 D1_ MDQ1 0 D1_ MDQ1 1 D1_ MDQ1 2 D1_ MDQ1 3 D1_ MDQ1 4 D1_ MDQ1 5 D1_ MDQ1 6 D1_ MDQ1 7 D1_ MDQ1 8 D1_ MDQ1 9 D1_ MDQ2 0 D1_ MDQ2 1 D1_ MDQ2 2 D1_ MDQ2 3 D1_ MDQ2 4 D1_ MDQ2 5 D1_ MDQ2 6 D1_ MDQ2 7 D1_ MDQ2 8 D1_ MDQ2 9 D1_ MDQ3 0 D1_ MDQ3 1 D1_ MDQ3 6 D1_ MECC0 D1_ MECC1 D1_ MECC4 D1_ MECC5 D1_ MAPAR_ ERR_ B D1_ MDM0 D1_ MDM1 D1_ MDM2 D1_ MDM3 D1_ MDM8 D1_ MDQS0 D1_ MDQS1 D1_ MDQS2 D1_ MDQS3 D1_ MDQS_B0 D1_ MDQS_B1 D1_ MDQS_B2 D1_ MDQS_B3 D1_ MDQS_B8 D1_ MB A2 D1_ MA01 D1_ MA0 2 D1_ MA0 3 D1_ MA0 4 D1_ MA0 5 D1_ MA0 6 D1_ MA0 7 D1_ MA0 8 D1_ MA0 9 D1_ MA11 D1_ MA12 D1_ MA14 D1_ MA15 D1_ MCKE0 D1_ MCKE1 TE ST _ OUT 0 TE ST _ OUT 1 TE ST _ OUT 4 TE ST _ OUT 5 TE ST _ OUT 7 D1_ MDIC0 IFC _ PAR0 IFC _ CS_B1 IFC _ CS_B2 IFC _ CS_B3 IFC _ NDDQS IFC _ AV D IFC _ CL E IFC _ OE_ B IFC _ WP0_B IFC _ RB_B0 IFC _ RB_B1 IFC _ CLK0 IFC _ CLK1 IFC _ CS_B4 IFC _ CS_B5 IFC _ CS_B6 IFC _ CS_B7 TMP_ DETECT_B SY SCLK DDRCL K RT C CKS TP _ OUT_B TC K TD I TD O TM S TRS T_B D1_ TP A D1_ MVREF TD1_ ANODE TD1_ CATHODE FA _ ANAL OG_ PI N FA _ ANAL OG_ G_ V NC0 1 DDR Interface 1 IFC DUART I2C eSPI MPI C Trust System Control ASLEEP SYSCL K DDR Clocking RT C Debug DF T JTA G Analog Signals Serdes 1 USB PHY 1 and 2 IEEE1 588 Ethernet MI 1 Ethernet Cont. 1 Ethernet Cont. 2 DIFF_SYSCL K USB CL K DMA Starlite TD M QE TD M eSDHC GND002 GND003 GND009 GND0 10 GND0 1 1 GND0 12 GND0 13 GND0 14 GND0 15 GND0 17 GND0 18 GND0 19 GND024 GND025 GND026 GND027 GND028 GND029 GND032 GND033 GND034 GND043 GND044 GND045 GND046 GND047 GND048 GND049 GND051 GND052 GND059 GND060 GND061 GND062 GND067 GND068 GND069 GND070 GND071 GND0 76 GND077 GND078 GND079 GND086 GND087 GND088 GND089 GND090 GND095 GND096 GND097 GND098 SENSE GND OVDD2 OVDD3 OVDD4 OVDD5 OVDD6 G1VDD0 1 G1VDD0 2 G1VDD0 3 G1VDD0 4 G1VDD0 5 G1VDD0 6 G1VDD0 7 G1VDD0 8 G1VDD0 9 G1VDD1 0 G1VDD1 1 FA _ VL VDD0 1 VDD0 2 VDD0 3 VDD0 6 VDD0 7 VDD0 8 VDD1 0 VDD1 1 VDD1 2 VDD1 5 VDD1 6 VDD1 7 VDD2 0 VDD2 1 VDD2 2 AVDD_ SENSE VDD Power Ground No Connects

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 2‐4. Detail C 1234567891 0 1 1 1 2 1 3 1 4 1234567891 0 1 1 1 2 1 3 1 4 R T U V W Y AA AB AC AD AE AF AG AH R T U V W Y AA AB AC AD AE AF AG AH UA R T1_ SOUT UA R T2_ SOUT UA R T1_ SI N UA R T2_ SI N UA R T1_ R TS_B UA R T2_ R TS_B UA R T1_ CTS_ B UA R T2_ CTS_ B IIC1_ SCL IIC1_ SD A IIC2_ SCL IIC2_ SD A IRQ0 6 IRQ0 7 IRQ0 8 IRQ0 9 IRQ1 1 SD1 _ TX0_ P SD1 _ TX1_ P SD1 _ TX2_ P SD1 _ TX3_ P SD1 _ TX0_ N SD1 _ TX1_ N SD1 _ TX2_ N SD1 _ TX3_ N SD1 _ RX0 _ P SD1 _ RX1 _ P SD1 _ RX2 _ P SD1 _ RX3 _ P SD1 _ RX0 _ N SD1 _ RX1 _ N SD1 _ RX2 _ N SD1 _ RX3 _ N SD1 _ REF _ CLK1_P SD1 _ REF _ CLK1_N SD1 _ IMP_ C AL_RX TSEC_ CLK_ IN TSEC_ TRIG_IN TSEC_ TRIG_IN TSEC_ ALARM_OUT TSEC_ ALARM_OUT TSEC_ CLK_ OUT TSEC_ PUL SE_OUT TSEC_ PUL SE_OUT EMI1_ MDC EMI1_ MDI O EC1 _ TXD3 EC1 _ TXD2 EC1 _ TXD1 EC1 _ TXD0 EC1 _ TX _ CT L EC1 _ TX _ ER EC1 _ GTX_ CL K EC1 _ GTX_ CLK1 25 EC1 _ RXD3 EC1 _ RXD2 EC1 _ RXD1 EC1 _ RXD0 EC1 _ RX_ CT L EC1 _ RX_ CL K EC1 _ RX_ ER EC1 _ COL EC2 _ TXD3 EC2 _ TXD2 EC2 _ TXD1 EC2 _ TXD0 EC2 _ TX _ CT L EC2 _ GTX_ CL K EC2 _ GTX_ CLK1 25 EC2 _ RXD3 EC2 _ RXD2 EC2 _ RXD1 EC2 _ RXD0 EC2 _ RX_ CTL EC2 _ RX_ CL K IIC3_ SCL IIC3_ SD A IIC4_ SCL IIC4_ SD A DMA1 _ DACK0_ B DMA1 _ DDONE0 _ B DMA2 _ DREQ0 _ B DMA2 _ DACK0_ B DMA2 _ DDONE0 _ B TDMA_ RXD TDMA_ RS YNC TDMA_ TX D TDMA_ TS YNC TDMA_ RQ TDMB_ RXD TDMB_ RS YNC TDMB_ TX D TDMB_ TS YNC TDMB_ RQ NC0 8 NC0 9 NC1 0 NC1 1 NC1 2 NC1 3 NC1 4 NC1 5 NC1 6 NC1 7 NC1 8 NC1 9 NC2 0 NC2 1 NC2 2 NC2 3 NC2 4 NC2 5 NC2 6 DDR Interface 1 IFC DUART I2C eSPI MPI C Trust System Control ASLEE P SYSCL K DDR Clocking RT C Debug DF T JTA G Analog Signals Serdes 1 USB PHY 1 and 2 IEEE1 588 Ethernet MI 1 Ethernet Cont. 1 Ethernet Cont. 2 DIFF_SYSCL K USB CL K DMA Starlite TD M QE TD M eSDHC GND099 GND1 00 GND1 01 GND1 02 GND1 08 GND1 09 GND1 10 GND1 1 1 GND1 12 GND1 13 GND1 19 GND1 20 GND1 21 GND1 22 GND1 27 GND1 28 GND1 29 GND1 30 GND1 36 GND1 37 GND1 38 GND1 39 GND1 40 GND1 41 GND1 43 GND1 44 GND1 45 GND1 48 GND1 50 GND1 51 GND1 52 GND1 57 GND1 58 GND1 60 GND1 63 GND1 65 GND1 66 GND1 67 GND1 71 X1GND0 1 X1GND0 2 X1GND0 3 X1GND0 4 X1GND0 9 X1GND1 0 X1GND1 4 X1GND1 5 S1GND0 1 S1GND0 5 S1GND1 0 S1GND1 3 S1GND1 4 S1GND1 5 S1GND1 6 S1GND1 7 S1GND2 4 S1GND2 5 S1GND2 9 S1GND3 0 SENSE GNDC DVDD3 L1VDD1 L1VDD2 LVDD1 LVDD2 S1VDD7 X1VDD1 X1VDD2 VDD2 3 VDD2 4 VDD2 8 VDD3 2 VDD3 6 VDD4 0 VDDC0 6 VDDC0 7 VDDC0 8 VDDC0 9 VDDC1 0 VDDC1 1 VDDC1 2 SENSE VDDC Power Ground No Connects

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 2‐5. Detail D 15 16 17 18 19 20 21 22 23 24 25 26 27 28 15 16 17 18 19 20 21 22 23 24 25 26 27 28 R T U V W Y AA AB AC AD AE AF AG AH R T U V W Y AA AB AC AD AE AF AG AH D1_ MDQ3 2 D1_ MDQ3 3 D1_ MDQ3 4 D1_ MDQ3 5 D1_ MDQ3 7 D1_ MDQ3 8 D1_ MDQ3 9 D1_ MDQ4 0 D1_ MDQ4 1 D1_ MDQ4 2 D1_ MDQ4 3 D1_ MDQ4 4 D1_ MDQ4 5 D1_ MDQ4 6 D1_ MDQ4 7 D1_ MDQ4 8 D1_ MDQ4 9 D1_ MDQ5 0 D1_ MDQ5 1 D1_ MDQ5 2 D1_ MDQ5 3 D1_ MDQ5 4 D1_ MDQ5 5 D1_ MDQ5 6 D1_ MDQ5 7 D1_ MDQ5 8 D1_ MDQ5 9 D1_ MDQ6 0 D1_ MDQ6 1 D1_ MDQ6 2 D1_ MDQ6 3 D1_ MECC2 D1_ MECC3 D1_ MECC6 D1_ MECC7 D1_ MAPAR _ OUT D1_ MDM4 D1_ MDM5 D1_ MDM6 D1_ MDM7 D1_ MDQS4 D1_ MDQS5 D1_ MDQS6 D1_ MDQS7 D1_ MDQS8 D1_ MDQS_B4 D1_ MDQS_B5 D1_ MDQS_B6 D1_ MDQS_B7 D1_ MB A0 D1_ MB A1 D1_ MA0 0 D1_ MA10 D1_ MA13 D1_ MWE_ B D1_ MRA S_ B D1_ MC AS_B D1_ MCS_B0 D1_ MCS_B1 D1_ MCS_B2 D1_ MCS_B3 D1_ MCK0 D1_ MCK1 TE ST _ OUT 6 D1_ MCK_B0 D1_ MCK_B1 D1_ MODT 0 D1_ MODT 1 TE ST _ OUT 2 TE ST _ OUT 3 D1_ MDIC1 TE ST _ OUT 8 SD1 _ TX4_ P SD1 _ TX5_ P SD1 _ TX6_ P SD1 _ TX7_ P SD1 _ TX4_ N SD1 _ TX5_ N SD1 _ TX6_ N SD1 _ TX7_ N SD1 _ RX4 _ P SD1 _ RX5 _ P SD1 _ RX6 _ P SD1 _ RX7 _ P SD1 _ RX4 _ N SD1 _ RX5 _ N SD1 _ RX6 _ N SD1 _ RX7 _ N SD1 _ REF _ CLK2_P SD1 _ REF _ CLK2_N SD1 _ IMP_ C AL_TX SD1 _ PLL1_ TP A SD1 _ PLL2_ TP A SD1 _ PLL1_ TP D SD1 _ PLL2_ TP D NC_ DET NC_ 1040 DDR Interface 1 IFC DUART I2C eSPI MPI C Trust System Control ASLEEP SYSCL K DDR Clocking RT C Debug DF T JTA G Analog Signals Serdes 1 USB PHY 1 and 2 IEEE1 588 Ethernet MI 1 Ethernet Cont. 1 Ethernet Cont. 2 DIFF_SYSCL K USB CL K DMA Starlite TD M QE TD M eSDHC GND1 03 GND1 04 GND1 05 GND1 06 GND1 07 GND1 14 GND1 15 GND1 16 GND1 17 GND1 18 GND1 23 GND1 24 GND1 25 GND1 26 GND1 31 GND1 32 GND1 33 GND1 34 GND1 35 GND1 42 GND1 46 GND1 47 GND1 49 GND1 53 GND1 54 GND1 55 GND1 56 GND1 59 GND1 61 GND1 62 GND1 64 GND1 68 GND1 69 GND1 70 X1GND0 5 X1GND0 6 X1GND0 7 X1GND0 8 X1GND1 1 X1GND1 2 X1GND1 3 X1GND1 6 X1GND1 7 X1GND1 8 S1GND0 2 S1GND0 3 S1GND0 4 S1GND0 6 S1GND0 7 S1GND0 8 S1GND0 9 S1GND1 1 S1GND1 2 S1GND1 8 S1GND1 9 S1GND2 0 S1GND2 1 S1GND2 2 S1GND2 3 S1GND2 6 S1GND2 7 S1GND2 8 S1GND3 1 S1GND3 2 S1GND3 3 AGND_ SD1_PLL AGND_ SD1_PLL G1VDD1 2 G1VDD1 3 G1VDD1 4 G1VDD1 5 G1VDD1 6 G1VDD1 7 G1VDD1 8 G1VDD1 9 S1VDD1 S1VDD2 S1VDD3 S1VDD4 S1VDD5 S1VDD6 X1VDD3 X1VDD4 X1VDD5 VDD2 5 VDD2 6 VDD2 7 VDD2 9 VDD3 0 VDD3 1 VDD3 3 VDD3 4 VDD3 5 VDD3 7 VDD3 8 VDD3 9 AVDD_ SD1 _ PLL1 AVDD_ SD1 _ PLL2 Powe r Ground No Connects

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

2.2 Pinout list

This table provides the pinout listing for the T1040 by bus. Primary functions are bolded in the table. Table 2‐1. Pinout list by bus Signal Signal description Package pin number Pin type Power supply Notes DDR SDRAM Memory Interface 1 D1_MA00 Address V28 O G1V DD – D1_MA01 Address N28 O G1V DD – D1_MA02 Address N27 O G1V DD – D1_MA03 Address M28 O G1V DD – D1_MA04 Address L27 O G1V DD – D1_MA05 Address L28 O G1V DD – D1_MA06 Address K28 O G1V DD – D1_MA07 Address J28 O G1V DD – D1_MA08 Address J27 O G1V DD – D1_MA09 Address G27 O G1V DD – D1_MA10 Address Y27 O G1V DD – D1_MA11 Address H28 O G1V DD – D1_MA12 Address G28 O G1V DD – D1_MA13 Address AE28 O G1V DD – D1_MA14 Address E27 O G1V DD (25) D1_MA15 Address D28 O G1V DD (25) D1_MAPAR_ERR_B Address Parity Error F28 I G1V DD (1)(6)(25) D1_MAPAR_OUT Address Parity Out V27 O G1V DD (25) D1_MBA0 Bank Select Y28 O G1V DD – D1_MBA1 Bank Select W28 O G1V DD – D1_MBA2 Bank Select E28 O G1V DD (25) D1_MCAS_B Column Address Strobe AC28 O G1V DD (25) D1_MCK0 Clock T27 O G1V DD – D1_MCK1 Clock R27 O G1V DD – D1_MCKE0 Clock Enable C27 O G1V DD (2) D1_MCKE1 Clock Enable C28 O G1V DD (2) D1_MCK0_B Clock Complement T28 O G1V DD – D1_MCK1_B Clock Complement R28 O G1V DD – D1_MCS0_B Chip Select AB28 O G1V DD – D1_MCS1_B Chip Select AC27 O G1V DD – D1_MCS2_B Chip Select AG27 O G1V DD – D1_MCS3_B Chip Select AF28 O G1V DD – D1_MDIC0 Driver Impedence Calibration P28 IO G1V DD (3) D1_MDIC1 Driver Impedence Calibration U28 IO G1V DD (3)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 D1_MDM0 Data Mask B22 O G1V DD (1)(25) D1_MDM1 Data Mask C25 O G1V DD (1)(25) D1_MDM2 Data Mask F23 O G1V DD (1)(25) D1_MDM3 Data Mask K26 O G1V DD (1)(25) D1_MDM4 Data Mask U26 O G1V DD (1)(25) D1_MDM5 Data Mask Y24 O G1V DD (1)(25) D1_MDM6 Data Mask AD24 O G1V DD (1)(25) D1_MDM7 Data Mask AF24 O G1V DD (1)(25) D1_MDM8 Data Mask N24 O G1V DD (1)(25) D1_MDQ00 Data C21 IO G1V DD – D1_MDQ01 Data A22 IO G1V DD – D1_MDQ02 Data A26 IO G1V DD – D1_MDQ03 Data B26 IO G1V DD – D1_MDQ04 Data B21 IO G1V DD – D1_MDQ05 Data A21 IO G1V DD – D1_MDQ06 Data B24 IO G1V DD – D1_MDQ07 Data A25 IO G1V DD – D1_MDQ08 Data C23 IO G1V DD – D1_MDQ09 Data C24 IO G1V DD – D1_MDQ10 Data F25 IO G1V DD – D1_MDQ11 Data F26 IO G1V DD – D1_MDQ12 Data D22 IO G1V DD – D1_MDQ13 Data D23 IO G1V DD – D1_MDQ14 Data B27 IO G1V DD – D1_MDQ15 Data E25 IO G1V DD – D1_MDQ16 Data E23 IO G1V DD – D1_MDQ17 Data E24 IO G1V DD – D1_MDQ18 Data J23 IO G1V DD – D1_MDQ19 Data K23 IO G1V DD – D1_MDQ20 Data F22 IO G1V DD – D1_MDQ21 Data H22 IO G1V DD – D1_MDQ22 Data H23 IO G1V DD – D1_MDQ23 Data J24 IO G1V DD – D1_MDQ24 Data H26 IO G1V DD – D1_MDQ25 Data J25 IO G1V DD – D1_MDQ26 Data P26 IO G1V DD – D1_MDQ27 Data N25 IO G1V DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] D1_MDQ28 Data G25 IO G1V DD – D1_MDQ29 Data H25 IO G1V DD – D1_MDQ30 Data M26 IO G1V DD – D1_MDQ31 Data M25 IO G1V DD – D1_MDQ32 Data T25 IO G1V DD – D1_MDQ33 Data U25 IO G1V DD – D1_MDQ34 Data AA26 IO G1V DD – D1_MDQ35 Data AA25 IO G1V DD – D1_MDQ36 Data P25 IO G1V DD – D1_MDQ37 Data R25 IO G1V DD – D1_MDQ38 Data W26 IO G1V DD – D1_MDQ39 Data Y25 IO G1V DD – D1_MDQ40 Data V24 IO G1V DD – D1_MDQ41 Data W23 IO G1V DD – D1_MDQ42 Data AA22 IO G1V DD – D1_MDQ43 Data AC22 IO G1V DD – D1_MDQ44 Data W22 IO G1V DD – D1_MDQ45 Data V23 IO G1V DD – D1_MDQ46 Data AB24 IO G1V DD – D1_MDQ47 Data AB23 IO G1V DD – D1_MDQ48 Data AD26 IO G1V DD – D1_MDQ49 Data AD25 IO G1V DD – D1_MDQ50 Data AD23 IO G1V DD – D1_MDQ51 Data AE22 IO G1V DD – D1_MDQ52 Data AB25 IO G1V DD – D1_MDQ53 Data AC25 IO G1V DD – D1_MDQ54 Data AC23 IO G1V DD – D1_MDQ55 Data AE23 IO G1V DD – D1_MDQ56 Data AG25 IO G1V DD – D1_MDQ57 Data AH25 IO G1V DD – D1_MDQ58 Data AH22 IO G1V DD – D1_MDQ59 Data AF22 IO G1V DD – D1_MDQ60 Data AF26 IO G1V DD – D1_MDQ61 Data AH26 IO G1V DD – D1_MDQ62 Data AH23 IO G1V DD – D1_MDQ63 Data AF23 IO G1V DD – D1_MDQS0 Data Strobe A24 IO G1V DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 D1_MDQS1 Data Strobe D26 IO G1V DD – D1_MDQS2 Data Strobe G24 IO G1V DD – D1_MDQS3 Data Strobe L25 IO G1V DD – D1_MDQS4 Data Strobe W25 IO G1V DD – D1_MDQS5 Data Strobe AA23 IO G1V DD – D1_MDQS6 Data Strobe AE25 IO G1V DD – D1_MDQS7 Data Strobe AG24 IO G1V DD – D1_MDQS8 Data Strobe R23 IO G1V DD – D1_MDQS0_B Data Strobe A23 IO G1V DD – D1_MDQS1_B Data Strobe D25 IO G1V DD – D1_MDQS2_B Data Strobe G23 IO G1V DD – D1_MDQS3_B Data Strobe K25 IO G1V DD – D1_MDQS4_B Data Strobe V25 IO G1V DD – D1_MDQS5_B Data Strobe Y23 IO G1V DD – D1_MDQS6_B Data Strobe AF25 IO G1V DD – D1_MDQS7_B Data Strobe AH24 IO G1V DD – D1_MDQS8_B Data Strobe P23 IO G1V DD – D1_MECC0 Error Correcting Code L24 IO G1V DD – D1_MECC1 Error Correcting Code N23 IO G1V DD – D1_MECC2 Error Correcting Code T23 IO G1V DD – D1_MECC3 Error Correcting Code U23 IO G1V DD – D1_MECC4 Error Correcting Code L23 IO G1V DD – D1_MECC5 Error Correcting Code M23 IO G1V DD – D1_MECC6 Error Correcting Code R24 IO G1V DD – D1_MECC7 Error Correcting Code T24 IO G1V DD – D1_MODT0 On Die Termination AD28 O G1V DD (2) D1_MODT1 On Die Termination AE27 O G1V DD (2) D1_MRAS_B Row Address Strobe AA28 O G1V DD (25) D1_MWE_B Write Enable AB27 O G1V DD (25) TEST_OUT0 Test Signal H21 O G1V DD (12) TEST_OUT1 Test Signal F21 O G1V DD (12) TEST_OUT2 Test Signal W21 O G1V DD (12) TEST_OUT3 Test Signal V21 O G1V DD (12) TEST_OUT4 Test Signal K22 O G1V DD (12) TEST_OUT5 Test Signal M22 O G1V DD (12) TEST_OUT6 Test Signal U22 O G1V DD (12) TEST_OUT7 Test Signal P22 O G1V DD (12) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] TEST_OUT8 Test Signal Y21 O G1V DD (12) Integrated Flash Controller IFC_A16 IFC Address C5 O OV DD (1)(5) IFC_A17 IFC Address C6 O OV DD (1)(5) IFC_A18 IFC Address D7 O OV DD (1)(5) IFC_A19 IFC Address C7 O OV DD (1)(5) IFC_A20 IFC Address D8 O OV DD (1)(5) IFC_A21/cfg_dram_type IFC Address C8 O OV DD (1)(4) IFC_A22 IFC Address D9 O OV DD (1) IFC_A23 IFC Address C9 O OV DD (1) IFC_A24 IFC Address D10 O OV DD (1) IFC_A25/GPIO2_25 / IFC_WP1_B IFC Address C10 O OV DD (1) IFC_A26/GPIO2_26/ IFC_WP2_B IFC Address E11 O OV DD (1) IFC_A27/GPIO2_27 / IFC_WP3_B IFC Address C11 O OV DD (1) IFC_A28/GPIO2_28 IFC Address D11 O OV DD (1) IFC_A29/GPIO2_29/ IFC_RB2_B IFC Address C12 O OV DD (1) IFC_A30/GPIO2_30/ IFC_RB3_B IFC Address D12 O OV DD (1) IFC_A31/GPIO2_31/ IFC_RB4_B IFC Address E12 O OV DD (1) IFC_AD00/cfg_gpinput0 IFC Address / Data A4 IO OV DD (4) IFC_AD01/cfg_gpinput1 IFC Address / Data B5 IO OV DD (4) IFC_AD02/cfg_gpinput2 IFC Address / Data A5 IO OV DD (4) IFC_AD03/cfg_gpinput3 IFC Address / Data B6 IO OV DD (4) IFC_AD04/cfg_gpinput4 IFC Address / Data A6 IO OV DD (4) IFC_AD05/cfg_gpinput5 IFC Address / Data A7 IO OV DD (4) IFC_AD06/cfg_gpinput6 IFC Address / Data B8 IO OV DD (4) IFC_AD07/cfg_gpinput7 IFC Address / Data A8 IO OV DD (4) IFC_AD08/cfg_rcw_src0 IFC Address / Data B9 IO OV DD (4) IFC_AD09/cfg_rcw_src1 IFC Address / Data A9 IO OV DD (4) IFC_AD10/cfg_rcw_src2 IFC Address / Data A10 IO OV DD (4) IFC_AD11/cfg_rcw_src3 IFC Address / Data B11 IO OV DD (4) IFC_AD12/cfg_rcw_src4 IFC Address / Data A11 IO OV DD (4) IFC_AD13/cfg_rcw_src5 IFC Address / Data B12 IO OV DD (4) IFC_AD14/cfg_rcw_src6 IFC Address / Data A12 IO OV DD (4) IFC_AD15/cfg_rcw_src7 IFC Address / Data A13 IO OV DD (4) IFC_AVD IFC Address Valid D17 O OV DD (1)(5) IFC_BCTL IFC Buffer control A14 O OV DD (1) IFC_CLE/cfg_rcw_src8 IFC Command Latch Enable F16 O OV DD (1)(4) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 IFC_CLK0 IFC Clock A17 O OV DD (1) IFC_CLK1 IFC Clock A19 O OV DD (1) IFC_CS0_B IFC Chip Select C13 O OV DD (1)(6) IFC_CS1_B/GPIO2_10 IFC Chip Select E15 O OV DD (1)(6) IFC_CS2_B/GPIO2_11 IFC Chip Select D16 O OV DD (1)(6) IFC_CS3_B/GPIO2_12 IFC Chip Select C16 O OV DD (1)(6) IFC_CS4_B/GPIO1_09 IFC Chip Select E17 O OV DD (1)(6) IFC_CS5_B/GPIO1_10 IFC Chip Select C17 O OV DD (1)(6) IFC_CS6_B/GPIO1_11 IFC Chip Select D18 O OV DD (1)(6) IFC_CS7_B/GPIO1_12 IFC Chip Select C19 O OV DD (1)(6) IFC_NDDDR_CLK IFC NAND DDR Clock D14 O OV DD (1) IFC_NDDQS IFC DQS Strobe A16 IO OV DD – IFC_OE_B/cfg_eng_use1 IFC Output Enable D15 O OV DD (1)(21) IFC_PAR0/GPIO2_13 IFC Address & Data Parity C15 IO OV DD – IFC_PAR1/GPIO2_14 IFC Address & Data Parity C14 IO OV DD – IFC_PERR_B/GPIO2_15 IFC Parity Error E14 I OV DD (1)(6) IFC_RB2_B/IFC_A29/ GPIO2_29 IFC Ready / Busy CS 2C 1 2 I O V DD (1) IFC_RB3_B/IFC_A30/ GPIO2_30 IFC Ready / Busy CS 3D 1 2 I O V DD (1) IFC_RB4_B/IFC_A31/ GPIO2_31 IFC Ready / Busy CS 4E 1 2 I O V DD (1) IFC_RB0_B IFC Ready / Busy CS0 B15 I OV DD (6) IFC_RB1_B IFC Ready / Busy CS1 A15 I OV DD (6) IFC_TE/cfg_ifc_te IFC External Transceiver Enable B14 O OV DD (1)(4) IFC_WE0_B/cfg_eng_use0 IFC Write Enable D13 O OV DD (1)(21) IFC_WP1_B/IFC_A25/ GPIO2_25 IFC Write Protect C10 O OV DD (1) IFC_WP2_B/IFC_A26/ GPIO2_26 IFC Write Protect E11 O OV DD (1) IFC_WP3_B/IFC_A27/ GPIO2_27 IFC Write Protect C11 O OV DD (1) IFC_WP0_B/cfg_eng_use2 IFC Write Protect F17 O OV DD (1)(21) DUART UART1_CTS_B/GPIO1_21/ UART3_SIN Clear To Send Y2 I DV DD (1) UART1_RTS_B/GPIO1_19/ UART3_SOUT Ready to Send Y1 O DV DD (1) UART1_SIN/GPIO1_17 Receive Data AA1 I DV DD (1) UART1_SOUT/GPIO1_15 Transmit Data AA2 O DV DD (1) UART2_CTS_B/GPIO1_22/ UART4_SIN Clear To Send Y4 I DV DD (1) UART2_RTS_B/GPIO1_20/ UART4_SOUT Ready to Send V4 O DV DD (1) UART2_SIN/GPIO1_18 Receive Data W4 I DV DD (1) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] UART2_SOUT/GPIO1_16 Transmit Data AA4 O DV DD (1) UART3_SIN/UART1_CTS_B/ GPIO1_21 Receive Data Y2 I DV DD (1) UART3_SOUT/ UART1_RTS_B/GPIO1_19 Transmit Data Y1 O DV DD (1) UART4_SIN/UART2_CTS_B/ GPIO1_22 Receive Data Y4 I DV DD (1) UART4_SOUT/ UART2_RTS_B/GPIO1_20 Transmit Data V4 O DV DD (1) I2C IIC1_SCL Serial Clock (supports PBL) W1 IO DV DD (7)(8) IIC1_SDA Serial Data (supports PBL) V1 IO DV DD (7)(8) IIC2_SCL Serial Clock V3 IO DV DD (7)(8) IIC2_SDA Serial Data Y3 IO DV DD (7)(8) eSPI Interface SPI_CLK SPI Clock N1 O CV DD (1) SPI_CS0_B/GPIO2_00/ SDHC_DAT4 SPI Chip Select M1 O CV DD (1) SPI_CS1_B/GPIO2_01/ SDHC_DAT5 / SDHC_CMD_DIR SPI Chip Select M2 O CV DD (1) SPI_CS2_B/GPIO2_02/ SDHC_DAT6/ SDHC_DAT0_DIR SPI Chip Select M3 O CV DD (1) SPI_CS3_B/GPIO2_03/ SDHC_DAT7 / SDHC_DAT123_DIR/ SDHC_CLK_SYNC_OUT SPI Chip Select N3 O CV DD (1) SPI_MISO Master In Slave Out P1 I CV DD (1) SPI_MOSI Master Out Slave In P2 IO CV DD – Programmable Interrupt Controller IRQ00 External Interrupt F7 I O1V DD (1) IRQ01 External Interrupt D3 I O1V DD (1) IRQ02 External Interrupt E9 I O1V DD (1) IRQ03/GPIO1_23/SDHC_VS External Interrupt D1 I O1V DD (1) IRQ04/GPIO1_24 External Interrupt D4 I O1V DD (1) IRQ05/GPIO1_25 External Interrupt D5 I O1V DD (1) IRQ06/GPIO1_26 External Interrupt AB4 I L1V DD (1) IRQ07/GPIO1_27 External Interrupt AD5 I L1V DD (1) IRQ08/GPIO1_28 External Interrupt AB1 I L1V DD (1) IRQ09/GPIO1_29 External Interrupt AC5 I L1V DD (1) IRQ10/GPIO1_30/ SDHC_CLK_SYNC_IN External Interrupt L4 I CV DD (1) IRQ11/GPIO1_31 External Interrupt U3 I DV DD (1) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 IRQ_OUT_B/EVT9_B Interrupt Output A3 O O1V DD (1)(6)(7) Trust TMP_DETECT_B Tamper Detect F19 I OV DD (1) System Control HRESET_B Hard Reset E8 IO O1V DD (7)(27) PORESET_B Power On Reset F13 I O1V DD (26) RESET_REQ_B Reset Request (POR or Hard) B3 O O1V DD (1)(5) Power Management ASLEEP/GPO1_13 Asleep B2 O O1V DD (1) SYSCLK SYSCLK System Clock G15 I O1V DD (17) DDR Clocking DDRCLK DDR Controller Clock J21 I OV DD (17) RTC RTC/GPIO1_14 Real Time Clock B17 I OV DD (1) Debug CKSTP_OUT_B Checkstop Out F18 O OV DD (1)(6)(7) CLK_OUT Clock Out E6 O O1V DD – EVT5_B/IIC4_SCL/GPIO4_02/ DIU_HSYNC Event 5A A 3 I O D V DD – EVT6_B/IIC4_SDA/GPIO4_03/ DIU_VSYNC Event 6A B 3 I O D V DD – EVT7_B/DMA2_DACK0_B/ GPIO4_08/TDM_RFS Event 7A A 5 I O D V DD – EVT8_B/DMA2_DDONE0_B/ GPIO4_09/TDM_RCK Event 8Y 5 I O D V DD – EVT9_B/IRQ_OUT_B Event 9A 3 I O O 1 V DD – EVT0_B Event 0D 6 I O O 1 V DD (9) EVT1_B Event 1C 4 I O O 1 V DD – EVT2_B Event 2C 1 I O O 1 V DD (6)(22) EVT3_B Event 3C 2 I O O 1 V DD – EVT4_B Event 4C 3 I O O 1 V DD – DFT SCAN_MODE_B Reserved F9 I O1V DD (10) TEST_SEL_B Reserved G8 I O1V DD (23) JTAG TCK Test Clock E18 I OV DD – TDI Test Data In A18 I OV DD (9) TDO Test Data Out C18 O OV DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] TMS Test Mode Select B18 I OV DD (9) TRST_B Test Reset D19 I OV DD (9) Analog Signals D1_MVREF SSTL Reference Voltage F20 IO G1V DD/2 – D1_TPA Reserved for internal use only J20 IO ‐ (12) FA_ANALOG_G_V Reserved for internal use only C20 IO ‐ (15) FA_ANALOG_PIN Reserved for internal use only B20 IO ‐ (15) SPARE1 Reserved for internal use only G6 ‐‐ (12) SPARE2 Reserved for internal use only H6 ‐‐ (12) SPARE3 Reserved for internal use only J6 ‐‐ (12) TD1_ANODE Thermal diode anode E21 IO (19) TD1_CATHODE Thermal diode cathode G21 IO (19) TH_TPA Reserved for internal use only F10 ‐‐ (12) Serdes 1 SD1_IMP_CAL_RX SerDes Receive Impedence Calibration AA12 I S1V DD (11) SD1_IMP_CAL_TX SerDes Transmit Impedance Calibration Y20 I X1V DD (16) SD1_PLL1_TPA Reserved for internal use only Y15 O AVDD_SD1_PLL1 (12) SD1_PLL1_TPD Reserved for internal use only AB15 O X1V DD (12) SD1_PLL2_TPA Reserved for internal use only Y19 O AVDD_SD1_PLL2 (12) SD1_PLL2_TPD Reserved for internal use only AB19 O X1V DD (12) SD1_REF_CLK1_N SerDes PLL 1 Reference Clock Complement AA14 I S1V DD – SD1_REF_CLK1_P SerDes PLL 1 Reference Clock AB14 I S1V DD – SD1_REF_CLK2_N SerDes PLL 2 Reference Clock Complement AA18 I S1V DD – SD1_REF_CLK2_P SerDes PLL 2 Reference Clock AB18 I S1V DD – SD1_RX0_N SerDes Receive Data (negative) AG10 I S1V DD – SD1_RX0_P SerDes Receive Data (positive) AH10 I S1V DD – SD1_RX1_N SerDes Receive Data (negative) AG11 I S1V DD – SD1_RX1_P SerDes Receive Data (positive) AH11 I S1V DD – SD1_RX2_N SerDes Receive Data (negative) AG13 I S1V DD – SD1_RX2_P SerDes Receive Data (positive) AH13 I S1V DD – SD1_RX3_N SerDes Receive Data (negative) AG14 I S1V DD – SD1_RX3_P SerDes Receive Data (positive) AH14 I S1V DD – SD1_RX4_N SerDes Receive Data (negative) AG16 I S1V DD – SD1_RX4_P SerDes Receive Data (positive) AH16 I S1V DD – SD1_RX5_N SerDes Receive Data (negative) AG17 I S1V DD – SD1_RX5_P SerDes Receive Data (positive) AH17 I S1V DD – SD1_RX6_N SerDes Receive Data (negative) AG19 I S1V DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 SD1_RX6_P SerDes Receive Data (positive) AH19 I S1V DD – SD1_RX7_N SerDes Receive Data (negative) AG20 I S1V DD – SD1_RX7_P SerDes Receive Data (positive) AH20 I S1V DD – SD1_TX0_N SerDes Transmit Data (negative) AE10 O X1V DD – SD1_TX0_P SerDes Transmit Data (positive) AD10 O X1V DD – SD1_TX1_N SerDes Transmit Data (negative) AE11 O X1V DD – SD1_TX1_P SerDes Transmit Data (positive) AD11 O X1V DD – SD1_TX2_N SerDes Transmit Data (negative) AE13 O X1V DD – SD1_TX2_P SerDes Transmit Data (positive) AD13 O X1V DD – SD1_TX3_N SerDes Transmit Data (negative) AE14 O X1V DD – SD1_TX3_P SerDes Transmit Data (positive) AD14 O X1V DD – SD1_TX4_N SerDes Transmit Data (negative) AE16 O X1V DD – SD1_TX4_P SerDes Transmit Data (positive) AD16 O X1V DD – SD1_TX5_N SerDes Transmit Data (negative) AE17 O X1V DD – SD1_TX5_P SerDes Transmit Data (positive) AD17 O X1V DD – SD1_TX6_N SerDes Transmit Data (negative) AE19 O X1V DD – SD1_TX6_P SerDes Transmit Data (positive) AD19 O X1V DD – SD1_TX7_N SerDes Transmit Data (negative) AE20 O X1V DD – SD1_TX7_P SerDes Transmit Data (positive) AD20 O X1V DD – USB PHY 1 & 2 USB1_DRVVBUS USB PHY Digital signal ‐ Drive VBUS F6 O USB_HV DD – USB1_PWRFAULT USB PHY Digital signal ‐ Power Fault F5 I USB_HV DD – USB1_UDM USB PHY Data Minus F2 IO USB_HV DD – USB1_UDP USB PHY Data Plus F1 IO USB_HV DD – USB1_UID USB PHY ID Detect F4 I USB_OV DD – USB1_VBUSCLMP USB PHY VBUS E4 I USB_HV DD – USB2_DRVVBUS USB PHY Digital signal ‐ Drive VBUS J5 O USB_HV DD – USB2_PWRFAULT USB PHY Digital signal ‐ Power Fault H5 I USB_HV DD – USB2_UDM USB PHY Data Minus H2 IO USB_HV DD – USB2_UDP USB PHY Data Plus H1 IO USB_HV DD – USB2_UID USB PHY ID Detect H4 I USB_OV DD – USB2_VBUSCLMP USB PHY VBUS J4 I USB_HV DD – USB_IBIAS_REXT USB PHY Impedance Calibration G4 IO USB_OV DD (20) IEEE1588 TSEC_1588_ALARM_OUT1/ GPIO3_03 Alarm Out 1A F 5 O L V DD (1) TSEC_1588_ALARM_OUT2/ GPIO3_04/EMI1_MDC Alarm Out 2A C 7 O L V DD (1) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] TSEC_1588_CLK_IN/ GPIO3_00 Clock In AC8 I LV DD (1) TSEC_1588_CLK_OUT/ GPIO3_05 Clock Out AD7 O LV DD (1) TSEC_1588_PULSE_OUT1/ GPIO3_06 Pulse Out 1A E 6 O L V DD (1) TSEC_1588_PULSE_OUT2/ GPIO3_07 Pulse Out 2A D 8 O L V DD (1) TSEC_1588_TRIG_IN1/ GPIO3_01 Trigger In 1A B 6 I L V DD (1) TSEC_1588_TRIG_IN2/ GPIO3_02/EMI1_MDIO Trigger In 2A E 5 I L V DD (1) Ethernet Management Interface 1 EMI1_MDC Management Data Clock AH3 O L1V DD – EMI1_MDC/ TSEC_1588_ALARM_OUT2/ GPIO3_04 Management Data Clock AC7 O LV DD (1) EMI1_MDIO Management Data In/Out AH4 IO L1V DD – EMI1_MDIO/ TSEC_1588_TRIG_IN2/ GPIO3_02 Management Data In/Out AE5 IO LV DD – Ethernet controller 1 and GPIO EC1_COL/GPIO3_10/ MII_COL/MAC2_MII_COL Collison Detect AC1 IO L1V DD – EC1_GTX_CLK/GPIO3_16/ MII_TX_CLK/ MAC2_GTX_CLK/ MAC2_MII_TX_CLK Transmit Clock Out AF3 O L1V DD (1) EC1_GTX_CLK125/ GPIO3_17 /MII_CRS/ MAC2_GTX_CLK125 / MAC2_MII_CRS Reference Clock AG3 I L1V DD (1) EC1_RXD0/GPIO3_21/ MII_RXD0/MAC2_RXD0/ MAC2_MII_RXD0 Receive Data AF2 I L1V DD (1) EC1_RXD1/GPIO3_20/ MII_RXD1/MAC2_RXD1/ MAC2_MII_RXD1 Receive Data AF1 I L1V DD (1) EC1_RXD2/GPIO3_19/ MII_RXD2/MAC2_RXD2/ MAC2_MII_RXD2 Receive Data AE1 I L1V DD (1) EC1_RXD3/GPIO3_18/ MII_RXD3/MAC2_RXD3/ MAC2_MII_RXD3 Receive Data AD2 I L1V DD (1) EC1_RX_CLK/GPIO3_23/ MII_RX_CLK/MAC2_RX_CLK/ MAC2_MII_RX_CLK Receive Clock AD1 I L1V DD (1) EC1_RX_CTL/GPIO3_22/ MII_RX_DV/MAC2_RX_CTL/ MAC2_MII_RX_DV Receive Data Valid AG2 I L1V DD (1) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 EC1_RX_ER/GPIO3_09/ MII_RX_ER/ MAC2_MII_RX_ER Receive Error AC2 IO L1V DD – EC1_TXD0/GPIO3_14/ MII_TXD0/MAC2_TXD0/ MAC2_MII_TXD0 Transmit Data AE3 O L1V DD (1) EC1_TXD1/GPIO3_13/ MII_TXD1/MAC2_TXD1/ MAC2_MII_TXD1 Transmit Data AE4 O L1V DD (1) EC1_TXD2/GPIO3_12/ MII_TXD2/MAC2_TXD2/ MAC2_MII_TXD2 Transmit Data AD3 O L1V DD (1) EC1_TXD3/GPIO3_11/ MII_TXD3/MAC2_TXD3/ MAC2_MII_TXD3 Transmit Data AC3 O L1V DD (1) EC1_TX_CTL/GPIO3_15 / MII_TX_EN/MAC2_TX_CTL/ MAC2_MII_TX_EN Transmit Enable AF4 O L1V DD (1)(14) EC1_TX_ER/GPIO3_08/ MII_TX_ER/ MAC2_MII_TX_ER Transmit Error AC4 IO L1V DD (14) Ethernet controller 2 and GPIO EC2_GTX_CLK/GPIO4_28 Transmit Clock Out AE8 O LV DD (1) EC2_GTX_CLK125/GPIO4_29 Reference Clock AC6 I LV DD (1) EC2_RXD0/GPIO3_31 Receive Data AH8 I LV DD (1) EC2_RXD1/GPIO3_30 Receive Data AG7 I LV DD (1) EC2_RXD2/GPIO3_29 Receive Data AH7 I LV DD (1) EC2_RXD3/GPIO3_28 Receive Data AH6 I LV DD (1) EC2_RX_CLK/GPIO4_31 Receive Clock AH5 I LV DD (1) EC2_RX_CTL/GPIO4_30 Receive Data Valid AG8 I LV DD (1) EC2_TXD0/GPIO3_27 Transmit Data AE7 O LV DD (1) EC2_TXD1/GPIO3_26 Transmit Data AF7 O LV DD (1) EC2_TXD2/GPIO3_25 Transmit Data AF6 O LV DD (1) EC2_TXD3/GPIO3_24 Transmit Data AG5 O LV DD (1) EC2_TX_CTL/GPIO4_27 Transmit Enable AF8 O LV DD (1)(14) DSYSCLK DIFF_SYSCLK "Single Oscillator Source" Reference Clock Differential (positive) G14 I O1V DD (18) DIFF_SYSCLK_B "Single Oscillator Source" Reference Clock Differential (negative) F14 I O1V DD (18) USB Clocking USBCLK USB PHY Clock In F8 I O1V DD (17) I2C 3 & 4 IIC3_SCL/GPIO4_00 Serial Clock V2 IO DV DD (7)(8) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] IIC3_SDA/GPIO4_01 Serial Data W3 IO DV DD (7)(8) IIC4_SCL/GPIO4_02/EVT5_B/ DIU_HSYNC Serial Clock AA3 IO DV DD (7)(8) IIC4_SDA/GPIO4_03/EVT6_B/ DIU_VSYNC Serial Data AB3 IO DV DD (7)(8) DMA DMA1_DACK0_B/GPIO4_05 / TDM_TFS DMA1 channel 0 acknowledge U5 O DV DD (1) DMA1_DDONE0_B/ GPIO4_06/TDM_TCK DMA1 channel 0 done R5 O DV DD (1) DMA1_DREQ0_B/GPIO4_04/ TDM_TXD DMA1 channel 0 request P5 I DV DD (1) DMA2_DACK0_B/GPIO4_08/ EVT7_B/TDM_RFS DMA2 channel 0 acknowledge AA5 O DV DD (1) DMA2_DDONE0_B/ GPIO4_09/EVT8_B/TDM_RCK DMA2 channel 0 done Y5 O DV DD (1) DMA2_DREQ0_B/GPIO4_07 / TDM_RXD DMA2 channel 0 request V5 I DV DD (1) QE_TDM CLK09/GPIO4_15 /BRGO2/ DIU_D10 External Clock P4 I DV DD (1) CLK10/GPIO4_22/BRGO3/ DIU_D11 External Clock P3 I DV DD (1) CLK11/GPIO4_16/BRGO4/ DIU_DE External Clock N4 I DV DD (1) CLK12/GPIO4_23/BRGO1/ DIU_CLK_OUT External Clock M4 I DV DD (1)(24) TDMA_RQ/GPIO4_14/ UC1_CDB_RXER/DIU_D4 Request R2 O DV DD (1) TDMA_RSYNC/GPIO4_11/ UC1_CTSB_RXDV/DIU_D1 Receive Sync U1 I DV DD (1) TDMA_RXD/GPIO4_10/ UC1_RXD7 /DIU_D0/ TDMA_TXD Receive Data U2 I DV DD (1) TDMA_TSYNC/GPIO4_13/ UC1_RTSB_TXEN/DIU_D3 Transmit Sync R1 I DV DD (1) TDMA_TXD/GPIO4_12/ UC1_TXD7 /DIU_D2/ TDMA_RXD_EXC Transmit Data T1 O DV DD (1) TDMB_RQ/GPIO4_21/ UC3_CDB_RXER/DIU_D9 Request R4 O DV DD (1) TDMB_RSYNC/GPIO4_18/ UC3_CTSB_RXDV/DIU_D6 Receive Sync T3 I DV DD (1) TDMB_RXD/GPIO4_17 / UC3_RXD7 /DIU_D5/ TDMB_TXD Receive Data U4 I DV DD (1) TDMB_TSYNC/GPIO4_20/ UC3_RTSB_TXEN/DIU_D8 Transmit Sync R3 I DV DD (1) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 TDMB_TXD/GPIO4_19/ UC3_TXD7 /DIU_D7 / TDMB_RXD_EXC Transmit Data T4 O DV DD (1) eSDHC SDHC_CD_B/GPIO4_24 SDHC Card Detect L5 I CV DD (1) SDHC_CLK/GPIO2_09 Host to Card Clock K1 IO EV DD – SDHC_CLK_SYNC_IN/IRQ10/ GPIO1_30 Clock Sync L4 I CV DD (1) SDHC_CLK_SYNC_OUT/ SPI_CS3_B/GPIO2_03/ SDHC_DAT7 / SDHC_DAT123_DIR Clock Sync N3 O CV DD (1) SDHC_CMD/GPIO2_04 Command/Response K3 IO EV DD – SDHC_CMD_DIR/SPI_CS1_B/ GPIO2_01/SDHC_DAT5 CMD direction control M2 O CV DD (1) SDHC_DAT0/GPIO2_05 Data L2 IO EV DD – SDHC_DAT0_DIR/ SPI_CS2_B/GPIO2_02/ SDHC_DAT6 Data M3 O CV DD (1) SDHC_DAT1/GPIO2_06 Data K4 IO EV DD – SDHC_DAT123_DIR/ SPI_CS3_B/GPIO2_03/ SDHC_DAT7 / SDHC_CLK_SYNC_OUT Data N3 O CV DD (1) SDHC_DAT2/GPIO2_07 Data L3 IO EV DD – SDHC_DAT3/GPIO2_08 Data L1 IO EV DD – SDHC_DAT4/SPI_CS0_B/ GPIO2_00 Data M1 IO CV DD – SDHC_DAT5 /SPI_CS1_B/ GPIO2_01/SDHC_CMD_DIR Data M2 IO CV DD – SDHC_DAT6/SPI_CS2_B/ GPIO2_02/SDHC_DAT0_DIR Data M3 IO CV DD – SDHC_DAT7 /SPI_CS3_B/ GPIO2_03/ SDHC_DAT123_DIR/ SDHC_CLK_SYNC_OUT Data N3 IO CV DD – SDHC_VS/IRQ03/GPIO1_23 Voltage Select D1 IO O1V DD – SDHC_WP/GPIO4_25 SDHC Write Protect M5 I CV DD (1) Power‐On‐Reset Configuration cfg_dram_type/IFC_A21 Power‐On‐Reset Configuration Signal C8 I OV DD (1)(4) cfg_eng_use0/IFC_WE0_B Power‐On‐Reset Configuration Signal D13 I OV DD (1)(21) cfg_eng_use1/IFC_OE_B Power‐On‐Reset Configuration Signal D15 I OV DD (1)(21) cfg_eng_use2/IFC_WP0_B Power‐On‐Reset Configuration Signal F17 I OV DD (1) cfg_gpinput0/IFC_AD00 Power‐On‐Reset Configuration Signal A4 I OV DD (1)(4) cfg_gpinput1/IFC_AD01 Power‐On‐Reset Configuration Signal B5 I OV DD (1)(4) cfg_gpinput2/IFC_AD02 Power‐On‐Reset Configuration Signal A5 I OV DD (1)(4) cfg_gpinput3/IFC_AD03 Power‐On‐Reset Configuration Signal B6 I OV DD (1)(4) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] cfg_gpinput4/IFC_AD04 Power‐On‐Reset Configuration Signal A6 I OV DD (1)(4) cfg_gpinput5 /IFC_AD05 Power‐On‐Reset Configuration Signal A7 I OV DD (1)(4) cfg_gpinput6/IFC_AD06 Power‐On‐Reset Configuration Signal B8 I OV DD (1)(4) cfg_gpinput7 /IFC_AD07 Power‐On‐Reset Configuration Signal A8 I OV DD (1)(4) cfg_ifc_te/IFC_TE Power‐On‐Reset Configuration Signal B14 I OV DD (1)(4) cfg_rcw_src0/IFC_AD08 Power‐On‐Reset Configuration Signal B9 I OV DD (1)(4) cfg_rcw_src1/IFC_AD09 Power‐On‐Reset Configuration Signal A9 I OV DD (1)(4) cfg_rcw_src2/IFC_AD10 Power‐On‐Reset Configuration Signal A10 I OV DD (1)(4) cfg_rcw_src3/IFC_AD11 Power‐On‐Reset Configuration Signal B11 I OV DD (1)(4) cfg_rcw_src4/IFC_AD12 Power‐On‐Reset Configuration Signal A11 I OV DD (1)(4) cfg_rcw_src5 /IFC_AD13 Power‐On‐Reset Configuration Signal B12 I OV DD (1)(4) cfg_rcw_src6/IFC_AD14 Power‐On‐Reset Configuration Signal A12 I OV DD (1)(4) cfg_rcw_src7 /IFC_AD15 Power‐On‐Reset Configuration Signal A13 I OV DD (1)(4) cfg_rcw_src8/IFC_CLE Power‐On‐Reset Configuration Signal F16 I OV DD (1)(4) General Purpose Input/Output GPIO1_09/IFC_CS4_B General Purpose Input/Output E17 IO OV DD – GPIO1_10/IFC_CS5_B General Purpose Input/Output C17 IO OV DD – GPIO1_11/IFC_CS6_B General Purpose Input/Output D18 IO OV DD – GPIO1_12/IFC_CS7_B General Purpose Input/Output C19 IO OV DD – GPO1_13/ASLEEP General Purpose Input/Output B2 O O1V DD (1) GPIO1_14/RTC General Purpose Input/Output B17 IO OV DD – GPIO1_15 /UART1_SOUT General Purpose Input/Output AA2 IO DV DD – GPIO1_16/UART2_SOUT General Purpose Input/Output AA4 IO DV DD – GPIO1_17 /UART1_SIN General Purpose Input/Output AA1 IO DV DD – GPIO1_18/UART2_SIN General Purpose Input/Output W4 IO DV DD – GPIO1_19/UART1_RTS_B/ UART3_SOUT General Purpose Input/Output Y1 IO DV DD – GPIO1_20/UART2_RTS_B/ UART4_SOUT General Purpose Input/Output V4 IO DV DD – GPIO1_21/UART1_CTS_B/ UART3_SIN General Purpose Input/Output Y2 IO DV DD – GPIO1_22/UART2_CTS_B/ UART4_SIN General Purpose Input/Output Y4 IO DV DD – GPIO1_23/IRQ03/SDHC_VS General Purpose Input/Output D1 IO O1V DD – GPIO1_24/IRQ04 General Purpose Input/Output D4 IO O1V DD – GPIO1_25 /IRQ05 General Purpose Input/Output D5 IO O1V DD – GPIO1_26/IRQ06 General Purpose Input/Output AB4 IO L1V DD – GPIO1_27 /IRQ07 General Purpose Input/Output AD5 IO L1V DD – GPIO1_28/IRQ08 General Purpose Input/Output AB1 IO L1V DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 GPIO1_29/IRQ09 General Purpose Input/Output AC5 IO L1V DD – GPIO1_30/IRQ10/ SDHC_CLK_SYNC_IN General Purpose Input/Output L4 IO CV DD – GPIO1_31/IRQ11 General Purpose Input/Output U3 IO DV DD – GPIO2_00/SPI_CS0_B/ SDHC_DAT4 General Purpose Input/Output M1 IO CV DD – GPIO2_01/SPI_CS1_B/ SDHC_DAT5 / SDHC_CMD_DIR General Purpose Input/Output M2 IO CV DD – GPIO2_02/SPI_CS2_B/ SDHC_DAT6/ SDHC_DAT0_DIR General Purpose Input/Output M3 IO CV DD – GPIO2_03/SPI_CS3_B/ SDHC_DAT7 / SDHC_DAT123_DIR/ SDHC_CLK_SYNC_OUT General Purpose Input/Output N3 IO CV DD – GPIO2_04/SDHC_CMD General Purpose Input/Output K3 IO EV DD – GPIO2_05 /SDHC_DAT0 General Purpose Input/Output L2 IO EV DD – GPIO2_06/SDHC_DAT1 General Purpose Input/Output K4 IO EV DD – GPIO2_07 /SDHC_DAT2 General Purpose Input/Output L3 IO EV DD – GPIO2_08/SDHC_DAT3 General Purpose Input/Output L1 IO EV DD – GPIO2_09/SDHC_CLK General Purpose Input/Output K1 IO EV DD – GPIO2_10/IFC_CS1_B General Purpose Input/Output E15 IO OV DD – GPIO2_11/IFC_CS2_B General Purpose Input/Output D16 IO OV DD – GPIO2_12/IFC_CS3_B General Purpose Input/Output C16 IO OV DD – GPIO2_13/IFC_PAR0 General Purpose Input/Output C15 IO OV DD – GPIO2_14/IFC_PAR1 General Purpose Input/Output C14 IO OV DD – GPIO2_15 /IFC_PERR_B General Purpose Input/Output E14 IO OV DD – GPIO2_25 /IFC_A25/ IFC_WP1_B General Purpose Input/Output C10 IO OV DD – GPIO2_26/IFC_A26/ IFC_WP2_B General Purpose Input/Output E11 IO OV DD – GPIO2_27 /IFC_A27/ IFC_WP3_B General Purpose Input/Output C11 IO OV DD – GPIO2_28/IFC_A28 General Purpose Input/Output D11 IO OV DD – GPIO2_29/IFC_A29/ IFC_RB2_B General Purpose Input/Output C12 IO OV DD – GPIO2_30/IFC_A30/ IFC_RB3_B General Purpose Input/Output D12 IO OV DD – GPIO2_31/IFC_A31/ IFC_RB4_B General Purpose Input/Output E12 IO OV DD – GPIO3_00/ TSEC_1588_CLK_IN General Purpose Input/Output AC8 IO LV DD – GPIO3_01/ TSEC_1588_TRIG_IN1 General Purpose Input/Output AB6 IO LV DD – GPIO3_02/ TSEC_1588_TRIG_IN2/ EMI1_MDIO General Purpose Input/Output AE5 IO LV DD – GPIO3_03/ TSEC_1588_ALARM_OUT1 General Purpose Input/Output AF5 IO LV DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] GPIO3_04/ TSEC_1588_ALARM_OUT2/ EMI1_MDC General Purpose Input/Output AC7 IO LV DD – GPIO3_05 / TSEC_1588_CLK_OUT General Purpose Input/Output AD7 IO LV DD – GPIO3_06/ TSEC_1588_PULSE_OUT1 General Purpose Input/Output AE6 IO LV DD – GPIO3_07 / TSEC_1588_PULSE_OUT2 General Purpose Input/Output AD8 IO LV DD – GPIO3_08/EC1_TX_ER/ MII_TX_ER/ MAC2_MII_TX_ER General Purpose Input/Output AC4 IO L1V DD – GPIO3_09/EC1_RX_ER/ MII_RX_ER/ MAC2_MII_RX_ER General Purpose Input/Output AC2 IO L1V DD – GPIO3_10/EC1_COL/ MII_COL/MAC2_MII_COL General Purpose Input/Output AC1 IO L1V DD – GPIO3_11/EC1_TXD3/ MII_TXD3/MAC2_TXD3/ MAC2_MII_TXD3 General Purpose Input/Output AC3 IO L1V DD – GPIO3_12/EC1_TXD2/ MII_TXD2/MAC2_TXD2/ MAC2_MII_TXD2 General Purpose Input/Output AD3 IO L1V DD – GPIO3_13/EC1_TXD1/ MII_TXD1/MAC2_TXD1/ MAC2_MII_TXD1 General Purpose Input/Output AE4 IO L1V DD – GPIO3_14/EC1_TXD0/ MII_TXD0/MAC2_TXD0/ MAC2_MII_TXD0 General Purpose Input/Output AE3 IO L1V DD – GPIO3_15 /EC1_TX_CTL/ MII_TX_EN/MAC2_TX_CTL/ MAC2_MII_TX_EN General Purpose Input/Output AF4 IO L1V DD – GPIO3_16/EC1_GTX_CLK/ MII_TX_CLK/ MAC2_GTX_CLK/ MAC2_MII_TX_CLK General Purpose Input/Output AF3 IO L1V DD – GPIO3_17 / EC1_GTX_CLK125/MII_CRS/ MAC2_GTX_CLK125 / MAC2_MII_CRS General Purpose Input/Output AG3 IO L1V DD – GPIO3_18/EC1_RXD3/ MII_RXD3/MAC2_RXD3/ MAC2_MII_RXD3 General Purpose Input/Output AD2 IO L1V DD – GPIO3_19/EC1_RXD2/ MII_RXD2/MAC2_RXD2/ MAC2_MII_RXD2 General Purpose Input/Output AE1 IO L1V DD – GPIO3_20/EC1_RXD1/ MII_RXD1/MAC2_RXD1/ MAC2_MII_RXD1 General Purpose Input/Output AF1 IO L1V DD – GPIO3_21/EC1_RXD0/ MII_RXD0/MAC2_RXD0/ MAC2_MII_RXD0 General Purpose Input/Output AF2 IO L1V DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 GPIO3_22/EC1_RX_CTL/ MII_RX_DV/MAC2_RX_CTL/ MAC2_MII_RX_DV General Purpose Input/Output AG2 IO L1V DD – GPIO3_23/EC1_RX_CLK/ MII_RX_CLK/MAC2_RX_CLK/ MAC2_MII_RX_CLK General Purpose Input/Output AD1 IO L1V DD – GPIO3_24/EC2_TXD3 General Purpose Input/Output AG5 IO LV DD – GPIO3_25 /EC2_TXD2 General Purpose Input/Output AF6 IO LV DD – GPIO3_26/EC2_TXD1 General Purpose Input/Output AF7 IO LV DD – GPIO3_27 /EC2_TXD0 General Purpose Input/Output AE7 IO LV DD – GPIO3_28/EC2_RXD3 General Purpose Input/Output AH6 IO LV DD – GPIO3_29/EC2_RXD2 General Purpose Input/Output AH7 IO LV DD – GPIO3_30/EC2_RXD1 General Purpose Input/Output AG7 IO LV DD – GPIO3_31/EC2_RXD0 General Purpose Input/Output AH8 IO LV DD – GPIO4_00/IIC3_SCL General Purpose Input/Output V2 IO DV DD – GPIO4_01/IIC3_SDA General Purpose Input/Output W3 IO DV DD – GPIO4_02/IIC4_SCL/EVT5_B/ DIU_HSYNC General Purpose Input/Output AA3 IO DV DD – GPIO4_03/IIC4_SDA/EVT6_B/ DIU_VSYNC General Purpose Input/Output AB3 IO DV DD – GPIO4_04/DMA1_DREQ0_B/ TDM_TXD General Purpose Input/Output P5 IO DV DD – GPIO4_05 /DMA1_DACK0_B/ TDM_TFS General Purpose Input/Output U5 IO DV DD – GPIO4_06/ DMA1_DDONE0_B/TDM_TCK General Purpose Input/Output R5 IO DV DD – GPIO4_07 /DMA2_DREQ0_B/ TDM_RXD General Purpose Input/Output V5 IO DV DD – GPIO4_08/DMA2_DACK0_B/ EVT7_B/TDM_RFS General Purpose Input/Output AA5 IO DV DD – GPIO4_09/ DMA2_DDONE0_B/EVT8_B/ TDM_RCK General Purpose Input/Output Y5 IO DV DD – GPIO4_10/TDMA_RXD/ UC1_RXD7 /DIU_D0 General Purpose Input/Output U2 IO DV DD – GPIO4_11/TDMA_RSYNC/ UC1_CTSB_RXDV/DIU_D1 General Purpose Input/Output U1 IO DV DD – GPIO4_12/TDMA_TXD/ UC1_TXD7 /DIU_D2 General Purpose Input/Output T1 IO DV DD – GPIO4_13/TDMA_TSYNC/ UC1_RTSB_TXEN/DIU_D3 General Purpose Input/Output R1 IO DV DD – GPIO4_14/TDMA_RQ/ UC1_CDB_RXER/DIU_D4 General Purpose Input/Output R2 IO DV DD – GPIO4_15 /CLK09/BRGO2/ DIU_D10 General Purpose Input/Output P4 IO DV DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] GPIO4_16/CLK11/BRGO4/ DIU_DE General Purpose Input/Output N4 IO DV DD – GPIO4_17 /TDMB_RXD/ UC3_RXD7 /DIU_D5 General Purpose Input/Output U4 IO DV DD – GPIO4_18/TDMB_RSYNC/ UC3_CTSB_RXDV/DIU_D6 General Purpose Input/Output T3 IO DV DD – GPIO4_19/TDMB_TXD/ UC3_TXD7 /DIU_D7 General Purpose Input/Output T4 IO DV DD – GPIO4_20/TDMB_TSYNC/ UC3_RTSB_TXEN/DIU_D8 General Purpose Input/Output R3 IO DV DD – GPIO4_21/TDMB_RQ/ UC3_CDB_RXER/DIU_D9 General Purpose Input/Output R4 IO DV DD – GPIO4_22/CLK10/BRGO3/ DIU_D11 General Purpose Input/Output P3 IO DV DD – GPIO4_23/CLK12/BRGO1/ DIU_CLK_OUT General Purpose Input/Output M4 IO DV DD – GPIO4_24/SDHC_CD_B General Purpose Input/Output L5 IO CV DD – GPIO4_25 /SDHC_WP General Purpose Input/Output M5 IO CV DD – GPIO4_27 /EC2_TX_CTL General Purpose Input/Output AF8 IO LV DD – GPIO4_28/EC2_GTX_CLK General Purpose Input/Output AE8 IO LV DD – GPIO4_29/EC2_GTX_CLK125 General Purpose Input/Output AC6 IO LV DD – GPIO4_30/EC2_RX_CTL General Purpose Input/Output AG8 IO LV DD – GPIO4_31/EC2_RX_CLK General Purpose Input/Output AH5 IO LV DD – DIU DIU_CLK_OUT/CLK12/ GPIO4_23/BRGO1 Pixel Clock M4 O DV DD (1) DIU_D0/TDMA_RXD/ GPIO4_10/UC1_RXD7 DIU Data U2 O DV DD (1) DIU_D1/TDMA_RSYNC/ GPIO4_11/UC1_CTSB_RXDV DIU Data U1 O DV DD (1) DIU_D10/CLK09/GPIO4_15 / BRGO2 DIU Data P4 O DV DD (1) DIU_D11/CLK10/GPIO4_22/ BRGO3 DIU Data P3 O DV DD (1) DIU_D2/TDMA_TXD/ GPIO4_12/UC1_TXD7 DIU Data T1 O DV DD (1) DIU_D3/TDMA_TSYNC/ GPIO4_13/UC1_RTSB_TXEN DIU Data R1 O DV DD (1) DIU_D4/TDMA_RQ/ GPIO4_14/UC1_CDB_RXER DIU Data R2 O DV DD (1) DIU_D5 /TDMB_RXD/ GPIO4_17 /UC3_RXD7 DIU Data U4 O DV DD (1) DIU_D6/TDMB_RSYNC/ GPIO4_18/UC3_CTSB_RXDV DIU Data T3 O DV DD (1) DIU_D7 /TDMB_TXD/ GPIO4_19/UC3_TXD7 DIU Data T4 O DV DD (1) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 DIU_D8/TDMB_TSYNC/ GPIO4_20/UC3_RTSB_TXEN DIU Data R3 O DV DD (1) DIU_D9/TDMB_RQ/ GPIO4_21/UC3_CDB_RXER DIU Data R4 O DV DD (1) DIU_DE/CLK11/GPIO4_16/ BRGO4 Data Enable N4 O DV DD (1) DIU_HSYNC/IIC4_SCL/ GPIO4_02/EVT5_B Horizontal sync AA3 O DV DD (1) DIU_VSYNC/IIC4_SDA/ GPIO4_03/EVT6_B Vertical sync AB3 O DV DD (1) TDM TDM_RCK/ DMA2_DDONE0_B/ GPIO4_09/EVT8_B Receive clock Y5 IO DV DD – TDM_RFS/DMA2_DACK0_B/ GPIO4_08/EVT7_B Receive frame sync AA5 IO DV DD – TDM_RXD/DMA2_DREQ0_B/ GPIO4_07 Receive data V5 I DV DD (1) TDM_TCK/ DMA1_DDONE0_B/GPIO4_06 Transmit clock R5 IO DV DD – TDM_TFS/DMA1_DACK0_B/ GPIO4_05 Transmit frame sync U5 IO DV DD – TDM_TXD/DMA1_DREQ0_B/ GPIO4_04 Transmit data P5 O DV DD (1) QE BRGO1/CLK12/GPIO4_23/ DIU_CLK_OUT Baud rate generator M4 O DV DD (1) BRGO2/CLK09/GPIO4_15 / DIU_D10 Baud rate generator P4 O DV DD (1) BRGO3/CLK10/GPIO4_22/ DIU_D11 Baud rate generator P3 O DV DD (1) BRGO4/CLK11/GPIO4_16/ DIU_DE Baud rate generator N4 O DV DD (1) UC1_CDB_RXER/TDMA_RQ/ GPIO4_14/DIU_D4 Receive Error R2 I DV DD (1) UC1_CTSB_RXDV/ TDMA_RSYNC/GPIO4_11/ DIU_D1 Receive DV U1 I DV DD (1) UC1_RTSB_TXEN/ TDMA_TSYNC/GPIO4_13/ DIU_D3 Transmit Enable R1 O DV DD (1) UC1_RXD7 /TDMA_RXD/ GPIO4_10/DIU_D0 Receive Data U2 I DV DD (1) UC1_TXD7 /TDMA_TXD/ GPIO4_12/DIU_D2 Transmit Data T1 O DV DD (1) UC3_CDB_RXER/TDMB_RQ/ GPIO4_21/DIU_D9 Receive Error R4 I DV DD (1) UC3_CTSB_RXDV/ TDMB_RSYNC/GPIO4_18/ DIU_D6 Receive DV T3 I DV DD (1) UC3_RTSB_TXEN/ TDMB_TSYNC/GPIO4_20/ DIU_D8 Transmit Enable R3 O DV DD (1) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] UC3_RXD7 /TDMB_RXD/ GPIO4_17 /DIU_D5 Receive Data U4 I DV DD (1) UC3_TXD7 /TDMB_TXD/ GPIO4_19/DIU_D7 Transmit Data T4 O DV DD (1) Power and Ground Signals GND001 GND A2 – – – GND002 GND A20 – – – GND003 GND A27 – – – GND004 GND B1 – – – GND005 GND B4 – – – GND006 GND B7 – – – GND007 GND B10 – – – GND008 GND B13 – – – GND009 GND B16 – – – GND010 GND B19 – – – GND011 GND B23 – – – GND012 GND B25 – – – GND013 GND B28 – – – GND014 GND C22 – – – GND015 GND C26 – – – GND016 GND D2 – – – GND017 GND D20 – – – GND018 GND D21 – – – GND019 GND D24 – – – GND020 GND E5 – – – GND021 GND E7 – – – GND022 GND E10 – – – GND023 GND E13 – – – GND024 GND E16 – – – GND025 GND E19 – – – GND026 GND E22 – – – GND027 GND E26 – – – GND028 GND F15 – – – GND029 GND F24 – – – GND030 GND G7 – – – GND031 GND G13 – – – GND032 GND G16 – – – GND033 GND G22 – – – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 GND034 GND G26 – – – GND035 GND H7 – – – GND036 GND H8 – – – GND037 GND H9 – – – GND038 GND H10 – – – GND039 GND H11 – – – GND040 GND H12 – – – GND041 GND H13 – – – GND042 GND H14 – – – GND043 GND H15 – – – GND044 GND H16 – – – GND045 GND H17 – – – GND046 GND H18 – – – GND047 GND H19 – – – GND048 GND H20 – – – GND049 GND H24 – – – GND050 GND J7 – – – GND051 GND J22 – – – GND052 GND J26 – – – GND053 GND K2 – – – GND054 GND K5 – – – GND055 GND K6 – – – GND056 GND K7 – – – GND057 GND K12 – – – GND058 GND K14 – – – GND059 GND K16 – – – GND060 GND K18 – – – GND061 GND K20 – – – GND062 GND K24 – – – GND063 GND L7 – – – GND064 GND L9 – – – GND065 GND L11 – – – GND066 GND L13 – – – GND067 GND L15 – – – GND068 GND L17 – – – GND069 GND L19 – – – GND070 GND L22 – – – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] GND071 GND L26 – – – GND072 GND M7 – – – GND073 GND M10 – – – GND074 GND M12 – – – GND075 GND M14 – – – GND076 GND M16 – – – GND077 GND M18 – – – GND078 GND M20 – – – GND079 GND M24 – – – GND080 GND N2 – – – GND081 GND N5 – – – GND082 GND N7 – – – GND083 GND N9 – – – GND084 GND N11 – – – GND085 GND N13 – – – GND086 GND N15 – – – GND087 GND N17 – – – GND088 GND N19 – – – GND089 GND N22 – – – GND090 GND N26 – – – GND091 GND P7 – – – GND092 GND P10 – – – GND093 GND P12 – – – GND094 GND P14 – – – GND095 GND P16 – – – GND096 GND P18 – – – GND097 GND P20 – – – GND098 GND P24 – – – GND099 GND R7 – – – GND100 GND R9 – – – GND101 GND R11 – – – GND102 GND R13 – – – GND103 GND R15 – – – GND104 GND R17 – – – GND105 GND R19 – – – GND106 GND R22 – – – GND107 GND R26 – – – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 GND108 GND T2 – – – GND109 GND T5 – – – GND110 GND T7 – – – GND111 GND T10 – – – GND112 GND T12 – – – GND113 GND T14 – – – GND114 GND T16 – – – GND115 GND T18 – – – GND116 GND T20 – – – GND117 GND T22 – – – GND118 GND T26 – – – GND119 GND U7 – – – GND120 GND U9 – – – GND121 GND U11 – – – GND122 GND U13 – – – GND123 GND U15 – – – GND124 GND U17 – – – GND125 GND U19 – – – GND126 GND U24 – – – GND127 GND V7 – – – GND128 GND V10 – – – GND129 GND V12 – – – GND130 GND V14 – – – GND131 GND V16 – – – GND132 GND V18 – – – GND133 GND V20 – – – GND134 GND V22 – – – GND135 GND V26 – – – GND136 GND W2 – – – GND137 GND W5 – – – GND138 GND W7 – – – GND139 GND W9 – – – GND140 GND W11 – – – GND141 GND W13 – – – GND142 GND W24 – – – GND143 GND Y7 – – – GND144 GND Y10 – – – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] GND145 GND Y12 – – – GND146 GND Y22 – – – GND147 GND Y26 – – – GND148 GND AA11 – – – GND149 GND AA24 – – – GND150 GND AB2 – – – GND151 GND AB5 – – – GND152 GND AB7 – – – GND153 GND AB22 – – – GND154 GND AB26 – – – GND155 GND AC24 – – – GND156 GND AC26 – – – GND157 GND AD4 – – – GND158 GND AD6 – – – GND159 GND AD22 – – – GND160 GND AE2 – – – GND161 GND AE24 – – – GND162 GND AE26 – – – GND163 GND AF9 – – – GND164 GND AF21 – – – GND165 GND AG1 – – – GND166 GND AG4 – – – GND167 GND AG6 – – – GND168 GND AG22 – – – GND169 GND AG23 – – – GND170 GND AG26 – – – GND171 GND AH2 – – – USB_AGND01 USB PHY Transceiver GND E1 – – – USB_AGND02 USB PHY Transceiver GND E2 – – – USB_AGND03 USB PHY Transceiver GND E3 – – – USB_AGND04 USB PHY Transceiver GND F3 – – – USB_AGND05 USB PHY Transceiver GND G1 – – – USB_AGND06 USB PHY Transceiver GND G2 – – – USB_AGND07 USB PHY Transceiver GND G3 – – – USB_AGND08 USB PHY Transceiver GND G5 – – – USB_AGND09 USB PHY Transceiver GND H3 – – – USB_AGND10 USB PHY Transceiver GND J1 – – – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 USB_AGND11 USB PHY Transceiver GND J2 – – – USB_AGND12 USB PHY Transceiver GND J3 – – – X1GND01 Serdes 1 transceiver GND AC10 – – – X1GND02 Serdes 1 transceiver GND AC11 – – – X1GND03 Serdes 1 transceiver GND AC13 – – – X1GND04 Serdes 1 transceiver GND AC14 – – – X1GND05 Serdes 1 transceiver GND AC16 – – – X1GND06 Serdes 1 transceiver GND AC17 – – – X1GND07 Serdes 1 transceiver GND AC19 – – – X1GND08 Serdes 1 transceiver GND AC20 – – – X1GND09 Serdes 1 transceiver GND AD9 – – – X1GND10 Serdes 1 transceiver GND AD12 – – – X1GND11 Serdes 1 transceiver GND AD15 – – – X1GND12 Serdes 1 transceiver GND AD18 – – – X1GND13 Serdes 1 transceiver GND AD21 – – – X1GND14 Serdes 1 transceiver GND AE9 – – – X1GND15 Serdes 1 transceiver GND AE12 – – – X1GND16 Serdes 1 transceiver GND AE15 – – – X1GND17 Serdes 1 transceiver GND AE18 – – – X1GND18 Serdes 1 transceiver GND AE21 – – – S1GND01 Serdes 1 core logic GND Y14 – – – S1GND02 Serdes 1 core logic GND Y16 – – – S1GND03 Serdes 1 core logic GND Y17 – – – S1GND04 Serdes 1 core logic GND Y18 – – – S1GND05 Serdes 1 core logic GND AA13 – – – S1GND06 Serdes 1 core logic GND AA15 – – – S1GND07 Serdes 1 core logic GND AA17 – – – S1GND08 Serdes 1 core logic GND AA19 – – – S1GND09 Serdes 1 core logic GND AA21 – – – S1GND10 Serdes 1 core logic GND AB13 – – – S1GND11 Serdes 1 core logic GND AB17 – – – S1GND12 Serdes 1 core logic GND AB21 – – – S1GND13 Serdes 1 core logic GND AF10 – – – S1GND14 Serdes 1 core logic GND AF11 – – – S1GND15 Serdes 1 core logic GND AF12 – – – S1GND16 Serdes 1 core logic GND AF13 – – – S1GND17 Serdes 1 core logic GND AF14 – – – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] S1GND18 Serdes 1 core logic GND AF15 – – – S1GND19 Serdes 1 core logic GND AF16 – – – S1GND20 Serdes 1 core logic GND AF17 – – – S1GND21 Serdes 1 core logic GND AF18 – – – S1GND22 Serdes 1 core logic GND AF19 – – – S1GND23 Serdes 1 core logic GND AF20 – – – S1GND24 Serdes 1 core logic GND AG9 – – – S1GND25 Serdes 1 core logic GND AG12 – – – S1GND26 Serdes 1 core logic GND AG15 – – – S1GND27 Serdes 1 core logic GND AG18 – – – S1GND28 Serdes 1 core logic GND AG21 – – – S1GND29 Serdes 1 core logic GND AH9 – – – S1GND30 Serdes 1 core logic GND AH12 – – – S1GND31 Serdes 1 core logic GND AH15 – – – S1GND32 Serdes 1 core logic GND AH18 – – – S1GND33 Serdes 1 core logic GND AH21 – – – AGND_SD1_PLL1 Serdes 1 PLL 1 GND AA16 – – – AGND_SD1_PLL2 Serdes 1 PLL 2 GND AA20 – – – SENSEGND GND Sense pin G20 – – – SENSEGNDC GND Sense pin for VDDC domain AB10 – – – O1VDD1 General I/O supply ‐ Always on J11 – O1V DD – O1VDD2 General I/O supply ‐ Always on J12 – O1V DD – O1VDD3 General I/O supply ‐ Always on J13 – O1V DD – OVDD1 General I/O supply ‐ Switchable J14 – OV DD – OVDD2 General I/O supply ‐ Switchable J15 – OV DD – OVDD3 General I/O supply ‐ Switchable J16 – OV DD – OVDD4 General I/O supply ‐ Switchable J17 – OV DD – OVDD5 General I/O supply ‐ Switchable J18 – OV DD – OVDD6 General I/O supply ‐ Switchable J19 – OV DD – DVDD1 UART/I2C/DMA/TDM supply ‐ Switchable N8 – DV DD – DVDD2 UART/I2C/DMA/TDM supply ‐ Switchable P8 – DV DD – DVDD3 UART/I2C/DMA/TDM supply ‐ Switchable R8 – DV DD – CVDD SPI supply ‐ Switchable M8 – CV DD – EVDD eSDHC supply ‐ Switchable L8 – EV DD – L1VDD1 Ethernet controller 1 and GPIO supply‐ Always ON T8 – L1V DD – L1VDD2 Ethernet controller 1 and GPIO supply‐ Always ON U8 – L1V DD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 LVDD1 Ethernet controller 2, 1588 and GPIO supply‐ Switchable V8 – LV DD – LVDD2 Ethernet controller 2, 1588 and GPIO supply‐ Switchable W8 – LV DD – G1VDD01 DDR supply for port 1 ‐ Switchable D27 – G1V DD – G1VDD02 DDR supply for port 1 ‐ Switchable F27 – G1V DD – G1VDD03 DDR supply for port 1 ‐ Switchable H27 – G1V DD – G1VDD04 DDR supply for port 1 ‐ Switchable K21 – G1V DD – G1VDD05 DDR supply for port 1 ‐ Switchable K27 – G1V DD – G1VDD06 DDR supply for port 1 ‐ Switchable L21 – G1V DD – G1VDD07 DDR supply for port 1 ‐ Switchable M21 – G1V DD – G1VDD08 DDR supply for port 1 ‐ Switchable M27 – G1V DD – G1VDD09 DDR supply for port 1 ‐ Switchable N21 – G1V DD – G1VDD10 DDR supply for port 1 ‐ Switchable P21 – G1V DD – G1VDD11 DDR supply for port 1 ‐ Switchable P27 – G1V DD – G1VDD12 DDR supply for port 1 ‐ Switchable R21 – G1V DD – G1VDD13 DDR supply for port 1 ‐ Switchable T21 – G1V DD – G1VDD14 DDR supply for port 1 ‐ Switchable U21 – G1V DD – G1VDD15 DDR supply for port 1 ‐ Switchable U27 – G1V DD – G1VDD16 DDR supply for port 1 ‐ Switchable W27 – G1V DD – G1VDD17 DDR supply for port 1 ‐ Switchable AA27 – G1V DD – G1VDD18 DDR supply for port 1 ‐ Switchable AD27 – G1V DD – G1VDD19 DDR supply for port 1 ‐ Switchable AF27 – G1V DD – S1VDD1 SerDes 1 core logic supply ‐ Switchable W15 – S1V DD – S1VDD2 SerDes 1 core logic supply ‐ Switchable W16 – S1V DD – S1VDD3 SerDes 1 core logic supply ‐ Switchable W17 – S1V DD – S1VDD4 SerDes 1 core logic supply ‐ Switchable W18 – S1V DD – S1VDD5 SerDes 1 core logic supply ‐ Switchable W19 – S1V DD – S1VDD6 SerDes 1 core logic supply ‐ Switchable W20 – S1V DD – S1VDD7 SerDes 1 core logic supply ‐ Switchable Y13 – S1V DD – X1VDD1 SerDes 1 transceiver supply ‐ Switchable AC9 – X1V DD – X1VDD2 SerDes 1 transceiver supply ‐ Switchable AC12 – X1V DD – X1VDD3 SerDes 1 transceiver supply ‐ Switchable AC15 – X1V DD – X1VDD4 SerDes 1 transceiver supply ‐ Switchable AC18 – X1V DD – X1VDD5 SerDes 1 transceiver supply ‐ Switchable AC21 – X1V DD – PROG_SFP SFP Fuse Programming supply F12 – PROG_SFP – PROG_MTR Reserved for Internal Use Only F11 – PROG_MTR (15) FA_VL Reserved for Internal Use Only G18 – FA_VL (15) Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] TH_VDD Thermal Monitor Unit supply ‐‐ Switchable G9 – TH_V DD – VDD01 Supply for cores and platform ‐ Switchable K15 – VDD – VDD02 Supply for cores and platform ‐ Switchable K17 – VDD – VDD03 Supply for cores and platform ‐ Switchable K19 – VDD – VDD04 Supply for cores and platform ‐ Switchable L12 – VDD – VDD05 Supply for cores and platform ‐ Switchable L14 – VDD – VDD06 Supply for cores and platform ‐ Switchable L16 – VDD – VDD07 Supply for cores and platform ‐ Switchable L18 – VDD – VDD08 Supply for cores and platform ‐ Switchable L20 – VDD – VDD09 Supply for cores and platform ‐ Switchable M13 – VDD – VDD10 Supply for cores and platform ‐ Switchable M15 – VDD – VDD11 Supply for cores and platform ‐ Switchable M17 – VDD – VDD12 Supply for cores and platform ‐ Switchable M19 – VDD – VDD13 Supply for cores and platform ‐ Switchable N12 – VDD – VDD14 Supply for cores and platform ‐ Switchable N14 – VDD – VDD15 Supply for cores and platform ‐ Switchable N16 – VDD – VDD16 Supply for cores and platform ‐ Switchable N18 – VDD – VDD17 Supply for cores and platform ‐ Switchable N20 – VDD – VDD18 Supply for cores and platform ‐ Switchable P11 – VDD – VDD19 Supply for cores and platform ‐ Switchable P13 – VDD – VDD20 Supply for cores and platform ‐ Switchable P15 – VDD – VDD21 Supply for cores and platform ‐ Switchable P17 – VDD – VDD22 Supply for cores and platform ‐ Switchable P19 – VDD – VDD23 Supply for cores and platform ‐ Switchable R12 – VDD – VDD24 Supply for cores and platform ‐ Switchable R14 – VDD – VDD25 Supply for cores and platform ‐ Switchable R16 – VDD – VDD26 Supply for cores and platform ‐ Switchable R18 – VDD – VDD27 Supply for cores and platform ‐ Switchable R20 – VDD – VDD28 Supply for cores and platform ‐ Switchable T13 – VDD – VDD29 Supply for cores and platform ‐ Switchable T15 – VDD – VDD30 Supply for cores and platform ‐ Switchable T17 – VDD – VDD31 Supply for cores and platform ‐ Switchable T19 – VDD – VDD32 Supply for cores and platform ‐ Switchable U14 – VDD – VDD33 Supply for cores and platform ‐ Switchable U16 – VDD – VDD34 Supply for cores and platform ‐ Switchable U18 – VDD – VDD35 Supply for cores and platform ‐ Switchable U20 – VDD – VDD36 Supply for cores and platform ‐ Switchable V13 – VDD – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 VDD37 Supply for cores and platform ‐ Switchable V15 – VDD – VDD38 Supply for cores and platform ‐ Switchable V17 – VDD – VDD39 Supply for cores and platform ‐ Switchable V19 – VDD – VDD40 Supply for cores and platform ‐ Switchable W14 – VDD – VDDC01 Always ON supply K11 – VDDC – VDDC02 Always ON supply K13 – VDDC – VDDC03 Always ON supply L10 – VDDC – VDDC04 Always ON supply M11 – VDDC – VDDC05 Always ON supply N10 – VDDC – VDDC06 Always ON supply R10 – VDDC – VDDC07 Always ON supply T11 – VDDC – VDDC08 Always ON supply U10 – VDDC – VDDC09 Always ON supply U12 – VDDC – VDDC10 Always ON supply V11 – VDDC – VDDC11 Always ON supply W10 – VDDC – VDDC12 Always ON supply W12 – VDDC – AVDD_CGA1 e5500 Cluster Group A PLL1 supply (SDHC /Cores fed through this) ‐ Switchable G11 – AVDD_CGA1 – AVDD_CGA2 e5500 Cluster Group A PLL2 supply (Cores are fed through this) ‐ Switchable G12 – AVDD_CGA2 – AVDD_PLAT Platform PLL supply ‐ Always ON G10 – AVDD_PLAT – AVDD_D1 DDR1 PLL supply ‐ Switchable E20 – AVDD_D1 – AVDD_SD1_PLL1 SerDes1 PLL 1 supply ‐ Switchable AB16 – AVDD_SD1_PLL1 – AVDD_SD1_PLL2 SerDes1 PLL 2 supply ‐ Switchable AB20 – AVDD_SD1_PLL2 – SENSEVDD Vdd Sense pin ‐ Switchable G19 – SENSEVDD – SENSEVDDC Vddc Sense pin ‐ Always ON AB9 – SENSEVDDC – USB_HVDD1 USB PHY Transceiver 3.3V Supply ‐ "Optionally Switchable or Always ON" J8 – USB_HV DD – USB_HVDD2 USB PHY Transceiver 3.3V Supply ‐ "Optionally Switchable or Always ON" K8 – USB_HV DD – USB_OVDD1 USB PHY Transceiver 1.8V Supply ‐ "Optionally Switchable or Always ON" J9 – USB_OV DD – USB_OVDD2 USB PHY Transceiver 1.8V Supply ‐ "Optionally Switchable or Always ON" J10 – USB_OV DD – USB_SVDD1 USB PHY Analog 1.0V Supply ‐ "Optionally Switchable or Always ON" K9 – USB_SV DD – USB_SVDD2 USB PHY Analog 1.0V Supply ‐ "Optionally Switchable or Always ON" K10 – USB_SV DD – No Connection Pins NC01 No Connection G17 – – – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Notes: 1. Functionally, this pin is an output or an input, but structurally it is an I/O because it either sample configuration input dur‐ ing reset, is a muxed pin, or has other manufacturing test functions. This pin is therefore be described as an I/O for boundary scan. 2. During reset this output signal is actively driven rather than being tri‐stated. 3. MDIC[0] is grounded through a 162 precision 1% resistor and MDIC[1] is connected to GV1DD through a 162 precision 1% resistor. For either full or half driver strength calibration of DDR IOs, use the same MDIC resistor value of 162. Mem‐ ory controller register setting can be used to determine automatic calibration is done to full or half drive strength. These pins are used for automatic calibration of the DDR3L/DDR4 IOs. The MDIC[0:1] pins must be connected to 162 precision 1% resistors. 4. This pin is a reset configuration pin. It has a weak (~20 k) internal pull‐up P‐FET that is enabled only when the processor is in its reset state. This pull‐up is designed such that it can be overpowered by an external 4.7 k resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull‐up or active driver is needed. NC02 No Connection L6 – – – NC03 No Connection M6 – – – NC04 No Connection M9 – – – NC05 No Connection N6 – – – NC06 No Connection P6 – – – NC07 No Connection P9 – – – NC08 No Connection R6 – – – NC09 No Connection T6 – – – NC10 No Connection T9 – – – NC11 No Connection U6 – – – NC12 No Connection V6 – – – NC13 No Connection V9 – – – NC14 No Connection W6 – – – NC15 No Connection Y6 – – – NC16 No Connection Y8 – – – NC17 No Connection Y9 – – – NC18 No Connection Y11 – – – NC19 No Connection AA6 – – – NC20 No Connection AA7 – – – NC21 No Connection AA8 – – – NC22 No Connection AA9 – – – NC23 No Connection AA10 – – – NC24 No Connection AB8 – – – NC25 No Connection AB11 – – – NC26 No Connection AB12 – – – NC_DET No Connection AG28 – – – NC_1040 No Connection AH27 – – – Table 2‐1. Pinout list by bus (Continued) Signal Signal description Package pin number Pin type Power supply Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 5. Pin must NOT be pulled down during power‐on reset. This pin may be pulled up, driven high, or if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external pull‐up is required to drive this pin to a safe state during reset. 6. Recommend that a weak pull‐up resistor (2‐10 k) be placed on this pin to the respective power supply. 7. This pin is an open‐drain signal. 8. Recommend that a weak pull‐up resistor (1 k) be placed on this pin to the respective power supply. 9. This pin has a weak (~20 k) internal pull‐up P‐FET that is always enabled. 10. These are test signals for factory use only and must be pulled up (100 to 1‐k) to the respective power supply for nor‐ mal operation. 11. This pin requires a 200 pull‐up to respective power‐supply. 12. Do not connect. These pins should be left floating. 13. 14. This pin requires an external 1‐k pull‐down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 15. These pins must be pulled to ground (GND). 16. This pin requires a 698 pull‐up to respective power‐supply. 17. This pin should be connected to ground through 2‐10k resistor when not used. 18. This pin should be connected to ground through 2‐10k resistor when SYSCLK input is used as system clock. 19. This pin should be tied to ground if the diode is not utilized for temperature monitoring. 20. This pin should be connected to GND through a 10k ± 1% resistor with a low temperature coefficient of = 25ppm/×C for bias generation 21. This pin has a weak (~20 k) internal pull‐up P‐FET that is enabled only when the processor is in its reset state. This pin should have an optional pull down resistor on board. This is required to support DIFF_SYSCLK/DIFF_SYSCLK_B 22. This pin should not be sampled until PORESET_B gets deasserted. 23. This pin must be pulled to O1VDD through a 100‐ohm to 1k‐ohm resistor for a 4 core T1042 and tied to ground for a 2 core T1022 device. 24. External “CLK12”pin is connected internally to both CLK12 and CLK8 pins of QE. 25. 26. PORESET_B should be asserted zero during the JTAG Boundary scan operation, and is required to be controllable on board. 27. This pin requires a pull‐up to the respective power supply so as to meet the timing requirements in Table 3‐20. Warning See Section 4.5 ”Connection recommendations” on page 154 for additional details on properly con‐ necting these pins for specific applications. 3. ELECTRICAL CHARACTERISTICS This section provides the AC and DC electrical specifications for the chip. The chip is currently targeted to these specifications, some of which are independent of the I/O cell but are included for a more com‐ plete reference. These are not purely I/O buffer design specifications.

3.1 Overall DC electrical characteristics

This section describes the ratings, conditions, and other characteristics.

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.1.1 Absolute maximum ratings

This table provides the absolute maximum ratings. Table 3‐1. Absolute maximum ratings(1) Characteristic Symbol Max Value Unit Notes Core and platform supply voltage V DD ‐0.3 to 1.1 V (9) Always ON supply voltage V DDC ‐0.3 to 1.1 V – PLL supply voltage (core PLL/eSDHC, platform, DDR) AVDD_CGA1 AVDD_CGA2 AVDD_PLAT AVDD_D1 PLL supply voltage (SerDes, filtered from X1VDD) AVDD_SD1_PLL1 AVDD_SD1_PLL2 ‐0.3 to 1.48 V – SFP fuse programming PROG_SFP ‐0.3 to 1.98 V – Thermal monitor unit supply TH_V DD ‐0.3 to 1.98 V – MPIC, GPIO, system control and power management, clocking, debug, IFC, DDRCLK supply, and JTAG I/O voltage OVDD O1VDD ‐0.3 to 1.98 V – DUART, I2C, DMA, TDM, QE, MPIC, DIU DV DD ‐0.3 to 2.75 ‐0.3 to 1.98 ‐0.3 to 3.63 eSPI, SDHC_WP , SDHC_CD, SDHC_DAT[4:7] CV DD ‐0.3 to 1.98 ‐0.3 to 3.63 V– eSDHC EV DD ‐0.3 to 1.98 ‐0.3 to 3.63 V– DDR4 and DDR3L DRAM I/O voltage DDR4 G1V DD ‐0.3 to 1.32 V – DDR3L ‐0.3 to 1.48 Main power supply for internal circuitry of SerDes and pad power supply for SerDes receivers S1VDD ‐0.3 to 1.1 V – Pad power supply for SerDes transmitter X1V DD ‐0.3 to 1.48 V – Ethernet interface 2, 1588, GPIO LV DD ‐0.3 to 1.98 ‐0.3 to 2.75 ‐0.3 to 3.63 Ethernet interface 1, Ethernet management interface 1 (EMI1), GPIO L1V DD ‐0.3 to 1.98 ‐0.3 to 2.75 ‐0.3 to 3.63 USB PHY Transceiver supply voltage USB_HV DD ‐0.3 to 3.63 V – USB_OVDD ‐0.3 to 1.98 V – USB PHY Analog supply voltage USB_SV DD ‐0.3 to 1.1 V – Input voltage DDR4 and DDR3L DRAM signals MV IN ‐0.3 to (G1VDD + 0.3) V (2) DDR4 and DDR3L DRAM reference D1_M VREF ‐0.3 to (G1VDD/2 + 0.3) V (5) Ethernet signals LVIN LV1IN ‐0.3 to (LnVDD + 0.3) V (4)(5) MPIC, GPIO, system control and power management, clocking, debug, IFC, DDRCLK supply, and JTAG I/O voltage OVIN O1VIN ‐0.3 to (OnVDD + 0.3) V (3)(5) eSDHC signals EV IN ‐0.3 to (EVDD + 0.3) V (7)(5) eSPI signals CV IN ‐0.3 to (CVDD + 0.3) V (8)(5)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Notes: 1. Functional operating conditions are given in Table 3‐2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause perma‐ nent damage to the device. 2. Caution: MVIN must not exceed G1VDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power‐on reset and power‐down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power‐on reset and power‐down sequences. 4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power‐ on reset and power‐down sequences. 5. (S,G,L,O,D,E,C)V IN, USBn_VIN_3P3, USBn_VIN_1P8 and Dn_MVREF may overshoot/undershoot to a voltage and for a maxi‐ mum duration as shown in Figure 3‐1. 6. Caution: DVIN must not exceed DVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power‐on reset and power‐down sequences. 7. Caution: EVIN must not exceed EVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power‐ on reset and power‐down sequences. 8. Caution: CVIN must not exceed CVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power‐ on reset and power‐down sequences. 9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the sense pin. 10. AVDD_PLAT, AVDD_CGA1, AVDD_CGA2 and AVDD_D1 are measured at the input to the filter (as shown in AN4825) and not at the pin of the device.

3.1.2 Recommended operating conditions

This table provides the recommended operating conditions for this chip. NOTE The values shown are the recommended operating conditions and proper device operation outside these conditions is not guaranteed. DUART, I2C, DMA, TDM, QE, MPIC, DIU DV IN ‐0.3 to (DVDD + 0.3) V (5)(6) SerDes signals S1V IN ‐0.4 to (S1VDD + 0.3) V (5) USB PHY Transceiver signals USB_HV IN ‐0.3 to (USB_HVDD + 0.3) V (5) USB_OVIN ‐0.3 to (USB_OVDD + 0.3) V (5) Storage temperature range TSTG ‐55 to 150 °C – Table 3‐1. Absolute maximum ratings(1) Characteristic Symbol Max Value Unit Notes Table 3‐2. Recommended operating conditions Characteristic Symbol Recommended Value Unit Status in Deep Sleep(6) Notes Core and platform supply voltage V DD 1.0 ± 30 mV V OFF (3)(4)(5) Always ON Core and Platform supply V DDC 1.0 ± 30 mV V ON (3)(4)(5) PLL supply voltage (core PLL/eSDHC, platform, DDR) AVDD_CGA1 1.8 V ± 90 mV V OFF – AVDD_CGA2 OFF AVDD_PLAT ON AVDD_D1 OFF

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] 2. PROG_SFP must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range only during secure boot fuse programming. For all other operating conditions, PROG_SFP must be tied to GND, subject to the power sequencing constraints shown in Power sequencing. 3. Refer to Core and platform supply voltage filtering for additional information. 4. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the sense pin. 5. Operation at 1.1V is allowable for up to 25ms at initial power on. 6. The Power supplies designated as OFF in this column should be switched OFF during Deep Sleep and those designated as ON should not be switched OFF. There are few power supplies which can be optionally switched OFF, for more details refer T1040 QorIQ Integrated Multicore Communications Processor Reference Manual. Warning When the device is in Deep Sleep mode, all external voltage supplies applied to any I/O pins, with the exception of wake‐up pins, must be turned off. Applying external voltage to any I/O pins, except the wake up pins, while the device is in Deep Sleep mode may cause permanent damage to the device. This figure shows the undershoot and overshoot voltages at the interfaces of the chip. PLL supply voltage (SerDes, filtered from X1VDD) AVDD_SD1_PLL1 AVDD_SD1_PLL2 1.35 V ± 67 mV V OFF – SFP fuse programming PROG_SFP 1.8 V ± 90 mV V ON (2) Thermal monitor unit supply TH_VDD 1.8 V ± 90 mV V OFF – IFC, GPIO, Trust, DDRCLK supply, RTC and JTAG I/O voltage OVDD 1.8 V ± 90 mV V OFF – MPIC, GPIO, system control, debug and SYSCLK supply O1VDD 1.8 V ± 90 mV V ON – DUART, I2C, DMA, MPIC, QE, TDM, DIU D VDD

2.5 V ± 125 mV

1.8 V ± 90 mV

3.3 V ± 165 mV

VO F F– eSPI, SDHC_WP , SDHC_CD, SDHC_DAT[4:7] CVDD

3.3 V ± 165mV

1.8 V ± 90mV VO F F–

3.3 V ±165 mV

1.8 V ± 90 mV VO F F–

DDR4 G1V DD 1.2V ± 60 mV V OFF – DDR3L 1.35 V ± 67 mV Main power supply for internal circuitry of SerDes and pad power supply for SerDes receivers S1VDD

1.0 V + 50 mV

1.0 V ‐ 30 mV VO F F–

Pad power supply for SerDes transmitters X1VDD 1.35 V ± 67 mV V OFF – Ethernet interface 2, 1588, GPIO LVDD VO F F (1) Table 3‐2. Recommended operating conditions (Continued) Characteristic Symbol Recommended Value Unit Status in Deep Sleep(6) Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 3‐1. Overshoot/Undershoot voltage for G1VDD/L1VDD/OVDD/SVDD/DVDD/CVDD/ LVDD/EVDD Notes: tCLOCK refers to the clock period associated with the respective interface: For I2C OVDD, tCLOCK references SYSCLK. For DDR GVDD, tCLOCK references Dn_MCLK. For eSPI OVDD, tCLOCK references SPI_CLK. For JTAG OVDD, tCLOCK references TCK. For SerDes SVDD, tCLOCK references SD_REF_CLK. For Ethernet LVDD, tCLOCK references ECn_GTX_CLK125. See Table 3‐2 for actual recommended core voltage. Voltage to the processor interface I/Os are pro‐ vided through separate sets of supply pins and must be provided at the voltages shown in Table 3‐2. The input voltage threshold scales with respect to the associated I/O supply voltage. DVDD, OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied Dn_MVREF signal (nominally set to G1VDD/2) as is appropriate for the SSTL_1.35/SSTL_1.2 electrical signaling stan‐ dard. The DDR MDQS receivers cannot be operated in single‐ended fashion. The complement signal must be properly driven and cannot be grounded. V IH Nominal D/S/G/L/OVDD + 20% V IL GND GND - 0.3 V GND - 0.7 V Not to exceed 10% of tCL OCK 1 D/S/G/L/O VDD + 5% D/S/G/L/OVDD Note: GND - 0.6 V for SerDes receiver inputs

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.1.3 Output driver characteristics

This chip provides information on the characteristics of the output driver strengths. NOTE These values are preliminary estimates. Notes: 1. The drive strength of the DDR4 or DDR3L interface in half‐strength mode is at Tj = 105 °C and at G1VDD (min). 2. Estimated number based on best case processed device. 3. Estimated number based on worst case processed device.

3.1.4 General AC timing specifications

This table provides AC timing specifications for the sections not covered under the specific interface sections. Note: 1. Rise time refers to signal transitions from 10% to 90% of Supply; fall time refers to transitions from 90% to 10% of supply Table 3‐3. Output drive capability Driver type Output impedance () Supply Voltage NotesMinimum(2) Typical Maximum (3) DDR4 signal – 18(full‐strength mode) 27(half‐strength mode) –G 1 V DD = 1.2V (1) DDR3L signal – 18(full‐strength mode) 27(half‐strength mode) –G 1 V DD = 1.35V (1) Ethernet signals 45 – 90 L1V DD / LVDD = 3.3V – 40 – 90 L1V DD / LVDD = 2.5V 40 – 75 L1V DD / LVDD = 1.8V MPIC, GPIO, system control and power management, clocking, debug, IFC,DDRCLK supply, and JTAG I/O voltage 23 – 51 OV DD, O1VDD = 1.8V – DUART, DMA, MPIC, QE, TDM, I2C, DIU 45 – 90 DV DD = 3.3V – 40 – 90 DV DD = 2.5V 40 – 75 DV DD = 1.8V eSPI, SDHC_WP , SDHC_CD 45 – 90 CV DD = 3.3V – 40 – 75 CV DD = 1.8V eSDHC 45 – 90 EV DD = 3.3V – 40 – 75 EV DD = 1.8V Table 3‐4. AC Timing specifications Parameter Symbol Min Max Unit Notes Input signal rise and fall times t R/tF – 5n s (1)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.2 Power sequencing

The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. Power up sequence when DDR3L is used 1. O1V DD, OVDD, DVDD, CVDD, EVDD, L1VDD, LVDD, TH_VDD, USB_HVDD, USB_OVDD, AVDD_CGA1, AVDD_CGA2, AVDD_PLAT, AVDD_D1. Drive PROG_SFP = GND a. PORESET_B should be driven asserted and held during this step. 2. V DDC, VDD, USB_SVDD, S1VDD a. When Deep Sleep is not used, it is recommended to source VDD and VDDC from same power supply. b. When Deep Sleep is used, VDDC should ramp up before VDD. Alternatively VDD may ramp up together with VDDC provided that the relative timing between VDDC and VDD ramp up con‐ forms to Figure 3‐2 3. G1V DD, X1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2 a. All supplies in Step 3 may be sourced from same supply Power up sequence when DDR4 is used 1. O1V DD, OVDD, DVDD, CVDD, EVDD, L1VDD, LVDD, TH_VDD, USB_HVDD, USB_OVDD, AVDD_CGA1, AVDD_CGA2, AVDD_PLAT, AVDD_D1, X1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2. Drive PROG_SFP = GND a. PORESET_B should be driven asserted and held during this step. 2. V DDC, VDD, USB_SVDD, S1VDD a. When Deep Sleep is not used, it is recommended to source VDD and VDDC from same power supply. b. When Deep Sleep is used, VDDC should ramp up before VDD. Alternatively VDD may ramp up together with VDDC provided that the relative timing between VDDC and VDD ramp up con‐ forms to Figure 3‐2 3. G1VDD The supplies mentioned as OFF in "Status in Deep Sleep" column of Table 3‐2 are switched ON while exit from Deep sleep power management mode. These supplies should also follow the same power up sequence as mentioned above. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. All supplies must be at their stable values within 75 ms. Negate PORESET_B input when the required assertion/hold time has been met per Table 3‐20. NOTE

• E V T 2 _ B may be unstable when PORESET_B is asserted. The signal should not be used to enable switchable power supplies during this period.
• R a m p rate requirements should be met per Table 3‐6.

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Warning Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary. This figure provides the VDDC and VDD ramp up diagram. Figure 3‐2. VDDC and VDD ramp up diagram For secure boot fuse programming, use the following steps: 1. After negation of PORESET_B, drive PROG_SFP = 1.8 V after a required minimum delay per Table 3‐5. 2. After fuse programming is completed, it is required to return PROG_SFP = GND before the sys‐ tem is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 3‐5. See Security fuse processor, for additional details. Warning No activity other than that required for secure boot fuse programming is permitted while PROG_SFP is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while PROG_SFP = GND. This figure provides the PROG_SFP timing diagram. NOTE: PROG_SFP must be stable at 1.8 V prior to initiating fuse programming. V DD V DDC 10 % 90% 90% 10 % T1 <= 1 us T2 <= 1 us

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 3‐3. PROG_SFP timing diagram NOTE: PROG_SFP must be stable at 1.8 V prior to initiating fuse programming This table provides information on the power ‐down and power ‐up sequence parameters for PROG_SFP. Notes: 1. Delay required from the deassertion of PORESET_B to driving PROG_SFP ramp up. Delay measured from PORESET_B deassertion at 90% OVDD to 10% PROG_SFP ramp up. 2. Delay required from fuse programming finished to PROG_SFP ramp down start. Fuse programming must complete while PROG_SFP is stable at 1.8V. No activity other than that required for secure boot fuse programming is permitted while PROG_SFP driven to any voltage above GND, including the read‐ ing of the fuse block. The reading of the fuse block may only occur while PROG_SFP = GND. After fuse programming is completed, it is required to return PROG_SFP = GND. 3. Delay required from PROG_SFP ramp down complete to VDD ramp down start. PROG_SFP must be grounded to minimum 10% PROG_SFP before VDD is at 90% VDD. 4. Delay required from PROG_SFP ramp down complete to PORESET_B assertion. PROG_SFP must be grounded to minimum 10% PROG_SFP before PORESET_B assertion reaches 90% OVDD. 5. Only two secure boot fuse programming events are permitted per lifetime of a device.

3.3 Power ‐down requirements

The power‐down cycle must complete such that power supply values are below 0.4 V before a new power‐up cycle can be started. If performing secure boot fuse programming per Power sequencing, it is required that PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 3‐5.

3.4 Power ‐on ramp rate

This section describes the AC electrical specifications for the power‐on ramp rate requirements. Con‐ trolling the maximum power‐on ramp rate is required to avoid excess in‐rush current. Table 3‐5. PROG_SFP timing(5) Driver type Min Max Unit Notes tPROG_SFP_DELAY 100 – SYSCLKs (1) tPROG_SFP_PROG 0 – µs (2) tPROG_SFP_VDD 0 – µs (3) tPROG_SFP_RST 0 – µs (4) PR OG_SFP V DD PORESET_B 90% OV DD Fuse pr ogramming tPR OG_SFP_PR OG tPR OG_SFP_DELA Y 10% PR OG_SFP tPR OG_SFP_R ST tPR OG_SFP_VDD 10% PR OG_SFP 90% V DD 90% OV DD

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This table provides the power supply ramp rate specifications. Notes: 1. Ramp rate is specified as a linear ramp from 10% to 90%. If non‐linear (for example, exponential), the maximum rate of change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry. 2. Over full recommended operating temperature range (see Table 3‐2).

3.5 Power characteristics

This table shows the power dissipations of the VDD and VDDC supply for various operating platform clock frequencies versus the core and DDR clock frequencies. Notes: 1. Combined power of VDDC, VDD and S1VDD with platform at power‐on reset default state, DDR controller and all SerDes banks active. Does not include I/O power. 2. Typical power assumes Dhrystone running with activity factor of 70% (on all cores) and is executing DMA on the platform with 100% activity factor. 3. Typical power based on nominal, processed device. 4. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and is executing DMA on the plat‐ form at 115% activity factor. Table 3‐6. Power supply ramp rate Parameter Min Max Unit Notes Required ramp rate for all voltage supplies (including OVDD/O1VDD/DVDD/ G1VDD/S1VDD/X1VDD/LVDD/L1VDD/EVDD/CVDD all core and platform VDD supplies, D1_MVREF and all AVDD supplies.) Required ramp rate for PROG_SFP – 25 V/ms (1)(2) Required ramp rate for USB_HVDD –2 6 . 7 V / m s (1)(2) Table 3‐7. T1042 core power dissipation Core freq (MHz) Platform freq (MHz) DDR data rate (MT/s) VDD, VDDC (V) S1V DD (V) Junction temp. (ºC) Power mode Power (W) Total Core and platform power (W)(1) NotesVDD VDDC S1VDD 105 Thermal 7.51 0.91 0.47 8.89 (5)(7) 125 Thermal 8.88 1.09 0.49 10.46 (5)(7) M a x i m u m9 . 6 31 . 0 90 . 4 9 1 1 . 2 1 (4)(6)(7) 105 Thermal 5.83 0.69 0.41 6.93 (5)(7) 125 Thermal 7.20 0.87 0.43 8.50 (5)(7) 105 Thermal 5.10 0.63 0.41 6.15 (5)(7) 125 Thermal 6.47 0.81 0.43 7.71 (5)(7)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 5. Thermal power assumes Dhrystone running with activity factor of 70% (on all cores) and executing DMA on the platform at 100% activity factor. 6. Maximum power is provided for power supply design sizing. 7. Thermal and maximum power are based on worst case processed device. Notes: 1. Combined power of VDDC, VDD and S1VDD with platform at power‐on reset default state, DDR controller and all SerDes banks active. Does not include I/O power. 2. Typical power assumes Dhrystone running with activity factor of 80% (on all cores) and is executing DMA on the platform with 100% activity factor. 3. Typical power based on nominal, processed device. 4. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and is executing DMA on the plat‐ form at 115% activity factor. 5. Thermal power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform at 100% activity factor. 6. Maximum power is provided for power supply design sizing. 7. Thermal and maximum power are based on worst case processed device. This table shows the power dissipation in deep sleep mode. Note: 1. V DD and S1VDD are switched off during deep sleep mode. Table 3‐8. T1022 core power dissipation Core freq (MHz) Platform freq (MHz) DDR data rate (MT/s) VDD, VDDC (V) S1 VDD (V) Junction temp. (ºC) Power mode Power (W) Total Core and platform power (W)(1) NotesVDD VDDC S1VDD 105 Thermal 6.00 0.91 0.47 7.38 (5)(7) 125 Thermal 7.37 1.09 0.49 8.95 (5)(7) 105 Thermal 4.63 0.69 0.41 5.73 (5)(7) 125 Thermal 6.00 0.87 0.43 7.30 (5)(7) 105 Thermal 4.01 0.63 0.41 5.05 (5)(7) 125 Thermal 5.38 0.81 0.43 6.62 (5)(7) Table 3‐9. Deep sleep power dissipation, 1.0V, 35°C Power (W) Total Core and platform power (W) VDD VDDC S1VDD ‐ 0.4 ‐ 0.4

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This table provides low power mode saving estimation. Notes: 1. Power for VDD only. 2. Typical power assumes Dhrystone running ( PH00 state) with activity factor of 70%. 3. Typical power based on nominal process distribution for this device. 4. PH10, PH15, LPM20 power savings with 1 core. Maximum savings would be N times, where N is the number of used cores. 5. LPM20 has all platform clocks disabled.

3.5.1 I/O DC power supply recommendation

This table provides the estimated I/O power numbers for each block: DDR, PCI Express, eLBC, eTSEC, SGMII, eSDHC, USB, eSPI, DUART, IIC, DIU, SATA and GPIO. Note that these numbers are based on design estimates only. Table 3‐10. Single core, Single cluster low power mode power savings, 1.0V 65°C(1)(2)(3) Mode Core Frequency = 1.0 GHz Core Frequency = 1.2 GHz Core Frequency = 1.4 GHz Core Frequency = 1.5 GHz Units Comment Notes PH10 0.19 0.23 0.27 0.29 Watts Saving realized moving from PH00 to PH10 state, single core. (4) PH15 0.19 0.23 0.27 0.29 Watts Saving realized moving from PH10 state to PH15 state, single core. (4) LPM20 0.32 0.38 0.45 0.48 Watts Saving realized moving from PH15 to LPM20, single core (4)(5) Table 3‐11. I/O power supply estimated values Interface Parameter Symbol Typical Maximum Deep Sleep Unit Note DDR3L 1600MT/s data rate G1VDD(1.35V) 860 1760 – mW (1)(2)(6) DDR4 1600MT/s data rate G1VDD(1.2V) 660 1000 – mW (1)(8)(9) PCI Express 1x, 2.5 GT/s X1VDD(1.35V) 50 62 – mW (1)(4)(7) 2x, 2.5 GT/s 81 94 4x, 2.5 GT/s 145 158 8x, 2.5 GT/s 274 287 1x, 5 GT/s 50 70 2x, 5 GT/s 90 100 4x, 5 GT/s 150 160 8x, 5 GT/s 280 290 SGMII 1x, 1.25 G‐baud X1VDD(1.35V) 50 60 – mW (1)(4)(7) 2x, 1.25 G‐baud 70 90 4x, 1.25 G‐baud 130 140 SGMII 1x, 3.125 G‐baud X1VDD(1.35V) 50 60 – mW (1)(4)(7) 2x, 3.125 G‐baud 80 90 SATA 1x, 3.0 Gbps X1VDD(1.35V) 50 60 – mW (1)(4)(7) 2x, 3.0 Gbps 70 80 IFC 16 ‐bit, 100MHz OVDD(1.8V) 35 61 – mW (1)(3)(7) EC1 RGMII L1VDD(2.5V) 155 220 13 mW (1)(3)(7)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Notes: 1. The typical values are estimates based on simulations 65ºC junction temperature. 2. Typical DDR power numbers are based on 2 Rank DIMM with 40% utilization. 3. Assuming 15 pF total capacitance load per pin. RGMII L1VDD(1.8V) 115 180 11 mW (1)(3)(7) MII L1VDD(3.3V) 155 220 18 mW (1)(3)(7) EC2 RGMII LVDD(2.5V) 155 220 – mW (1)(3)(7) RGMII LVDD(1.8V) 115 180 – eSDHC EVDD(3.3V) 11 17 – mW (1)(3)(7) EVDD(1.8V) 7 10 – USB1, USB2 USB_HVDD(3.3V) 40 60 60 mW (1)(3)(7) USB_OVDD(1.8V) 100 110 100 eSPI CVDD(3.3V) 14 22 – mW (1)(3)(7) CVDD(1.8V) 11 16 – DIU DVDD(3.3V) 70 90 – mW (1)(3)(7) QE DVDD(3.3V) 15 21 – mW (1)(3)(7) DVDD(2.5V) 11 17 – I2C DVDD(3.3V) 14 22 – mW (1)(3)(7) DVDD(2.5V) 10 16 – DVDD(1.8V) 8 13 – DUART DVDD(3.3V) 14 22 – mW (1)(3)(5)(7) DVDD(2.5V) 10 15 – DVDD(1.8V) 8 12 – TDM DVDD(3.3V) 10 14 – mW (1)(3)(7) IEEE1588 LVDD(2.5V) 16 21 – mW (1)(3)(7) GPIO x8 3.3V 5 8 – mW (1)(3)(7) x8 2.5V 4 7 – x8 1.8V 3 5 – System Control O1VDD(1.8V) 45 70 9 mW (1)(3)(7) PLL core and system AVDD_CGA1 (1.8V) 20 20 – mW (1)(3)(7) AVDD_CGA2 (1.8V) – AVDD_PLAT(1.8V) 2 PLL DDR AVDD_D1(1.8V) 30 40 – mW (1)(3)(7) PLL SerDes AVDD_SD1_PLL1, AVDD_SD1_PLL2(1.35V) 50 50 – mW (1)(3)(7) PROG_SFP PROG_SFP (1.8V) 173 – mW – TH_VDD TH_VDD (1.8V) 1 – mW – Table 3‐11. I/O power supply estimated values (Continued) Interface Parameter Symbol Typical Maximum Deep Sleep Unit Note

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] 4. The total power numbers of X1VDD is dependent on customer application use case. This table lists all the SerDes configu‐ rations possible for the device. To get the X1VDD power numbers, the user should add the combined lanes to match to the total SerDes Lanes used, not simply multiply the power numbers by the number of lanes. 5. GPIO are supported on OVDD , O1VDD , L1VDD , LVDD , DVDD , CVDD and EVDD power rails. 6. Maximum DDR power numbers are based on 2 Ranks DIMM with 100% utilization. 7. The maximum values are dependent on actual use case such as what application, external components used, environ‐ mental conditions such as temperature voltage and frequency. This is not intended to be the maximum guaranteed power. Expect different results depending on the use case.The maximum values are estimated and they are based on sim‐ ulations at 105ºC junction temperature. 8. Typical DDR4 power numbers are based on single Rank DIMM with 40% utilization. 9. Maximum DDR4 power numbers are based on single Rank DIMM with 100% utilization.

3.6 Input clocks

3.6.1 System clock (SYSCLK) timing specifications

This section provides the system clock DC and AC timing specifications.

3.6.1.1 System clock DC timing specifications

This table provides the system clock (SYSCLK) DC specifications. Notes: 1. The min VIL and max VIH values are based on the respective min and max O1VIN values found in Table 3‐2. 2. The symbol OVIN, in this case, represents the O1VIN symbol referenced in Recommended operating conditions. 3. At recommended operating conditions with O1VDD = 1.8V, see Table 3‐2.

3.6.1.2 System clock AC timing specifications

This table provides the system clock (SYSCLK) AC timing specifications. Table 3‐12. SYSCLK DC electrical characteristics(3) Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 1.2 –– V (1) Input low voltage V IL –– 0.6 V (1) Input capacitance CIN – 71 2 p F – Input current (O1VIN = 0V or O1VIN = O1VDD ) IIN –– ± 50 µA (2) Table 3‐13. SYSCLK AC timing specifications(1) Parameter/condition Symbol Min Typ Max Unit Notes SYSCLK frequency fSYSCLK 64.0 – 133.3 MHz (2)(5) SYSCLK cycle time tSYSCLK 7.5 – 15.6 ns (1)(2) SYSCLK duty cycle tKHK/tSYSCLK 40 – 60 % (2) SYSCLK slew rate – 1 – 4V / n s (3) SYSCLK peak period jitter ––– ± 150 ps – SYSCLK jitter phase noise at –56 dBc ––– 500 KHz (4) AC Input Swing Limits at 1.8V O1VDD VAC 1.08 – 1.8 V –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Notes: 1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency does not exceed their respective maximum or minimum operating frequencies. 2. Measured at the rising edge and/or the falling edge at O1VDD /2 . 3. Slew rate as measured from 0.35 × O1VDD to 0.65 × O1VDD . 4. Phase noise is calculated as FFT of TIE jitter. 5. At recommended operating conditions with O1VDD = 1.8V, see Table 3‐2.

3.6.2 Spread ‐spectrum sources

Spread‐spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise mag‐ nitude in order to meet industry and government requirements. These clock sources intentionally add long‐term jitter to diffuse the EMI spectral content. The jitter specification given in Table 3‐13 considers short‐term (cycle‐to‐cycle) jitter only. The clock generator's cycle‐to‐cycle output jitter should meet the chip's input cycle‐to‐cycle jitter requirement. Frequency modulation and spread are separate concerns; the chip is compatible with spread‐spectrum sources if the recommendations listed in Table 3‐13 are observed. Notes: 1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and maximum specifications given in Table 3‐13. 2. Maximum spread‐spectrum frequency may not result in exceeding any maximum operating frequency of the device. 3. At recommended operating conditions with O1VDD = 1.8V, see Table 3‐2. CAUTION The processor's minimum and maximum SYSCLK and core/ platform/DDR frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated core/platform/DDR frequency should avoid violating the stated limits by using down‐spreading only.

3.6.3 Real ‐time clock timing

The real‐time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum period of the RTC signal should be greater than or equal to 16x the period of the platform clock with a 50% duty cycle. There is no minimum RTC frequency; RTC may be grounded if not needed. Table 3‐14. Spread‐spectrum clock source recommendations(3) Parameter Min Max Unit Notes Frequency modulation – 60 kHz – Frequency spread – 1.0 % (1)(2)

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.6.4 Gigabit Ethernet reference clock timing

This table provides the Ethernet gigabit reference clock DC specifications. Notes: 1. At recommended operating conditions with L1VDD /LVDD = 1.8V 2. The min VIL and max VIH values are based on the respective min and max VIN values found in Table 3‐2. 3. The symbol VIN, in this case, represents the L1VIN/LVIN symbol referenced in Recommended operating conditions. 4. ECn_GTX_CLK125 is powered by L1VDD and LVDD. VDD should be replaced by the respective IO power supply. This table provides the Ethernet gigabit reference clock DC specifications. Notes: 1. At recommended operating conditions with L1VDD /LVDD = 2.5V 2. The min VIL and max VIH values are based on the respective min and max VIN values found in Table 3‐2. 3. The symbol VIN, in this case, represents the L1VIN/LVIN symbol referenced in Recommended operating conditions. 4. ECn_GTX_CLK125 is powered by L1VDD and LVDD. VDD should be replaced by the respective IO power supply. This table provides the Ethernet gigabit reference clocks AC timing specifications. Notes: 1. At recommended operating conditions with L1/LVDD = 1.8V ± 90mV / 2.5V ± 125 mV. 3. EC n_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter. See RGMII AC timing specifications for duty cycle for 10Base‐T and 100Base‐T reference clock. Table 3‐15. ECn_GTX_CLK125 DC electrical characteristics (L1VDD/LVDD=1.8V) Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 0.7 * VDD –– V (2)(4) Input low voltage VIL –– 0.2 * VDD V (2)(4) Input capacitance CIN –– 6p F – Input current (VIN = 0V or VIN = L1VDD)/LVDD) IIN –– ± 50 µA (3) Table 3‐16. ECn_GTX_CLK125 DC electrical characteristics ((L1VDD/LVDD=2.5V) Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 0.7 * VDD –– V (2)(4) Input low voltage VIL –– 0.2 * VDD V (2)(4) Input capacitance CIN –– 6p F – Input current (VIN = 0V or VIN = L1VDD)/LVDD) IIN –– ± 50 µA (3) Table 3‐17. ECn_GTX_CLK125 AC timing specifications (1) Parameter/Condition Symbol Min Typical Max Unit Notes ECn_GTX_CLK125 frequency tG125 125 – 100 ppm 125 125 + 100 ppm MHz – ECn_GTX_CLK125 cycle time tG125 – 8 – ns – ECn_GTX_CLK125 rise and fall time L1/LVDD = 1.8V L1/LVDD = 2.5V tG125R/tG125F –– 0.54 0.75 ns (2) ECn_GTX_CLK125 duty cycle 1000Base–T for RGMII tG125H/tG125 40 – 60 % (3) ECn_GTX_CLK125 jitter –– – ± 150 ps (3)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.6.5 DDR clock timing

This section provides the DDR clock DC and AC timing specifications.

3.6.5.1 DDR clock DC timing specifications

This table provides the DDR clock (DDRCLK) DC specifications. Notes: 1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3‐2. 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions. 3. At recommended operating conditions with OVDD = 1.8V, see Table 3‐2.

3.6.5.2 DDR clock AC timing specifications

This table provides the DDR clock (DDRCLK) AC timing specifications. Notes: 1. Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequency does not exceed their respective maximum or minimum operating frequencies. 2. Measured at the rising edge and/or the falling edge at OVDD/2 . 3. Slew rate as measured from 0.35 × OVDD to 0.65 × OVDD. 4. Phase noise is calculated as FFT of TIE jitter. 5. At recommended operating conditions with OVDD = 1.8V, see Table 3‐2. Table 3‐18. DDRCLK DC electrical characteristics(1) Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 1.25 –– V (1) Input low voltage VIL –– 0.6 V (1) Input capacitance CIN – 71 2 p F – Input current (OVIN = 0V or OVIN = OVDD) IIN –– ±50 µA (2) Table 3‐19. DDRCLK AC timing specifications(5) Parameter/Condition Symbol Min Typ Max Unit Notes DDRCLK frequency fDDRCLK 64.0 – 133.3 MHz (1)(2) DDRCLK cycle time tDDRCLK 7.5 – 15.6 ns (1)(2) DDRCLK duty cycle tKHK/tDDRCLK 40 – 60 % (2) DDRCLK slew rate – 1 – 4V / n s (3) DDRCLK peak period jitter –– – ± 150 ps – DDRCLK jitter phase noise at –56 dBc –– – 500 KHz (4) AC Input Swing Limits at 1.8V OVDD VAC 1.08 – 1.8 V –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.6.6 Differential System clock (DIFF_SYSCLK/DIFF_SYSCLK_B) timing specifications

"Single Oscillator Source" clocking mode requires single onboard oscillator to provide reference clock input to Differential System clock pair (DIFF_SYSCLK/ DIFF_SYSCLK_B). This Differential clock pair can be configured to provide clock to Core, Platform, DDR and USB PLL's This figure shows a receiver reference diagram of the Differential System clock. Figure 3‐4. LVDS receiver This section provides the differential system clock DC and AC timing specifications.

3.6.6.1 Differential System clock DC timing specifications

For DC timing specification, see DC‐level requirement for SerDes reference clocks The Differential System clock receivers core power supply voltage requirements (O1VDD) are as speci‐ fied in Recommended operating conditions. The Differential system clock can also be single‐ended. For this DIFF_SYSCLK_B should be connected to O1VDD/2.

3.6.6.2 Differential System clock AC timing specifications

Differential System clock (DIFF_SYSCLK/DIFF_SYSCLK_B) input pair supports input clock frequency of 100MHz For AC timing specification, see AC requirements for SerDes reference clocks Spread Spectrum clocking is not supported on Differential System clock pair input.

3.6.7 Other input clocks

A description of the overall clocking of this device is available in the chip reference manual in the form of a clock subsystem block diagram. For information about the input clock requirements of functional modules sourced external of the chip, such as SerDes, Ethernet management, eSDHC, IFC, see the spe‐ cific interface section. DIFF_SYSCLK DIFF_SYSCLK_B

100 Ohm LVDS

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3.7 RESET initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements. This table describes the AC electrical specifications for the RESET initialization timing. Notes: 1. PORESET_B must be driven asserted before the core and platform power supplies are powered up. 2. SYSCLK is the primary clock input for the chip. 3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power‐on reset process. The 4. device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is documented in section "Power‐On Reset Sequence" in the chip reference manual. 5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. This table provides the PLL lock times.

3.8 DDR4 and DDR3L SDRAM controller

This section describes the DC and AC electrical specifications for the DDR4 and DDR3L SDRAM control‐ ler interface. Note that the required G1VDD(typ) voltage is 1.2V when interfacing to DDR4 SDRAM and the G1VDD(typ) voltage is 1.35V when interfacing to DDR3L SDRAM. Table 3‐20. RESET Initialization timing specifications Parameter/Condition Min Max Unit Notes Required assertion time of PORESET_B 1 – ms (1) Required input assertion time of HRESET_B 32 – SYSCLKs (2)(3) Maximum rise/fall time of HRESET_B – 10 SYSCLK (4) Maximum rise/fall time of PORESET_B – 1S Y S C L K (4) PLL input setup time with stable SYSCLK before HRESET_B negation 100 – µs – Input setup time for POR configs with respect to negation of PORESET_B 4 – SYSCLKs (2) Input hold time for all POR configs with respect to negation of PORESET_B 2 – SYSCLKs (2) Maximum valid‐to‐high impedance time for actively driven POR configs with respect to negation of PORESET_B – 5S Y S C L K s (2) Table 3‐21. PLL lock times Parameter/Condition Min Max Unit Notes PLL lock times (Core, platform, DDR only) – 100 µs –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.8.1 DDR4 and DDR3L SDRAM interface DC electrical characteristics

This table provides the recommended operating conditions for the DDR SDRAM controller when inter‐ facing to DDR3L SDRAM. Notes: 1. G1V DD is expected to be within 50 mV of the DRAM's voltage supply at all times. The voltage supply of DRAM and memory controller may or may not be from the same source. 2. D1_MV REF is expected to be equal to 0.5 × G1VDD and to track G1VDD DC variations as measured at the receiver. Peak‐ to‐ peak noise on D1_MVREF may not exceed the D1_MVREF DC level by more than ±1% of G1VDD (that is, ±13.5mV). 3. V TT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to D1_MVREF with a min value of D1_MVREF ‐ 0.04 and a max value of D1_MVREF + 0.04. VTT should track variations in the DC level of D1_MVREF . 4. The voltage regulator for D1_MVREF must meet the specifications stated in Table 3‐24. 5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models. 6. Output leakage is measured with all outputs disabled, 0V VOUT G1VDD. 7. See the IBIS model for the complete output IV curve characteristics. 8. I OH and IOL are measured at G1VDD = 1.283V. 9. For recommended operating conditions, see Table 3‐2. This table provides the recommended operating conditions for the DDR SDRAM controller when inter‐ facing to DDR4 SDRAM. Notes: 1. G1V DD is expected to be within 60 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's voltage supply may or may not be from the same source. 2. VTT and VREFCA are applied directly to the DRAM device. Both VTT and VREFCA voltages must track G1VDD/ 2. 3. Input capacitance load for MDQ, MDQS, and MDQS_B are available in the IBIS models. 4. I OH and IOL are measured at G1VDD = 1.14V. 5. Refer to the IBIS model for the complete output IV curve characteristics. Table 3‐22. DDR3L SDRAM interface DC electrical characteristics (G1VDD = 1.35V)(1)(9) Parameter Symbol Min Max Unit Note I/O reference voltage D1_MV REF 0.49 × G1VDD 0.51 × G1VDD V (2)(3)(4) Input high voltage VIH D1_MVREF + 0.090 G1V DD V (5) Input low voltage VIL GND D1_MV REF – 0.090 V (5) I/O leakage current IOZ –100 100 µA (6) Output high current (VOUT = 0.641V) I OH – –23.3 mA (7)(8) Output low current (VOUT =0.641V) IOL 23.3 – mA (7)(8) Table 3‐23. DDR4 SDRAM interface DC electrical characteristics (G1VDD = 1.2V)(1)(8) Parameter Symbol Min Max Unit Note Input low VIL – 0.7 × G1VDD – 0.175 V (3)(7) Input high VIH 0.7 × G1VDD + 0.175 – V (3)(7) Output high current (VOUT = 0.57V) I OH – –20.7 mA (4)(5) Output low current (VOUT =0.57V) IOL 20.7 – mA (4)(5) I/O leakage current IOZ –100 100 µA (6)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 6. Output leakage is measured with all outputs disabled, 0V VOUT G1VDD. 7. Internal Vref for data bus must be set to 0.7 × G1VDD. 8. For recommended operating conditions, see Table 3‐2. This table provides the current draw characteristics for D1_MVREF. Note: 1. For recommended operating conditions, see Table 3‐2.

3.8.2 DDR4 and DDR3L SDRAM interface AC timing specifications

This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports DDR4 and DDR3L memories. Note that the required G1VDD(typ) voltage is 1.35V or 1.2V when interfacing to DDR3L or DDR4 SDRAM respectively.

3.8.2.1 DDR4 and DDR3L SDRAM interface input AC timing specifications

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM. Note: 1. For recommended operating conditions, see Table 3‐2. This table provides the input AC timing specifications for the DDR controller when interfacing to DDR4 SDRAM. Note: 1. For recommended operating conditions, see Table 3‐2. Table 3-24. Current draw characteristics for D1_MV REF 1 Parameter Symbol Min Max Unit Notes Current draw for DDR3L SDRAM for D1_MVREF ID1_MVREF – 500 µA – Table 3‐25. DDR3L SDRAM interface input AC timing specifications1 Parameter Symbol Min Max Unit Notes AC input low voltage > 1200 MT/s data rate VILAC – D1_MVREF‐ 0.135 V – 1200 MT/s data rate D1_MVREF ‐ 0.160 AC input high voltage > 1200 MT/s data rate VIHAC D1_MVREF+ 0.135 – V – 1200 MT/s data rate D1_MVREF+ 0.160 Table 3‐26. DDR4 SDRAM interface input AC timing specifications1 Parameter Symbol Min Max Unit Notes AC input low voltage 1600 MT/s data rate VILAC – 0.7 × G1VDD – 0.175 V – AC input high voltage 1600 MT/s data rate VIHAC 0.7 × G1VDD + 0.175 – V –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L and DDR4 SDRAM. Notes: 1. t CISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This must be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be deter‐ mined by the following equation: tDISKEW = ±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 3. For recommended operating conditions, see Table 3‐2. 4. DDR3L only This figure shows the DDR4 and DDR3L SDRAM interface input timing diagram. Figure 3‐5. DDR4 and DDR3L SDRAM Interface Input Timing Diagram Table 3‐27. DDR4 and DDR3L SDRAM interface input AC timing specifications(3) Parameter Symbol Min Max Unit Notes Controller Skew for MDQS‐MDQ/MECC tCISKEW ps

1600 MT/s data rate –112 112 (1)

1300 MT/s data rate –125 125 (1)

1200 MT/s data rate –142 142 (1)(4)

1000 MT/s data rate –170 170 (1)(4)

Tolerated Skew for MDQS‐MDQ/MECC tDISKEW ps

1600 MT/s data rate –200 200 (2)

1300 MT/s data rate –250 250 (2)

1200 MT/s data rate –275 275 (2)(4)

1000 MT/s data rate –300 300 (2)(4)

MCK[n]_B MCK[n] MDQS[n] MDQ[x] tDISKEW tDISKEW tDISKEW D0 D1

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.8.2.2 DDR4 and DDR3L SDRAM interface output AC timing specifications

This table contains the output AC timing targets for the DDR4 SDRAM interface. Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals. 3. ADDR/CMD/CNTL includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of the tim‐ ing modifications enabled by the use of these bits. 5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization. 6. DDR3L only Table 3‐28. DDR4 and DDR3L SDRAM interface output AC timing specifications(8) Parameter Symbol (1) Min Max Unit Notes MCK[n] cycle time tMCK 1250 1876 ps (2) ADDR/CMD output setup with respect to MCK tDDKHAS ps

1600 MT/s data rate 495 – (3)

1300 MT/s data rate 606 – (3)

1200 MT/s data rate 675 – (3)(6)

1000 MT/s data rate 744 – (3)(6)

ADDR/CMD output hold with respect to MCK tDDKHAX ps MCK to MDQS Skew tDDKHMH ps (4) > 1000 MT/s data rate, = 1600 MT/s data rate –245 245 (7) MDQ/MECC/MDM output Data eye tDDKXDEYE ps

1600 MT/s data rate 400 – (5)

1300 MT/s data rate 500 – (5)

1200 MT/s data rate 550 – (5)(6)

1000 MT/s data rate 600 – (5)(6)

MDQS preamble tDDKHMP 900 × tMCK –p s– MDQS postamble tDDKHME 400 × tMCK 600 × tMCK ps –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] 7. Note that it is required to program the start value of the MDQS adjust for write leveling. 8. For recommended operating conditions, see Table 3‐2. NOTE For the ADDR/CMD/CNTL setup and hold specifications in Table 3‐28, it is assumed that the clock control register is set to adjust the memory clocks by ½ applied cycle. This figure shows the DDR4 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 3‐6. tDDKHMH timing diagram tMCK MCK[n]_B MCK[n] MDQS MDQS tDDKHMH(max) tDDKHMH(min)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This figure shows the DDR4 and DDR3L SDRAM output timing diagram. Figure 3‐7. DDR4 and DDR3L output timing diagram 3.9 eSPI interface This section describes the DC and AC electrical specifications for the eSPI interface. 3.9.1 eSPI DC electrical characteristics This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 1.8V. Notes: 1. For recommended operating conditions, see Table 3‐2. 2. The min VIL and max VIH values are based on the respective min and max CVIN values found in Table 3‐2. 3. The symbol VIN, in this case, represents the CVIN symbol referenced in Recommended operating conditions. tMCK MCK_B MCK MDQS[n] MDQ[x] tDDKXDEYE tDDKXDEYE D0 D1 tDDKHMH tDDKHME tDDKHMP ADDR/CMD Write A0 NOOP tDDKHAS tDDKHAX Table 3‐29. eSPI DC electrical characteristics (1.8V)1 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * CVDD – V2 Input low voltage VIL – 0.2 * CVDD V 2 Input current (VIN = 0V or VIN = CVDD) IIN – ±50 µA 3 Output high voltage (CVDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (CVDD = min, IOL = 0.5 mA) VOL – 0.4 V –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 3.3V. Notes: 1. For recommended operating conditions, see Table 3‐2. 2. The min VIL and max VIH values are based on the respective min and max CVIN values found in Table 3‐2. 3.9.2 eSPI AC timing specifications This table provides the eSPI input and output AC timing specifications. Notes: 1. See the chip reference manual for details about the SPMODE register. 2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 3. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V). 4. Refer AN4375 to calculate maximum achievable eSPI interface frequency on a system. This figure provides the AC test load for the eSPI. Table 3‐30. eSPI DC electrical characteristics (3.3V)1 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * CVDD – V2 Input low voltage VIL – 0.2 * CVDD V 2 Input current (VIN = 0V or VIN = CVDD) IIN – ±50 µA – Output high voltage (CVDD = min, IOH = –2.0 mA) VOH 2.4 – V – Output low voltage (CVDD = min, IOL = 2.0 mA) VOL – 0.4 V – Table 3‐31. eSPI AC timing specifications(3) Parameter/Condition Symbol (2) Min Max Unit Notes SPI_MOSI output‐Master data (internal clock) hold time tNIKHOX –0.49 + (tPLATFORM_CLK/ 2 * SPMODE[HO_ADJ]) –n s (1)(2) SPI_MOSI output‐Master data (internal clock) delay tNIKHOV – 0.89 + (tPLATFORM_CLK/ 2 * SPMODE[HO_ADJ]) ns (1)(2) SPI_CS outputs‐Master data (internal clock) hold time tNIKHOX2 –100 – ps (1) SPI_CS outputs‐Master data (internal clock) delay tNIKHOV2 –6 . 0 n s (1) SPI inputs‐Master data (internal clock) input setup time tNIIVKH 6.6 – ns – SPI inputs‐Master data (internal clock) input hold time tNIIXKH 0– n s – Clock‐high time tNIKCKH 4– n s Clock–low time tNIKCKL 4– n s –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 3‐8. eSPI AC test load This figure provides the eSPI clock output timing diagram. Figure 3‐9. eSPI clock output timing diagram Note: 1. SPICLK appears on the interface only after CS assertion. This figure represents the AC timing from Table 3‐30 in master mode (internal clock). Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Also, note that the clock edge is selectable on eSPI. Figure 3‐10. eSPI AC timing in master mode (internal clock) diagram

3.10 DUART interface

This section describes the DC and AC electrical specifications for the DUART interface. Output Z0= 50Ω RL = 50Ω CVDD/2 eSPI clock tNIKCKH tNIKCKL VOH VOL SPICLK (output)1 tNIIXKH tNIKHOV Input Signals: Output Signals: tNIIVKH tNIKHOX Output Signals: SPI_CS[0:3] 1 tNIKHOV2 tNIKHOX2

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.10.1 DUART DC electrical characteristics

This table provides the DC electrical characteristics for the DUART interface at DVDD = 3.3V. Notes: 1. The min VIL and max VIH values are based on the min and max DVIN respective values found in Table 3‐ 2. The symbol DVIN represents the input voltage of the supply. It is referenced in Recommended operat‐ ing conditions. 3. For recommended operating conditions, see Table 3‐2. 4. VDD should be replaced by the respective IO power supply. This table provides the DC electrical characteristics for the DUART interface at DVDD = 2.5V. Notes: 1. The min VIL and max VIH values are based on the min and max DVIN respective values found in Table 3‐ 2. The symbol DVIN represents the input voltage of the supply. It is referenced in Recommended operat‐ ing conditions. 3. For recommended operating conditions, see Table 3‐2. 4. VDD should be replaced by the respective IO power supply. Table 3‐32. DUART DC electrical characteristics (3.3V)(3) Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7*VDD – V (1)(4) Input low voltage VIL –0 . 2 * V D DV (1)(4) Input current (VIN = 0V or VIN = DVDD) IIN –± 5 0 µ A (3) Output high voltage VOH 2.4 – V – (DVDD = min, IOH = –2.0 mA) Output low voltage VOL –0 . 4V – (DVDD = min, IOL = 2.0 mA) Table 3‐33. DUART DC electrical characteristics(2.5V)(3) Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7*VDD – V (1)(4) Input low voltage VIL –0 . 2 * V D DV (1)(4) Input current (DVIN = 0V or DVIN= DVDD) IIN –± 5 0 µ A (2) Output high voltage (DVDD = min, IOH = –1 mA) VOH 2.0 – V – Output low voltage (DVDD = min, IOL= 1 mA) VOL –0 . 4V –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This table provides the DC electrical characteristics for the DUART interface at DVDD = 1.8V. Notes: 1. The min VIL and max VIH values are based on the min and max DVIN respective values found in Table 3‐ 2. The symbol DVIN represents the input voltage of the supply.It is referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. 4. VDD should be replaced by the respective IO power supply.

3.10.2 DUART AC electrical specifications

This table provides the AC timing parameters for the DUART interface. Notes: 1. f PLAT refers to the internal platform clock. 2. The actual attainable baud rate is limited by the latency of interrupt processing. 3. The middle of a start bit is detected as the eighth sampled 0 after the 1‐to‐0 transition of the start bit. Subsequent bit values are sampled each 16th sample.

3.11 Ethernet interface, Ethernet management interface, IEEE Std 1588™

This section provides the AC and DC electrical characteristics for the Ethernet controller and the Ether‐ net management interface.

3.11.1 SGMII interface

Each SGMII port features a 4‐wire AC‐coupled serial link from the SerDes interface of the chip, as shown in Figure 3‐11, where CTX is the external (on board) AC‐coupled capacitor. Each SerDes transmit‐ ter differential pair features 100‐ output impedance. Each input of the SerDes receiver differential pair features 50‐ on‐die termination to XGNDn. The reference circuit of the SerDes transmitter and receiver is shown in Figure 3‐62.

3.11.1.1 SGMII clocking requirements for SD1_REF_CLKn_P and SD1_REF_CLKn_N

When operating in SGMII mode, the ECn_GTX_CLK125 clock is not required for this port. Instead, a Ser‐ Des reference clock is required on SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N pins. SerDes lanes may be used for SerDes SGMII configurations based on the RCW Configuration field SRDS_PRTCL. For more information on these specifications, see SerDes reference clocks. Table 3‐34. DUART DC electrical characteristics(1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7*VDD – V 1, 4 Input low voltage VIL –0 . 2 * V D DV 1 , 4 Input current (DVIN = 0V or DVIN= DVDD) IIN –± 5 0 µ A 2 Output high voltage (DVDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (DVDD = min, IOL= 0.5 mA) VOL –0 . 4V – Table 3‐35. DUART AC timing specifications Parameter Value Unit Notes Minimum baud rate f PLAT/(2 × 1,048,576) baud 1, 3 Maximum baud rate f PLAT/(2 × 16) baud 1, 2

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.11.1.2 SGMII DC electrical characteristics

This section discusses the electrical characteristics for the SGMII interface. This table describes the SGMII SerDes transmitter AC‐coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD1_TXn_P and SD1_TXn_N)as shown in Figure 3‐12. Notes: 1. This does not align to DC‐coupled SGMII. 2. I VOD I = I VSD_TXn_P – VSD_TXn_N I. I VOD I is also referred to as output differential peak voltage. VTX‐DIFFp‐p = 2 × I VOD I. 3. The I VOD I value shown in the Typ column is based on the condition of XVDD_SRDSn‐Typ = 1.35V, no common mode offset variation. SerDes transmitter is terminated with 100‐ differential load between SDn _TXn_P and SDn_TXn_N. 4. For recommended operating conditions, see Table 3‐2. 5. Example amplitude reduction setting for SGMII on SerDes1 lane E: SRDS1LN4TECR0[AMP_RED] = 0b000001 for an output differential voltage of 459 mV typical. Table 3‐36. SGMII DC transmitter electrical characteristics (X1VDD = 1.35V)(4) Parameter Symbol Min Typ Max Unit Notes Output high voltage V OH –– 1 . 5 × I VOD I –max mV (1) Output low voltage V OL I VOD I –min/2 – – m V (1) Output differential voltage(2)(3)(5) (XVDD‐Typ at 1.35V) I VOD I 320 500.0 725.0 mV TECR0[AMP_RED]=0b00 0000 293.8 459.0 665.6 TECR0[AMP_RED]=0b00 0001 266.9 417.0 604.7 TECR0[AMP_RED]=0b00 0011 240.6 376.0 545.2 TECR0[AMP_RED]=0b00 0010 213.1 333.0 482.9 TECR0[AMP_RED]=0b00 0110 186.9 292.0 423.4 TECR0[AMP_RED]=0b00 0111 160.0 250.0 362.5 TECR0[AMP_RED]=0b01 0000 Output impedance (differential) R O 80 100 120  –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This figure shows an example of a 4‐wire AC‐coupled SGMII serial link connection. Figure 3‐11. 4‐wire AC‐coupled SGMII serial link connection example 100Ω 50Ω 50Ω T r ansmitter SGMI I SerDes Int erface SDn_TXn_P SDn_TXn_N SDn_RXn_N SDn_RXn_P C TX C TX R eceiv er 100 T r ansmitter SDn_TXn_P SDn_TXn_NSDn_RXn_N SDn_RXn_P C TX C TX R eceiv er

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This figure shows the SGMII transmitter DC measurement circuit. Figure 3‐12. SGMII transmitter DC measurement circuit This table defines the SGMII 2.5G transmitter DC electrical characteristics for 3.125 GBaud. Note: 1. For recommended operating conditions, see Table 3‐2. This table lists the SGMII DC receiver electrical characteristics. Source synchronous clocking is not sup‐ ported. Clock is recovered from the data. Notes: 1. Input must be externally AC coupled. 2. V RX_DIFFp‐p is also referred to as peak‐to‐peak input differential voltage. 100Ω 50Ω 50Ω T r ansmitter SGMII SerDes Int erface SDn_TXn_P SDn_TXn_N V OD Table 3‐37. SGMII 2.5G transmitter DC electrical characteristics (X1VDD = 1.35 V)(1) Parameter Symbol Min Typical Max Unit Notes Output differential voltage ¦VOD¦ 400 ‐ 600 mV ‐ Output impedance (differential) R O 80 100 120  ‐ Table 3‐38. SGMII DC receiver electrical characteristics (S1VDD = 1.0V)(4) Parameter Symbol Min Typ Max Unit Notes DC input voltage range – N/A – (1) Input differential voltage REIDL_TH = 001 VRX_DIFFp‐p 100 – 1200 mV (2)(5) REIDL_TH = 100 175 – Loss of signal threshold REIDL_TH = 001 VLOS 30 – 100 mV (3)(5) REIDL_TH = 100 65 – 175 Receiver differential input impedance ZRX_DIFF 80 – 120  –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See PCI Express DC physical layer receiver specifications, and PCI Express AC physical layer receiver specifications, for further explanation. 4. For recommended operating conditions, see Table 3‐2. 5. The REIDL_TH shown in the table refers to the chip's SRDSxLNmGCR1[REIDL_TH] bit field. This table defines the SGMII 2.5G receiver DC electrical characteristics for 3.125 GBaud. Note: 1. For recommended operating conditions, see Table 3‐2.

3.11.1.3 SGMII AC timing specifications

This section discusses the AC timing specifications for the SGMII interface. This table provides the SGMII and SGMII 2.5G transmit AC timing specifications. A source synchronous clock is not supported. The AC timing specifications do not include RefClk jitter. Notes: 1. Each UI is 800 ps ± 100 ppm or 320 ps ± 100 ppm. 2. See Figure 3‐14 for single frequency sinusoidal jitter measurements. 3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter output. 4. For recommended operating conditions, see Table 3‐2.

3.11.1.3.2 SGMII AC measurement details

Table 3‐39. SGMII 2.5G receiver DC timing specifications (S1VDD = 1.0V)(1) Parameter Symbol Min Typical Max Unit Notes Input differential voltage VRX_DIFFp‐p 200 ‐ 1200 mV ‐ Loss of signal threshold VLOS 75 ‐ 200 mV ‐ Receiver differential input impedance ZRX_DIFF 80 ‐ 120  ‐ Table 3‐40. SGMII transmit AC timing specifications4 Parameter Symbol Min Typ Max Unit Notes Deterministic jitter JD ‐‐ 0.17 UI p‐p ‐ Total jitter JT ‐‐ 0.35 UI p‐p2 Unit Interval: 1.25 GBaud (SGMII) UI 800 ‐ 100 ppm 800 800 + 100 ppm ps 1 Unit Interval: 3.125 GBaud (2.5G SGMII]) UI 320 ‐ 100 ppm 320 320 + 100 ppm ps 1 AC coupling capacitor CTX 10 ‐ 200 nF 3

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD1_TXn_P and SD1_TXn_N) or at the receiver inputs (SD1_RXn_P and SD1_RXn_N) respectively, as depicted in this figure. Figure 3‐13. SGMII AC test/measurement load This table provides the SGMII and SGMII 2.5G receiver AC timing specifications. The AC timing specifica‐ tions do not include RefClk jitter. Source synchronous clocking is not supported. Clock is recovered from the data. Notes: 1. Measured at receiver 2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 3‐14. The sinusoidal jitter com‐ ponent is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. 3. For recommended operating conditions, see Table 3‐2. T r ansmitter silicon + pac kage D + package pin D - package pin C = C TX C = C TX R = 50Ω R = 50 Ω Table 3‐41. SGMII Receive AC timing specifications3 Parameter Symbol Min Typ Max Unit Notes Deterministic jitter tolerance J D ‐‐ 0.37 UI p‐p1 Combined deterministic and random jitter tolerance JDR ‐‐ 0.55 UI p‐p1 Total jitter tolerance J T ‐‐ 0.65 UI p‐p1 , 2 Bit error ratio BER ‐‐ 10‐12 ‐‐ Unit Interval: 1.25 GBaud (SGMII) UI 800 ‐ 100 ppm 800 800 + 100 ppm ps 1 Unit Interval: 3.125 GBaud (2.5G SGMII]) UI 320 ‐ 100 ppm 320 320 + 100 ppm ps 1

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of this figure. Figure 3‐14. Single‐frequency sinusoidal jitter limits 3.11.2 1000Base ‐KX interface This section discusses the electrical characteristics for the 1000Base‐KX. Only AC‐ coupled operation is supported. 3.11.2.1 1000Base ‐KX DC electrical characteristics 3.11.2.1.1 1000Base‐KX Transmitter DC Specifications This table describes the 1000Base‐KX SerDes transmitter DC specification at TP1 per IEEE Std 802.3ap‐ 2007. Transmitter DC characteristics are measured at the transmitter outputs (SD1_TXn_P and SD1_TXn_N). Notes: 1. SRDSxLNmTECR0[AMP_RED]=00_0000. 2. For recommended operating conditions, see Table 3‐2. 20 dB/dec 0.1 0 UI p-p

20 MHz

8.5 UI p-p

Table 3‐42. 1000Base‐KX Transmitter DC Specifications Parameter Symbols Min Typ Max Units Notes Output differential voltage VTX‐DIFFp‐p 800 ‐ 1600 mV (1) Differential resistance TRD 80 100 120 ohm ‐

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] 3.11.2.1.2 1000Base‐KX Receiver DC Specifications Table below provides the 1000Base‐KX receiver DC timing specifications. 1. For recommended operating conditions, see Table 3‐2. 3.11.2.2 1000Base ‐KX AC electrical characteristics 3.11.2.2.1 1000Base‐KX Transmitter AC Specifications Table below provides the 1000Base‐KX transmitter AC specification. Notes: 1. Total jitter is specified at a BER of 10‐12. 2. For recommended operating conditions, Table 3‐2. 3.11.2.2.2 1000Base‐KX Receiver AC Specifications Table below provides the 1000Base‐KX receiver AC specification with parameters guided by IEEE Std 802.3ap‐2007. Notes: 1. Random jitter is specified at a BER of 10‐12. 2. The receiver interference tolerance level of this parameter shall be measured as described in Annex 69A of the IEEE Std 802.3ap‐2007. 3. Per IEEE 802.3ap‐clause 70. 4. The AC specifications do not include Refclk jitter. 5. For recommended operating conditions, Table 3‐2. Table 3‐43. 1000Base‐KX Receiver DC Specifications Parameter Symbols Min Typ Max Units Notes Output differential voltage VRX‐DIFFp‐p ‐‐ 1600 mV 1 Differential resistance TRDIN 80 ‐ 120 ohm ‐ Table 3‐44. 1000Base‐KX Transmitter AC Specifications Parameter Symbols Min Typical Max Units Notes Baud Rate TBAUD 1.25‐100ppm 1.25 1.25+100ppm Gb/s ‐ Uncorrelated High Probability Jitter/ Random Jitter TUHPJTRJ ‐‐ 0.15 UI p‐p ‐ Deterministic Jitter TDJ ‐‐ 0.10 UI p‐p ‐ Total Jitter TTJ ‐‐ 0.25 UI p‐p1 Table 3‐45. 1000Base‐KX Receiver AC Specifications Parameter Symbols Min Typical Max Units Notes Receiver Baud Rate TBAUD 1.25‐100ppm 1.25 1.25+100ppm Gb/s – Random Jitter RRJ –– 0 . 1 5 U I p‐p1 Sinusoidal Jitter, maximum RSJ‐max –– 0 . 1 0 U I p‐p2 Total Jitter RTJ –– S e e Note 3U I p‐p2

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.11.3 RGMII electrical specifications

This section discusses the electrical characteristics for the RGMII interface.

3.11.3.1 RGMII DC electrical characteristics

This table shows the DC electrical characteristics for the RGMII interface. Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3‐2. 2. The symbol LVIN , in this case, represents the LVIN and L1VIN symbol referenced in Recommended operating conditions. 3. The symbol LVDD, in this case, represents the LVDD and L1VDD symbol referenced in Recommended operating conditions. 4. For recommended operating conditions, see Table 3‐2. This table provides the DC electrical characteristics for the RGMII interface at L1VDD/LVDD = 1.8 V. Notes: 1. The min VIL and max VIH values are based on the min and max LVIN values found in Table 3‐2. 2. The symbol LVIN, in this case, represents the LVIN and L1VIN symbol referenced in Recommended operating conditions. 3. The symbol LVDD, in this case, represents the LVDD and L1VDD symbol referenced in Recommended operating conditions. 4. For recommended operating conditions, see Table 3‐2. Table 3‐46. RGMII DC electrical characteristics(LVDD, L1VDD = 2.5V)(4) Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 * LVDD – V (1) Input low voltage VIL –0 . 2 * LVDD V (1) Input current (LVIN = 0V or LVIN = LVDD) IIH –± 5 0 µ A (2)(3) Output high voltage (LVDD = min, IOH = –1.0 mA) VOH 2.00 – V (3) Output low voltage (LVDD = min, IOL = 1.0 mA) VOL –0 . 4V (3) Table 3‐47. RGMII DC electrical characteristics (1.8V)(4) Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * LVDD – V (1) Input low voltage VIL –0 . 2 * LVDD V (1) Input current (LVIN = 0V or L1VIN = LVDD) IIN –± 5 0 µ A (2)(3) Output high voltage (LVDD = min, IOH = –0.5 mA) VOH 1.35 – V (3) Output low voltage (LVDD = min, IOL = 0.5 mA) VOL –0 . 4V (3)

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.11.3.2 RGMII AC timing specifications

This table presents the RGMII AC timing specifications. Notes: 1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 2.5 ns is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so, additional PCB delay is probably not needed. 3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Applies to inputs and outputs. 6. System/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is guar‐ anteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. 7. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300 ppm. 8. For recommended operating conditions, see Table 3‐2. Table 3‐48. RGMII AC timing specifications (LVDD = 2.5 /1.8 V)8 Parameter/Condition Symbol 1 Min Typ Max Unit Notes Data to clock output skew (at transmitter) tSKRGT_TX ‐620 0 520 ps 7 Data to clock input skew (at receiver) tSKRGT_RX 2.0 ‐ 3.0 ns 2 Clock period duration tRGT 7.2 8.0 8.8 ns 3 Duty cycle for 10BASE‐T and 100BASE‐TX tRGTH/tRGT 40 50 60 % 3, 4 Duty cycle for Gigabit tRGTH/tRGT 45 50 55 % ‐ Rise time (20%‐80%) L1/LVDD = 2.5V L1/LVDD = 1.8V tRGTR ‐‐ ‐ 0.75 0.54 ns 5, 6 Fall time (20%‐80%) L1/LVDD = 2.5V L1/LVDD = 1.8V tRGTF ‐‐ ‐ 0.75 0.54 ns 5, 6

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This figure shows the RGMII AC timing and multiplexing diagrams. Figure 3‐15. RGMII AC timing and multiplexing diagrams Warning e2v guarantees timings generated from the MAC. Board designers must ensure delays needed at the PHY or the MAC. GTX_CL K tRG T tRGTH tSKRGT_TX TX_CTL TXD[8:5] TXD[7:4] TXD[9 ] TXER R TXD[4 ] TXEN TXD[3:0] (At MAC, output) TXDS [8:5][3:0] TXD[7:4][3:0 ] TX_CL K (At PHY, input) RX_CTL RXD[8:5] RXD[7:4] RXD[9 ] RXERR RXD[4 ] RXDV RXD[3:0] RX _CLK (At MAC, input) tSKRGT_RX tRGT H tRGT RX_CLK (At PHY, output ) RXD[8:5][3:0] RXD[7:4][3:0] tSKRGT_RX PHY equi valent to t SKRGT_T X tSKRGT_T X PHY equiv alent to t SK RGT_RXPHY equiv alent to t SKRGT_RX (At MAC, output) (At MAC, output) (At PHY, output) (At PHY, output ) PHY equiv alent to t SKRGT_TX

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.11.4 MII electrical specifications

This section discusses the electrical characteristics for the MII interface.

3.11.4.1 MII DC electrical characteristics

This table shows the MII DC electrical characteristics when operating from a 3.3V supply. Notes: 1. The min VIL and max VIH values are based on the respective min and max L1VIN values found in Table 3‐2 2. The symbol VIN, in this case, represents the L1VIN symbols referenced in Table for "Absolute Maximum Ratings" This table shows the MII DC electrical characteristics when operating from a 2.5V supply.

3.11.4.2 MII AC timing specifications

This section describes the MII transmit and receive AC timing specifications. Table 3‐49. MII DC electrical characteristics Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * L1VDD – V (1) Input low voltage VIL –0 . 2 * L1VDD V (1) Input high current (VIN= L1VDD) IIH –5 0 µ A (2) Input low current (VIN= GND) IIL –50 – µA (2) Output high voltage (L1VDD = min, IOH = –2.0 mA) VOH 2.4 – V – Output low voltage (L1VDD = min, IOL= 2.0 mA) VOL –0 . 4 0V – Table 3‐50. MII DC electrical characteristics Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * L1VDD – V 1 Input low voltage VIL –0 . 2 * L1VDD V 1 Input high current (VIN= L1VDD) IIH –5 0 µ A2 Input low current (VIN= GND) IIL –50 – µA 2 Output high voltage (L1VDD = min, IOH = –1.0 mA) VOH 2.0 – V – Output low voltage (L1VDD = min, IOL= 1.0 mA) VOL –0 . 4 0V – Table 3‐51. MII transmit AC timing specifications Parameter Symbol Min Typ Max Unit TX_CLK clock period 10 Mbps tMTX –4 0 0– n s TX_CLK clock period 100 Mbps tMTX –4 0–n s TX_CLK duty cycle t MTXH/tMTX 35 – 65 % TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 0– 2 5 n s TX_CLK data clock rise (20%–80%) tMTXR 1.0 – 4.0 ns TX_CLK data clock fall (80%–20%) tMTXF 1.0 – 4.0 ns

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.11.5 Ethernet management interface (EMI)

This section discusses the electrical characteristics for the EMI1 interface. The EMI1 interface timing is compatible with IEEE Std 802.3ô clause 22.

3.11.5.1 Ethernet management interface 1 DC electrical characteristics

The DC electrical characteristics for EMI1_MDIO and EMI1_MDC are provided in this section. The pins are available on LVDD and L1VDD. Refer to Table 3‐2 for operating voltages. Notes: 1. The min VIL and max VIH values are based on the respective min and max L1VIN values found in Table 3‐2. 2. The symbol LVIN, in this case, represents the L1VIN symbol referenced in Recommended operating conditions 3. For recommended operating conditions, see Table 3‐2 Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN/L1VIN values found in Table 3‐2. 2. The symbol VIN, in this case, represents the LVIN/L1VIN symbols referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. 4. The symbol LVDD, in this case, represents the LVDD/L1VDD symbols referenced in Recommended oper‐ ating conditions. Table 3‐53. Ethernet management interface 1 DC electrical characteristics (L1VDD = 3.3V)(3) Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * L1VDD – V (1) Input low voltage VIL –0 . 2 * L1VDD V (1) Input current (LVIN = 0V or LVIN= LVDD) IIN –± 5 0 µ A (2) Output high voltage (L1VDD = min, IOH = –2 mA) VOH 2.4 – V – Output low voltage (L1VDD = min, IOL = 2 mA) VOL –0 . 4V – Table 3‐54. Ethernet management interface 1 DC electrical characteristics (LVDD = 2.5V)3, 4 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 * LVDD – V 1, 4 Input low voltage VIL –0 . 2 * LVDD V 1, 4 Input high current (VIN = LVDD) IIH –5 0 µ A 2 , 4 Input low current (VIN = GND) IIL –50 – µA – Output high voltage (LVDD = min, IOH = –1.0 mA) VOH 2.00 – V – Output low voltage (LVDD = min, IOL = 1.0 mA) VOL –0 . 4 0 V –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Notes: 1. The min VIL and max VIH values are based on the min and max LVIN/L1VIN respective values found in Table 3‐2. 2. The symbol LVIN represents the LVIN/L1VIN symbols referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. 4. The symbol LVDD, in this case, represents the LVDD and L1VDD symbols referenced in Recommended operating conditions.

3.11.5.2 Ethernet management interface 1 AC electrical specifications

This table provides the Ethernet management interface 1 AC timing specifications. Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. 2. This parameter is dependent on the Ethernet clock frequency (MDIO_CFG [MDIO_CLK_DIV] field determines the clock frequency of the MgmtClk Clock EC_MDC). 3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to 5 Ethernet clock periods ± 3 ns. For example, with an Ethernet clock of 400 MHz, the min/max delay is 12.5 ns ± 3 ns. 4. t enet_clk is the Ethernet clock period (Frame Manager clock period × 2). 5. For recommended operating conditions, see Table 3‐2. Table 3‐55. Ethernet management interface 1 DC electrical characteristics (1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * LVDD – V 1, 4 Input low voltage VIL –0 . 2 * LVDD V 1, 4 Input current (LVIN = 0V or LVIN = LVDD) IIN – ±50 µA 2, 4 Output high voltage (LVDD = min, IOH = –0.5 mA) VOH 1.35 – V 4 Output low voltage (LVDD = min, IOL = 0.5 mA) VOL –0 . 4 V 4 Table 3‐56. Ethernet management interface 1 AC timing specifications(5) Parameter/Condition Symbol (1) Min Typ Max Unit Notes MDC frequency fMDC –– 2 . 5 M H z (2) MDC clock pulse width high tMDCH 160 – – ns – MDC to MDIO delay tMDKHDX (5 × tenet_clk) – 3–( 5 × tenet_clk) + 3n s (3)(4) MDIO to MDC setup time tMDDVKH 8–– n s – MDIO to MDC hold time tMDDXKH 0–– n s –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.11.6 IEEE 1588 electrical specifications

3.11.6.1 IEEE 1588 DC electrical characteristics

This table shows IEEE 1588 DC electrical characteristics when operating at LVDD = 3.3V supply. Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3‐2. 2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. This table shows IEEE 1588 DC electrical characteristics when operating at LVDD = 2.5V supply. Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3‐2. 2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. This table shows IEEE 1588 DC electrical characteristics when operating at LVDD = 1.8V supply. Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3‐2. 2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. Table 3‐57. IEEE 1588 DC electrical characteristics(LVDD = 3.3V)(3) Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 * LVDD – V (1) Input low voltage VIL –0 . 2 * LVDD V (1) Input current (LVIN= 0V or LVIN= LVDD) IIH –± 5 0 µ A (2) Output high voltage (LVDD = min, IOH = –2.0 mA) VOH 2.4 – V – Output low voltage (LVDD = min, IOL = 2.0 mA) VOL –0 . 4 0V – Table 3‐58. IEEE 1588 DC electrical characteristics(LVDD = 2.5V)3 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 * LVDD – V 1 Input low voltage VIL –0 . 2 * LVDD V 1 Input current (LVIN= 0V or LVIN= LVDD) IIH –± 5 0 µ A 2 Output high voltage (LVDD = min, IOH = –1.0 mA) VOH 2.00 – V – Output low voltage (LVDD = min, IOL = 1.0 mA) VOL –0 . 4 0 V – Table 3‐59. IEEE 1588 DC electrical characteristics(LVDD = 1.8V)3 Parameters Symbol Min Max Unit Notes Input high voltage VIH 0.7 * LVDD – V 1 Input low voltage VIL –0 . 2 * LVDD V 1 Input current (LVIN= 0V or LVIN= LVDD) IIH –± 5 0 µ A 2 Output high voltage (LVDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (LVDD = min, IOL = 0.5 mA) VOL –0 . 4 0 V –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.11.6.2 IEEE 1588 AC specifications

This table provides the IEEE 1588 AC timing specifications. Notes: 1. T RX_CLK is the maximum clock period of ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip reference manual for a description of TMR_CTRL registers. 2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference man‐ ual for a description of TMR_CTRL registers. 3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively. 4. There are 3 input clock sources for 1588 that is, TSEC_1588_CLK_IN, RTC and MAC clock / 2. When using TSEC_1588_CLK_IN, the minimum clock period is 2 × tT1588CLK. 5. For recommended operating conditions, see Table 3‐2. 6. FM_CLK = platform clock This figure shows the data and command output AC timing diagram. Figure 3‐19. EEE 1588 output AC timing Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non‐inverting. Otherwise, it is counted starting at the falling edge. Table 3‐60. IEEE 1588 AC timing specifications(5) Parameter/Condition Symbol Min Typ Max Unit Notes TSEC_1588_CLK_IN clock period tT1588CLK FM_CLK/ 2 – TRX_CLK × 7n s (1)(3)(6) TSEC_1588_CLK_IN duty cycle tT1588CLKH/ tT1588CLK 40 50 60 % (2) TSEC_1588_CLK_IN peak‐to‐peak jitter tT1588CLKINJ – – 250 ps – Rise time TSEC_1588_CLK_IN (20%‐80%) tT1588CLKINR 1.0 – 2.0 ns – Fall time TSEC_1588_CLK_IN (80%‐20%) tT1588CLKINF 1.0 – 2.0 ns – TSEC_1588_CLK_OUT clock period tT1588CLKOUT 5.0 – – ns (4) TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/ tT1588CLKOUT 30 50 70 % – TSEC_1588_PULSE_OUT1/ 2, TSEC_1588_ALARM_OUT1/ 2 tT1588OV 0.5 – 3.0 ns – TSEC_1588_TRIG_IN1/ 2 pulse width tT1588TRIGH 2 × tT1588CLK_MAX –– n s (3) TSEC_1588_CLK_OUT TSEC_1588_ALARM_OUT1/2 TSEC_1588_PULSE_OUT1/2 tT1588OV tT1588CLKOUTH tT1588CLKOUT

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This figure shows the data and command input AC timing diagram. Figure 3‐20. IEEE 1588 input AC timing

3.12 QUICC Engine Specifications

3.12.1 HDLC, Transparent, and Synchronous UART interfaces

This section describes the DC and AC electrical specifications for the high level data link control HDLC, transparent and synchronous UART.

3.12.1.1 HDLC, Transparent and Synchronous UART DC electrical characteristics

This table provides the DC electrical characteristics for the HDLC, Transparent and Synchronous UART protocols. Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐2 2. The symbol VIN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. TSEC_1588_CLK_IN TSEC_1588_TRIG_IN1/2 tT1588CLK tT1588CLKH tT1588TRIGH Table 3‐61. HDLC, Transparent and Synchronous UART DC electrical characteristics (DVDD=3.3V)(3) Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V (1) Input low voltage VIL –0 . 2 * DVDD V (1) Input current (VIN = 0V or VIN = DVDD) IIN –± 5 0 µA (2) Output high voltage (DVDD = min, IOH = –2 mA) VOH 2.4 – V – Output low voltage (DVDD = min, IOH = 2 mA) VOL –0 . 4V –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This table provides the DC electrical characteristics for the HDLC, Transparent and Synchronous UART protocols. Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐ 2. The symbol VIN, in this case, represents the input voltage of the supply. It is referenced in Recom‐ mended operating conditions. 3. For recommended operating conditions, see Table 3‐2.

3.12.1.2 HDLC, Transparent and Synchronous UART AC timing specifications

This table provides the input and output AC timing specifications for HDLC, and Transparent and Syn‐ chronous UART protocols. Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. For recommended operating conditions, see Table 3‐2. 3. The Maximum frequency of operation is 50MHz Table 3‐62. HDLC, Transparent and Synchronous UART DC electrical characteristics (DVDD=2.5V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1 Input low voltage VIL –0 . 2 * DVDD V 1 Input current (VIN = 0V or VIN = DVDD) IIN –± 5 0 µA2 Output high voltage (DVDD = min, IOH = –1 mA) VOH 2.0 – V – Output low voltage (DVDD = min, IOH = 1 mA) VOL –0 . 4 V – Table 3‐63. HDLC, Transparent AC timing specifications Parameter Symbol Min Max Unit Notes Outputs‐Internal clock delay tHIKHOV 05 . 5 n s 1 Outputs‐External clock delay tHEKHOV 18 . 5 n s 1 Outputs‐Internal clock High Impedance tHIKHOX 05 . 5 n s 1 Outputs‐External clock High Impedance tHEKHOX 18 . 2 n s 1 Inputs‐Internal clock input setup time tHIIVKH 8.0 – ns – Inputs‐External clock input setup time tHEIVKH 4– n s – Inputs‐Internal clock input Hold time tHIIXKH 0– n s – Inputs‐External clock input hold time tHEIXKH 1– n s –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This figure shows the timing with internal clock. Figure 3‐23. AC timing (internal clock) diagram

3.12.2 TDM/SI

This section describes the DC and AC electrical specifications for the time‐division‐ multiplexed and serial interface (TDM/SI).

3.12.2.1 TDM/SI DC electrical characteristics

This table provides the TDM/SI DC electrical characteristics. Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐ 2 on page 44 2. The symbol VIN, in this case, represents the input voltage of the supply. It is referenced in Recom‐ mended operating conditions. 3. For recommended operating conditions, see Table 3‐2. Serial CLK (output) Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable t HIIVKH t HIIXKH tHIKHOV t HIKHOX Table 3‐65. TDM/SI DC electrical characteristics (DVDD=3.3V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1 Input low voltage VIL –0 . 2 * DVDD V 1 Input current (VIN = 0V or VIN = DVDD) IIN –± 5 0 µA2 Output high voltage (DVDD = min, IOH = –2 mA) VOH 2.4 – V – Output low voltage (DVDD = min, IOH = 2 mA) VOL –0 . 4 V –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐ 2. The symbol VIN, in this case, represents the input voltage of the supply. It is referenced in Recom‐ mended operating conditions. 3. For recommended operating conditions, see Table 3‐2.

3.12.2.2 TDM/SI AC timing specifications

This table provides the TDM/SI input and output AC timing specifications. Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. For recommended operating conditions, see Table 3‐2. NOTE The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of DVDD; fall time refers to transitions from 90% to 10% of DVDD This figure provides the AC test load for the TDM/SI. Figure 3‐24. TDM/SI AC test load Table 3‐66. TDM/SI DC electrical characteristics (DVDD=2.5V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1 Input low voltage VIL –0 . 2 * DVDD V 1 Input current (VIN = 0V or VIN = DVDD) IIN –± 5 0 µA2 Output high voltage (DVDD = min, IOH = –1 mA) VOH 2.0 – V – Output low voltage (DVDD = min, IOH = 1 mA) VOL –0 . 4 V – Table 3‐67. TDM/SI AC timing specifications 1 Parameter Symbol 1 Min Max Unit TDM/SI outputs‐External clock delay tSEKHOV 21 1 n s TDM/SI outputs‐External clock High Impedance tSEKHOX 21 0 n s TDM/SI inputs‐External clock input setup time tSEIVKH 5– n s TDM/SI inputs‐External clock input hold time tSEIXKH 2– n s Output DVDD /2 RL = 50Ω = 50ΩZ0

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This figure represents the AC timing from Table 3‐68. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. This figure shows the TDM/SI timing with external clock. Figure 3‐25. TDM/SI AC timing (external clock) diagram

3.13 USB interface

This section provides the AC and DC electrical specifications for the USB interface.

3.13.1 USB DC electrical characteristics

This table provides the DC electrical characteristics for the USB interface at USB_HVDD = 3.3V. Notes: 1. The min VIL and max VIH values are based on the respective min and max USB_HVIN values found in Table 3‐2. 2. The symbol USB_HVIN, in this case, represents the USB_HVIN symbol referenced in Recommended operating conditions 3. For recommended operating conditions, see Table 3‐2 tSEKHOX Output Signals: TDM/SI (See Note) Input Signals: TDM/SI (See Note) TDM/SICLK (input) t SEIVKH tSEIXKH tSEKHOV Table 3‐68. USB DC electrical characteristics (USB_HVDD = 3.3V) 3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 – V 1 Input low voltage VIL –0 . 8V 1 Input current (USB_HVIN = 0V or USB_HVIN= USB_HVDD) IIN –± 5 0 µ A 2 Output high voltage (USB_HVDD = min, IOH = –2 mA) VOH 2.8 – V – Output low voltage (USB_HVDD = min, IOL = 2 mA) VOL –0 . 3V –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This table provides the DC electrical characteristics for the USBCLK at O1VDD = 1.8V. Notes: 1. The min VIL and max VIH values are based on the respective min and max O1VIN values found in Table 3‐2. 2. The symbol VIN, in this case, represents the O1VIN symbol referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2.

3.13.2 USB AC timing specifications

This section describes the AC timing specifications for the on‐chip USB PHY. See Chapter 7 in the Uni‐ versal Serial Bus Revision 2.0 Specification for more information. This table provides the USB clock input (USBCLK) AC timing specifications. Notes: 1. For recommended operating conditions, see Table 3‐2 2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. Table 3‐69. USBCLK DC electrical characteristics (1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.25 – V 1 Input low voltage VIL –0 . 6V 1 Input current (VIN = 0V or VIN = O1VDD) IIN –± 5 0 µ A 2 Table 3‐70. USBCLK AC timing specifications(1) Parameter Condition Symbol Min Typ Max Unit Notes Frequency range – fUSB_CLK_IN –2 4– M H z – Rise/Fall time Measured between 10% and 90% tUSRF ––6 n s (2) Clock frequency tolerance – tCLK_TOL 0.005 00 . 0 0 5 % – Reference clock duty cycle Measured at rising edge and/or failing edge at O1VDD/2 tCLK_DUTY 40 50 60 % – Total input jitter/time interval error RMS value measured with a second‐order, band‐pass filter of 500 kHz to 4 MHz bandwidth at 10‐12 BER tCLK_PJ ––5 p s –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.14 Integrated flash controller

This section describes the DC and AC electrical specifications for the integrated flash controller.

3.14.1 Integrated flash controller DC electrical characteristics

This table provides the DC electrical characteristics for the integrated flash controller when operating at OVDD= 1.8V. Notes: 1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3‐2. 2. The symbol VIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2.

3.14.2 Integrated flash controller AC timing

This section describes the AC timing specifications for the integrated flash controller.

3.14.2.1 Test condition

This figure provides the AC test load for the integrated flash controller. Figure 3‐26. Integrated flash controller AC test load

3.14.2.2 Integrated flash controller Input AC timing specifications

This table describes the input AC timing specifications of the IFC‐GPCM and IFC‐ GASIC interface. Table 3‐71. Integrated flash controller DC electrical characteristics (1.8V)3 Parameter Symbol Min Max Unit Note Input high voltage VIH 1.2 – V 1 Input low voltage VIL –0 . 6V 1 Input current (VIN = 0V or VIN = OVDD) IIN –± 5 0 µ A 2 Output high voltage (OVDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (OVDD = min, IOL = 0.5 mA) VOL –0 . 3 2V – Output Z0= 50Ω RL = 50Ω OVDD/2 Table 3‐72. Integrated Flash Controller input timing specifications for GPCM and GASIC mode (OVDD = 1.8V) Parameter Symbol Min Max Unit Notes Input setup tIBIVKH1 4– n s – Input hold tIBIXKH1 1– n s –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This table describes the input timing specifications of the IFC‐NAND interface. Notes: 1. t IP_CLK is the period of ip clock on which IFC is running. 2. For recommended operating conditions, see Table 3‐2 This figure shows the AC input timing diagram for input signals of IFC‐NAND interface. Here TRAD is a programmable delay parameter, refer to IFC section of T1040 QorIQ Integrated Processor Reference Manual for more information. Figure 3‐29. IFC‐NAND Interface input AC timings tIP_CLK is the period of ip clock (not the IFC_CLK) on which IFC is running.

3.14.2.3 Integrated flash controller output AC timing specifications

This table describes the output AC timing specifications of IFC‐GPCM and IFC‐GASIC interface. Notes: 1. Output hold is negative. This means that output transition happens earlier than the falling edge of IFC_CLK. 2. For recommended operating conditions, see Table 3‐2 Table 3‐74. Integrated Flash Controller input timing specifications for NAND mode (OVDD = 1.8V) Parameter Symbol Min Max Unit Notes Input setup tIBIVKH3 (2 × tIP_CLK) +2 – ns 1 Input hold tIBIXKH3 (1 × tIP_CLK) –n s1 IFC_RB_B pulse width tIBCH 2– tIP_CLK 1 AD [0:15] RE_B (TRAD +1 ) x tIP_CLK tIBIVKH3 IBIXKH3t Table 3‐75. Integrated Flash Controller IFC‐GPCM and IFC‐GASIC interface output timing specifications (OVDD = 1.8V) Parameter Symbol Min Max Unit Notes IFC_CLK cycle time tIBK 10 – ns – IFC_CLK duty cycle tIBKH/ tIBK 45 55 % – Output delay tIBKLOV1 –1 . 5 n s – Output hold tIBKLOX –– 2 n s1 IFC_CLK[0] to IFC_CLK[m] skew tIBKSKEW 0± 7 5 p s –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This figure shows the AC timing diagram for output signals of IFC‐NAND interface.The timing specs have been illustrated here by taking timings between two signals, CS_B and CLE as an example. CLE is sup‐ pose to change TCCST (a programmable delay, refer to IFC section of T1040 QorIQ Integrated Processor Reference Manual for more information) time after CS_B. Because of skew between the signals CLE may change anywhere within time window tIBKLOV3 (min) and tIBKLOV3 (max). This concept applies to other output signals of IFC‐NAND interface as well. The diagram is an example to show the skew between any two chronological toggling signals as per the protocol. Here is the list of output signals NDWE_B, NDRE_B, NDALE, WP_B, NDCLE, CS_B, AD. Figure 3‐32. IFC‐NAND Interface Output AC Timings

3.14.2.4 Integrated flash controller NAND Source Synchronous Interface AC timing specifications

This table describes the AC timing specifications of IFC‐NAND Source Synchronous interface. CS_B CLE TCCST tIBKLOV3 Table 3‐78. Integrated Flash Controller IFC‐NAND Source Synchronous Interface AC Timing Specifications (OVDD = 1.8V) Parameter Symbol I/O Min Max Unit Notes Command/address DQ hold time tCAH O2 . 5 – n s – CLE and ALE hold time tCALH O2 . 5 – n s – CLE and ALE setup time tCALS O2 . 5 – n s – Command/address DQ setup time tCAS O2 . 5 – n s – CE# hold time tCH O2 . 5 – n s – Data DQ setup time tDS O1 – n s – Data DQ hold time tDH O1 – n s – Average clock cycle time t CK(avg) or tCK O1 0 – n s (1) Absolute clock period t CK(abs) O 9.5 10.5 ns – Clock cycle high tCKH(abs) O 0.44 0.56 tCK (2) Clock cycle low tCKL(abs) O 0.44 0.56 tCK – DQS output high pulse width tDQSH O 0.43 0.57 tCK (3) DQS output low pulse width tDQSL O 0.43 0.57 tCK (3) DQS‐DQ skew, DQS to last DQ valid, per access tDQSQ I–1 n s – Data output to first DQS latching transition tDQSS O 0.75+150(ps) 1.15 tCK DQS cycle time tDSC O1 0 – n s – DQS falling edge to CLK rising – hold time tDSH O0 . 2 2 8 – tCK – DQS falling edge to CLK rising – setup time tDSS O0 . 3 – tCK – Input data valid window tDVW I2 . 1– n s –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Notes: 1. t CK(avg) is the average clock period over any consecutive 200 cycle window. 2. t CKH(abs) and tCKL(abs) include static off set and duty cycle jitter. 3. t DQSL and tDQSH are relative to tCK when CLK is running . If CLK is stopped during data input, then tDQSL and tDQSH are relative to tDSC. 4. For recommended operating conditions, see Table 3‐2 These figures show the AC timing diagram for IFC‐NAND source synchronous interface. Figure 3‐33. Command Cycle Half‐clock period tHP O4 . 4 – n s – The deviation of a given tCK(abs) from tCK(avg) t JIT (per) O –0.5 0.5 ns – DQ‐DQS hold, DQS to first DQ to go non‐ valid, per access tQH I3 . 1– n s – Table 3‐78. Integrated Flash Controller IFC‐NAND Source Synchronous Interface AC Timing Specifications (OVDD = 1.8V) CE_B CLE ALE CLK W/R_B DQS DQ[7:0] tCALS tCALS tCALS tCALH tCKL tCKH tCK tCALS tDQSHZ tCALH tCAS tCAH tCH Command

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 3‐36. Read Cycle

3.15 Enhanced secure digital host controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface. 3.15.1 eSDHC DC electrical characteristics This table provides the DC electrical characteristics for the eSDHC interface. Notes: 1. The min VIL and VIH values are based on the respective min and max VIN values found in Table 3‐2. 2. Open ‐drain mode is for MMC cards only. 3. For recommended operating conditions, see Table 3‐2. 4. SDHC interface is powered by EVDD and CVDD. The VDD and VIN in the table above should be replaced by the respective IO power supply. CE_B CLE ALE CLK W/R_B DQS DQ[7:0] tCALS tCALS tCALH tCALHtCALS tHP tHP tDSC tDQSD tCKH tCKL tDVWtDVW tDVW tCALS tDQSHZ tDQSQ Don't Care tCK tHP tHP tHP tHP tDQSQ tQH tQH tQH tQH tDQSQ tDQSQ Data Transitioning Device Driving tCH D1D0 tDVW tDVW D2 D3 D0 D0 D0 D0 Table 3‐79. eSDHC interface DC electrical characteristics (dual‐voltage cards)(3) Characteristic Symbol Condition Min Max Unit Notes Input high voltage VIH –0 . 7 × VDD –V (1) Input low voltage VIL –– 0 . 2 × VDD V (1) Input/Output leakage current IIN/IOZ –– 5 0 5 0 µA– Output high voltage VOH IOH = –100 µA at VDD min V DD – 0.2V – V – Output low voltage VOL IOL= 100 µA at VDD min – 0.2 V – Output high voltage VOH IOH = –100 µAV DD – 0.2 – V (2) Output low voltage VOL IOL = 2 mA – 0.3 V (2)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 3.15.2 eSDHC AC timing specifications This table provides the eSDHC AC timing specifications as defined in Figure 3‐37 and Figure 3‐38 (EVDD/CVDD = 1.8V or 3.3V). Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and (first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC high‐speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. In full‐speed mode, the clock frequency value can be 0‐25 MHz for an SD/SDIO card and 0‐20 MHz for an MMC card. In high‐speed mode, the clock frequency value can be 0‐50 MHz for an SD/SDIO card and 0‐52 MHz for an MMC card. 3. To satisfy setup timing, one‐way board‐routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the one way board routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1.5ns. 4. C CARD = 10 pF, (1 card), and CL = CBUS + CHOST + CCARD = 40 pF. 5. The parameter values apply to both full‐speed and high‐speed modes. 6. For recommended operating conditions, see Table 3‐2 This figure provides the eSDHC clock input timing diagram. Figure 3‐37. eSDHC clock input timing diagram Table 3‐80. eSDHC AC timing specifications (High Speed/Full Speed)6 Parameter Symbol 1 Min Max Unit Notes SDHC_CLK clock frequency SD/SDIO (full‐speed/high‐speed mode) fSCK 02 5 / 5 0 M H z 2 , 4 MMC full‐speed/high‐speed mode 20/52 SDHC_CLK clock low time (full‐speed/high‐speed mode) tSCKL 10/7 – ns 4 SDHC_CLK clock high time (full‐speed/high‐speed mode) tSCKH 10/7 – ns 4 SDHC_CLK clock rise and fall times tSCKR/ tSCKF –3 n s 4 Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK tNIIVKH 2.5 – ns 3, 4, 5 Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK tNIIXKH 2.5 – ns 4, 5 Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tNIKHOX –3 – ns 4, 5 Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tNIKHOV –3 n s 4 , 5 eSDHC external clock VM VM VM tSCK tSCKL tSCKH tSCKR tSCKF VM = Midpoint voltage (OVDD/2)

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This figure provides the data and command input/output timing diagram. Figure 3‐38. eSDHC data and command input/output timing diagram referenced to clock This table provides the eSDHC AC timing specifications for SDR50 mode (EVDD/CVDD = 1.8V). Notes: 1. C CARD = 10 pF, (1 card), and CL = CBUS + CHOST + CCARD = 30 pF. 2. For recommended operating conditions, see Table 3‐2. SDHC_CLK external clock VM VM VM tNIIXKH SDHC_DAT/CMD inputs SDHC_DAT/CMD outputs VM tNIIVKH tNIKHOV VM = Midpoint voltage (OVDD/2) tNIKHOX Table 3‐81. eSDHC AC timing (SDR50)2 Parameter Symbol Min Max Unit Notes SDHC_CLK clock frequency: fSCK 100 MHz SDHC_CLK duty cycle 47 53 % SDHC_CLK clock rise and fall times tSCKR/ tSCKF –2 n s 1 Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK – –0.1 0.1 ns – Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK_SYNC_IN tNIIVKH 2.1 – ns Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK_SYNC_IN tNIIXKH 0.9 – ns Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid, SDHC_DATx_DIR, SDHC_CMD_DIR tNIKHOX 2.4 – ns Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid, SDHC_DATx_DIR, SDHC_CMD_DIR tNIKHOV –6 . 3 n s

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This figure shows the eSDHC output AC timing diagram for SDR50 mode. Figure 3‐41. eSDHC SDR50 mode output AC timing diagram This table provides the eSDHC AC timing specifications for DDR50/eMMC DDR mode (EVDD/CVDD = 1.8V). SDHC_CMD/SDHC_CMD_DIR SDHC_DAT/SDHC_DATn_DIR output NIKHOVT NIKHOXT CLKT SDHC_CLK Table 3‐82. eSDHC AC timing (DDR50/eMMC DDR)3 Parameter Symbol Min Max Units Notes SDHC_CLK clock frequency SD/SDIO DDR50 mode fSCK –5 0 M H z – eMMC DDR mode 50 SDHC_CLK duty cycle – 47 53 % – Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK – –0.1 0.1 ns – SDHC_CLK clock rise and fall times SD/SDIO DDR50 mode tSCKR/ tSCKF –4 n s 1 eMMC DDR mode 2 2 Input setup times: SDHC_DATx to SDHC_CLK_SYNC_IN SD/SDIO DDR50 mode tNDIVKH 0.5 – ns – eMMC DDR mode 0.6 Input hold times: SDHC_DATx to SDHC_CLK_SYNC_IN SD/SDIO DDR50 mode tNDIXKH 0.98 – ns – eMMC DDR mode 0.98 Output hold time: SDHC_CLK to SDHC_DATx valid, SDHC_DATx_DIR SD/SDIO DDR50 mode tNDKHOX 2.2 – ns – eMMC DDR mode 3.9 Output delay time: SDHC_CLK to SDHC_DATx valid, SDHC_DATx_DIR SD/SDIO DDR50 mode tNDKHOV –5 . 7 n s – eMMC DDR mode 6.3

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Notes: 1. C CARD = 10 pF, (1 card). 2. C L = CBUS + CHOST + CCARD = 20 pF for MMC. 40pF for SD. 3. For recommended operating conditions, see Table 3‐2. This table provides the eSDHC AC timing specifications for eMMC DDR mode (EVDD/CVDD = 3.3V). Input setup times: SDHC_CMD to SDHC_CLK_SYNC_IN SD/SDIO DDR50 mode tNIIVKH 3.3 – ns – eMMC DDR mode 2.7 Input hold times: SDHC_CMD to SDHC_CLK_SYNC_IN SD/SDIO DDR50 mode tNIIXKH 0.4 – ns – eMMC DDR mode 0.4 Output hold time: SDHC_CLK to SDHC_CMD valid, SDHC_CMD_DIR SD/SDIO DDR50 mode tNIKHOX 2.2 – ns – eMMC DDR mode 4.4 Output delay time: SDHC_CLK to SDHC_CMD valid, SDHC_CMD_DIR SD/SDIO DDR50 mode tNIKHOV –1 2 . 2 n s – eMMC DDR mode 14.6 Table 3‐82. eSDHC AC timing (DDR50/eMMC DDR)3 (Continued) Table 3‐83. eSDHC AC timing (eMMC DDR)3 Parameter Symbol Min Max Units Notes SDHC_CLK clock frequency eMMC DDR mode fSCK –4 9 M H z – SDHC_CLK duty cycle – 47 53 % – Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK – –0.1 0.1 ns – SDHC_CLK clock rise and fall times eMMC DDR mode tSCKR/ tSCKF –2 n s 2 Input setup times: SDHC_DATx to SDHC_CLK_SYNC_IN eMMC DDR mode tNDIVKH 1.33 – ns – Input hold times: SDHC_DATx to SDHC_CLK_SYNC_IN eMMC DDR mode tNDIXKH 1.32 – ns 4 Output hold time: SDHC_CLK to SDHC_DATx valid, SDHC_DATx_DIR eMMC DDR mode tNDKHOX 3.9 – ns – Output delay time: SDHC_CLK to SDHC_DATx valid, SDHC_DATx_DIR eMMC DDR mode tNDKHOV –6 . 3 n s – Input setup times: SDHC_CMD to SDHC_CLK_SYNC_IN eMMC DDR mode tNIIVKH 2.7 – ns –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Notes: 1. C CARD = 10 pF, (1 card). 2. C L = CBUS + CHOST + CCARD = 20 pF for MMC. 40pF for SD. 3. For recommended operating conditions, see Table 3‐2. 4. Refer eSDHC A‐008936 This figure shows the eSDHC DDR50/eMMC DDR mode input AC timing diagram. Figure 3‐42. eSDHC DDR50/DDR mode input AC timing diagram Input hold times: SDHC_CMD to SDHC_CLK_SYNC_IN eMMC DDR mode tNIIXKH 0.4 – ns – Output hold time: SDHC_CLK to SDHC_CMD valid, SDHC_CMD_DIR eMMC DDR mode tNIKHOX 4.4 – ns – Output delay time: SDHC_CLK to SDHC_CMD valid, SDHC_CMD_DIR eMMC DDR mode tNIKHOV –1 4 . 6 n s – Table 3‐83. eSDHC AC timing (eMMC DDR)3 (Continued) SDHC_CLK_SYNC_IN SDHC_DAT input SDHC_CMD input TCLK TNDIVKH TNDIXKH T NIIVKH TNIIXKH

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This figure provides the SDR104/HS200 mode timing diagram. Figure 3‐44. SDR104/eMMC HS200 mode timing diagram

3.16 Multicore programmable interrupt controller (MPIC)

This section describes the DC and AC electrical specifications for the multicore programmable interrupt controller.

3.16.1 MPIC DC specifications

These tables provides the DC electrical characteristics for the MPIC interface. IRQ's pins are on L1VDD, O1VDD, DVDD and CVDD power supplies. Notes: 1. The min VIL and max VIH values are based on the min and max DVIN respective values found in Table 3‐2. 2. The symbol O1VIN, in this case, represents the O1VIN symbol referenced in Table 3‐2. 3. For recommended operating conditions, see Table 3‐2. SDHC_CLK SDHC_CMD/ SDHC_D A T input SDHC_CMD/SDHC_CMD_DIR SDHC_D AT/SDHC_D ATn_DIR output D ATA D ATA D ATA TNIKHO X TNIKHO V T IDV Tclk Table 3‐85. MPIC DC electrical characteristics (O1VDD = 1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.2 – V 1 Input low voltage VIL –0 . 6V 1 Input current (O1VIN = 0V or O1VIN = O1VDD) IIN –± 5 0 µ A 2 Output high voltage (O1VDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (O1VDD = min, IOL = 0.5 mA) VOL –0 . 4V –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Notes: 1. The min VILand max VIH values are based on the min and max DVIN respective values found in Table 3‐2. 2. The symbol DVIN, in this case, represents the DVIN symbol referenced in Table 3‐2. 3. For recommended operating conditions, see Table 3‐2. 4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, DVDD or CVDD. Notes: 1. The min VILand max VIH values are based on the min and max DVIN respective values found in Table 3‐2. 2. The symbol DVIN, in this case, represents the DVIN symbol referenced in Table 3‐2. 3. For recommended operating conditions, see Table 3‐2. 4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, DVDD or CVDD. Notes: 1. The min VILand max VIH values are based on the min and max DVIN respective values found in Table 3‐2. 2. The symbol DVIN, in this case, represents the DVIN symbol referenced in Table 3‐2. 3. For recommended operating conditions, see Table 3‐2. 4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, DVDD or CVDD. Table 3‐86. MPIC DC electrical characteristics (DVDD = 1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1, 4 Input low voltage VIL –0 . 2 * DVDD V 1, 4 Input current (DVIN = 0V or DVIN = DVDD) IIN –± 5 0 µ A 2 Output high voltage (DVDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (DVDD = min, IOL = 0.5 mA) VOL –0 . 4V – Table 3‐87. MPIC DC electrical characteristics (DVDD = 2.5V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1, 4 Input low voltage VIL –0 . 2 * DVDD V 1, 4 Input current (DVIN = 0V or DVIN = DVDD) IIN –± 5 0 µ A 2 Output high voltage (DVDD = min, IOH = –1 mA) VOH 2.0 – V – Output low voltage (DVDD = min, IOL = 1 mA) VOL –0 . 4V – Table 3‐88. MPIC DC electrical characteristics (DVDD = 3.3V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1, 4 Input low voltage VIL –0 . 2 * DVDD V 1, 4 Input current (DVIN = 0V or DVIN = DVDD) IIN –± 4 0 µ A 2 Output high voltage (DVDD = min, IOH = –2 mA) VOH 2.4 – V – Output low voltage (DVDD = min, IOL = 2 mA) VOL –0 . 4V –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.16.2 MPIC AC timing specifications

This table provides the MPIC input and output AC timing specifications. Notes: 1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs must be synchronized before use by any external synchronous logic. MPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode. 2. For recommended operating conditions, see Table 3‐2. 3. Entry and exit from deep sleep respectively require a minimum pulse width tPIWID of 25 SYSCLK. See the Reference Manual for details on Entry and Exit from deep sleep.

3.17 JTAG controller

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface.

3.17.1 JTAG DC electrical characteristics

This table provides the JTAG DC electrical characteristics. Notes: 1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 3‐ 2. The symbol VIN, in this case, represents the OVIN symbol found in Table 3‐2. 3. For recommended operating conditions, see Table 3‐2.

3.17.2 JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 3‐45 through Figure 3‐48. Table 3‐89. MPIC Input AC timing specifications2 Characteristic Symbol Min Max Unit Notes MPIC inputs‐minimum pulse width tPIWID 3– S Y S C L K s 1 , 3 Table 3‐90. JTAG DC electrical characteristics (OVDD = 1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.2 – V 1 Input low voltage VIL –0 . 6V 1 Input current (OVIN = 0V or OVIN = OVDD) IIN –± 5 0 µ A 2 Output high voltage (OVDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (OVDD = min, IOL= 0.5 mA) VOL –0 . 4V – Table 3‐91. JTAG AC timing specifications4 Parameter Symbol 1 Min Max Unit Notes JTAG external clock frequency of operation fJTG 02 5 M H z – JTAG external clock cycle time tJTG 40 – ns – JTAG external clock pulse width measured at 1.4V tJTKHKL 15 – ns – JTAG external clock rise and fall times tJTGR/tJTGF 02 n s – TRST_B assert time tTRST 25 – ns 2

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This figure provides the TRST_B timing diagram. Figure 3‐47. TRST_B timing diagram This figure provides the boundary‐scan timing diagram. Figure 3‐48. Boundary‐scan timing diagram

3.18 I2C interface

This section describes the DC and AC electrical characteristics for the I2C interface.

3.18.1 I2C DC electrical characteristics

This table provides the DC electrical characteristics for the I2C interfaces operating at 3.3V. Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐2. 2. See the chip reference manual for information about the digital filter used. tTRST VM = Midpoint voltage (OVDD/2) VM VM TRST_B JTAG External Clock Boundary Data Inputs Boundary Data Outputs VMVM Input Data Valid Output Data Valid VM = Midpoint Voltage (OVDD/2) tJTKLDV tJTKLDX tJTDVKH tJTDXKH Table 3‐92. I2C DC electrical characteristics (DVDD = 3.3V)5 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD ‐ V1 Input low voltage VIL ‐ 0.2 * DVDD V1 Output low voltage (IOL = 3.0 mA) VOL ‐ 0.4 V ‐ Pulse width of spikes which must be suppressed by the input filter tI2KHKL 05 0 n s3 Input current each I/O pin (input voltage is between 0.1 x DVDD and 0.9 x DVDD(max) II ‐50 50 µA 4 Capacitance for each I/O pin C I ‐ 10 pF ‐

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 3. I/O pins obstruct the SDA and SCL lines if DVDD is switched off. 4. For recommended operating conditions, see Table 3‐2. This table provides the DC electrical characteristics for the I2C interfaces operating at 2.5V. Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐2. 2. See the chip reference manual for information about the digital filter used. 3. I/O pins obstruct the SDA and SCL lines if DVDD is switched off. 4. For recommended operating conditions, see Table 3‐2. This table provides the DC electrical characteristics for the I2C interfaces operating at 1.8V. Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐2. 2. See the chip reference manual for information about the digital filter used. 3. I/O pins obstruct the SDA and SCL lines if DVDD is switched off. 4. For recommended operating conditions, see Table 3‐2. Table 3‐93. I2C DC electrical characteristics (DVDD = 2.5V)5 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1 Input low voltage VIL –0 . 2 * DVDD V 1 Output low voltage (DVDD = min, IOL = 3 mA) VOL 00 . 4 V – Pulse width of spikes which must be suppressed by the input filter tI2KHKL 05 0 n s 3 Input current each I/O pin (input voltage is between 0.1 × DVDD and 0.9 × DVDD(max) II –50 50 µA 4 Capacitance for each I/O pin C I –1 0 p F – Table 3‐94. I2C DC electrical characteristics (DVDD = 1.8V)5 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1 Input low voltage VIL –0 . 2 * DVDD V 1 Output low voltage (DVDD = min, IOL = 3 mA) VOL 00 . 3 6 V – Pulse width of spikes which must be suppressed by the input filter tI2KHKL 05 0 n s 3 Input current each I/O pin (input voltage is between 0.1 × DVDD and 0.9 × DVDD(max) II –50 50 µA 4 Capacitance for each I/O pin C I –1 0 p F –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.18.2 I 2C AC timing specifications

This table provides the AC timing parameters for the I2C interfaces. Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condi‐ tion (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. 2. The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for SCL (AN2919). 3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter, see Determining the I2C Frequency Divider Ratio for SCL (AN2919). 4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal. 5. For recommended operating conditions, see Table 3‐2. Table 3‐95. I2C AC timing specifications5 Parameter Symbol 1 Min Max Unit Notes SCL clock frequency fI2C 04 0 0 k H z 2 Low period of the SCL clock tI2CL 1.3 – µs– High period of the SCL clock tI2CH 0.6 – µs– Setup time for a repeated START condition tI2SVKH 0.6 – µs– Hold time (repeated) START condition (after this period, the first clock pulse is generated) tI2SXKL 0.6 – µs– Data setup time tI2DVKH 100 – ns – Data input hold time: tI2DXKL µs3 CBUS compatible masters I2C bus devices Data output delay time tI2OVKL –0 . 9 µs4 Setup time for STOP condition tI2PVKH 0.6 – µs– Bus free time between a STOP and START condition tI2KHDX 1.3 – µs– Noise margin at the LOW level for each connected device (including hysteresis) VNL 0.1 × OVDD –V – Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 × OVDD –V – Capacitive load for each bus line Cb – 400 pF –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 3‐49. 2C AC test load This figure shows the AC timing diagram for the I2C bus. Figure 3‐50. I2C Bus AC timing diagram

3.19 GPIO interface

This section describes the DC and AC electrical characteristics for the GPIO interface. GPIO pins are on OVDD, O1VDD, DVDD, CVDD, EVDD, L1VDD and LVDD power supplies.

3.19.1 GPIO DC electrical characteristics

This table provides the DC electrical characteristics for GPIO pins operating at 3.3V. GPIO pins on DVDD, CVDD, EVDD, L1VDD and LVDD power supplies. Notes: 1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐2 2. The symbol VIN, in this case, represents the DVIN symbol referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. 4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, LVDD, EVDD or CVDD. Output Z0= 50Ω RL = 50Ω DVDD/2 SDA SCL S Sr P S tI2KHDX tI2PVKH tI2KHKL tI2SVKH tI2SXKL tI2CH tI2DVKH tI2DXKL, tI2OVKL tI2CL tI2SXKL Table 3‐96. GPIO DC electrical characteristics (3.3V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1, 4 Input low voltage VIL –0 . 2 * DVDD V 1, 4 Input current (VIN = 0V or VIN = DVDD) IIN –± 5 0 µA2 Output high voltage (DVDD = min, IOH = –2 mA) VOH 2.4 – V – Output low voltage (DVDD = min, IOL = 2 mA) VOL –0 . 4V –

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This table provides the DC electrical characteristics for GPIO pins operating at 2.5V. GPIO pins on DVDD, CVDD, EVDD, L1VDD and LVDD power supplies. Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3‐2 2. The symbol VIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. 4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, LVDD, EVDD or CVDD. This table provides the DC electrical characteristics for GPIO pins operating at 1.8V. GPIO pins on DVDD, CVDD, EVDD, L1VDD and LVDD power supplies. Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3‐ 2. The symbol VIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions. 3. For recommended operating conditions, see Table 3‐2. 4. DVDD should be replaced by the respective IO power supply i.e. L1VDD, LVDD, EVDD or CVDD. Table 3‐97. GPIO DC electrical characteristics (2.5V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1, 4 Input low voltage VIL –0 . 2 * DVDD V 1, 4 Input current (VIN = 0V or VIN= DVDD) IIN –± 5 0 µA2 Output high voltage (DVDD = min, IOH = –1 mA) VOH 2.0 – V – Output low voltage (DVDD = min, IOL = 1 mA) VOL –0 . 4 V – Table 3‐98. GPIO DC electrical characteristics (1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1, 4 Input low voltage VIL –0 . 2 * DVDD V 1, 4 Input current (VIN = 0V or VIN = DVDD) IIN –± 5 0 µA2 Output high voltage (DVDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (DVDD = min, IOL = 0.5 mA) VOL –0 . 4 V –

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This table provides the DC electrical characteristics for GPIO pins operating at O1VDD/OVDD = 1.8V. Notes: 1. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3‐ 2. The symbol VIN, in this case, represents the OVIN/O1VIN symbol referenced in Recommended operat‐ ing conditions. 3. For recommended operating conditions, see Table 3‐2.

3.19.2 GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications. Notes: 1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation. 2. For recommended operating conditions, see Table 3‐2. 3. Entry and exit from deep sleep respectively require a minimum pulse width tPIWID of 35 SYSCLK. See the Reference Manual for details on Entry and Exit from deep sleep. This figure provides the AC test load for the GPIO. Figure 3‐51. GPIO AC test load Table 3‐99. GPIO DC electrical characteristics (OVDD/O1VDD = 1.8V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.2 – V 1 Input low voltage VIL –0 . 6V 1 Input current (VIN = 0V or VIN = OVDD) IIN –± 5 0 µA2 Output high voltage (OVDD/O1VDD = min, IOH = –0.5 mA) VOH 1.35 – V – Output low voltage (OVDD/O1VDD = min, IOL = 0.5 mA) VOL –0 . 4V – Table 3‐100. GPIO input AC timing specifications2 Parameter Symbol Min Unit Notes GPIO inputs–minimum pulse width tPIWID 20 ns 1, 3 Output Z0= 50Ω RL = 50Ω (L/O) VDD/2

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.20 Display interface unit

This section describes the DIU DC and AC electrical characteristics.

3.20.1 DIU DC electrical characteristics

This table provides the DIU DC electrical characteristics. Note: 1. For recommended operating conditions, see Table 3‐2.

3.20.2 DIU AC timing specifications

The table provides the output AC timing specifications for DIU interface. Note: 1. Display pixel clock frequency must be less than or equal to 1/ 4 of the platform clock. Figure 3‐52. DIU interface AC timing diagram Table 3‐101. DIU DC electrical characteristics (3.3V)1 Parameter Symbol Min Max Unit Notes Output high voltage (DVDD = min, IOH = –2 mA) VOH 2.4 – V – Output low voltage (DVDD = min, IOL = 2 mA) VOL –0 . 4V – Table 3‐102. DIU interface timing parameters Parameter Symbol Min Typ Max Unit Display pixel clock period tpcp 6.67 – – ns Display pixel clock high time tCKH 0.45 × tPCP 0.5 × tPCP 0.55 × tPCP ns LCD interface pixel clock low time tCKL 0.45 × tPCP 0.5 × tPCP 0.55 × tPCP ns Pixel data output setup with respect to pixel clock tDIUKHDS tDIUKLDS 1.2 – – ns Pixel data output hold with respect to pixel clock tDIUKHDX tDIUKLDX 1.2 – – ns VSYNC/ HSYNC/ DE output setup respect to pixel clock tDIUKHSS 1.2 – – ns VSYNC/ HSYNC/ DE output hold respect to pixel clock tDIUKHSX 3.8 – – ns tC K H tC K L tP C P tD IU K H D X tD IU K H D S tD IU K L D S tD IU K L D X tD IU K H S S tD IU K H S X DIU_LD DIU_CLK_OUT DIU_VSYNC/ DIU_HSYNC/ DIU_DE

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.21 TDM interface

This section describes the DC and AC electrical specifications for the TDM interface.

3.21.1 TDM DC Timing Specifications

This table provides the DC electrical characteristics for the TDM interface. Notes: 1. Note that the min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3‐2 2. Note that the symbol DVIN represents the input voltage of the supply. It is referenced in Recommended operating conditions 3. For recommended operating conditions, see Table 3‐2

3.21.2 TDM AC Timing Specifications

This table provides the input and output AC timing specifications for the TDM interface. Notes: 1. All values are based on a maximum TDM interface frequency of 50 MHz. 2. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference) (state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal tim‐ ing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 3‐103. TDM DC Electrical Characteristics(DVDD = 3.3V)3 Parameter Symbol Min Max Unit Notes Input high voltage VIH 0.7 * DVDD – V 1 Input low voltage VIL –0 . 2 * DVDD V 1 Input current (DVIN = 0V or DVIN = DVDD) IIN –± 5 0 µA2 Output high voltage (DVDD = min, IOH = –2 mA) VOH 2.4 – V – Output low voltage (DVDD = min, IOL = 2 mA) VOL –0 . 4V – Table 3‐104. DM AC Timing Specifications for 50 MHz1 Characteristic Symbol Min Max Unit Notes TDM_RXCLK/TDM_TXCLK tDM 20.0 – ns – TDM_RXCLK/TDM_TXCLK high pulse width tDM_HIGH 8.0 – ns – TDM_RXCLK/TDM_TXCLK low pulse width tDM_LOW 8.0 – ns – TDM all input setup time tDMIVKH 3.0 – ns 2 TDM_RXD hold time tDMRDIXKH 3.5 – ns – TDM_TFS/TDM_RFS input hold time tDMFSIXKH 2.0 – ns 2 TDM_TXCLK high to TDM_TXD output active tDM_OUTAC 4.0 – ns 2, 3 TDM_TXCLK high to TDM_TXD output valid tDMTKHOV – 14.0 ns 2, 3 TDM_TXD hold time tDMTKHOX 2.0 – ns – TDM_TXCLK high to TDM_TXD output high impedance tDM_OUTHI – 10.0 ns – TDM_TFS/TDM_RFS output valid tDMFSKHOV – 13.5 ns 2 TDM_TFS/TDM_RFS output hold time tDMFSKHOX 2.5 – ns 2

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] 3. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. TDMxTCK and TDMxRCK are shown using the rising edge. 4. Output values are based on 30 pF capacitive load. This figure shows the TDM receive signal timing. Figure 3‐53. TDM Receive Signals This figure shows the TDM transmit signal timing. Figure 3‐54. TDM Transmit Signals

3.22 High –speed serial interfaces (HSSI)

The chip features a serializer/deserializer (SerDes) interface to be used for high‐speed serial intercon‐ nect applications. The SerDes interface can be used for PCI Express, SATA, SGMII and QSGMII data transfers. This section describes the common portion of SerDes DC electrical specifications: the DC requirement for SerDes reference clocks. The SerDes data lane's transmitter (Tx) and receiver (Rx) reference circuits are also shown. TDMxRFS (output) TDMxRCK DMIVKHt TDMxRD DMIVKHt TDMxRFS tDMFSKHOV t DM tDMFSKHOX t DM_HIGH tDMRDIXKH t DMFSIXKH t DM_LOW TDMx TCK ~~~~ TDMxTFS (output) TDMxTD TDMxRCK tDMFSKHOV t DM tDMFSKHOX t DM_HIGH tDMTKHOV t DM_LOW TDMxTFS (input) tDMFSIXKHtDMIVKH DM_OUTHIt DMTKHOXt DM_OUTACt

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.22.1 Signal terms definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines the terms that are used in the description and specification of differential signals. This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This figure shows the waveform for either a transmitter output (SD_TX n_P and SD_TXn_N) or a receiver input (SD_RXn_P and SD_RXn_N). Each signal swings between A volts and B volts where A > B. Figure 3‐55. Differential voltage definitions for transmitter or receiver Using this waveform, the definitions are as shown in the following list. To simplify the illustration, the definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment: Single‐Ended Swing The transmitter output signals and the receiver input signals SD_TXn_P, SD_TXn_N, SD_RXn_P and SD_RXn_N each have a peak‐to‐peak swing of A ‐ B volts. This is also referred as each signal wire's sin‐ gle‐ended swing. Differential Output Voltage, VOD (or Differential Output Swing) The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VSD_TXn_P‐ VSD_TXn_N. The VOD value can be either positive or negative. Differential Input Voltage, VID (or Differential Input Swing) The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two com‐ plimentary input voltages: VSD_RXn_P‐ VSD_RXn_N. The VID value can be either positive or negative. Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as the differential peak voltage, VDIFFp = |A ‐ B| volts. A Volts B Volts SD_TXn_P or SD_RXn_P SD_TXn_N or SD_RXn_N Vcm= (A + B)/2 Differential swing, VID orVOD = A - B Differential peak voltage, VDIFFp = |A - B| Differential peak-to-peak voltage, VDIFFpp =2 x VDIFFp (not shown)

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Differential Peak‐to‐Peak, VDIFFp‐p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A ‐ B to ‐(A ‐ B) volts, the peak‐to‐peak value of the differential transmitter output sig‐ nal or the differential receiver input signal is defined as differential peak‐to‐peak voltage, VDIFFp‐p = 2 × VDIFFp = 2 × |(A ‐ B)| volts, which is twice the differential swing in amplitude, or twice of the differential peak. For example, the output differential peak‐to‐peak voltage can also be calculated as VTX‐ DIFFp‐p = 2 × |VOD|. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SD_TXn_N, for example) from the non‐inverting signal (SD_TXn_P, for example) within a differential pair. There is only one sig‐ nal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. See Figure 3‐60 as an example for differential waveform. Common Mode Voltage, Vcm The common mode voltage is equal to half of the sum of the voltages between each conductor of a bal‐ anced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSD_TXn+ VSD_TXn_B) ˜ 2 = (A + B) ˜ 2, which is the arithmeƟc mean of the two complimentary output voltages within a differ‐ ential pair. In a system, the common mode voltage may often differ from one component's output to the other's input. It may be different between the receiver input and driver output circuits within the same component. It is also referred to as the DC offset on some occasions. To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common mode voltage of 2.25V and outputs, TD and TD_B. If these outputs have a swing from 2.0V to 2.5V, the peak‐to‐peak voltage swing of each signal (TD or TD_B) is 500 mV p‐p, which is referred to as the single‐ended swing for each signal. Because the differential signaling envi‐ ronment is fully symmetrical in this example, the transmitter output's differential swing (VOD) has the same amplitude as each signal's single‐ended swing. The differential output signal ranges between 500 mV and –500 mV. In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp ) is 500 mV. The peak‐to‐peak differential voltage (VDIFFp ‐p) is 1000 mV p‐p.

3.22.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N. SerDes may be used for various combinations of the following IP blocks based on the RCW Configura‐ tion field SRDS_PRTCLn:

• S G M I I (1.25 and 3.125 Gbaud)
• PEX1/ 2/3/ 4 (2.5 and 5Gbps)
• A u r o r a (2.5 and 5 Gbps)
• S A T A 1 / 2 (1.5 and 3.0 Gbps)

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 The following sections describe the SerDes reference clock requirements and provide application information.

3.22.2.1 SerDes spread‐spectrum clock source recommendations

SDn_REF_CLKn_P/SDn_REF_CLKn_N are designed to work with spread‐spectrum clock for PCI Express protocol only with the spreading specification defined in Table 3‐106. When using spread‐spectrum clocking for PCI Express, both ends of the link partners should use the same reference clock. For best results, a source without significant unintended modulation must be used. For SATA protocol, the SerDes transmitter does not support spread‐spectrum clocking. The SerDes receiver does support spread ‐spectrum clocking on receive, which means the SerDes receiver can receive data correctly from a SATA serial link partner using spread‐ spectrum clocking. The spread‐spectrum clocking cannot be used if the same SerDes reference clock is shared with other non‐spread‐spectrum supported protocols. For example, if the spread‐ spectrum clocking is desired on a SerDes reference clock for PCI Express and the same reference clock is used for any other protocol such as SATA/SGMII due to the SerDes lane usage mapping option, spread‐spectrum clocking cannot be used at all. Notes: 1. At recommended operating conditions. See Table 3‐2. 2. Only down‐spreading is allowed.

3.22.2.2 SerDes reference clock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks. Figure 3‐56. Receiver of SerDes reference clocks Table 3‐105. SerDes spread‐spectrum clock source recommendations 1 Parameter Min Max Unit Notes Frequency modulation 30 33 kHz – Frequency spread +0 –0.5 % 2 Input amp 50Ω 50Ω SD1_REF_CLKn_P SD1_REF_CLKn_N

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] The characteristics of the clock signals are as follows:

• T h e SerDes transceivers core power supply voltage requirements (S1VDD) are as specified in Recommended operating conditions.
• T h e SerDes reference clock receiver reference circuit structure is as follows: –T h e SD1_REF_CLKn_P and SD1_REF_CLKn_N are internally AC‐coupled differential inputs as shown in Figure 3‐56. Each differential clock input (SD1_REF_CLKn_P or SD1_REF_CLKn_N) has on‐chip 50 termination to SGNDn followed by on‐chip AC‐coupling. –T h e external reference clock driver must be able to drive this termination. –T h e SerDes reference clock input can be either differential or single‐ended. See the differential mode and single‐ended mode descriptions below for detailed requirements.
• T h e maximum average current requirement also determines the common mode voltage range. –W h e n the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input is AC‐coupled on‐chip. –T h i s current limitaƟon sets the maximum common mode input voltage to be less than 0.4V (0.4V ˜ 50 = 8 mA) while the minimum common mode input level is 0.1V above SGNDn. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0‐0.8V), such that each phase of the differential input has a single‐ ended swing from 0V to 800 mV with the common mode voltage at 400 mV. –I f the device driving the SD1_REF_CLKn_P and SD1_REF_CLKn_N inputs cannot drive 50 to SGNDn DC or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC‐coupled off‐chip.
• T h e input amplitude requirement is described in detail in the following sections.

3.22.2.3 DC ‐level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below:

• Differential Mode –T h e input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak‐to‐peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single‐ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external DC‐coupled or AC‐coupled connection. –F o r an external DC‐coupled connection, as described in SerDes reference clock receiver characteristics, the maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 3‐57 shows the SerDes reference clock input requirement for DC‐coupled connection scheme.

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 3‐59. Single‐ended reference clock input DC requirements

3.22.2.4 AC requirements for SerDes reference clocks

This table lists the AC requirements for SerDes reference clocks for protocols running at data rates up to 5 Gb/s. clocks to be guaranteed by the customer's application design. Notes: 1. For recommended operating conditions, see Table 3‐2. 2. Caution: Only 100 and 125 have been tested.In‐between values do not work correctly with the rest of the system. 3. For PCI Express(2.5, 5 GT/s) 400 mV < SD_REF_CLKn input amplitude < 800 mV SD1_REF_CLKn_P SD1_REF_CLKn_N 0 V Table 3‐106. SD1_REF_CLKn_P and SD1_REF_CLKn_N input clock requirements (S1VDDn = 1.0V) 1 Parameter Symbol Min Typ Max Unit Notes frequency range tCLK_REF –1 0 0 / 1 2 5– M H z 2 SD1_REF_CLKn_P/SD1_REF_CLKn_N clock frequency tolerance tCLK_TOL –300 – 300 ppm 3 SD1_REF_CLKn_P/SD1_REF_CLKn_N clock frequency tolerance tCLK_TOL –100 – 100 ppm 4 reference clock duty cycle tCLK_DUTY 40 50 60 % 5 SD1_REF_CLKn_P/SD1_REF_CLKn_N max deterministic peak–to‐peak jitter at 10‐6 BER tCLK_DJ –– 4 2 p s – SD1_REF_CLKn_P/SD1_REF_CLKn_N total reference clock jitter at 10‐6 BER (peak‐to‐ peak jitter at refClk input) tCLK_TJ –– 8 6 p s 6 SD1_REF_CLKn_P/SD1_REF_CLKn_N 10 kHz to 1.5 MHz RMS jitter tREFCLK‐LF‐RMS ––3 p s RMS 7 SD1_REF_CLKn_P/SD1_REF_CLKn_N > 1.5 MHz to Nyquist RMS jitter tREFCLK‐HF‐RMS –– 3 . 1 p s RMS 7 rising/falling edge rate tCLKRR/tCLKFR 0.6 – 4 V/ns 9 Differential input high voltage VIH 150 – – mV 5 Differential input low voltage VIL – – –150 mV 5 Rising edge rate (SD1REF_CLKn_P) to falling edge rate (SD1_REF_CLKn_N) matching Rise‐Fall Matching – – 20 % 10, 11

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.22.3 SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane's transmitter and receiver. Figure 3‐62. SerDes transmitter and receiver reference circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below based on the application usage:

• P C I Express
• A u r o r a interface
• Serial ATA (SATA) interface
• S G M I I interface
• Q S G M I I interface Note that external AC‐coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in the specification of each protocol section.

3.22.4 PCI Express

This section describes the clocking dependencies, DC and AC electrical specifications for the PCI Express bus.

3.22.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance. 50Ω 50Ω SDn_RXn_P SDn_RXn_N Receiver100Ω Transmitter SDn_TXn_P SDn_TXn_N

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.22.4.2 PCI Express DC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this chip.

3.22.4.2.1 PCI Express DC physical layer transmitter specifications

This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s. This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all trans‐ mitters. The parameters are specified at the component pins. Note: 1. For recommended operating conditions, see Table 3‐2. This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all trans‐ mitters. The parameters are specified at the component pins. Note: 1. For recommended operating conditions, see Table 3‐2. Table 3‐107. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (X1VDD = 1.35V)1 Parameter Symbol Min Typical Max Units Notes Differential peak‐to‐peak output voltage VTX‐DIFFp‐p 800 1000 1200 mV VTX‐DIFFp‐p = 2 × I VTX‐D+ – VTX‐D‐ I De‐emphasized differential output voltage (ratio) VTX‐DE‐RATIO 3.0 3.5 4.0 dB Ratio of the VTX‐DIFFp‐p of the second and following bits after a transition divided by the VTX‐ DIFFp‐p of the first bit after a transition. DC differential transmitter impedance ZTX‐DIFF‐DC 80 100 120  Transmitter DC differential mode low Impedance Transmitter DC impedance ZTX‐DC 40 50 60  Required transmitter D+ as well as D‐ DC Impedance during all states Table 3‐108. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (X1VDD = 1.35 V)1 Parameter Symbol Min Typical Max Units Notes Differential peak‐to‐peak output voltage VTX‐DIFFp‐p 800 1000 1200 mV V TX‐DIFFp‐p = 2 × I VTX‐D+ ‐ VTX‐D‐ I Low power differential peak‐ to‐peak output voltage VTX‐DIFFp‐p_low 400 500 1200 mV V TX‐DIFFp‐p = 2 × I VTX‐D+ ‐ VTX‐D‐ I De‐emphasized differential output voltage (ratio) VTX‐DE‐RATIO‐3.5dB 3.0 3.5 4.0 dB Ratio of the VTX‐DIFFp‐p of the second and following bits after a transition divided by the VTX‐DIFFp‐p of the first bit after a transition. De‐emphasized differential output voltage (ratio) VTX‐DE‐RATIO‐6.0dB 5.5 6.0 6.5 dB Ratio of the VTX‐DIFFp‐p of the second and following bits after a transition divided by the VTX‐DIFFp‐p of the first bit after a transition. DC differential transmitter impedance ZTX‐DIFF‐DC 80 100 120  Transmitter DC differential mode low impedance Transmitter DC Impedance ZTX‐DC 40 50 60  Required transmitter D+ as well as D‐ DC impedance during all states

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.22.4.3 PCI Express DC physical layer receiver specifications

This section discusses the PCI Express DC physical layer receiver specifications for 2.5 GT/s and 5 GT/s. This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receiv‐ ers. The parameters are specified at the component pins. Notes: 1. Measured at the package pins with a test load of 50 to GND on each pin. 2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground. 4. For recommended operating conditions, see Table 3‐2. Table 3‐109. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SVDD = 1.0V)4 Parameter Symbol Min Typ Max Units Notes Differential input peak‐to‐peak voltage VRX‐DIFFp‐p 120 1000 1200 mV VRX‐DIFFp‐p = 2 × |VRX‐D+ ‐ VRX‐D‐| See Note 1. DC differential input impedance ZRX‐DIFF‐DC 80 100 120  Receiver DC differential mode impedance. See Note 2 DC input impedance ZRX‐DC 40 50 60  Required receiver D+ as well as D‐ DC Impedance (50 ± 20% tolerance). See Notes 1 and 2. Powered down DC input impedance ZRX‐HIGH‐IMP‐DC 50 – – k  Required receiver D+ as well as D‐ DC Impedance when the receiver terminations do not have power. See Note 3. Electrical idle detect threshold VRX‐IDLE‐DET‐ DIFFp‐p 65 – 175 mV Measured at the package pins of the receiver

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins. Notes: 1. Measured at the package pins with a test load of 50  to GND on each pin. 2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground. 4. For recommended operating conditions, see Table 3‐2.

3.22.4.4 PCI Express AC physical layer specifications

This section contains the AC specifications for the physical layer of PCI Express on this device.

3.22.4.4.1 PCI Express AC physical layer transmitter specifications

This section discusses the PCI Express AC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s. This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all trans‐ mitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 3‐110. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (SVDD = 1.0V)4 Parameter Symbol Min Typ Max Units Notes Differential input peak‐to‐peak voltage VRX‐DIFFp‐p 120 1000 1200 mV See Note 1. DC differential input impedance ZRX‐DIFF‐DC 80 100 120  Receiver DC differential mode impedance. See Note 2 DC input impedance ZRX‐DC 40 50 60  Required receiver D+ as well as D‐ DC Impedance (50 ± 20% tolerance). See Notes 1 and 2. Powered down DC input impedance ZRX‐HIGH‐IMP‐DC 50 – – k  Required receiver D+ as well as D‐ DC Impedance when the receiver terminations do not have power. See Note 3. Electrical idle detect threshold VRX‐IDLE‐DET‐ DIFFp‐p 65 – 175 mV VRX‐IDLE‐DET‐DIFFp‐p = 2 × |VRX‐D+ ‐ VRX‐D‐| Measured at the package pins of the receiver

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Notes: 1. Specified at the measurement point into a timing and voltage test load as shown in Figure 3‐64 and measured over any 250 consecutive transmitter UIs. 2. A TTX‐EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX‐JITTER‐MAX = 0.25 UI for the trans‐ mitter collected over any 250 consecutive transmitter UIs. The TTX‐EYE‐MEDIAN‐to‐MAX‐JITTER median is less than half of the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 3. The chip's SerDes transmitter does not have CTX built‐in. An external AC coupling capacitor is required. 4. For recommended operating conditions, see Table 3‐2. Table 3‐111. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4 Parameter Symbol Min Typ Max Units Notes Unit interval UI 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread‐spectrum clock dictated variations. Minimum transmitter eye width TTX‐EYE 0.75 – – UI The maximum transmitter jitter can be derived as TTX‐MAX‐JITTER = 1 ‐ TTX‐EYE = 0.25 UI. Does not include spread‐spectrum or RefCLK jitter. Includes device random jitter at 10‐12. See Notes 1 and 2. Maximum time between the jitter median and maximum deviation from the median TTX‐EYE‐MEDIAN‐ to‐ MAX‐JITTER – – 0.125 UI Jitter is defined as the measurement variation of the crossing points (VTX‐DIFFp‐p = 0V) in relation to a recovered transmitter UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI. See Notes 1 and 2. AC coupling capacitor C TX 75 – 200 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 3.

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all trans‐ mitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Notes: 1. Specified at the measurement point into a timing and voltage test load as shown in Figure 3‐64 and measured over any 250 consecutive transmitter UIs. 2. The chip's SerDes transmitter does not have CTX built‐in. An external AC coupling capacitor is required. 3. For recommended operating conditions, see Table 3‐2. Table 3‐112. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications3 Parameter Symbol Min Typ Max Units Notes Unit Interval UI 199.94 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not account for spread‐spectrum clock dictated variations. Minimum transmitter eye width TTX‐EYE 0.75 – – UI The maximum transmitter jitter can be derived as: TTX‐MAX‐JITTER = 1 ‐ TTX‐EYE = 0.25 UI. See Note 1. Transmitter RMS deterministic jitter > 1.5 MHz TTX‐HF‐DJ‐DD –– 0 . 1 5 p s Transmitter RMS deterministic jitter < 1.5 MHz TTX‐LF‐RMS –3 . 0– p s Reference input clock RMS jitter (< 1.5 MHz) at pin < 1 ps AC coupling capacitor C TX 75 – 200 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 2.

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

3.22.4.4.2 PCI Express AC physical layer receiver specifications

This section discusses the PCI Express AC physical layer receiver specifications for 2.5 GT/s and 5 GT/s. This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receiv‐ ers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Notes: 1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 3‐64 must be used as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 2. A TRX‐EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and inter‐ connect collected any 250 consecutive UIs. The TRX‐EYE‐MEDIAN‐to‐MAX‐JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with exper‐ imental and simulated data. 4. For recommended operating conditions, see Table 3‐2. Table 3‐113. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications4 Parameter Symbol Min Typ Max Units Notes Unit Interval UI 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread‐spectrum clock dictated variations. Minimum receiver eye width TRX‐EYE 0.4 – – UI The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX‐MAX‐ JITTER = 1 ‐ TRX‐EYE= 0.6 UI. See Notes 1 and 2. Maximum time between the jitter median and maximum deviation from the median. TRX‐EYE‐ MEDIAN‐ to‐ MAX‐JITTER –– 0 . 3 U I Jitter is defined as the measurement variation of the crossing points (VRX‐DIFFp‐p = 0V) in relation to a recovered transmitter UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI. See Notes 1, 2 and 3.

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Note: 1. For recommended operating conditions, see Table 3‐2. Figure 3‐63. Swept sinusoidal jitter mask

3.22.4.5 Test and measurement load

The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in the following figure. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/ board routing may benefit from D+ and D‐ not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and D‐ package pins. Table 3‐114. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications1 Parameter Symbol Min Typ Max Units Notes Unit Interval UI 199.40 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not account for spread‐spectrum clock dictated variations. Max receiver inherent timing error TRX‐TJ‐CC –– 0 . 4 U I The maximum inherent total timing error for common RefClk receiver architecture Max receiver inherent deterministic timing error TRX‐DJ‐DD‐CC –– 0 . 3 0 U I The maximum inherent deterministic timing error for common RefClk receiver architecture 20 dB decade ~ 3.0 ps RMS 1000 MHz100 MHz10 MHz1 .0 MHz0.1 MHz0.01 MHz 1 .0 UI 0.1 UI

0.03 MHz 100 MHz

Rj (ps RMS) Sj (UI PP)

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 3‐64. Test/measurement load

3.22.5 Aurora interface

This section describes the Aurora clocking requirements and its DC and AC electrical characteristics.

3.22.5.1 Aurora clocking requirements for SD1_REF_CLKn_P and SD1_REF_CLKn_N

For more information on these specifications, see SerDes reference clocks.

3.22.5.2 Aurora DC electrical characteristics

This section describes the DC electrical characteristics for the Aurora interface.

3.22.5.2.1 Aurora transmitter DC electrical characteristics

This table defines the Aurora transmitter DC electrical characteristics. Note: 1. For recommended operating conditions, see Table 3‐2.

3.22.5.2.2 Aurora receiver DC electrical characteristics

This table defines the Aurora receiver DC electrical characteristics for the Aurora interface. Notes: 1. For recommended operating conditions, see Table 3‐2. 2. Measured at receiver 3. DC Differential receiver impedance Transmitter silicon + package D + package pin D - package pin C = CTX C = CTX R = 50Ω R = 50 Ω Table 3‐115. Aurora transmitter DC electrical characteristics (XVDD = 1.35V) 1 Parameter Symbol Min Typical Max Unit Differential output voltage VDIFFPP 800 1000 1600 mV p‐p DC Differential transmitter impedance ZTX‐DIFF‐DC 80 100 120  Table 3‐116. Aurora receiver DC electrical characteristics (SVDD = 1.0V)1 Parameter Symbol Min Typical Max Unit Notes Differential input voltage V IN 200 – 1600 mV p‐p2 DC Differential receiver impedance ZRX‐DIFF‐DC 80 100 120  3

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3.22.5.3 Aurora AC timing specifications

This section describes the AC timing specifications for Aurora.

3.22.5.3.1 Aurora transmitter AC timing specifications

This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not included. Note: 1. For recommended operating conditions, see Table 3‐2.

3.22.5.3.2 Aurora receiver AC timing specifications

This table defines the Aurora receiver AC timing specifications. RefClk jitter is not included. Notes: 1. Measured at receiver 2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 3‐14. The sinusoidal jitter com‐ ponent is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. 3. For recommended operating conditions, see Table 3‐2. Table 3‐117. Aurora transmitter AC timing specifications1 Parameter Symbol Min Typical Max Unit Deterministic jitter J D –– 0 . 1 7 U I p‐p Total jitter J T –– 0 . 3 5 U I p‐p Unit interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps Unit interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps Table 3‐118. Aurora receiver AC timing specifications3 Parameter Symbol Min Typical Max Unit Notes Deterministic jitter tolerance J D –– 0 . 3 7 U I p‐p1 Combined deterministic and random jitter tolerance JDR –– 0 . 5 5 U I p‐p1 Total jitter tolerance J T –– 0 . 6 5 U I p‐p1 , 2 Bit error rate BER – – 10 ‐12 –– Unit Interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps – Unit Interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps –

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3.22.6 Serial ATA (SATA) interface

This section describes the DC and AC electrical specifications for the serial ATA (SATA) interface.

3.22.6.1 SATA DC electrical characteristics

This section describes the DC electrical characteristics for SATA.

3.22.6.1.1 SATA DC transmitter output characteristics

This table provides the differential transmitter output DC characteristics for the SATA interface at Gen1i/1m or 1.5 Gbits/s transmission. Notes: 1. Terminated by 50  load 2. DC impedance 3. For recommended operating conditions, see Table 3‐2. This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i/2m or 3.0 Gbits/s transmission. Notes: 1. Terminated by 50  load. 2. For recommended operating conditions, see Table 3‐2.

3.22.6.1.2 SATA DC receiver input characteristics

This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface. Notes: 1. Voltage relative to common of either signal comprising a differential pair 2. DC impedance 3. For recommended operating conditions, see Table 3‐2. Table 3‐119. Gen1i/1m 1.5G transmitter DC specifications (X1VDD = 1.35V)3 Parameter Symbol Min Typ Max Units Notes Tx differential output voltage VSATA_TXDIFF 400 500 600 mV p‐p1 Tx differential pair impedance ZSATA_TXDIFFIM 85 100 115  2 Table 3‐120. Gen 2i/2m 3G transmitter DC specifications (X1VDD = 1.35V)2 Parameter Symbol Min Typ Max Units Notes Transmitter differential output voltage VSATA_TXDIFF 400 – 700 mV p‐p1 Transmitter differential pair impedance ZSATA_TXDIFFIM 85 100 115  – Table 3‐121. Gen1i/1m 1.5 G receiver input DC specifications (SVDD = 1.0V)3 Parameter Symbol Min Typical Max Units Notes Differential input voltage VSATA_RXDIFF 240 500 600 mV p‐p1 Differential receiver input impedance ZSATA_RXSEIM 85 100 115  2 OOB signal detection threshold VSATA_OOB 50 120 240 mV p‐p–

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 This table provides the Gen2i/2m or 3 Gbits/s differential receiver input DC characteristics for the SATA interface. Notes: 1. Voltage relative to common of either signal comprising a differential pair 2. DC impedance 3. For recommended operating conditions, see Table 3‐2.

3.22.6.2 SATA AC timing specifications

This section discusses the SATA AC timing specifications.

3.22.6.2.1 AC requirements for SATA REF_CLK

The AC requirements for the SATA reference clock listed in this table are to be guaranteed by the cus‐ tomer's application design. Notes: 1. Caution:Only 100 and 125MHz have been tested. In‐between values do not work correctly with the rest of the system. 2. At RefClk input 3. In a frequency band from 150 kHz to 15 MHz at BER of 10‐12 4. Total peak‐to‐peak deterministic jitter must be less than or equal to 50 ps. 5. Measurement taken from differential waveform 6. For recommended operating conditions, see Table 3‐2. Table 3‐122. Gen2i/2m 3 G receiver input DC specifications (SVDD = 1.0V)3 Parameter Symbol Min Typical Max Units Notes Differential input voltage VSATA_RXDIFF 240 – 750 mV p‐p1 Differential receiver input impedance ZSATA_RXSEIM 85 100 115  2 OOB signal detection threshold VSATA_OOB 75 120 240 mV p‐p2 Table 3‐123. SATA reference clock input requirements6 Parameter Symbol Min Typ Max Unit Notes SD1_REF_CLKn_P/SD1_REF_CLKn_N frequency range tCLK_REF – 100/125 – MHz 1 SD1_REF_CLKn_P/SD1_REF_CLKn_N clock frequency tolerance tCLK_TOL –350 – +350 ppm – SD1_REF_CLKn_P/SD1_REF_CLKn_N reference clock duty cycle tCLK_DUTY 40 50 60 % 5 SD1_REF_CLKn_P/SD1_REF_CLKn_N cycle‐ to‐cycle clock jitter (period jitter) tCLK_CJ – – 100 ps 2 SD1_REF_CLKn_P/SD1_REF_CLKn_N total reference clock jitter, phase jitter (peak‐to‐peak) tCLK_PJ –50 – +50 ps 2, 3, 4

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3.22.6.3 AC transmitter output characteristics

This table provides the differential transmitter output AC characteristics for the SATA interface at Gen1i/1m or 1.5 Gbits/s transmission. The AC timing specifications do not include RefClk jitter. Notes: 1. Measured at transmitter output pins peak to peak phase variation, random data pattern 2. For recommended operating conditions, see Table 3‐2. This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not include RefClk jitter. Notes: 1. Measured at transmitter output pins peak‐to‐peak phase variation, random data pattern 2. For recommended operating conditions, see Table 3‐2. Table 3‐124. Gen1i/1m 1.5 G transmitter AC specifications2 Parameter Symbol Min Typ Max Unit Notes Channel speed tCH_SPEED – 1.5 – Gbps – Unit Interval TUI 666.4333 666.6667 670.2333 ps – Total jitter data‐data 5 UI USATA_TXTJ5UI –– 0 . 3 5 5 U I p‐p1 Total jitter, data‐data 250 UI USATA_TXTJ250UI –– 0 . 4 7 U I p‐p1 Deterministic jitter, data‐data 5 UI USATA_TXDJ5UI – – 0.175 UI p‐p1 Deterministic jitter, data‐data 250 UI USATA_TXDJ250UI – – 0.22 UI p‐p1 Table 3‐125. Gen 2i/2m 3 G transmitter AC specifications2 Parameter Symbol Min Typ Max Unit Notes Channel speed tCH_SPEED – 3.0 – Gbps – Unit Interval TUI 333.2167 333.3333 335.1167 ps – Total jitter fC3dB = fBAUD ÷ 500 USATA_TXTJfB/500 –– 0 . 3 7 U I p‐p1 Total jitter fC3dB = fBAUD ÷ 1667 USATA_TXTJfB/1667 – – 0.55 UI p‐p1 Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_TXDJfB/500 –– 0 . 1 9 U I p‐p1 Deterministic jitter, fC3dB = fBAUD ÷ 1667 USATA_TXDJfB/1667 –– 0 . 3 5 U I p‐p1

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

3.22.6.4 AC differential receiver input characteristics

This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing specifications do not include RefClk jitter. Notes: 1. Measured at receiver. 2. For recommended operating conditions, see Table 3‐2. This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not include RefClk jitter. Notes: 1. Measured at receiver 2. For recommended operating conditions, see Table 3‐2. 4. HARDWARE DESIGN CONSIDERATIONS

4.1 System clocking

This section describes the PLL configuration of the chip.

4.1.1 PLL characteristics

Characteristics of the chip's PLLs include the following:

• T h e r e are two core cluster PLLs which generate a clock for each core cluster from the externally supplied SYSCLK input.
• C o r e cluster Group A PLL 1 and Core cluster group A PLL 2
• T h e frequency ratio between each of the core cluster PLLs and SYSCLK is selected using the configuration bits as described in Core cluster to SYSCLK PLL ratio. The frequency for each core cluster is selected using the configuration bits as described in Table 4‐6. Table 3‐126. Gen 1i/1m 1.5G receiver AC specifications2 Parameter Symbol Min Typ Max Unit Notes Unit Interval TUI 666.4333 666.6667 670.2333 ps – Total jitter data‐data 5 UI USATA_RXTJ5UI –– 0 . 4 3 U I p‐p1 Total jitter, data‐data 250 UI USATA_RXTJ250UI –– 0 . 6 0 U I p‐p1 Deterministic jitter, data‐data 5 UI USATA_RXDJ5UI – – 0.25 UI p‐p1 Deterministic jitter, data‐data 250 UI USATA_RXDJ250UI –– 0 . 3 5 U I p‐p1 Table 3‐127. Gen 2i/2m 3G receiver AC specifications2 Parameter Symbol Min Typical Max Unit Notes Unit Interval TUI 333.2167 333.3333 335.1167 ps – Total jitter fC3dB = fBAUD ÷ 500 USATA_RXTJfB/500 –– 0 . 6 0 U I p‐p1 Total jitter fC3dB = fBAUD ÷ 1667 USATA_RXTJfB/1667 –– 0 . 6 5 U I p‐p1 Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_RXDJfB/500 –– 0 . 4 2 U I p‐p1 Deterministic jitter, fC3dB = fBAUD ÷ 1667 USATA_RXDJfB/1667 –– 0 . 3 5 U I p‐p1

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• T h e platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Platform to SYSCLK PLL ratio.
• C l u s t e r group A generates an asynchronous clock for eSDHC SDR mode from CGA PLL1 or CGA PLL2. Described in eSDHC SDR mode clock select.
• T h e DDR block PLL generates an asynchronous DDR clock from the externally supplied DDRCLK input. The frequency ratio is selected using the Memory Controller Complex PLL multiplier/ratio configuration bits as described in DDR controller PLL ratios.
• S e r D e s block has 2 PLLs which generate a core clock from their respective
• externally supplied SD1_REF_CLKn_P/SD1_REF_CLKn_N inputs. The frequency ratio is selected using the SerDes PLL RCW configuration bits as described in SerDes PLL ratio.
• W h e n using Single Oscillator Source clocking mode, a single onboard oscillator can provide the reference clock (100MHz) to all the PLL's that is, Platform PLL, Core Cluster PLL's, DDR PLL, USB PLL and Serdes PLL's.

4.1.2 Clock ranges

This table provides the clocking specifications for the processor core, platform, memory, and inte‐ grated flash controller. Notes: 1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum operating frequencies 2. The core cluster can run at cluster group PLL/1 and PLL/ 2. For the PLL/1 case, the minimum frequency is 800 MHz. With a minimum cluster group PLL frequency of 800 MHz, this results in a minimum allowable core cluster frequency of 400 MHz for PLL/ 2. Frequency provided to the e5500 cluster after any dividers must always be greater than or equal to the platform frequency. For the case of the minimum platform frequency = 400 MHz, the minimum core cluster frequency is 400 MHz. 3. The memory bus clock speed is half the DDR3L/DDR4 data rate. 4. The memory bus clock speed is dictated by its own PLL. 5. The integrated flash controller (IFC) clock speed on IFC_CLK[0:1] is determined by the IFC module input clock (platform clock / 2) divided by the IFC ratio programmed in CCR[CLKDIV]. 6. See the chip reference manual for more information. 7. 1200MHz bin cannot support Gen2, x4 PCIe. The minimum platform frequency should meet the requirements in Mini‐ mum platform frequency requirements for high‐speed interfaces. 8. "Single Oscillator Source" Reference clock mode supports differential reference clock pair frequency of 100MHz. Table 4‐1. Processor, platform, and memory clocking specifications Characteristic Maximum processor core frequency Unit Notes

1200 MHz 1400 MHz 1500 MHz

Core cluster group PLL frequency 800 1200 800 1400 800 1500 MHz 1, 2 Core cluster frequency 400 1200 400 1400 400 1500 MHz 2 Platform clock frequency 300 500 300 600 300 600 MHz 1, 7 Memory bus clock frequency (DDR3L) 500 800 500 800 500 800 MHz 1, 3, 4 Memory bus clock frequency (DDR4) 625 800 625 800 625 800 MHz 1, 3, 4 IFC clock frequency – 100 – 100 – 100 MHz 5 FMAN 300 500 300 600 300 600 MHz 6

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018

4.1.2.1 DDR clock ranges

The DDR memory controller can run only in asynchronous mode, where the memory bus is clocked with the clock provided on the DDRCLK input pin, which has its own dedicated PLL. This table provides the clocking specifications for the memory bus. Notes: 1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK clock ratio settings must be chosen such that the resulting SYSCLK frequency, core frequency, and platform frequency do not exceed their respective maximum or minimum operat‐ ing frequencies. See Platform to SYSCLK PLL ratio, and Core cluster to SYSCLK PLL ratio, and DDR controller PLL ratios, for ratio settings. 2. The memory bus clock refers to the chip's memory controllers' D1_MCK[0:1] and D1_MCK[0:1]_B output clocks, running at half of the DDR data rate. 3. The memory bus clock speed is dictated by its own PLL. See DDR controller PLL ratios. 4. Minimum Frequency supported by DDR4 is 1250MT/s

4.1.3 Platform to SYSCLK PLL ratio

This table lists the allowed platform clock to SYSCLK ratios. Because the DDR operates asynchronously, the memory‐bus clock‐frequency is decoupled from the platform bus frequency. For all valid platform frequencies supported on this chip, set the RCW Configuration field SYS_PLL_CFG = 0b00. Table 4‐2. Memory bus clocking specifications Characteristic Min Max Unit Notes Memory bus clock frequency DDR3L 500 800 MHz 1, 2, 3, 4 DDR4 625 800 Table 4‐3. Platform to SYSCLK PLL ratios Binary Value of SYS_PLL_RAT Platform:SYSCLK Ratio 0_0011 3:1 0_0100 4:1 0_0101 5:1 0_0110 6:1 0_0111 7:1 0_1000 8:1 0_1001 9:1 All Others Reserved

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4.1.4 Core cluster to SYSCLK PLL ratio

The clock ratio between SYSCLK and each of the core cluster PLLs is determined by the binary value of the RCW Configuration field CGA_PLLn_RAT. This table describes the supported ratios. For all valid core cluster frequencies supported on this chip, set the RCW Configuration field CGA_PLLn_CFG = 0b00. This table lists the supported asynchronous core cluster to SYSCLK ratios.

4.1.5 Core complex PLL select

The clock frequency of each core cluster is determined by the binary value of the RCW Configuration field Cn_PLL_SEL. These tables describe the selections available to each core cluster, where each indi‐ vidual core cluster can select a frequency from their respective tables. NOTE There is a restriction that requires that the frequency provided to the e5500 core cluster after any dividers must always be greater than half of the platform frequency. Special care must be used when selecting the /2 outputs of a cluster PLL in which this restriction is observed. Table 4‐4. Core cluster PLL to SYSCLK ratios Binary value of CGA_PLLn_RAT(n=1 or 2) Core cluster:SYSCLK Ratio 00_0110 6:1 00_0111 7:1 00_1000 8:1 00_1001 9:1 00_1010 10:1 00_1011 11:1 00_1100 12:1 00_1101 13:1 00_1110 14:1 00_1111 15:1 01_0000 16:1 01_0010 18:1 01_0100 20:1 01_0110 22:1 01_1001 25:1 01_1010 26:1 01_1011 27:1 All others Reserved

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4.1.6 DDR controller PLL ratios

The DDR memory controller operates asynchronous to the platform. In asynchronous DDR mode, the DDR data rate to DDRCLK ratios supported are listed in the following table. This ratio is determined by the binary value of the RCW Configuration field MEM_PLL_RAT (bits 10‐15). The RCW Configuration field MEM_PLL_CFG (bits 8‐9) must be set to MEM_PLL_CFG = 0b00 for all valid DDR PLL reference clock frequencies supported on this chip. Table 4‐5. Core cluster PLL select Binary Value of Cn_PLL_SEL for n=1‐4C o r e cluster ratio

0000 CGA PLL1 /1

0001 CGA PLL1 /2

0100 CGA PLL2 /1

0101 CGA PLL2 /2

Table 4‐6. DDR clock ratio Binary value of MEM_PLL_RAT DDR data‐rate:DDRCLK ratio Maximum supported DDR data‐rate (MT/s) 00_1000 8:1 1066 00_1010 10:1 1333 00_1011 11:1 1465 00_1100 12:1 1600 00_1101 13:1 1300 00_1110 14:1 1400 00_1111 15:1 1500 01_0000 16:1 1600 1_0100 20:1 1333 1_1000 24:1 1600 All Others Reserved ‐

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4.1.7 SerDes PLL ratio

The clock ratio between each of the two SerDes PLLs and their respective externally supplied SD1_REF_CLKn_P/SD1_REF_CLKn_N inputs is determined by a set of RCW Configuration fields ‐ SRDS_PRTCL_S1, SRDS_PLL_REF_CLK_SEL_S1, and SRDS_DIV_*_S1 as shown in this table. Notes: 1. A spread‐spectrum reference clock is permitted for PCI Express. However, if any other high‐speed interface such as SATA, SGMII, SGMII 2.5G, 1000Base‐KX, is used concurrently on the same SerDes PLL, spread‐spectrum clocking is not permitted. 2. SerDes lanes configured as SATA initially operate at 3.0 Gbps. 1.5 Gbps operation may later be enabled through the SATA IP itself. It is possible for software to set each SATA at different rate. Table 4‐7. Valid SerDes RCW encodings and reference clocks SerDes protocol (given lane) Valid reference clock frequency Legal setting for SRDS_PRTCL_S1 Legal setting for SRDS_PLL_RE F_CLK_SEL_S1 Legal setting for SRDS_DIV_*_S1 Notes High‐speed serial interfaces PCI Express 2.5 Gbps (doesn't negotiate upwards) 100 MHz Any PCIe 0b0: 100 MHz 2b10: 2.5 G1

125 MHz 0b1: 125 MHz 1

(can negotiate up to 5 Gbps) 100 MHz Any PCIe 0b0: 100 MHz 2b01: 5.0 G1 SATA (1.5 or 3 Gbps) 100 MHz Any SATA 0b0: 100 MHz Don't care 2

125 MHz 0b1: 125 MHz

Debug (2.5 Gbps) 100 MHz Aurora @ 2.5 /5 Gbps 0b0: 100 MHz 0b1: 2.5 G ‐

125 MHz 0b1: 125 MHz ‐

Debug (5 Gbps) 100 MHz Aurora @ 2.5 /5 Gbps 0b0: 100 MHz 0b0: 5.0 G ‐ SGMII (1.25 Gbps) 100 MHz SGMII @ 1.25 Gbps 1000Base‐KX @ 1.25 Gbps 0b0: 100 MHz Don't care ‐ 2.5G SGMII (3.125 Gbps) 125 MHz SGMII @ 3.125 Gbps 0b0: 125 MHz Don't care ‐ SerDes protocol (given lane) Valid reference clock frequency Legal setting for SRDS_PRTCL_S1 Legal setting for SRDS_PLL_RE F_CLK_SEL_S1 Legal setting for SRDS_DIV_*_S1 Notes

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 4.1.8 eSDHC SDR mode clock select The eSDHC SDR mode is asynchronous to the platform. This table describes the clocking options that may be applied to the eSDHC SDR mode. The clock selec‐ tion is determined by the binary value of the RCW Clocking Configuration field HWA_CGA_M1_CLK_SEL. Notes: 1. For asynchronous mode, max frequency, see table "Processor clocking specifications" in the chip ref‐ erence manual. 2. For SDR104 and HS200 modes, CGA1 PLL should be set to provide a minimum of 1200MHz. 3. For SDR50 mode, Cluster PLL should be set to provide a minimum of 600MHz

4.1.9 Frequency options

This section discusses interface frequency options.

4.1.9.1 SYSCLK and core cluster frequency options

This table shows the expected frequency options for SYSCLK and core cluster frequencies. Table 4‐8. eSDHC SDR mode clock select Binary value of HWA_CGA_M1_CLK_SEL eSDHC SDR mode frequency1 0b000 Reserved 0b001 Cluster group A PLL 1/1 0b010 Cluster group A PLL 1/ 2 0b011 Cluster group A PLL 1/3 0b100 Cluster group A PLL 1/ 4 0b101 Reserved 0b110 Cluster group A PLL 2/ 2 0b111 Cluster group A PLL 2/3 Table 4‐9. SYSCLK and core cluster frequency options Core cluster: SYSCLK Ratio SYSCLK (MHz) Core cluster Frequency (MHz)1 6:1 800 7:1 875 933 8:1 800 1000 1067 9:1 900 1125 1200 10:1 1000 1250 1333 11:1 1100 1375 12:1 800 1200 1500 13:1 832 867 1300 14:1 896 933 1400

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Notes: 1. Core cluster frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed) 2. When using Single Source clocking only 100MHz input is available.

4.1.9.2 SYSCLK and platform frequency options

This table shows the expected frequency options for SYSCLK and platform frequencies. Notes: 1. Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed) 2. When using Single source clocking, only 100MHz options are valid 15:1 960 1000 1500 16:1 1024 1067 18:1 1152 1200 20:1 1280 1333 21:1 1344 1400 Table 4‐9. SYSCLK and core cluster frequency options (Continued) Table 4‐10. SYSCLK and platform frequency options Platform: SYSCLK Ratio SYSCLK (MHz) Platform Frequency (MHz)(1) 3:1 300 375 400 4:1 400 500 533 5:1 320 333 500 6:1 384 400 600 7:1 448 467 8:1 512 533 Platform Frequency (MHz) (1) 9:1 576 600

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4.1.9.3 DDRCLK and DDR data rate frequency options

This table shows the expected frequency options for DDRCLK and DDR data rate frequencies. Notes: 1. DDR data rate values are shown rounded up to the nearest whole number (decimal place accuracy removed) 2. When using Single Source clocking, only 100MHz options are available. 3. Minimum Frequency supported by DDR4 is 1250MT/s

4.1.9.4 SYSCLK and eSDHC High Speed modes frequency options

These table shows the expected frequency options for SYSCLK and eSDHC High Speed modes. Notes: 1. Resultant frequency values are shown rounded up to the nearest whole number (decimal place accu‐ racy removed) 2. For Low speed operation, eSDHC is clocked from Platform PLL and does not use CGA PLL. Table 4‐11. DDRCLK and DDR data rate frequency options DDR data rate: DDRCLK Ratio DDRCLK (MHz) DDR Data Rate (MT/s)1 8:1 1000 1066 10:1 1000 1250 1333 11:1 1100 1375 1465 12:1 1200 1500 1600 13:1 1300 14:1 1400 15:1 1000 1500 16:1 1024 1067 1600 20:1 1280 1333 24:1 1536 1600 Table 4‐12. SYSCLK and eSDHC High Speed mode frequency options (clocked by CGA PLL1 /1) Core cluster: SYSCLK Ratio SYSCLK (MHz) Resultant Frequency (MHz)1 9:1 1200 12:1 1200 18:1 1152 1200

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4.1.9.5 Minimum platform frequency requirements for high‐speed interfaces

The platform clock frequency must be considered for proper operation of high‐speed interfaces as described below. For proper PCI Express operation, the platform clock frequency must be greater than or equal to: Figure 4‐1. Gen 1 PEX minimum platform frequency Figure 4‐2. Gen 2 PEX minimum platform frequency See section "Link Width," in the chip reference manual for PCI Express interface width details. Note that "PCI Express link width" in the above equation refers to the negotiated link width as the result of PCI Express link training, which may or may not be the same as the link width POR selection. It refers to the widest port in use, not the combined width of the number ports in use. For instance, if two x4 PCIe Gen2 ports are in use, 527MHz platform frequency is needed to support by using Gen 2 equation (527 x 4 / 4, not 527 x 4 x 2 / 4). NOTE 1. Platform needs to run at a minimum frequency of 527MHz for PEX in Gen2 speed with x4 link width. 2. Platform needs to run at a minimum frequency of 400MHz for PEX in Gen2 speed

4.2 Power supply design

4.2.1 Core and platform supply voltage filtering

The VDD, VDDC supply is normally derived from a high current capacity linear or switching power sup‐ ply which can regulate its output voltage very accurately despite changes in current demand from the chip within the regulator's relatively low bandwidth. Several bulk decoupling capacitors must be dis‐ tributed around the PCB to supply transient current demand above the bandwidth of the voltage regulator. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. However, customers should work directly with their power regulator ven‐ dor for best values and types of bulk capacitors. As a guideline for customers and their power regulator vendors, e2v recommends that these bulk capacitors be chosen to maintain the positive transient power surges to less than 1.0V+50 mV (negative transient undershoot should comply with specification of 1.0V‐30mV) for current steps of up to 10A with a slew rate of 12 A/us. These bulk decoupling capacitors will ideally supply a stable voltage for current transients into the megahertz range. Above that, see Decoupling recommendations for further decoupling recommendations.

527 MHz x (PCI Express link width)

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4.2.2 PLL power supply filtering

Each of the PLLs described in System clocking is provided with power through independent power sup‐ ply pins (AVDD_PLAT, AVDD_CGA1, AVDD_CGA2, AVDD_D1 and AVDD_SD1_PLLn). AVDD_PLAT, AVDD_CGA1, AVDD_CGA2 and AVDD_D1 voltages must be derived directly from a 1.8 V voltage source through a low frequency filter scheme. AVDD_SD1_PLLn voltages must be derived directly from the X1VDD source through a low frequency fil‐ ter scheme. The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in Figure 4‐3, one for each of the AVDD pins. By providing independent fil‐ ters to each PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLL's resonant frequency range from a 500 kHz to 10 MHz range. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the footprint, without the inductance of vias. This figure shows the PLL power supply filter circuit. Where:

• R = 5 ± 5%
• C 1 = 10 µF ± 10%, 0603, X5R, with ESL = 0.5 nH
• C 2 = 1.0 µF ± 10%, 0402, X5R, with ESL = 0.5 nH NOTE A higher capacitance value for C2 may be used to improve the filter as long as the other C2 param‐ eters do not change (0402 body, X5R, ESL = 0.5 nH). NOTE Voltage for AVDD is defined at the input of the PLL supply filter and not the pin of AVDD. Figure 4‐3. PLL power supply filter circuit The AVDD_SD1_PLLn signals provides power for the analog portions of the SerDes PLL. To ensure sta‐ bility of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 4‐4. For maximum effectiveness, the filter circuit is placed as closely as possi‐ ble to the AVDD_SD1_PLLn balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SD1_PLLn balls. The 0.003‐µF capacitors closest to the balls, fol‐ lowed by a 4.7‐µF and 47‐µF capacitor, and finally the 0.33 resistor to the board supply plane. The capacitors are connected from AVDD_SD1_PLLn to the ground plane. Use ceramic chip capacitors with the highest possible self‐resonant frequency. All traces should be kept short, wide, and direct. 1 .8 V source R C1 C2 GND Low-ESL surface-mount capacitors AVDD_PLAT, AVDD_CGA1, AVDD_CGA2, AVDD_D1

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Note the following: Figure 4‐4. SerDes PLL power supply filter circuit

• AVDD_SDn_PLLn should be a filtered version of XnVDD.
• Signals on the SerDes interface are fed from the X1VDD power plane.
• V o l t a g e for AVDD_SD1_PLLn is defined at the PLL supply filter and not the pin of AVDD_SD1_PLLn.
• A 47‐µF 0805 XR5 or XR7, 4.7‐µF 0603, and 0.003‐µF 0402 capacitor are recommended. The size and material type are important. A 0.33‐ ± 1% resistor is recommended.
• T h e r e needs to be dedicated analog ground, AGND_SD1_PLLn for each AVDD_SD1_PLLn pin up to the physical local of the filters themselves.

4.2.3 S1VDD power supply filtering

S1VDD should be supplied by a linear regulator. An example solution for S1VDD filtering, is illustrated in Figure 4‐5. The component values in this exam‐ ple filter are system dependent and are still under characterization, component values may need adjustment based on the system or environment noise. Where:

• C 1 = 0.003 µF ± 10%, X5R, with ESL = 0.5 nH
• C 2 and C3 = 2.2 µF ± 10%, X5R, with ESL = 0.5 nH
• F 1 and F2 = 120 at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)
• B u l k and decoupling capacitors are added, as needed, per power supply design. Figure 4‐5. SVDD power supply filter circuit Note the following:
• R e f e r to Power‐on ramp rate, for maximum S1VDD power‐up ramp rate.
• T h e r e needs to be enough output capacitance or a soft start feature to assure ramp rate requirement is met.
• T h e ferrite beads should be placed in parallel to reduce voltage droop.
• B e s i d e s a linear regulator, a low noise dedicated switching regulator can also be used. 10 mVp‐p, 50kHz ‐ 500MHz is the noise goal. 1VDD 0.33Ω AV DD_SD1_PLL 47 µF 4.7 µF 0.003 µF AGND_SD1_PLLn S1VDD Linear regulator output C1 C2 C3 GND Bulk and decoupling capacitors

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4.2.4 X1VDD power supply filtering

X1VDD may be supplied by a linear regulator or sourced by a filtered G1VDD. Systems may design in both options to allow flexibility to address system noise dependencies. However, for initial system bring‐up, the linear regulator option is highly recommended. An example solution for X1VDD filtering, where X1VDD is sourced from a linear regulator, is illustrated in Figure 4‐6. The component values in this example filter are system dependent and are still under characterization, component values may need adjustment based on the system or environment noise. Where:

• C 1 = 0.003 µF ± 10%, X5R, with ESL = 0.5 nH
• C 2 and C3 = 2.2 µF ± 10%, X5R, with ESL = 0.5 nH
• F 1 and F2 = 120 at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)
• B u l k and decoupling capacitors are added, as needed, per power supply design. Figure 4‐6. X1VDD power supply filter circuit Note the following:
• S e e Power‐on ramp rate for maximum X1VDD power‐up ramp rate.
• T h e r e needs to be enough output capacitance or a soft‐start feature to assure ramp rate requirement is met.
• T h e ferrite beads should be placed in parallel to reduce voltage droop.
• B e s i d e s a linear regulator, a low‐noise, dedicated switching regulator can be used. 10 mVp‐p, 50 kHz ‐ 500 MHz is the noise goal.

4.2.5 USB_HVDD and USB_OVDD power supply filtering

USB_HVDD and USB_OVDD must be sourced by a filtered 3.3 V and 1.8 V voltage source using a star connection. An example solution for USB_HVDD and USB_OVDD filtering, where USB_HVDD and USB_OVDD are sourced from a 3.3 V and 1.8 V voltage source, is illustrated in the following figure. The component values in this example filter is system dependent and are still under characterization, com‐ ponent values may need adjustment based on the system or environment noise. Where:

• C 1 = 0.003 µF ± 10%, X5R, with ESL = 0.5 nH
• C 2 and C3 = 2.2 µF ± 10%, X5R, with ESL = 0.5 nH
• F 1 = 120 at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)
• B u l k and decoupling capacitors are added, as needed, per power supply design. X1VDD C1 C2 C3 GND Bulk and decoupling capacitors Linear regulator output

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 4‐7. USB_HVDD and USB_OVDD power supply filter circuit

4.2.6 USB_SVDD power supply filtering

USB_SVDD must be sourced by a filtered VDD or VDDCusing a star connection. An example solution for USB_SVDD filtering, where USB_SVDD is sourced from VDD, is illustrated in the following figure. The component values in this example filter is system dependent and are still under characterization, com‐ ponent values may need adjustment based on the system or environment noise. Where:

• C 1 = 2.2 µF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)
• F 1 = 120 at 100‐MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
• B u l k and decoupling capacitors are added, as needed, per power supply design. Figure 4‐8. USB_SVDD power supply filter circuit

4.3 Decoupling recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the chip system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, VDDC, CVDD, OnVDD, DVDD, EVDD, GnVDD, and LnVDD pin of the device. These decoupling capacitors should receive their power from separate VDD, CVDD, OnVDD, DVDD, EVDD, GnVDD, LnVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a stan‐ dard escape pattern. Others may surround the part. These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capaci‐ tors should be used to minimize lead inductance, preferably 0402 or 0201 sizes. As presented in Core and platform supply voltage filtering, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, VDDC and other planes (for example, CVDD, OnVDD, DVDD, EVDD, GnVDD, and LnVDD), to enable quick recharging of the smaller chip capacitors. C1 C2 C3 GND Bulk and decoupling capacitors USB_HVDD or USB_OVDD

3.3 V or

1 .8 V source USB_SVDD VDD GND Bulk and decoupling capacitors C1 Bulk and decoupling capacitors / VDDC

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4.4 SerDes block power supply decoupling recommendations

The SerDes block requires a clean, tightly regulated source of power (S1VDD and X1VDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. NOTE Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. 1. The board should have at least 1 x 0.1‐uF SMT ceramic chip capacitor placed as close as possi‐ ble to each supply ball of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. 2. Between the device and any SerDes voltage regulator there should be a lower bulk capacitor for example a 10‐uF, low ESR SMT tantalum or ceramic and a higher bulk capacitor for example a 100uF ‐ 300‐uF low ESR SMT tantalum or ceramic capacitor.

4.5 Connection recommendations

The following is a list of connection recommendations:

• T o ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unless otherwise noted in this document, all unused active low inputs should be tied to VDD, OnVDD, DVDD, GnVDD, EVDD, CVDD and LnVDD as required. All unused active high inputs should be connected to GND. All NC (no‐connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OnVDD, DVDD, GnVDD, LnVDD , EVDD , CVDD and GND pins of the device.
• T h e TEST_SEL_B pin must be pulled to O1VDD through a 100‐ohm to 1k‐ohm resistor for T1042 and tied to ground for 2 core T1022.
• T h e chip has temperature diodes on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461Aô). If a temperature diode monitoring device is not connected, these pins may be connected to test points or grounded.

4.5.1 Legacy JTAG configuration signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 4‐10. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. Boundary‐scan testing is enabled through the JTAG interface signals. The TRST_B signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors built on Power Architecture tech‐ nology. The device requires TRST_B to be asserted during power‐on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation. While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST_B during the power‐on reset flow. Simply tying TRST_B to PORESET_B is not practical because the JTAG interface is also used for accessing the common on‐chip processor (COP), which implements the debug interface to the chip.

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert PORESET_B or TRST_B in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push‐button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 4‐10 allows the COP port to independently assert PORESET_B or TRST_B, while ensuring that the target can drive PORESET_B as well. The COP interface has a standard header, shown in Figure 4‐9, for connection to the target system, and is based on the 0.025" square‐post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examina‐ tion/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header; so emulator vendors have issued many differ‐ ent pin numbering schemes. Some COP headers are numbered top‐to‐ bottom then left‐to‐right, while others use left‐to‐right then top‐to‐bottom. Still others number the pins counter‐clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal placement recommended in Figure 4‐9 is common to all known emulators.

4.5.1.1 Termination of unused signals

If the JTAG interface and COP header will not be used, e2v recommends the following connections:

• T R S T _ B should be tied to PORESET_B through a 0 k isolation resistor so that it is asserted when the system reset signal (PORESET_B) is asserted, ensuring that the JTAG scan chain is initialized during the power‐on reset flow. e2v recommends that the COP header be designed into the system as shown in Figure 4‐10. If this is not possible, the isolation resistor will allow future access to TRST_B in case a JTAG interface may need to be wired onto the system in future debug situations.
• N o pull‐up/pull‐down is required for TDI, TMS or TDO.

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 4‐9. Legacy COP Connector Physical Pinout KEY No pi n COP_TD O COP_TD I NC COP_TC K COP_TM S COP_SRESET_B COP_HRESET_B COP_CHKS TP_OUT_B GND NC NC NC COP_TR S T_B COP_VDD_SENSE COP_CHKS TP_IN_B

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 4‐10. Legacy JTAG Interface Connection Notes: 1. The COP port and target board should be able to independently assert PORESET_B and TRST_B to the processor in order to fully control the processor as shown here. 2. Populate this with a 10 Ù resistor for short‐circuit/current‐limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a no‐connect, some debug tools may use pin 12 as an additional GND pin for improved sig‐ nal integrity. 5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to posi‐ tion B. COP connect or physical pinout 10 k NC COP_VDD_SENSE 2 COP_TR S T_B 10 k 10 k 10 k 10 k 10 k 1 k HRESET_B 6 PORESET_B 1 TRS T_B 1 TMS TDO TDI TCK OV DD 7HRESET_B PORESET_B Fr om target board sour ces (if an y) COP_HRESET_B B A KEY No pi n 10 k NC NC COP_TCK COP_TDI COP_TDO COP_TMS COP_CHKS TP_IN_B Sy stem logic COP_SRESET_B COP_CHKS TP_OUT_B COP header 143 CKS TP_OUT_B 10 k

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 6. Asserting HRESET_B causes a hard reset on the device 7. This is an open‐drain output gate.

4.5.2 Aurora configuration signals

Correct operation of the Aurora interface requires configuration of a group of system control pins as demonstrated in the figures below. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. e2v recommends that the Aurora 34 pin duplex connector be designed into the system as shown in Fig‐ ure 4‐13 or the 70 pin duplex connector be designed into the system as shown in Figure 4‐14. If the Aurora interface will not be used, e2v recommends the legacy COP header be designed into the system as described in . Figure 4‐11. Aurora 34 pin connector duplex pinout TX0_P TX0_N GND TX1_P TX1_N GND RX0_P RX0_N VIO (VSense) TD O TR ST TC K TM S TD I GND RX1_P RX1_N GND TX2_P TX2_N GND TX3_P TX3_N Vendor I/O 0 Vendor I/O 1 Vendor I/O 2 Vendor I/O 3 RESET GND CLK_P CLK_N GND Vendor I/O 4 Vendor I/O 5

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 4‐12. Aurora 70 pin connector duplex pinout TX0_P TX0_N GND TX1_P TX1_N GND RX0_P RX0_N VIO (VSense ) TDO TR ST TCK TMS TDI GND RX1_P RX1_N GND TX2_P TX2_N GND TX3_P TX3_N Vendor I/O 0 Vendor I/O 1 Vendor I/O 2 Vendor I/O 3 RESET GND CLK_ P CLK_ N GND Vendor I/O 4 Vendor I/O 5 GND RX2_P RX2_N 35 36 RX3_P RX3_N TX4_P N/C N/C GND TX4_N GND TX5_P TX5_N GND TX6_P TX6_N GND TX7_P N/C N/C N/C N/C GND GND N/C GND N/C GND GND GND N/C N/C N/C TX7_N GND N/C 69 70

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 4‐13. Aurora 34 pin connector duplex interface connection Notes: 1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in order to fully control the processor as shown here. 2. Populate this with a 1 k resistor for short‐circuit/current‐limiting protection. 3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to posi‐ tion B. 4. Asserting HRESET_B causes a hard reset on the device. Duplex 34 C onnector Ph ysical Pinout 29, 30 23, 24 5, 1 1, 17 32, 33 27 , 31 20, 25 NC REF_CLK_PREF_CLK_N REF_CLK1_P REF_CLK1_N 6 6 0.01 uF 0.01 uF RX1_N RX1_P RX0_N RX0_P TX1_N TX1_P TX0_N TX0_P CLK_N CLK_P 100 nF 100 nF Vendor I/O 0 (A urora_HAL T_B) Ve ndor I/O 1 (A urora_Ev ent_In_B) Vendor I/O 2 (A urora_Ev ent_Out_B) Vendor I/O 5 (A urora_HRESET_B) 10 kΩ AU R ORA_TCK AU R ORA_TDI AU R ORA_TDO AU R ORA_TMS VIO VSense AU R ORA_TRS T_B 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 kΩ HRESET_B4 PORESET_B 1 TRS T_B 1 TMS TDO TDI TCK EVT[4] EVT[1] EVT[0] SD1_REF_CLKn_P SD1_REF_CLKn_N SD1_TX4_P SD1_TX4_N SD1_RX4_P SD1_RX4_N OV DD 5HRESET_B PORESET_B Fr om target board sour ces (if an y) RESET B A 1 kΩ

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] 5. This is an open‐drain output gate. 6. REF_CLK_P/REF_CLK_N and REF_CLK1_P/REFCLK1_N are buffered clocks from the same common source. 7. RX1_P/RX1_N and TX1_P/TX1_N can be left floating at Aurora Header Figure 4‐14. Aurora 70 pin connector duplex interface connection Notes: 1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in order to fully control the processor as shown here. 2. Populate this with a 1 k resistor for short‐circuit/current‐limiting protection. Duplex 70 C onnector Ph ysical Pinout 5, 1 1, 17 , 23, 24, 42, 47 , 48, 53, 54, 59, 60, 65, 66 20, 25, 27 , 31, 32, 33, 37 , 38, 39, 40, 43, 44, 45, 46, 49, 50, 51, 52, 55, 56, 57 , 58, 61, 62, 63, 64, 67 , 68, 69, 70 NC REF_CLK_PREF_CLK_N REF_CLK1_P REF_CLK1_N 6 6 0. 01 uF 0.01 uF RX1_N RX1_P RX0_N RX0_P TX1_N TX1_P TX0_N TX0_P CLK_N CLK_P 100 nF 100 nF Vendor I/O 5 (A urora_HRESET_B) 10 kΩ AU R ORA_TCK AU R ORA_TDI AU R ORA_TDO AU R ORA_TMS VIO VSense AU R ORA_TRS T_B 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 kΩ HRESET_B 4 PORESET_B 1 TRS T_B 1 TMS TDO TDI TCK SD1_REF_CLKn_P SD1_REF_CLKn_N SD1_TX4_P SD1_TX4_N SD1_RX4_P SD1_RX4_N 35 36 69 70 Aurora Header OV DD 5HRESET_B PORESET_B Fr om target board sour ces (if an y) R eset B A Vendor I/O 0 (A urora_HAL T_B) Vendor I/O 1 (A urora_Ev ent_In_B) Vendor I/O 2 (A urora_Ev ent_Out_B) EVT[4] EVT[1] EVT[0] 1 kΩ

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to posi‐ tion B. 4. Asserting HRESET_B causes a hard reset on the device 5. This is an open‐drain output gate. 6. REF_CLK_P/REF_CLK_N and REF_CLK1_P/REFCLK1_N are buffered clocks from the same common source. 7. RX1_P/RX1_N and TX1_P/TX1_N can be left floating at Aurora Header

4.5.3 Guidelines for high‐speed interface termination

4.5.3.1 SerDes interface entirely unused

If the high‐speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. Note that S1VDD, X1VDD and AVDD_SD1_PLL1 must remain powered. For AVDD_SD1_PLL1, it must be connected to X1VDD through a zero ohm resistor (instead of filter cir‐ cuit shown in Figure 4‐4). The following pins must be left unconnected:

• SD1_TX[7:0]_P
• SD1_TX[7:0]_N
• SD1_IMP_CAL_RX
• SD1_IMP_CAL_TX The following pins must be connected to S1GND:
• S D 1 _ R E F _ C L K 1 _ P , SD1_REF_CLK2_P
• S D 1 _ R E F _ C L K 1 _ N , SD1_REF_CLK2_N It is recommended for the following pins to be connected to S1GND:
• SD1_RX[7:0]_P
• SD1_RX[7:0]_N It is possible to disable SerDes module by disabling all PLLs associated with it. SerDes is disabled as follows:
• SRDS_PLL_PD_S1 = 2’b11 (both PLLs configured as powered down, all data lanes selected by the protocols defined in SRDS_PRTCL_S1 associated to the PLLs are powered down as well)
• SRDS_PLL_REF_CLK_SEL_S1 = 2’b00
• SRDS_PRTCL_S1 = 2 (no other values permitted when both PLLs are powered down

4.5.3.2 SerDes interface partly unused

If only part of the high speed SerDes interface pins are used, the remaining high‐speed serial I/O pins should be terminated as described in this section. Note that both S1VDD and X1VDD must remain powered. If any of the PLLs are un‐used, the corresponding AVDD_SD1_PLL1 must be connected to X1VDD through a zero ohm resistor (instead of filter circuit shown in Figure 4‐4). The following unused pins must be left unconnected:

• SD1_TX[7:0]_P

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary]

• SD1_TX[7:0]_N The following unused pins must be connected to S1GND:
• SD1_REF_CLK[1:2]_P , SD1_REF_CLK[1:2]_N (If entire SerDes unused) It is recommended for the following unused pins to be connected to S1GND:
• SD1_RX[7:0]_P
• SD1_RX[7:0]_N In the RCW configuration field SRDS_PLL_PD_S1, the respective bits for each unused PLL must be set to power it down. A module is disabled when both its PLLs are turned off. Unused lanes must be powered down through the SRDSx Lane m General Control Register 0 (SRDSxLNmGCR0) as follows:
• SRDSxLNmGCR0[RRST] = 0
• SRDSxLNmGCR0[TRST] = 0
• SRDSxLNmGCR0[RX_PD] = 1
• SRDSxLNmGCR0[TX_PD] = 1 Note that in the case where the SerDes pins are connected to slots , it is acceptable to have these pins unterminated when unused.

4.5.4 USB controller connections

This section details the hardware connections required for the USB controllers.

4.5.4.1 USB divider network

This figure shows the required divider network for the VBUS interface for the chip. Additional require‐ ments for the external components are:

• B o t h resistors require 1% accuracy and a current capability of up to 1 mA. They must both have the same temperature coefficient and accuracy.
• T h e zener diode must have a value of 5 V‐5.25 V.
• T h e 0.6 V diode requires an IF = 10 mA, IR < 500 nA and VF(Max) = 0.8 V. If the USB PHY does not support OTG mode, this diode can be removed from the schematic or made a DNP component. Figure 4‐15. Divider network at VBUS VBUS (USB connect or)

5 V Z

51.2 kΩ 18.1 kΩ

0.6 V F

USBn_DR VVBUS USBn_PWRF AU L T USBn_VBUSCLMP Chi p

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4.6 Thermal

This table shows the thermal characteristics for the chip. Note that these numbers are based on design estimates and are preliminary. Notes: 1. Junction temperature is a function of die size, on‐chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51‐3 and JESD51‐6 with the board (JESD51‐9) horizontal. 3. Thermal resistance between the die and the printed‐circuit board per JEDEC JESD51‐8. Board temperature is measured on the top surface of the board near the package. 4. Junction ‐to‐case‐top at the top of the package determined using MIL‐STD 883 Method 1012.1. The cold plate tempera‐ ture is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5. See Thermal management information, for additional details. Table 4‐13. Package thermal characteristics(5) Rating Board Symbol Value Unit Notes Junction to ambient, natural convection Single ‐layer board (1s) R JA 28 °C/W (1)(2) Junction to ambient, natural convection Four‐layer board (2s2p) RJA 19 °C/W (1)(3) Junction to ambient (at 200 ft./min.) Single ‐layer board (1s) R JMA 22 °C/W (1)(2) Junction to ambient (at 200 ft./min.) Four‐layer board (2s2p) RJMA 15 °C/W (1)(2) Junction to board – R JB 9° C / W (3) Junction to case top – R JCtop <0.1 °C/W (4)

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] This table provides the thermal resistance with heat sink in open flow Notes: 1. Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease. 2. Simulation details: Substrate metal thicknesses: 0.015, 0.025 mm Substrate core thickness: 0.4 mm

4.7 Recommended thermal model

Information about Flotherm models of the package or thermal data not available in this document can be obtained from your local e2v sales office. Table 4‐14. Thermal Resistance with Heat Sink in Open Flow Heat Sink with Thermal Grease Air Flow Thermal Resistance (°C/W) 53 × 53 × 25 mm Pin Fin Natural Convection 6.6 0.5 m/s 3.9 1 m/s 2.9 2 m/s 2.5 4 m/s 2.2 35x31x23 mm Pin Fin Natural Convection 8.7 0.5 m/s 5.0 1 m/s 4.2 2 m/s 3.6 4 m/s 3.1 30x30x9.4 mm Pin Fin Natural Convection 12.1 0.5 m/s 8.2 1 m/s 6.4 2 m/s 5.0 4 m/s 4.1 43x41x16.5 mm Pin Fin Natural Convection 8.9 0.5 m/s 5.4 1 m/s 4.2 2 m/s 3.3 4 m/s 2.7

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4.8 Temperature diode

The chip has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461A). These devices feature series resistance cancellation using 3 current measurements, where up to 1.5k of resistance can be automatically cancelled from the temperature result, allowing noise filtering and a more accurate reading. The following are the specifications of the chip's on‐board temperature diode: Operating range: 10 ‐ 230µA Ideality factor over 13.5 ‐ 220 µA; Temperature range 80°C ‐ 105°C: n = 1.004 ± 0.008

4.9 Thermal management information

This section provides thermal management information for the flip‐chip, plastic‐ball, grid array (FC‐ PBGA) package for air‐cooled applications. Proper thermal control design is primarily dependent on the system‐level design‐the heat sink, airflow, and thermal interface material. The recommended attachment method to the heat sink is illustrated in Figure 4‐16. The heat sink should be attached to the printed‐circuit board with the spring force centered over the die. This spring force should not exceed 15 pounds force (65 Newton). Figure 4‐16. Package exploded, cross‐sectional view‐FC‐PBGA (no lid) The system board designer can choose between several types of heat sinks to place on the device. There are several commercially‐available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. For additional information regarding thermal management of lid‐less flip‐chip packages, refer to appli‐ cation note AN4871, "Assembly Handling and Thermal Solutions for Lidless Flip Chip Ball Grid Array Packages" Heat sink Heat sink clip Adhesiv e or Die Printed circuit-board thermal interface material FC-PBGA package (no lid)

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4.9.1 Internal package conduction resistance

For the package, the intrinsic internal conduction thermal resistance paths are as follows:

• T h e die junction‐to‐case thermal resistance
• T h e die junction‐to‐board thermal resistance This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed‐circuit board. Figure 4‐17. Package with heat sink mounted to a printed‐circuit board The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the silicon and through the heat sink attach material (or thermal interface mate‐ rial), and finally to the heat sink. The junction‐to‐case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.

4.9.2 Thermal interface materials

A thermal interface material is required at the package‐to‐heat sink interface to minimize the thermal contact resistance. The performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by means of a spring clip attach‐ ment to the printed‐circuit board (see Figure 4‐16). The system board designer can choose among several types of commercially‐available thermal inter‐ face materials. Ext ernal r esistance Internal r esistance Radiation Co nvection Radiation Co nvection Heat sink Die/Pa ckage Die junctio n Pa ckage/Solder balls (Note the internal versus external package resistance) External resistance Printed-circuit board Thermal interface material

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 5. PACKAGE INFORMATION

5.1 Package parameters for the FC‐PBGA

The package parameters are as provided in the following list. The package type is 23 mm x 23 mm, 780 flip‐chip, plastic‐ball, grid array (FC‐PBGA).

• P a c k a g e outline ‐ 23 mm x 23 mm
• Interconnects ‐ 780
• B a l l Pitch ‐ 0.8 mm
• B a l l Diameter (typical) ‐ 0.45 mm
• S o l d e r Balls ‐ 96.5% Sn, 3% Ag, 0.5% Cu
• S o l d e r Balls ‐ 63% Sn, 37% Pb
• Module height ‐ 1.77 mm (minimum), 1.92 mm (typical), 2.07 mm (maximum)

5.2 Mechanical dimensions of the FC‐PBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the chip.

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Figure 5‐1. Mechanical dimensions of the FC‐PBGA ‐ C5 Pb free A1 INDEX AREA 27 X 0.8 TOP VIEW 27X 0.8 AH AG AF AE AD AC AB AA H G F E D C B A J K L M N P R T U V W Y 1 3 5 7 9 1 1 13 15 17 19 21 23 25 272 4 6 8 10 12 14 16 18 20 22 24 26 28 A1 INDEX AREA BOTTOM VIEW 780X Ø Ø Ø SOLDER BALLS 0.1 5 0.45 +0.05 0.08 3MM MA X UNDERFILL FR OM DIE EDGE ON ALL SIDES VIEW D - D D 2X 0.2 B C D 780X 0.2 5 0.2 A SEATING PLANE A A M AB C MA 0.2 2X 2X 21 .6 NOTES: 1. ALL DIMENSIONS IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M- 1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 0.77 1 .62 1.92 ± 0.15 0.3 ± 0.1

1176B–HIREL–10/18 T1042/T1022 [Preliminary] Teledyne e2v Semiconductors SAS 2018 Figure 5‐2. Mechanical dimensions of the FC‐PBGA ‐ C5 leaded A1 INDEX AREA 27 X 0.8 TOP VIEW 27X 0.8 AH AG AF AE AD AC AB AA H G F E D C B A J K L M N P R T U V W Y 1 3 5 7 9 1 1 13 15 17 19 21 23 25 272 4 6 8 10 12 14 16 18 20 22 24 26 28 A1 INDEX AREA BOTTOM VIEW 780X Ø Ø Ø SOLDER BALLS 0.1 5 0.08 3MM MA X UNDERFILL FR OM DIE EDGE ON ALL SIDES VIEW D - D D 2X 0.2 B C D 780X 0.2 5 0.2 A SEATING PLANE A A M AB C MA 0.2 2X 2X 21 .6 NOTES: 1. ALL DIMENSIONS IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M- 1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 0.77 1 .62 1.92 ± 0.15 0.3 ± 0.1 0.5 ± 0.05

1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] 6. SECURITY FUSE PROCESSOR This chip implements the QorIQ platform's Trust Architecture, supporting capabilities such as secure boot. Use of the Trust Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP can be found in the chip reference manual. To program SFP fuses, the user is required to supply 1.8 V to the PROG_SFP pin per Power sequencing. PROG_SFP should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles. All other times PROG_SFP should be connected to GND. The sequencing requirements for raising and lowering PROG_SFP are shown in Figure 3‐3. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temper‐ ature range per Table 3‐2. NOTE Users not implementing the QorIQ platform's Trust Architecture features should connect PROG_SFP to GND. 7. ORDERING INFORMATION Contact your local e2v sales office or regional marketing team for order information. Notes: 1. For availability of the different versions, contact your local e2v sales office. 2. The letter × in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX part‐number is not guaranteed and such part‐number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes. 8. REVISION HISTORY This table provides revision history for this document. Table 7‐1. Ordering Information tn n n n x e x x x xQ x x Generation Platform Number of virtual cores Derivatives Temperature range Encryption Package Type CPU Speed DDR Data Rate Die Revision T(X) = 28 nm 1 04 = 4 cores 02 = 2 cores 2 = First product A = –40/105 F = –40/125 M = –55 /125 E = SEC present N = SEC not present 3 = FCPBGA C4 Pb‐free /C5 Leaded 7 = FC‐PBGA C4 Pbfree M = 1200 MHz P= 1400 MHz W = 1500 MHz Q = 1600 MT/s A = Rev 1.0 B = Rev 1.1 Table 8‐1. Revision History Rev. No Date Substantive Change(s) 1176B 10/ 2018 Table 7‐1, “Ordering Information,” on page 171: ‐ Changed the temperature range from V (‐40/110) to A (‐40/105) 1176A 03/ 2016 Initial revision

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i 1176B–HIREL–10/18 Teledyne e2v Semiconductors SAS 2018 T1042/T1022 [Preliminary] Table of Contents

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