SM560 CYPRESS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
Features
- 25- to 108-MHz operating frequency range
- Wide (9) range of spread selections
- Accepts clock and crystal inputs
- Low power dissipation
- 3.3V = 85 mw (50 MHz)
- Frequency Spread disable function
- Center Spread modulation
- Low cycle-to cycle jitter
- Eight-pin SOIC package
Applications
- VGA controllers
- LCD panels and monitors
- Printers and multi-function devices (MFP) Benefits
- Peak electromagnetic interference (EMI) reduction by 8 to 16 dB
- Fast time to market
- Cost reduction Block Diagram Pin Configuration PD VCO Xin/ CLK Xout REFERENCE DIVIDER 4 pf 8 pF 250 K FEEDBACK DIVIDER MODULATION CONTROL DIVIDER AND MUX VDD SSCC SSCLKVSS 4 LF INPUT DECODER LOGIC S1 S0 CP Xin/CLK VDD SSCLK VSS Xout SSCC SM560
of Clock (SSCLK1) is greatly reduced. market without degrading the system performance. Table 1 for programming details. with the frequency range of 25 to 108 MHz. logic at the S0 and S1 digital control inputs. centered on the input frequency. comparison of system performance during EMI testing. to 70°C operating temperature range. 1 Xin/CLK I Clock or Crystal connection input. Refer to Table 1 for input frequency range selection. 2 VDD P Positive power supply. 3 GND P Power supply ground. 4 SSCLK O Modulated clock output. when input is high and disabled when input is low. This pin is pulled high internally. 6 S1 I Tri-level Logic input control pin used to select frequency and bandwidth. Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1. 7 S0 I Tri-level Logic input control pin used to select frequency and bandwidth. Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1. Table 1. Frequency and Spread% Selection (Center Spread)
Document #: 38-07020 Rev. *E Page 3 of 8 Tri-level Logic With binary logic, four states can be programmed with two control lines, whereas Tri-level Logic can program nine logic states using two control lines. Tri-level Logic in the SM560 is implemented by defining a third logic state in addition to the standard logic “1” and “0.” Pins 6 and 7 of the SM560 recognize a logic state by the voltage applied to the respective pin. These states are defined as “0” (Low), “M” (Middle), and “1” (One). Each of these states has a defined voltage range that is interpreted by the SM560 as a “0,” “M,” or “1” logic state. Refer to Table 2 for voltage ranges for each logic state. By using two equal value resistors (typically 20K) the “M” state can be easily programmed. Pins 6 or 7 can be tied directly to ground or VDD for Logic “0” or “1” respectively VDD = 3.3 VDC VDD = 3.3 VDC VDD = 3.3 VDC SM560 SM560
1.65 VDC
0 VDC
EX. 1 EX. 2 EX. 3 20K 20K Figure 1.
output clock, the SM560 becomes a Low EMI clock generator. discussed in the following sections. All digital clocks generate unwanted energy in their harmonics. bandwidth, and lowering the Q.
- Single Power Supply: The V oltage on any input or I/O pin cannot exceed the power pin during power up.
Table 2. DC Electrical Characteristics: VDD = 3.3V, Temp. = 25°C and CL (Pin 4) = 15 pF, unless otherwise noted Table 3. Electrical Timing Characteristics: VDD = 3.3V, T = 25°C and CL = 15 pF, unless otherwise noted
the voltage requirement for an “M” state. profile that has a 1.7% peak to peak spread.
- The value of L1 is calculated such that L1 and C3 are tuned to a frequency that is 130% higher than the fundamental frequency of the crystal.
- The ordering part number differs from the marking on the actual device.
40 MHz
Figure 3. Application Schematic[2]
Document #: 38-07020 Rev. *E Page 7 of 8 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Package Drawing and Dimensions SEATING PLANE P I N1I D 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 0° ~8° 0.016[0.406] 0.010[0.254] X 45° 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.004[0.102]
8 Lead (150 Mil) SOIC - S08
- REFERENCE JEDEC MS-012 PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 4. PACKAGE WEIGHT 0.07gms 51-85066-*C 8-lead (150-Mil) SOIC S8
Document #: 38-07020 Rev. *E Page 8 of 8 Document History Page Document Title: SM560 Spread Spectrum Clock Generator Document Number: 38-07020 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 106948 06/07/01 IKA Convert from IMI to Cypress *A 113520 04/10/02 DMG Package suffix changed (per Cypress standard) *B 119445 10/16/02 RGL Corrected the values in the Absolute Maximum Ratings to match the device. *C 122675 12/14/02 RBI Added power up requirements to operating conditions information. *D 231055 See ECN RGL Added Lead Free Devices *E 237630 See ECN RGL Minor Change: Added letter C in the ordering for Lead Free