S8T26AF

AM8T28 AMD | Alldatasheet

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Schottky Three-State Quad Bus Driver/Receiver rr Distinctive Characteristics ®@ Advanced Schottky technology © Driver propagation delay — 14ns max. for 8T26A @ 48mA driver sink current 171ns max. for 8T28 © Three-state outputs on driver and reciever © Receiver propagation delay — 14ns max. for 8T26A @ PNP inputs 17ns max. for 8T28 @ Am8T26A has inverting outputs © 100% reliability assurance testing in compliance wit @ Am8T28 has non-inverting outputs MIL-STD-883 FUNCTIONAL DESCRIPTION LoGic symBoL The Am8T26A/Am8T28 are high speed bus transceivers consisting of four bus drivers with three-state outputs and four bus receivers, also with three-state outputs. Each driver , . ” output is internally connected to a receiver input, Both the drivers and receivers have PNP inputs. DO; Bp Bs tof — 2 One buffered common “bus enable” input is connected to sore a the four drivers and another buffered common “receiver amazon fe 1" enable” input is connected to the receivers. A LOW on the or hy 1“ bus enable (B/E) input forces the four driver outputs to the ae high-impedance state. A HIGH on the bus enable allows y input data to be transferred onto the data bus. te we A HIGH on the receiver enable (R/E) input forces the four receiver outputs to the high-impedance state while a LOW ‘on the receiver enable input allows the received data to be transferred to the output. The complementary design of the bus enable and receiver enable inputs allows these control Vee = Pin 16 inputs to be connected together externally such that a single GND = Pas transmit/receive function is derived. UC-ser LOGIC DIAGRAMS Am8T26A ‘AmB8T28 Inverting Output (Three-State) Non-Inverting Output (Three-State) 29 oy Dp 23 20 oy 2 D3 a o au nm im o ® fo oe oe — a eS oe | oo no) a md “ a 15) oD nas " a o wD on UC-S62 Fo Lt Rp "3 0 Ry ed Ry UC-563 ORDERING INFORMATION CONNECTION DIAGRAM (Top View) Am8T26A — Am8T28 Nec SE Ry 83 Dz Rp & Dp Package Temperature Order Order Type Range Number Number Molded DIP O°C to #75°C_ —s N8T26AB_=—sN8T28B ceiaiailied Hermetic DIP 0°C to +75°C N8T26AF N8T28F % 25 ws ee Dice OPC to +75°C_ — AMBT2GAXC_ AM8T28XC. Coo oo oo Hermetic DIP. ~55°C to +125°C SBT 26AF S8T28F WE fq 6 Op My 8 0) GND Dice —55°C to +125°C AMBT26AXM AM8T28XM. Note: Pin 1 is marked for orientation. Uc-564 12-84

MAXIMUM RATINGS (Above which the useful life may be impaired) torage Temperature —65°C to +150°C “emperature (Ambient) Under Bias —55°C to +125°C upply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous =0.5V t047V 3C Voltage Applied to Outputs for HIGH Output State =0.5V to +Voc¢ max. 3€ Input Voltage —0.5V to +5,5V XC Output Current, Into Outputs (Receiver) 30mA 3C Output Current, Into Outputs (BUS) 80mA 3C Input Current —30mA to +5.0mA :LECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE “he Following Conditions Apply Unless Otherwise Noted: W8T2GA, NBT2ZB Ta=0°C to +7S°C(COM'L) MIN. =4.75V MAX. =5.25V i8T26A, S8T2B Ta=—-55°Cto+125°C(MIL) MIN.=4.50V MAX.= 5. SOV >C CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE Tye. rarameters Description Test Conditions (Note 1) Min, (Note2) Max. —_—_Units Driver Receiver Cm OES Tout = —100xA, Voc = 5.0V 35 Vor | High Level Output Voltage 100 eh Voc = = Volts lour = —2.0mA (Note 6) 24 re Tos _ | Short Circuit Ourput Current Vout =0V. Voc = VecMAX. ee Both Driver and Receiver High Level Output OM Leakage Current | VouT=24V ee ee Wap compvonee sama Vo [anaraeal Vec=vecmaX. tec tamerz6 [ Voo=Vecwax ra Switching Characteristics (Ta = +25°C, Vcc = 5.0V) Am8T26A, Am8T28 Parameters Description Test Conditions Min, Typ. Max. Min, Typ. Max. __ Units river Input t0 Bus a [te [oe Ps | zu Diver Enabo to Bus Figure a a — | 2 | je Receiver Enable to Figure 4 [of |e fa | Lear canaitiont Ihows ay MIN or MAX uve the appropriate value specified under Electrical Gherecteristice for the applicable device type 2. Typical limits are at Voc « $.0V, 25°C ambient and maximum loading. 3. Actual input currents © Unit Load Current x input Load Factor (See Loading Rules! e Navoore then one output should be shorted at a time. Duration of the short circuit test should not exceed one second, 5. Output sink current is supplied through a resistor to Voc. &. Measurements apply to each output and the associated data input independently. 12-85

DEFINITION OF FUNCTIONAL TERMS LOADING RULES {In Unit Loads) Do, D4,D2,D3 The four driver inputs, , By, Bz, Bg The four dri ‘tputs and recei r Low Fanout toe % rca ° Teaver cusps ener inpus Input Output Output - Input/Output _PinNo.’s Unit Load HIGH LOW Ro, Ry, R2,Rg The four receiver outputs. Data from the a | cc | Se eed bus is inverted while data from the driver inputs is non- ———— —_. SS inverted, fo 80 B/E Bus enable input. When the bus enable input is LOW, __8o 3 116 260 25 the four driver outputs are in the high-impedance state. 0 4 18 = = R/E Receiver enable input, When the receiver enable input Ry “3s 50 10 is HIGH, the four receiver outputs are in the high-impedance a state oo 7? 1 — =~ GND 8 = Se D2 9 18 = = 82 10 16 250 B Rz io = 50 10 D3 2 v8 = 83 a Ine 250 25 R3 4 = 50 10 BE i we = = Vee 16 = = = A TTL Unit Load is defined as —1.6mA measured at 0.4V LOW and 40uA measured at 2.4V HIGH, DRIVER FUNCTION TABLE RECEIVER FUNCTION TABLE ‘Am8T26A | Am8T28 ‘Am8T26A | Am@T28 INPUTS OUTPUT | OUTPUT INPUTS OUTPUT | OUTPUT pee | > | ae fa | pre [oe [oa [on | L x Zz Zz H x Zz z H L H L l L H L H H L H L H L H L= Low X = Don’t Care t= Low X = Don't Care He HIGH Z= High Impedance H= HIGH Z = High Impedance INPUT/OUTPUT CURRENT INTERFACE CONDITIONS sus paver neceiven ‘our ‘ouTrur auc inrurs Yoo eo | eo | 0 can om No [ | l 2 | | Note: Actual current flow direction shown. uc-s65 12-86

‘Am8T26A/8T28 AC TEST CIRCUITS AND WAVEFORMS PROPAGATION DELAY (Data In to Bus) ag gvegssav ae ad ° xa: inpur, 15V 150 Cyne bo | va! ke es | an aes woos Soe oust Xo fo cettSion a Eo = Racer eee nfo Fat oat Feisty am ese? uc-868 Figure 1 uc-568 ee PROPAGATION DELAY (Bus to Receiver Out) 6 veess0v rr wn fee Ne ott ale ° = Le won our Yow fe [| mfee | omk Sian EET af ue #70 uic-se9 - "Figure 2 ues ee PROPAGATION DELAY (Bus Enable to Bus Output) oy "0 ° (PROBE! ¥ a [ae ¥ Persons ios 90) CJ. «fo tre! Se BO duty ec! I vesra esr Figure 3 ues ee PROPAGATION DELAY: (Receive Enable to Receive Output) vce ® inpuT ft 1s \\ 1 = we Lt) - Qsov " | _4 ° muse |p FI 7 Tm A 4 wt al on ee auteur a | a ee to, fo . ineurruise " af Peer een afro Setanta a en | a " Sent ee nce a ° uc-576 UC-575 Figure 4 i LUC-S77 12-87

f pppuication = LJ LI i Metallization and Pad Layouts Am8T26A Am8T28 .— ia poe et we? Opie 0 ne Pee to? = “oy | at is 2 aa cee). ne ee 2) oS ween oS oy? Se ob my? So Sn - — I i = DIE SIZE 0.056" x 0091" DIE SIZE 0.068" x 0.081" 12-88