S79FL256S

S79FL256S CYPRESS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 General Description
• 1.2 Glossary
• 1.3 Other Resources
• 2.1 Input/Output Summary
• 2.2 Multiple Input / Output (Dua l-Quad SPI)
• 2.3 RESET#
• 2.4 Multiple Input / Output (Dual- Quad)
• 2.5 Serial Clock (SCK)
• 2.6 Chip Select (CS#)
• 2.7 Input Output IO0 - IO7
• 2.8 Core Voltage Supply (V
• 2.9 Versatile I/O Power Supply (V IO)
• 2.10 Supply and Signal Ground (V SS)
• 2.11 Not Connected (NC)
• 2.12 Reserved for Future Use (RFU )
• 2.13 Do Not Use (DNU)
• 2.14 Block Diagrams
• 3.1 SPI Clock Modes
• 3.2 Command Protocol
• 3.3 Interface States
• 3.4 Configuration Register Effects on the Interface
• 3.5 Data Protection
• 4.1 Absolute Maximum Ratings
• 4.2 Operating Ranges
• 4.3 Power-Up and Power-Down
• 4.4 DC Characteristics
• 5.1 Key to Switching Waveforms
• 5.2 AC Test Conditions
• 5.3 Reset
• 5.4 SDR AC Characteristics
• 5.5 DDR AC Characteristics
• 6.1 Dual-Quad SOIC 16-Lead Pa ckage
• 6.2 SOIC 16 Physical Diagram
• 7.1 Overview
• 7.2 Flash Memory Array
• 7.3 ID-CFI Address Space
• 7.4 OTP Address Space
• 7.5 Registers
• 8.1 Secure Silicon Region (OTP)
• 8.2 Write Enable Command
• 8.3 Block Protection
• 8.4 Advanced Sector Protection
• 9.1 Command Set Summary
• 9.2 Identification Commands
• 9.3 Register Access Commands
• 9.4 Read Memory Array Commands
• 9.5 Program Flash Array Commands
• 9.6 Erase Flash Array Commands
• 9.7 One Time Program Array Commands
• 9.8 Advanced Sector Protection Commands
• 9.9 Reset Commands
• 9.10 Embedded Algorithm Performa nce Tables
• 10.1 Erase Endurance
• 10.2 Data Retention
• 11.1 Command Summary
• 11.2 Device ID and Common Flash Interface
• 11.3 Initial Delivery State

Features

 Density – 256 Mbit (32 Mbytes) – 512 Mbit (64 Mbytes)  Serial Peripheral Interface (SPI) – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate (DDR) option – Extended Addressing: 24- or 32-bit address options  READ Commands – Dual-Quad SPI Quad Read: 104 MHz clock rate (104 MB/ – Dual-Quad SPI Quad DDR Read: 80 MHz clock rate (160 MB/s) – Normal, Fast, Quad, Quad DDR – AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address – Common Flash Interface (CFI) data for configuration information.  Programming (3 Mbytes/s) – 512-byte or 1024-byte Page Programming buffer options – Quad-Input Page Programming (QPP) for slow clock systems – Automatic ECC - internal hardware Error Correction Code generation with single bit error correction  Erase (1 Mbyte/s) – Hybrid sector size option – physical set of thirty two 8-kbyte sectors at top or bottom of address space with all remaining sectors of 128 kbytes – Uniform sector option – always erase 512-kbyte blocks for software compatibility with higher density and future devices.  Cycling Endurance – 100,000 Program-Erase Cycles on any sector, minimum  Data Retention – 20 Year Data Retention, minimum  Security features – Separate One Time Program (OTP) array of 2048 bytes – Block Protection: – Status Register bits to control protection against program or erase of a contiguous range of sectors. – Hardware and software control options – Advanced Sector Protection (ASP) – Individual sector protection controlled by boot code or password  Cypress ® 65 nm MirrorBit® Technology with Eclipse™ Architecture  Core Supply Voltage: 2.7V to 3.6V  Temperature Range: – Industrial (-40°C to +85°C) – Industrial Plus (-40°C to +105°C) – Automotive, AEC-Q100 Grade 3 (-40°C to +85°C) – Automotive, AEC-Q100 Grade 2 (-40°C to +105°C)  Packages (all Pb-free) – 16-lead SOIC (300 mil)  Software Features – Program Suspend and Resume – Erase Suspend and Resume – Status Register provides status of embedded erase or programming operation – Common Flash Interface (CFI) Compliant — allows host system to identify the flash device and determine its capabilities – User-configurable Configuration Register  Hardware Features – Hardware Reset input (RESET#) - resets device to standby state

Document Number: 002-00518 Rev. *D Page 2 of 111 S79FL256S/S79FL512S Performance Summary Maximum Read Rates SDR Dual-Quad SPI Command Clock Rate (MHz) Mbytes/s Read 50 12.5 Fast Read 133 33 Quad Read 104 104 Maximum Read Rates DDR Dual-Quad SPI Command Clock Rate (MHz) Mbytes/s DDR Quad Read 80 160 Typical Program and Erase Rates Dual-Quad SPI Operation kbytes/s Page Programming (512-byte page buffer) 2000 Page Programming (1024-byte page buffer) 3000 8-kbyte Physical Sector Erase (Hybrid Sector Option) 60 128-kbyte Physical Sector Erase (Hybrid Sector Option) 1000 512-kbyte Logical Sector Erase 1000 Typical Current Consumption, Dual-Quad SPI Operation Current (mA) Serial Read 50 MHz 32 (max) Serial Fast Read 133 MHz 66 (max) Quad Read 104 MHz 122 (max) Program 200 (max) Erase 200 (max) Standby 0.14 (typ)

Document Number: 002-00518 Rev. *D Page 4 of 111 S79FL256S/S79FL512S 1. Overview

1.1 General Description

The Cypress S79FL256S/S79FL512S devices are flash non-volatile memory products using:  MirrorBit technology - that stores two data bits in each memory array transistor  Eclipse architecture - that dramatically improves program and erase performance  65 nm process lithography The S79FL256S/S79FL512S devices connect two Quad I/O SPI devices with a single CS# resulting in an eight bit I/O data path. This Byte I/O interface is called Dual-Quad I/O. These devices connect to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (IO1 and IO5) is supported as well as four-bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, these two devices add support for Double Data Rate (DDR) read commands for QIO that transfers address and read data on both edges of the clock. The Eclipse architecture features a Page Programming Buffer that allows up to 256 words (512 bytes) or 512 words (1024 bytes) to be programmed in one operation, resulting in significantly faster effective programming (up to 2 MB/s or 3 MB/s respectively) and erase (up to 1 MB/s) than prior generation SPI program or erase algorithms. Executing code directly from flash memory is often called Execute-In-Place or XIP. By using the S79FL-S devices at the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically. The S79FL-S products offer high density coupled with the fastest read and write performance required by a variety of embedded applications. They are ideal for code shadowing, XIP, and data storage.

1.2 Glossary

All information transferred between the host system and memory during one period while CS# is low. This includes the instruction (sometimes called an operation code or opcode) and any required address, mode bits, latency cycles, or data. DDP (Dual Die Package) Two die stacked within the same package to increase the memory capacity of a single package. Often also referred to as a Multi-Chip Package (MCP). DDR (Double Data Rate) When input and output are latched on every edge of SCK. ECC ECC Unit = 16 byte aligned and length data groups in the main Flash array and OTP array, each of which has its own hidden ECC syndrome to enable error correction on each group. Flash The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases large blocks of memory bits in parallel, making the erase operation much faster than early EEPROM. High A signal voltage level ≥ VIH or a logic level representing a binary one (1). Instruction The 8 bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). The instruction is always the first 8 bits transferred from host system to the memory in any command. Low A signal voltage level  V IL or a logic level representing a binary zero (0). LSB (Least Significant Bit) Generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value. MSB (Most Significant Bit) Generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data value. Non-Volatile No power is needed to maintain data stored in the memory.

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1.3 Other Resources

1.3.1 Cypress Flash Memory Roadmap

www.cypress.com/product-roadmaps/cypress-flash-memory-roadmap

1.3.2 Links to Software

www.cypress.com/software-and-drivers-cypress-flash-memory

1.3.3 Links to Application Notes

www.cypress.com/appnotes

1.3.4 Specification Bulletins

Specification bulletins provide information on temporary differences in feature description or parametric variance since the publication of the last full data sheet. Contact your local sales office for details. Obtain the latest list of company locations and contact information at www.cypress.com/contact-us. OPN (Ordering Part Number) The alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration, etc. used to select the desired device. Page 512 or 1024 bytes aligned and length group of data. PCB Printed Circuit Board. Register Bit References Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB: bit_range_LSB]. SDR (Single Data Rate) When input is latched on the rising edge and output on the falling edge of SCK. Sector Erase unit size; depending on device model and sector location, this may be 8 kbytes, 128 kbytes or 512 kbytes. Write An operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. When changing non-volatile data, an erase and reprogramming of any unchanged non- volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified – as a single operation. The non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data.

many signals switching and the larger package increases cost. power, and either reduces the host connection count or frees host connectors for use in providing other features. internally tied together in the package.

2.1 Input/Output Summary

Table 1. Dual-Quad Input/Output Descriptions the host system if not used. absolute maximum (Supply Voltage). may take advantage of future enhanced features in compatible footprint devices.

2.2 Multiple Input / Output (Dual-Quad SPI)

Quad Input / Output (I/O) commands send instructions to the memory only on the IO0 (Quad SPI-1) and IO4 (Quad SPI-2) signals. IO7 (Quad SPI-2). Data is sent and returned to the host as bytes on IO0 - IO7.

2.3 RESET#

 and resets the internal Control Unit to standby state. RESET# causes the same initialization process as is performed when power comes up and requires tPU time. be reinitiated once the device is ready to accept a command sequence. device draws CMOS standby current (ISB). RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.

2.4 Multiple Input / Output (Dual-Quad)

Quad Input / Output (I/O) commands send instructions to the memory only on the IO0 (Quad SPI-1) and IO4 (Quad SPI-2) signals. IO7 (Quad SPI-2). Data is sent and returned to the host as bytes on IO0 - IO7.

2.5 Serial Clock (SCK)

Table 1. Dual-Quad Input/Output Descriptions (Continued)

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2.6 Chip Select (CS#)

The chip select signal indicates when a command for the device is in process and the other signals are relevant for the memory device. When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Registers (WRR) embedded operation is in progress, the device will be in the Standby Power mode. Driving the CS# input to logic low state enables the device, placing it in the Active Power mode. After Power-up, a falling edge on CS# is required prior to the start of any command.

2.7 Input Output IO0 - IO7

These signals are input and outputs for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

2.8 Core Voltage Supply (V CC)

VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read, program, and erase. The voltage may vary from 2.7V to 3.6V.

2.9 Versatile I/O Power Supply (V IO)

VIO functionality is not supported on the standard configuration of the S79FL256S/S79FL512S devices.

2.10 Supply and Signal Ground (V SS)

VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.

2.11 Not Connected (NC)

No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC must not have voltage levels higher than VCC.

2.12 Reserved for Future Use (RFU)

No device internal signal is currently connected to the package connector but is there potential future use of the connector. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices.

2.13 Do Not Use (DNU)

A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.

2.14 Block Diagrams

Figure 1. SPI Host and S79FL256S / S79FL512S Dual-Quad SPI Devices in the 16-Pin SOIC Package

1. The Chip Select (CS#) and Clock (SCK) signals for Quad SPI-1 and Quad SPI-2 are internally tied together in the 16-pin SOIC package.

3.1 SPI Clock Modes

3.1.1 Single Data Rate (SDR)

The S25FL-S devices can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes. always available from the falling edge of the SCK clock signal. The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data. Figure 2. Dual-Quad SPI SDR Modes Supported at the beginning of a command.

3.1.2 Double Data Rate (DDR)

of the last instruction bit. The first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle. of SCK because SCK is already low at the beginning of a command.

Figure 3. Dual-Quad SPI DDR Modes Supported

3.2 Command Protocol

All communication between the host system and S25FL-S memory devices is in the form of units called commands. instruction, address, and data information is transferred serially between the host system and memory device. as 2-8-8 for Quad I/O command protocols. the Chip Select (CS#) signal low throughout a command.  The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory. of information transfer or device operation to be performed. address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.

higher numbered IO signal. Single bits or parallel bit groups are transferred in most to least significant bit order. read data is returned to the host.  Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands. edge. Each following transfer occurs on the next SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.  If the command returns read data to the host, the device continues sending data transfers until the host takes the CS# signal high. The CS# signal can be driven high after any transfer in the read data sequence. This will terminate the command. high exactly at the eight SCK cycle boundary of the instruction or write data, the command is rejected and not executed. bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. embedded operation. These are discussed in the individual command descriptions. available to determine when the command completes execution and whether the command was successful.

3.2.1 Command Sequence Examples

Figure 4. Dual-Quad Stand Alone Instruction Command

1. Instruction needs to be the same for both IO0 (Quad SPI-1) and IO4 (Quad SPI-2).

3.3 Interface States

This section describes the input and output signal levels as related to the SPI interface behavior.

3.3.1 Power-Off

react to external signals, and is prevented from performing any program or erase operation.

3.3.2 Low Power Hardwa re Data Protection

start when the core supply voltage is out of the operating range. Table 2. Dual-Quad Interface States Summary

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3.3.3 Power-On (Cold) Reset

When the core voltage supply remains at or below the VCC (low) voltage for  tPD time, then rises to  VCC (Minimum) the device will begin its Power-On Reset (POR) process. POR continues until the end of tPU. During tPU the device does not react to external input signals nor drive any outputs. Following the end of tPU the device transitions to the Interface Standby state and can accept commands. For additional information on POR see Power-On (Cold) Reset on page 24.

3.3.4 Hardware (Warm) Reset

Some of the device package options provide a RESET# input. When RESET# is driven low for tRP time the device starts the hardware reset process. The process continues for tRPH time. Following the end of both tRPH and the reset hold time following the rise of RESET# (tRH) the device transitions to the Interface Standby state and can accept commands. For additional information on hardware reset see POR followed by Hardware Reset on page 25.

3.3.5 Interface Standby

When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface waits for the beginning of a new command. The next interface state is Instruction Cycle when CS# goes low to begin a new command. While in interface standby state the memory device draws standby current (ISB) if no embedded algorithm is in progress. If an embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to standby current draw.

3.3.6 Instruction Cycle

When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device captures the MSB of the instruction that begins the new command. On each following rising edge of SCK the device captures the next lower significance bit of the 8 bit instruction. The host keeps RESET# high, CS# low. Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command. The transfer format may be Single, Quad output, Quad I/O, or DDR Quad I/O. The expected next interface state depends on the instruction received. Some commands are stand alone, needing no address or data transfer to or from the memory. The host returns CS# high after the rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.

3.3.7 Single Input Cycle — Host to Memory Transfer

Several commands transfer information after the instruction on the single serial input (SI) signal from host to the memory device. The quad output commands send address to the memory using only SI but return read data using the I/O signals. The host keeps RESET# high, CS# low, HOLD# high, and drives SI as needed for the command. The memory does not drive the Serial Output (IO1 and IO5) signals. The expected next interface state depends on the instruction. Some instructions continue sending address or data to the memory using additional Single Input Cycles. Others may transition to Single Latency, or directly to Single, or Quad Output.

3.3.8 Single Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and SCK toggles. The host may drive the IO0 and IO4 signals during these cycles or the host may leave IO0 and IO4 floating. The memory does not use any data driven on IO0 and IO4 or other I/O signals during the latency cycles. In quad read commands, the host must stop driving the I/O signals on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the Serial Output (IO0 and IO4) or I/O signals during the latency cycles. The next interface state depends on the command structure i.e. the number of latency cycles, and whether the read is single, or quad width.

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3.3.9 Dual-Quad Single Output Cycle — Memory to Host Transfer

Several commands transfer information back to the host on the Serial Outputs (IO1 and IO5) signals. The host keeps RESET# high, CS# low. The memory ignores the Serial Input (IO0 and IO4) signals. The memory drives IO1 and IO5 with data. The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the command.

3.3.10 QPP or QOR Address Input Cycle

The Quad Page Program and Quad Output Read commands send address to the memory only on IO0 and IO4. The other IO signals are ignored because the device must be in Quad mode for these commands thus the Hold and Write Protect features are not active. The host keeps RESET# high, CS# low, and drives IO0. For QPP the next interface state following the delivery of address is the Quad Input Cycle. For QOR the next interface state following address is a Quad Latency Cycle if there are latency cycles needed or Quad Output Cycle if no latency is required.

3.3.11 Quad Input Cycle — Host to Memory Transfer

The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad Page Program command transfers four data bits to the memory in each cycle. The host keeps RESET# high, CS# low, and drives the IO signals. For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency Cycle if there are latency cycles needed or Quad Output Cycle if no latency is required. For Quad Page Program the host returns CS# high following the delivery of data to be programmed and the interface returns to standby state.

3.3.12 Quad Latency (Dummy) Cycle

Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low. The host may drive the IO signals during these cycles or the host may leave the IO floating. The memory does not use any data driven on IO during the latency cycles. The host must stop driving the IO signals on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the IO signals during the latency cycles. The next interface state following the last latency cycle is a Quad Output Cycle.

3.3.13 Quad Output Cycle — Memory to Host Transfer

The Quad Output Read and Quad I/O Read return data to the host eight bits in each cycle. The host keeps RESET# high, and CS# low. The memory drives data on IO0-IO3 signals during the Quad output cycles. The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the command.

3.3.14 DDR Quad Input Cycle — Host to Memory Transfer

The DDR Quad I/O Read command sends address, and mode bits to the memory on all the IO signals. Eight bits are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.

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3.3.15 DDR Latency Cycle

DDR Read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR1[7:6]). During the latency cycles, the host keeps RESET# high and CS# low. The host may not drive the IO signals during these cycles. So that there is sufficient time for the host drivers to turn off before the memory begins to drive. This prevents driver conflict between host and memory when the signal direction changes. The memory has an option to drive all the IO signals with a Data Learning Pattern (DLP) during the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles so that there is at least one cycle of high impedance for turn around of the IO signals before the memory begins driving the DLP. When there are more than 4 cycles of latency the memory does not drive the IO signals until the last four cycles of latency. The next interface state following the last latency cycle is a DDR Quad Output Cycle, depending on the instruction.

3.3.16 DDR Quad Output Cycle — Memory to Host Transfer

The DDR Quad I/O Read command returns bits to the host on all the IO signals. Eight bits are transferred on the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the command.

3.4 Configuration Register Effects on the Interface

The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code selects the number of mode bit and latency cycles for each type of instruction. The Configuration Register Bit-1 (CR1[1]) selects whether Quad mode is enabled and allow Quad Page Program, Quad Output Read, and Quad I/O Read commands. Quad mode must also be selected to allow Read DDR Quad I/O commands. This Quad bit is set to 1 by default for Dual-Quad SPI.

3.5 Data Protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the hardware design. These are described below. Other software managed protection methods are discussed in the software section (page 33) of this document.

3.5.1 Power-Up

When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not react to external signals, and is prevented from performing any program or erase operation. Program and erase operations continue to be prevented during the Power-on Reset (POR) because no command is accepted until the exit from POR to the Interface Standby state.

3.5.2 Low Power

When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range.

3.5.3 Clock Pulse Count

The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse count that is a multiple of eight before executing them. A command not having a multiple of 8 clock pulse count is ignored and no error status is set for the command.

1. Electrical Specifications

4.1 Absolute Maximum Ratings

1. See Input Signal Overshoot on page 20 for allowed maximums during signal transition.
2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one seco nd.
3. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the

rating conditions for extended periods may affect device reliability.

4.2 Operating Ranges

Operating ranges define those limits between which the functionality of the device is guaranteed.

4.2.1 Temperature Ranges

1. Automotive operating and performance parameters will be determine d by device characterization and may vary from standard industrial temperature range devices as

currently shown in this specification. Table 3. Absolute Maximum Ratings Table 4. Recommended Operating Ranges

4.2.2 Input Sign al Overshoot

may overshoot VSS to –2.0V or overshoot to VCC +2.0V, for periods up to 20 ns. Figure 11. Maximum Negative Overshoot Waveform Figure 12. Maximum Positive Overshoot Waveform

4.3 Power-Up and Power-Down

command should be sent to the device until the end of tPU. power up, the assertion of the RESET# signal or receiving a software reset command (RESET) will restart the POR process.

4.4 DC Characteristics

Applicable within operating -40°C to +85°C range.

1. Typical values are at T AI = 25°C and VCC = 3V.
2. Outputs switching current is not included.
3. Industrial temperature range / Automotive In-Cabin temperature range.

4.4.1 Active Power and Standby Power Modes

Standby Power mode, and power consumption drops to ISB. Table 6. DC Characteristics

5.1 Key to Switching Waveforms

Figure 15. Waveform Element Meanings Figure 16. Input, Output, and Timing Reference Levels

5.2 AC Test Conditions

Figure 17. Test Setup

1. Output High-Z is defined as the point where data is no longer driven.
2. Input slew rate: 1.5 V/ns.
3. AC characteristics tables assume clock and da ta signals have the same slew rate (slope).

5.2.1 Capacitance Characteristics

1. For more information on capacitance, please consult the IBIS models.

5.3 Reset

5.3.1 Power-On (Cold) Reset

until tRH after RESET# returns high. RESET# must return high for greater than tRS before returning low to initiate a hardware reset. Figure 18. Reset Low at the End of POR Table 7. AC Measurement Conditions Table 8. Capacitance

Figure 19. Reset High at the End of POR Figure 20. POR followed by Hardware Reset

5.3.2 Hardware (Warm) Reset

POR process instead of the hardware reset process and will require tPU to complete the POR process. The RESET# input provides a hardware method of resetting the flash memory device to standby state.  RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware reset. all outputs, and ignores all read/write commands for the duration of tRPH. The device resets the interface to standby state.  If CS# is low at the time RESET# is asserted, CS# must return high during tRPH before it can be asserted low again after tRH. Figure 21. Hardware Reset

1. RESET# Low is optional and ignored during Power-up (t PU). If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine
2. Sum of t RP and tRH must be equal to or greater than tRPH.

Table 9. Hardware Reset Parameters

5.4 SDR AC Characteristics

1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. Regulated V CC range (3.0 - 3.6V) and CL = 30 pF.
3. Regulated V CC range (3.0 - 3.6V) and CL = 15 pF.
4. ±10% duty cycle is supported for frequencies  50 MHz.
5. Maximum value only applies during Program/Erase Suspend/Resume commands.

Table 10. AC Characteristics (VCC 2.7V to 3.6V)

5.4.1 Clock Timing

Figure 22. Clock Timing

5.4.2 Input / Output Timing

Figure 23. SPI SDR Dual-Quad Timing

5.5 DDR AC Characteristics

1. Regulated V CC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.

5.5.1 DDR Input Timing

Figure 24. SPI DDR Input Timing Table 11. AC Characteristics DDR Operation

80 MHz

5.5.2 DDR Output Timing

Figure 25. SPI DDR Output Timing Figure 26. SPI DDR Data Valid Window

1. t CLH is the shorter duration of tCL or tCH.
2. t O_SKEW is the maximum difference (delta) between the minimum and maximum tV (output valid) across all IO signals.
3. t OTT is the maximum Output Transition Time from one valid data value to the next valid data value on each IO.
4. t OTT is dependent on system level considerations including:

a. Memory device output impedance (drive strength). b. System level parasitics on the IOs (primarily bus capacitance). c. Host memory controller input V IH and VIL levels at which 0 to 1 and 1 to 0 transitions are recognized. e. t OTT is not a specification tested by Cypress, it is system dependent and must be derived by the system designer based on the above considerations.

1. The minimum data valid window (t DV) can be calculated as follows:

6.1 Dual-Quad SOIC 16-Lead Package

Figure 27. 16-pin SOIC package (300 mil)

9 IO2

6.2 SOIC 16 Physical Diagram

Figure 28. SOIC 16-Lead, 300-mil Body Width (SS3016)

6.2.1 Special Handling Instru ctions for FBGA Packages

integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.

0.25 M DCA - B

0.20 C A-B

0.10 C D

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
2. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.

1. ALL DIMENSIONS ARE IN MILLIMETERS.

D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.

1. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
2. DATUMS A AND B TO BE DETERMINED AT DATUM H.
3. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
4. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
5. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

LOWER RADIUS OF THE LEAD FOOT. IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.

1. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
2. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE

10.30 BSC

1.27 BSC

7.50 BSC

1.40 REF

0.25 BSC

7.1 Overview

7.1.1 Extended Address

density. A 32-bit byte resolution address allows direct addressing of up to a 4 Gbytes (32 Gbits) of address space. 24-bit addresses are in use.  New commands — that perform both legacy and new functions, which expect 32-bit address. set for 24-bit addresses. This enables legacy software compatible access to the first 128 Mbits of a device.

7.1.2 Multiple Address Spaces

7.2 Flash Memory Array

The main flash array is divided into erase units called sectors. The sectors are organized as uniform 512-kbyte sectors. Table 12. S79FL512S Sector and Memory Address Map, Bottom 8-kbyte Sectors

Table 13. S79FL512S Sector and Memory Address Map, Top 8-kbyte Sectors Table 14. S79FL512S Sector and Memory Address Map, Uniform 512-kbyte Sectors Table 15. S79FL256S Sector and Memory Address Map, Bottom 8-kbyte Sectors Table 16. S79FL256S Sector and Memory Address Map, Top 8-kbyte Sectors

Note: These are condensed tables that use a couple of sectors as references. There are address ranges that are not explicitly listed.

7.3 ID-CFI Address Space

7.4 OTP Address Space

main flash array. The OTP area is divided into 64, individually lockable, 32-byte aligned and length regions. prevent further programming, by programming the related protection bit in the OTP Lock Bytes. space. The bytes are erased when shipped from Cypress. The remaining regions are erased when shipped from Cypress, and are available for programming of additional permanent data. Refer to Figure 29 for a pictorial representation of the OTP memory space. Cypress, can be used to “mate” a flash component with the system CPU/ASIC to prevent device substitution. programming during the remainder of normal power-on system operation. Table 17. S79FL256S Sector and Memory Address Map, Uniform 512-kbyte Sectors

Figure 29. OTP Address Space — Quad SPI-1 and SPI-2

1. It is recommended that the Lock Bytes for Quad SPI-1 and Quad SPI-2 be programmed with identical data.

Table 18. OTP Address Map for Quad SPI-1 and Quad SPI-2

7.5 Registers

codes) used for each register are noted in each register description. Register, Password Register, PPB Lock Register, PPB Access Register, DYB Access Register, and DDR Data Learning Registers. and writing to each of these registers must also be done in parallel for IO0-IO3 (Quad SPI-1) and for IO4-IO7 (Quad SPI-2). the bit is volatile. If the bit is non-volatile or OTP, the default state is the value of the bit when the device is shipped from Cypress. Non-volatile bits have the same cycling (erase and program) endurance as the main flash array.

7.5.1 Status Register-1 (SR1)

(WRDI 04h), Clear Status Register (CLSR 30h). SRWD bit has the same non-volatile endurance as the main flash array. Table 19. Status Register-1 (SR1)

7 SRWD Status Register

6 P_ERR Programming

Error Occurred Volatile, Read only 0 1 = Error occurred.

5 E_ERR Erase Error

4 BP2

2 BP0

1 WEL Write Enable

0 WIP Write in

can be reset to 0 with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected by the WRR command. command. This is a read-only bit and is not affected by the WRR command. endurance as the main flash array. hardware reset, or software reset, the Write Enable Latch is set to a 0 The WRR command does not affect this bit. the WIP bit is cleared to 0 no operation is in progress. This is a read-only bit.

7.5.2 Configuration Register-1 (CR1)

changed using the WRR command with sixteen input cycles. The configuration register controls certain interface and data protection functions. Table 20. Configuration Register (CR1)

7 LC1

0 Selects number of initial read latency cycles

5 TBPROT Configures Start of

4 RFU RFU RFU 0 Reserved for Future Use

3 BPNV Configures BP2-0 in

2 TBPARM

the start of read data output for all read commands. returned to the host system. Some read commands require additional latency cycles as the SCK frequency is increased. The following latency code tables provide different latency settings that are configured by Cypress. The Enhanced High Performance settings provide latency options the same or faster than additional alternate source SPI memories. there are 5 or more dummy cycles. See Read Memory Array Commands on page 70 for more information on the DLP.

1 QUAD Puts the device into

state is set for QUAD and should not be changed.

0 FREEZE

Table 20. Configuration Register (CR1) (Continued) Table 21. Latency Codes for SDR Enhanced High Performance

1. When using DDR I/O commands with the Data Learning Pattern (DLP) enabled, a Latency Code that provides 5 or more dummy cycles should be selected to allow 1

Data Learning Pattern (DLP) for DDR is used. attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]). attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]). for Serial Read still function normally. The QUAD bit in the S25FL-S devices is factory set to 1 and should not be changed. updating other values in CR1 by a single WRR command. Table 22. Latency Codes for DDR Enhanced High Performance

7.5.3 Status Register-2 (SR2)

Related Commands: Read Status Register-2 (RDSR2 07h). about the Erase Suspend/Resume commands. Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in Program Suspend mode. Resume (PGRS 8Ah) on page 80 for details.

7.5.4 AutoBoot Register

Related Commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).

7.5.5 Bank Address Register

are instead required to provide all four bytes of address. Table 23. Status Register-2 (SR2)

7 RFU Reserved 0 Reserved for Future Use

6 RFU Reserved 0 Reserved for Future Use

5 RFU Reserved 0 Reserved for Future Use

4 RFU Reserved 0 Reserved for Future Use

3 RFU Reserved 0 Reserved for Future Use

2 RFU Reserved 0 Reserved for Future Use

1 ES Erase Suspend Volatile, Read only 0 1 = In erase suspend mode

0 PS Program

Table 24. AutoBoot Register

0 ABE AutoBoot Enable Non-Volatile 0 1 = AutoBoot is enabled

require 4 bytes (32 bits) for the address field. This is a volatile bit.

7.5.6 ECC Status Register (ECCSR)

is an error in the ECC unit eight bit error correction code, the ECC unit of 16 Bytes of data, or that ECC is disabled for that ECC unit. ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC unit data. ECCSR[0] = 1 indicates the ECC is disabled. The default state of “0” for all these bits indicates no failures and ECC is enabled. bits should be treated as “don’t care” and ignored by any software reading status. Table 25. Bank Address Register (BAR)

7 EXTADD Extended Address

1 = 4-byte (32-bits) addressing required from command.

1 BA25 Bank Address Volatile 0 A25 for 1 Gb device

0 RFU Bank Address Volatile 0 RFU for lower density device

Table 26. ECC Status Register (ECCSR)

2 EECC Error in ECC Volatile, Read only 0

1 EECCD Error in ECC unit

0 ECCDI ECC Disabled Volatile, Read only 0 1 = ECC is disabled in the selected ECC unit. 0 = ECC is enabled in the selected ECC unit.

7.5.7 ASP Register (ASPR)

Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh).

1. Default value depends on ordering part number, see Initial Delivery State on page 107.

Reserved for Future Use (RFU) ASPR[15:3, 0]. permanently selected. PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to zero.

7.5.8 Password Register (PASS)

Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h). Table 27. ASP Register (ASPR)

8 RFU Reserved OTP (Note 1) Reserved for Future Use

7 RFU Reserved OTP (Note 1) Reserved for Future Use

6 RFU Reserved OTP 1 Reserved for Future Use

5 RFU Reserved OTP (Note 1) Reserved for Future Use

4 RFU Reserved OTP (Note 1) Reserved for Future Use

3 RFU Reserved OTP (Note 1) Reserved for Future Use

2 PWDMLB

OTP 1 0 = Password Protection Mode permanently enabled. 1 = Password Protection Mode not permanently enabled.

1 PSTMLB

OTP 1 0 = Persistent Protection Mode permanently enabled. 1 = Persistent Protection Mode not permanently enabled.

0 RFU Reserved OTP 1 Reserved for Future Use

Table 28. Password Register (PASS)

7.5.9 PPB Lock Register (PPBL)

7.5.10 PPB Access Re gister (PPBAR)

7.5.11 DYB Access Re gister (DYBAR)

Related Commands: DYB Read (DYBRD E0h) and DYB Program (DYBP E1h). Table 29. PPB Lock Register (PPBL)

0 PPBLOCK Protect PPB Array Volatile Persistent Protection Mode = 1

Table 30. PPB Access Register (PPBAR) sector from program or erase operations. sector from program or erase operations. Table 31. DYB Access Register (DYBAR)

7.5.12 SPI DDR Data Learning Registers

Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read (DLPRD 41h). edge all I/O’s will output 0, the 3rd will output 1, etc. When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR commands. Table 32. Non-Volatile Data Learning Register (NVDLR) Table 33. Volatile Data Learning Register (NVDLR) changed by the host during system operation.

Document Number: 002-00518 Rev. *D Page 46 of 111 S79FL256S/S79FL512S 8. Data Protection

8.1 Secure Silicon Region (OTP)

The device has a 2048-byte One Time Program (OTP) address space that is separate from the main flash array. The OTP area is divided into 32, individually lockable, 64-byte aligned and length regions. The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with the system CPU/ ASIC to prevent device substitution. See OTP Address Space on page 35, One Time Program Array Commands on page 85, and OTP Read (OTPR 4Bh) on page 85.

8.1.1 Reading OTP Memory Space

The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 2-kB OTP address range will yield indeterminate data.

8.1.2 Programming OTP Memory Space

The protocol of the OTP programming command is the same as Page Program. The OTP Program command can be issued multiple times to any given OTP address, but this address space can never be erased. Automatic ECC is programmed on the first programming operation to each 16-byte region. Programming within a 16-byte region more than once disables the ECC. It is recommended to program each 16-byte portion of each 32-byte region once so that ECC remains enabled to provide the best data integrity. The valid address range for OTP Program is depicted in Figure 29, OTP Address Space — Quad SPI-1 and SPI-2 on page 36. OTP Program operations outside the valid OTP address range will be ignored and the WEL in SR1 will remain high (set to 1). OTP Program operations while FREEZE = 1 will fail with P_ERR in SR1 set to 1.

8.1.3 Cypress Programmed Random Number

Cypress standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF) with a 128-bit random number using the Linear Congruential Random Number Method. The seed value for the algorithm is a random number concatenated with the day and time of tester insertion.

8.1.4 Lock Bytes

The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the highest address region related to the byte. The next higher address byte similarly protects the next higher 8 regions. The LSB bit of the lowest address Lock Byte protects the higher address 16 bytes of the lowest address region. In other words, the LSB of location 0x10 protects all the Lock Bytes and RFU bytes in the lowest address region from further programming. See Section 7.4, OTP Address Space on page 35.

8.2 Write Enable Command

The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data. The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes) during power-up, hardware reset, or after the device completes the following commands: –R e s e t – Page Program (PP) – Sector Erase (SE) – Bulk Erase (BE) – Write Disable (WRDI) – Write Registers (WRR) – Quad-input Page Programming (QPP) – OTP Byte Programming (OTPP)

8.3 Block Protection

value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT bit of the configuration register. used concurrently. Use one or the other, but not both.

8.3.1 Freeze Bit

Table 34. Upper Array Start of Protection (TBPROT = 0) Table 35. Lower Array Start of Protection (TBPROT = 1)

8.4 Advanced Sector Protection

enable programming or erase operations, individually, in any or all sectors. An overview of these methods is shown in Figure 30. Figure 30. Advanced Sector Protection Overview sector is protected from program and erase operations. the PPB Lock bit, Persistent Protection and Password Protection. Protection method to set the PPB Lock bit to 1, therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset. sometimes called Boot-code controlled sector protection. the PPB Lock bit to 0. This method requires use of a password to control PPB protection.

Document Number: 002-00518 Rev. *D Page 49 of 111 S79FL256S/S79FL512S

8.4.1 ASP Register

The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP) features. See Table 27, ASP Register (ASPR) on page 43. As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors unprotected, when power is applied. The device programmer or host system must then choose which sector protection method to use. Programming either of the, one-time programmable, Protection Mode Lock Bits, locks the part permanently in the selected mode:  ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.  ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.  ASPR[2:1] = 01 = Password Protection Mode permanently selected.  ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to zero results in a programming failure. ASP register programming rules:  If the password mode is chosen, the password must be programmed prior to setting the Protection Mode Lock Bits.  Once the Protection Mode is selected, the Protection Mode Lock Bits are permanently protected from programming and no further changes to the ASP register is allowed. The programming time of the ASP Register is the same as the typical page programming time. The system can determine the status of the ASP register programming operation by reading the WIP bit in the Status Register. See Status Register-1 (SR1) on page 37 for information on WIP. After selecting a sector protection method, each sector can operate in each of the following states:  Dynamically Locked — A sector is protect ed and can be changed by a simple command.  Persistently Locked — A sector is protec ted and cannot be changed if its PPB Bit is 0.  Unlocked — The sector is unprotected and can be changed by a simple command.

8.4.2 Persistent Protection Bits

The Persistent Protection Bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is related to each sector. When a PPB is 0, its related sector is protected from program and erase operations. The PPB are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased at the same time. The PPB have the same program and erase endurance as the main flash memory array. Preprogramming and verification prior to erasure are handled by the device. Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical sector erase time. During PPB bit programming and PPB bit erasing, status is available by reading the Status register. Reading of a PPB bit requires the initial access time of the device. Persistent Protection Notes:  Each PPB is individually programmed to 0 and all are erased to 1 in parallel.  If the PPB Lock bit is 0, the PPB Program or PPB Erase command does not execute and fails without programming or erasing the PPB.  The state of the PPB for a given sector can be verified by using the PPB Read command.

8.4.3 Dynamic Protection Bits

8.4.4 PPB Lock Bit (PPBL[0])

configured to the desired settings. sequence can set the PPB Lock bit to 1, only another hardware reset or power-up can set the PPB Lock bit. set to 1 by the Password Unlock command.

8.4.5 Sector Protection States Summary

unprotected after a power cycle, software reset, or hardware reset. saved across a power cycle or reset. Table 36. Sector Protection States

Document Number: 002-00518 Rev. *D Page 51 of 111 S79FL256S/S79FL512S

8.4.6 Persistent Protection Mode

The Persistent Protection method sets the PPB Lock bit to 1 during POR or Hardware Reset so that the PPB bits are unprotected by a device hardware reset. Software reset does not affect the PPB Lock bit. The PLBWR command can clear the PPB Lock bit to 0 to protect the PPB. There is no command to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset.

8.4.7 Password Protection Mode

Password Protection Mode allows an even higher level of security than the Persistent Sector Protection Mode, by requiring a 64-bit password for unlocking the PPB Lock bit. In addition to this password requirement, after power up and hardware reset, the PPB Lock bit is cleared to 0 to ensure protection at power-up. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock bit, allowing for sector PPB modifications. Password Protection Notes:  Once the Password is programmed and verified, the Password Mode (ASPR[2]=0) must be set in order to prevent reading the password.  The Password Program Command is only capable of programming ‘0’s. Programming a 1 after a cell is programmed as a 0 results in the cell left as a 0 with no programming error set.  The password is all 1’s when shipped from Cypress. It is located in its own memory space and is accessible through the use of the Password Program and Password Read commands.  All 64-bit password combinations are valid as a password.  The Password Mode, once programmed, prevents reading the 64-bit password and further password programming. All further program and read commands to the password region are disabled and these commands are ignored. There is no means to verify what the password is after the Password Mode Lock Bit is selected. Password verification is only allowed before selecting the Password Protection mode.  The Protection Mode Lock Bits are not erasable.  The exact password must be entered in order for the unlocking function to occur. If the password unlock command provided password does not match the hidden internal password, the unlock operation fails in the same manner as a programming operation on a protected sector. The P_ERR bit is set to one and the WIP Bit remains set. In this case it is a failure to change the state of the PPB Lock bit because it is still protected by the lack of a valid password.  The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly match a password. The Read Status Register-1 command may be used to read the WIP bit to determine when the device has completed the password unlock command or is ready to accept a new password command. When a valid password is provided the password unlock command does not insert the 100 µs delay before returning the WIP bit to zero.  If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.  ECC status may only be read from sectors that are readable. In read protection mode the addresses are forced to the boot sector address. ECC status is shown in that sector while read protection mode is active.

Document Number: 002-00518 Rev. *D Page 52 of 111 S79FL256S/S79FL512S 9. Commands All communication between the host system and the S25FL-S Dual-Quad SPI memory devices is in the form of units called commands. All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All instruction, address, and data information is transferred serially between the host system and memory device. All instructions are transferred from host to memory as a single bit serial sequence on the SI signal. Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to the host serially on SO signal. Quad Output commands provide an address sent to the memory only on the IO0 and IO4 signal. Data will be returned to the host as a sequence of 8-bit (byte) groups on IO0 - IO7. Quad Input/Output (I/O) commands provide an address sent from the host as four-bit (nibble) groups on Quad SPI-1 IO0 - IO3 and Quad SPI-2 IO4 - IO7. Data is returned to the host similarly as 8-bit (byte) groups on IO0 - IO7. Commands are structured as follows:  Each command begins with an eight bit (byte) instruction.  The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.  The S25FL-S Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data information to be done one, or four bits in parallel. This enables a trade off between the number of signal connections (IO bus width) and the speed of information transfer. If the host system can support a four-bit wide IO bus the memory performance can be increased by using the instructions that provide parallel four-bit (quad) transfers.  The width of all transfers following the instruction are determined by the instruction sent.  All sIngle bits or parallel bit groups are transferred in most to least significant bit order.  Some instructions send instruction modifier (mode) bits following the address to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of commands.  The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host.  Read latency may be zero to several SCK cycles (also referred to as dummy cycles).  All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted into the device with the most significant byte first. All data is transferred with the lowest address byte sent first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.  All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded operation. These are discussed in the individual command descriptions. While a program, erase, or write operation is in progress, it is recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most commands to the device, to ensure the new command can be accepted.  Depending on the command, the time for execution varies. A command to read status information from an executing command is available to determine when the command completes execution and whether the command was successful.  Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the host system and the memory device generally handle the details of signal relationships and timing. For this reason, signal relationships and timing are not covered in detail within this software interface focused section of the document. Instead, the focus is on the logical sequence of bits transferred in each command rather than the signal timing and relationships. Following are some general signal relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of commands, see Command Protocol on page 11.

Document Number: 002-00518 Rev. *D Page 53 of 111 S79FL256S/S79FL512S – The host always controls the Chip Select (CS#), Serial Clo ck (SCK), and Serial Input (IO0 and IO4) for single-bit wide transfers. The memory drives the IO0-IO7 signals during transfers. – All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is kept low throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for eight bit transfer multiples to transfer byte granularity information. Some commands will not be accepted if CS# is returned high not at an 8-bit boundary.

9.1 Command Set Summary

The S79FL256S/S79FL512S Dual-Quad SPI devices each contain two Quad SPI devices (Quad SPI-1 and Quad SPI-2)) stacked in a Dual Die Package (DDP). Both devices are selected to decode each command instruction and address when the CS# signal, shared by both devices, goes low. Quad SPI-1 device responds to commands, address, data in and data out on IO0-IO3. Quad SPI- 2 device responds to commands, address, data in and data out on IO4-IO7. All commands are executed by both devices in parallel. Both Quad SPI devices must be configured, by writing to the various status and configuration registers in parallel, to define the same overall sector map and behavior of both devices, selected by each CS# for the DDP.

9.1.1 Extended Addressing

To accommodate addressing above 128 Mb, there are three options: 1. New instructions are provided with 4-byte add ress, used to access up to 32 Gb of memory. Instruction Name Description Code (Hex) 4FAST_READ Read Fast (4-byte Address) 0C 4READ Read (4-byte Address) 13 4QOR Read Quad Out (4-byte Address) 6C 4QIOR Quad I/O Read (4-byte Address) EC 4DDRQIOR DDR Quad I/O Read (4-byte Address) EE 4PP Page Program (4-byte Address) 12 4QPP Quad Page Program (4-byte Address) 34 4P4E Parameter 8-kB Erase (4-byte Address) 21 4SE Erase 512 kB (4-byte Address) DC

1. For backward compatibility to the 3-byte address instructions , the standard instructions can be used in conjunction with

3 bytes to 4 bytes of address field.

1. For backward compatibility to the 3-byte addressing, the st andard instructions can be used in conjunction with the Bank

address selects an address within the bank selected by the Bank Address Register. ii. This applies to read, erase, and program commands. addresses greater than 16 Mbytes. c. Bank Register bits are volatile. i. On power up, the default is Bank0 (the lowest address 16 Mbytes). d. For Read, the device will continuously trans fer out data until the end of the array. i. There is no bank to bank delay. ii. The Bank Address Register is not updated. iii. The Bank Address Register value is used only for the initial address of an access. Table 37. Bank Address Map

Table 38. S79FL256S/S79FL512S Command Set (sorted by function)

9.1.2 Read Device Identification

S79FL512S devices support the three most common device information commands. Table 38. S79FL256S/S79FL512S Command Set (sorted by function) (Continued)

Document Number: 002-00518 Rev. *D Page 57 of 111 S79FL256S/S79FL512S

9.1.3 Register Read or Write

There are multiple registers for reporting embedded operation status or controlling device configuration options. There are commands for reading or writing these registers. Registers contain both volatile and non-volatile bits. Non-volatile bits in registers are automatically erased and programmed as a single (write) operation.

9.1.3.1 Monitoring Operation Status

The host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register-1 command provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR) bits in the status register indicate whether the most recent program or erase command has not completed successfully. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy. Under this condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET commands are valid commands. A Clear Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the device to standby state. CLSR clears the WIP, P_ERR, and E_ERR bits. WRDI clears the WEL bit. Alternatively, Hardware Reset, or Software Reset (RESET) may be used to return the device to standby state.

9.1.3.2 Configuration

There are commands to read, write, and protect registers that control interface path width, interface timing, interface address length, and some aspects of data protection.

9.1.4 Read Flash Array

Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from incrementally higher byte addresses until the host ends the data transfer by driving CS# input High. If the byte address reaches the maximum address of the memory array, the read will continue at address zero of the array. There are several different read commands to specify different access latency and data path widths. Double Data Rate (DDR) commands also define the address and data bit relationship to both SCK edges:  The Read command provides a single address bit per SCK rising edge on the IO0 and IO4 signal with read data returning a single bit per SCK falling edge on the IO1 and IO5 signal. This command has zero latency between the address and the returning data but is limited to a maximum SCK rate of 50 MHz.  Other read commands have a latency period between the address and returning data but can operate at higher SCK frequencies. The latency depends on the configuration register latency code.  The Fast Read command provides a single address bit per SCK rising edge on the IO0 and IO4 signal with read data returning a single bit per SCK falling edge on the IO1 and IO5 signal and may operate up to 133 MHz.  Quad Output read commands provide address a single bit per SCK rising edge on the IO0 and IO4 signal with read data returning four bits of data per SCK falling edge on the IO0- IO7 signals.  Quad I/O Read commands provide address four bits per SCK rising edge with read data returning four bits of data per SCK falling edge on the IO0-IO7 signals.  Quad Double Data Rate read command provides address four bits per every SCK edge with read data returning four bits of data per every SCK edge on the IO0-IO7 signals. Double Data Rate (DDR) operation is only supported for core and I/O voltages of 3 to 3.6V.

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9.1.5 Program Flash Array

Programming data requires two commands: Write Enable (WREN), and Page Program (PP or QPP). The Page Program command accepts from 1 byte up to 512 or 1024 consecutive bytes of data (page) to be programmed in one operation. Programming means that bits can either be left at 1, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation.

9.1.6 Erase Flash Array

The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. A bit needs to be first erased to 1 before programming can change it to a 0. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level.

9.1.7 OTP, Block Protection, an d Advanced Sector Protection

There are commands to read and program a separate One TIme Programmable (OTP) array for permanent data such as a serial number. There are commands to control a contiguous group (block) of flash memory array sectors that are protected from program and erase operations. There are commands to control which individual flash memory array sectors are protected from program and erase operations.

9.1.8 Reset

There is a command to reset to the default conditions present after power on to the device. There is a command to reset (exit from) the Enhanced Performance Read Modes.

9.1.9 Reserved

Some instructions are reserved for future use. In this generation of the S79FL256S/S79FL512S, some of these command instructions may be unused and not affect device operation, some may have undefined results. Some commands are reserved to ensure that a legacy or alternate source device command is allowed without affect. This allows legacy software to issue some commands that are not relevant for the current generation S79FL256S/S79FL512S devices with the assurance these commands do not cause some unexpected action. Some commands are reserved for use in special versions of the FL-S not addressed by this document or for a future generation. This allows new host memory controller designs to plan the flexibility to issue these command instructions. The command format is defined if known at the time this document revision is published.

9.2 Identification Commands

9.2.1 Read Identification — RE MS (Read_ID or REMS 90h)

not be used for new software designs. New software designs should instead make use of the RDID command. Figure 31. READ_ID (90h) Command Sequence Table 39. Read_ID Values

9.2.2 Read Identifi cation (RDID 9Fh)

standard. The device identification and CFI values are assigned by Cypress. independent, JEDEC manufacturer ID independent, forward and backward-compatible for the specified flash device families. driver from the CFI information of the device in use. program, erase, or write cycle that is in progress. sequence is terminated by driving CS# to the logic high state anytime during data output. Quad SPI-1 using IO0 and IO1. The maximum clock frequency for the RDID command is 133 MHz. Figure 32. Read Identification (RDID 9Fh) Command Sequence

9.2.3 Read Electronic Si gnature (RES) (ABh)

and should not be used for new software designs. New software designs should instead make use of the RDID command. clock frequency for the RES command is 50 MHz. The Electronic Signature can be read repeatedly by applying multiples of eight clock cycles. The RES command sequence is terminated by driving CS# to the logic high state anytime during data output. Figure 33. Read Electronic Signature (RES ABh) Command Sequence

9.3 Register Access Commands

9.3.1 Read Status Regi ster-1 (RDSR1 05h)

updated for each eight cycle read. The maximum clock frequency for the RDSR1 (05h) command is 133 MHz. Figure 34. Dual-Quad Read Status Register-1 (RDSR1 05h) Command Sequence

9.3.2 Read Status Regi ster-2 (RDSR2 07h)

updated for each eight cycle read. The maximum clock frequency for the RDSR2 command is 133 MHz. Figure 35. Dual-Quad Read Status Register-2 (RDSR2 07h) Command Sequence Table 40. RES Values

9.3.3 Read Configurati on Register (RDCR 35h)

Figure 36. Dual-Quad Read Configuration Register (RDCR 35h) Command Sequence

9.3.4 Bank Register Read (BRRD 16h)

providing multiples of eight clock cycles. The maximum operating clock frequency for the BRRD command is 133 MHz. Figure 37. Read Bank Register (BRRD 16h) Command

9.3.5 Bank Register Write (BRWR 17h)

flash memory, this command does not require the WREN command to precede it. The BRWR instruction is entered, followed by the data byte on SI. The Bank Register is one data byte in length. bit reserved for the future should always be written as a 0.

Figure 38. Bank Register Write (BRWR 17h) Command

9.3.6 Bank Register Access (BRAC B9h)

to send the legacy DPD (B9h) command. command as a write to the lower address bits of the BAR. A WREN command is not used between the BRAC and WRR commands. affect on the value of the ExtAdd bit (BAR[7]). normal interpretation of a WRR command as a write to Status Register-1 and the Configuration Register. (E_ERR) status bits are set to 1. Figure 39. BRAC (B9h) Command Sequence

9.3.7 Write Registers (WRR 01h)

The Write Registers (WRR) command allows new values to be written to both the Status Register-1 and Configuration Register. Before the Write Registers (WRR) command can be accepted by the device, a Write Enable (WREN) command must be received. Status Register to enable any write operations. SPI-2 on IO4. The Status Register is one data byte in length. Configuration Register bit reserved for the future must be written as a 0. the WRR command format with 16 data bits may be used. Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit. Figure 40. Dual-Quad Write Registers Figure 41. Dual-Quad Write Registers (WRR 01h) Command Sequence

Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) command. command. See Bank Register Access (BRAC B9h) on page 63.

9.3.8 Write Enable (WREN 06h)

IO0 for Quad SPI-1 and IO4 for Quad SPI-2., the write enable operation will not be executed. Figure 42. Dual-Quad Write Enable (WREN 06h) Command Sequence

9.3.9 Write Disable (WRDI 04h)

The Write Disable (WRDI) command sets the Write Enable Latch (WEL) bit of the Status Register-1 (SR1[1]) to a 0. possibly corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1. IO0 for Quad SPI-1 and IO4 for Quad SPI-2, the write disable operation will not be executed. Figure 43. Dual-Quad Write Disable (WRDI 04h) Command Sequence

9.3.10 Clear Status Register (CLSR 30h)

Figure 44. Dual-Quad Clear Status Register (CLSR 30h) Command Sequence

9.3.11 ECC Status Regi ster Read (ECCRD 18h)

Figure 45. ECC Status Register Read Command Sequence

9.3.12 AutoBoot

machine or from some host processor internal ROM code. S25FL-S device will delay code output for a pre-specified number of clock cycles before code streams out. – The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is needed by the host. – The host cannot send commands during this time. – If ABSD = 0, the maximum SCK frequency is 50 MHz. – If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is 0 or 104 MHz if the QUAD bit is set to 1. AutoBoot Register which specifies a 512 byte boundary aligned location; the default address is 00000000h.  Data will continuously shift out until CS# returns high. accept normal command operations. – A minimum of one byte must be transferred. – AutoBoot mode will not initiate again unt il another power cycle or a reset occurs.  An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.  The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value. Figure 46. AutoBoot Sequence (CR1[1]=1) Wait States (ABSD) D1 D2 D3 D4 D5 ...

9.3.13 AutoBoot Regist er Read (ABRD 14h)

clock cycles. The maximum operating clock frequency for ABRD command is 104 MHz. Figure 47. AutoBoot Register Read (ABRD 14h) Command

9.3.14 AutoBoot Register Write (ABWR 15h)

sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. each byte first. The ABWR data is 32 bits in length. P_ERR may be set depending on whether the erase or programming phase of updating the register fails. CS# must be driven to the logic high state after the 32nd bit of data has been latched. If not, the ABWR command is not executed. Latch (WEL) is set to a 0. The maximum clock frequency for the ABWR command is 133 MHz. Figure 48. AutoBoot Register Write (ABWR) Command

9.3.15 Program NVDLR (PNVDLR 43h)

Write Enable Latch (WEL) to enable the PNVDLR operation. The PNVDLR command is entered by shifting the instruction and the data byte on SI-IO0 for Quad SPI-1 and IO4 for Quad SPI-2. set to a 0 The maximum clock frequency for the PNVDLR command is 133 MHz. Figure 49. Program NVDLR (PNVDLR 43h) Command Sequence

9.3.16 Write VDLR (WVDLR 4Ah)

Enable Latch (WEL) to enable WVDLR operation. The WVDLR command is entered by shifting the instruction and the data byte on SI-IO0 for Quad SPI-1 and IO4 for Quad SPI-2. frequency for the PNVDLR command is 133 MHz. Figure 50. Write VDLR (WVDLR 4Ah) Command Sequence

9.3.17 Data Learning Pa ttern Read (DLPRD 41h)

by providing multiples of eight clock cycles. The maximum operating clock frequency for the DLPRD command is 133 MHz. Figure 51. Dual-Quad DLP Read (DLPRD 41h) Command Sequence

9.4 Read Memory Array Commands

 Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands (SDR).  Some SDR commands transfer address one bit per rising edge of SCK and return data 2, or 8 bits of data per rising edge of SCK. These are called Read or Fast Read for 2-bit data; Quad Output for 8-bit data.  Some SDR commands transfer both address and data 8 bits per rising edge of SCK. These are called Quad I/O for 8 bit. 256 Mbits or higher density, the traditional SPI 3-byte addresses are unable to directly address all locations in the memory array. series of Quad I/O read accesses. commands are used the host must stop driving the IO signals (outputs are high impedance) before the end of last dummy cycle. host stops driving address or mode bits.

SCK to data edges so that the memory controller can capture data at the center of the data eye. selected to allow additional time for the host to stop driving before the memory starts driving data, to minimize I/O driver conflict. cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP. whether the device remains in enhanced high performance read mode.

9.4.1 Read (Read 03h or 4READ 13h)

to 000000h, allowing the read sequence to be continued indefinitely. Figure 52. Dual-Quad Read Command Sequence (READ 03h or 13h)

1. A = MSB of address = 23 for command 03h, or 31 for command 13h.

9.4.2 Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)

The maximum operating clock frequency for FAST READ command is 133 MHz. to 000000h, allowing the read sequence to be continued indefinitely. Figure 53. Dual-Quad SPI Fast Read (FAST_READ) Command Sequence

9.4.3 Quad Output Read (QOR 6Bh or 4QOR 6Ch)

at the SCK frequency by the falling edge of the SCK signal. (refer to Table 21, Latency Codes for SDR Enhanced High Performance on page 39). to 000000h, allowing the read sequence to be continued indefinitely.

Figure 54. Dual-Quad, Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence

1. A = MSB of address = 23 for command 6Bh, or 31 for command 6Ch.

9.4.4 Quad I/O Read (Q IOR EBh or 4QIOR ECh)

might allow for code execution (XIP) directly from the S25FL-S device. The maximum operating clock frequency for Quad I/O Read is 104 MHz. latency code tables use the same latency values for the Quad I/O Read command. (8 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal. to 000000h, allowing the read sequence to be continued indefinitely.

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9.4.5 DDR Quad I/O Read (EDh, EEh)

The Read DDR Quad I/O command is similar to the Quad I/O Read command but allows input of the address four bits on every edge of the clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from the S25FL-S devices. The QUAD bit of the Configuration Register is set (CR[1]=1) to enable the Quad capability in the S25FL-S device. The instruction  EDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or  EDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or  EEh is followed by a 4-byte address (A31-A0) The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR fashion, with four bits at a time on each clock edge through IO0-IO7. The maximum operating clock frequency for Read DDR Quad I/O command is 80 MHz. For Read DDR Quad I/O, there is a latency required after the last address and mode bits are shifted into the IO0-IO7 signals before data begins shifting out of IO0-IO7. This latency period (dummy cycles) allows the device’s internal circuitry enough time to access the initial address. During these latency cycles, the data value on IO0-IO7 are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles. The number of dummy cycles is determined by the frequency of SCK. The number of dummy cycles is set by the LC bits in the Configuration Register (CR1). Both latency tables provide cycles for mode bits so a series of Quad I/O DDR commands may eliminate the 8-bit instruction after the first command sends a complementary mode bit pattern, as shown in Figure 57. This feature removes the need for the eight bit SDR instruction sequence and dramatically reduces initial access times (improves XIP performance). The Mode bits control the length of the next Read DDR Quad I/O operation through the inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to Continuous Read DDR Quad I/O Mode and the next address can be entered (after CS# is raised high and then asserted low) without requiring the EDh or EEh instruction, as shown in Figure 58 thus, eliminating eight cycles from the command sequence. The following sequences will release the device from Continuous Read DDR Quad I/O mode; after which, the device can accept standard SPI commands: 1. During the Read DDR Quad I/O Command Sequence, if the Mode bits are not complementary the next time CS# is raised high and then asserted low the device will be released from Read DDR Quad I/O mode. 2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 - IO7) are not set for a valid instruction sequence, then the device will be released from Read DDR Quad I/O mode. The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. The HOLD function is not valid during Quad I/O DDR commands. Note that the memory devices drive the IOs with a preamble prior to the first data value. The preamble is a pattern that is used by the host controller to optimize data capture at higher frequencies. The preamble drives the IO bus for the four clock cycles immediately before data is output. The host must be sure to stop driving the IO bus prior to the time that the memory starts outputting the preamble.

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9.5 Program Flash Array Commands

9.5.1 Program Granularity

9.5.1.1 Automatic ECC

Each 16 byte aligned and 16 byte length Programming Block has an automatic Error Correction Code (ECC) value. The data block plus ECC form an ECC unit. In combination with Error Detection and Correction (EDC) logic the ECC is used to detect and correct any single bit error found during a read access. When data is first programmed within an ECC unit the ECC value is set for the entire ECC unit. If the same ECC unit is programmed more than once the ECC value is changed to disable the Error Detection and Correction (EDC) function. A sector erase is needed to again enable Automatic ECC on that Programming Block. The 16 byte Program Block is the smallest program granularity on which Automatic ECC is enabled. These are automatic operations transparent to the user. The transparency of the Automatic ECC feature enhances data accuracy for typical programming operations which write data once to each ECC unit but, facilitates software compatibility to previous generations of FL-S family of products by allowing for single byte programming and bit walking in which the same ECC unit is programmed more than once. When an ECC unit has Automatic ECC disabled, EDC is not done on data read from the ECC unit location. An ECC status register is provided for determining if ECC is enabled on an ECC unit and whether any errors have been detected and corrected in the ECC unit data or the ECC (See Section 7.5.6, ECC Status Register (ECCSR) on page 42.) The ECC Status Register Read (ECCRD) command is used to read the ECC status on any ECC unit. EDC is applied to all parts of the Flash address spaces other than registers. An ECC is calculated for each group of bytes protected and the ECC is stored in a hidden area related to the group of bytes. The group of protected bytes and the related ECC are together called an ECC unit. ECC is calculated for each 16 byte aligned and length ECC unit.  Single Bit EDC is supported with 8 ECC bits per ECC unit, plus 1 bit for an ECC disable Flag.  Sector erase resets all ECC bits and ECC disable flags in a sector to the default state (enabled).  ECC is programmed as part of the standard Program commands operation.  ECC is disabled automatically if multiple programming operations are done on the same ECC unit.  Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16-byte ECC unit.  The ECC disable flag is programmed when ECC is disabled.  To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased.  To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC is stored for that unit and not disabled.  The calculation, programming, and disabling of ECC is done automatically as part of a programming operation. The detection and correction, if needed, is done automatically as part of read operations. The host system sees only corrected data from a read operation.  ECC protects the OTP region - however a second program operation on the same ECC unit will disable ECC permanently on that ECC unit (OTP is one time programmable, hence an erase operation to re-enable the ECC enable/indicator bit is prohibited).

9.5.1.2 Page Programming

Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory array. This sets an upper limit on the amount of data that can be programmed with a single programming command. Page Programming allows up to a page size (either 512 bytes or 1024 bytes) to be programmed in one operation. The page is aligned on the page size address boundary. It is possible to program from one bit up to a page size in each Page programming operation. It is recommended that a multiple of 16 byte length and aligned Program Blocks be written. For the very best performance, programming should be done in full pages of 1024 bytes aligned on 1024-byte boundaries with each Page being programmed only once.

9.5.1.3 Single Byte Programming

9.5.2 Page Program (PP 02h or 4PP 12h)

is a result of only requiring the user to enter one single page address to cover the entire page boundary. within the page, without having any affect on the other bytes of the same page. will save overall programming time versus loading less than a page size into the program buffer. that prevents successful completion of programming. Figure 59. Dual-Quad Page Program (PP 02h or 4PP 12h) Command Sequence

9.5.3 Quad Page Prog ram (QPP 32h or 38h, or 4QPP 34h)

maximum frequency for the QPP command is 80 MHz. must be executed before the device will accept the QPP command (Status Register-1, WEL=1). and at least two data bytes, into the IO signals. Data must be programmed at previously erased (FFh) memory locations. All other functions of QPP are identical to Page Program. The QPP command sequence is shown in the figure below. Figure 60. Dual-Quad, Quad Page Program Command Sequence

1. A = MSB of address = A23 for PP 02h, or A31 for PP 02h, or for 4PP 12h.

Instruction Address D1 D2 D3 D4 ...

9.5.4 Program Suspend (PGSP 85h) and Resume (PGRS 8Ah)

suspended sector or non-program-suspended-page. Program Suspend is valid only during a programming operation. tPSL, see Table 43, Program Suspend AC Parameters on page 93. programming operation was completed during the suspend operation, a resume command is not needed and has no effect if issued. Program Resume commands will be ignored unless a Program operation is suspended. Figure 61. Dual-Quad Program Suspend Command Sequence Figure 62. Dual Quad Program Resume Command Sequence

9.6 Erase Flash Array Commands

9.6.1 Parameter 8-kB Sector Erase (P4E 20h or 4P4E 21h)

configured with the 256-kB sector option. sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. memory array. If CS# is not driven high after the last bit of address, the sector erase operation will not be executed. the value of the Write-In Progress (WIP) bit to determine when the operation has been completed. The WIP bit will indicate a 1. when the erase cycle is in progress and a 0 when the erase cycle has been completed. Figure 63. Dual-Quad Parameter Sector Erase Command Sequence (P4E 20h or 4P4E 21h)

1. A = MSB of address = A23 for P4E 20h, or A31 for 4P4E 21h.

9.6.2 Sector Erase ( SE D8h or 4SE DCh)

the Write Enable Latch (WEL) in the Status Register to enable any write operations. after the last bit of address, the sector erase operation will not be executed.

a 1 when the erase cycle is in progress and a0 when the erase cycle has been completed. be executed and will set the E_ERR status. always erase 512 kbytes provides for software compatibility with higher density and future S79FL family devices. range and will set the E_ERR status. Figure 64. Dual-Quad Sector Erase (SE 20h or 4SE 21h) Command Sequence

1. A = MSB of address = A23 for SE D8h, or A31 for 4SE DCh.

9.6.3 Bulk Erase (BE 60h or C7h)

Enable Latch (WEL) in the Status Register to enable any write operations. after the last bit of instruction, the BE operation will not be executed. when the erase cycle is in progress and a 0 when the erase cycle has been completed. E_ERR status will not be set. Figure 65. Bulk Erase Command Sequence

9.6.4 Erase Suspend and Resume Co mmands (ERSP 75h or ERRS 7Ah)

completed at the time WIP changes to 0. If the erase operation was completed during the suspend operation, a resume command is not needed and has no effect if issued. Erase Resume commands will be ignored unless an Erase operation is suspended. program data to the device. Reading at any address within an erase-suspended sector produces undetermined data. A WREN command is required before any command that will change non-volatile data, even during erase suspend. command; in this special case the WRR is interpreted as a write to the Bank Address Register, not a write to SR1 or CR1. If a program command is sent for a location within an erase suspended sector the program operation will fail with the P_ERR bit set. will be ignored unless an Erase is Suspend. After an Erase Resume command is sent, the WIP bit in the status register will be set to a 1 and the erase operation will continue. Further Resume commands are ignored. resume and the next suspend command greater than or equal to tERS. See Table 44, Erase Suspend AC Parameters on page 93. Figure 66. Dual-Quad Erase Suspend Command Sequence

Figure 67. Dual-Quad Erase Resume Command Sequence Table 41. Commands Allowed During Program or Erase Suspend CLSR 30 X Clear status may be used if a program operation fails during erase suspend. programming during erase suspend. programming during erase suspend. ERRS 7A X Required to resume from erase suspend. FAST_READ 0B X X All array reads allowed in suspend. 4FAST_READ 0C X X All array reads allowed in suspend. MBR FF X X May need to reset a read operation during suspend. program suspend within an erase suspend. PGSP 85 X Program suspend allowed during erase suspend. PP 02 X Required for array program during erase suspend. 4PP 12 X Required for array program during erase suspend. QPP 32, 38 X Required for array program during erase suspend. 4QPP 34 X Required for array program during erase suspend. 4READ 13 X X All array reads allowed in suspend. DDRQIOR ED X X All array reads allowed in suspend. DDRQIOR4 EE X X All array reads allowed in suspend. QIOR EB X X All array reads allowed in suspend. 4QIOR EC X X All array reads allowed in suspend. QOR 6B X X All array reads allowed in suspend. 4QOR 6C X X All array reads allowed in suspend. RDSR1 05 X X Needed to read WIP to determine end of suspend process. RDSR2 07 X X Needed to read suspend status to determine whether the operation is suspended or complete. READ 03 X X All array reads allowed in suspend. RESET F0 X X Reset allowed anytime. WREN 06 X Required for program command within erase suspend.

9.7 One Time Program Array Commands

9.7.1 OTP Program (OTPP 42h)

issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. on page 78 for the command sequence.

9.7.2 OTP Read (OTPR 4Bh)

the latency code. The OTP read command always has one dummy byte of latency as shown below. Figure 68. Read OTP (OTPR 4Bh) Command Sequence program. WRR is allowed when following BRAC. Table 41. Commands Allowed During Program or Erase Suspend (Continued)

9.8 Advanced Sector Protection Commands

9.8.1 ASP Read (ASPRD 2Bh)

frequency for the ASP Read (ASPRD) command is 133 MHz. Figure 69. Dual-Quad SPI ASPRD Command Sequence

9.8.2 ASP Program (ASPP 2Fh)

enable any write operations. significant byte first. The ASP Register is two data bytes in length. Figure 70. ASPP (2Fh) Command

9.8.3 DYB Read (DYBRD E0h)

a separate DYB Read command. The maximum operating clock frequency for READ command is 133 MHz. Figure 71. DYBRD Command Sequence

9.8.4 DYB Write (DYBWR E1h)

enable any write operations. the data byte on SI. The DYB Access Register is one data byte in length. completed, the Write Enable Latch (WEL) is set to a 0. Figure 72. DYBWR (E1h) Command Sequence

9.8.5 PPB Read (PPBRD E2h)

access register contents are shifted out on SO. Read command. The maximum operating clock frequency for the PPB Read command is 133 MHz. Figure 73. PPBRD (E2h) Command Sequence

9.8.6 PPB Program (PPBP E3h)

enable any write operations. Figure 74. PPBP (E3h) Command Sequence

9.8.7 PPB Erase (PPBE E4h)

Register to enable any write operations. The instruction E4h is shifted into SI by the rising edges of the SCK signal. being driven to the logic high state after the eighth bit of the instruction, the PPB erase operation will not be executed. been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed. Erase suspend is not allowed during PPB Erase. Figure 75. PPB Erase (PPBE E4h) Command Sequence

9.8.8 PPB Lock Bit Read (PLBRD A7h)

Status Register before issuing a new command to the device. Figure 76. PPB Lock Register Read Command Sequence

9.8.9 PPB Lock Bit Write (PLBWR A6h)

(WEL) in the Status Register to enable any write operations. The PLBWR command is entered by driving CS# to the logic low state, followed by the instruction. the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the PLBWR command is 133 MHz. Figure 77. PPB Lock Bit Write (PLBWR A6h) Command Sequence

9.8.10 Password R ead (PASSRD E7h)

the PASSRD command is ignored. Figure 78. Password Read (PASSRD E7h) Command Sequence

9.8.11 Password Program (PASSP E8h)

Latch (WEL) to enable the PASSP operation. to 0 in the ASP Register (ASP[2]). After the Password Protection Mode is selected the PASSP command is ignored. SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length. maximum clock frequency for the PASSP command is 133 MHz. Figure 79. Password Program (PASSP E8h) Command Sequence

9.8.12 Password Unlock (PASSU E9h)

SI, least significant byte first, most significant bit of each byte first. The password is sixty-four (64) bits in length. is a 1 during the self-timed PASSU cycle, and is a 0 when it is completed. If the password does match, the PPB Lock bit is set to 1. The maximum clock frequency for the PASSU command is 133 MHz. Figure 80. Password Unlock (PASSU E9h) Command Sequence

9.9 Reset Commands

9.9.1 Software Reset Command (RESET F0h)

and requires tRPH time to execute. Figure 81. Dual-Quad Software Reset (RESET F0h) Command Sequence

9.9.2 Mode Bit Reset (MBR FFh)

The MBR command sends Ones on IO0 and IO4 for 8 SCK cycles. IO1 - IO3 and IO5 - IO7 are “don’t care” during these cycles. Figure 82. Dual-Quad SPI Mode Bit (MBR FFh) Reset Command Sequence

9.10 Embedded Algorithm Performance Tables

1. Typical program and erase times assume the following conditions: 25°C, V CC = 3.0V; random data pattern.
2. Under worst case conditions of 90°C; 100,000 cycles max.
3. Maximum value also applies to OTPP , PPBP, ASPP, PASSP , ABWR, and PNVDLR programming commands.
4. Maximum value also applies to the PPBE erase command.

Table 42. Program and Erase Performance Table 43. Program Suspend AC Parameters Table 44. Erase Suspend AC Parameters

10.1 Erase Endurance

1. Each write command to a non-volatile register causes a PE cycle on the entire non-volatile register array.

10.2 Data Retention

Table 45. Erase Endurance Table 46. Data Retention

1. Software Interface Reference

11.1 Command Summary

Table 47. S79FL256S/S79FL512S Instruction Set (sorted by instruction)

01 WRR Write Register (Status-1, Configuration-1) 133

02 PP Page Program (3- or 4-byte address) 133

03 READ Read (3- or 4-byte address) 50

04 WRDI Write Disable 133

05 RDSR1 Read Status Register-1 133

06 WREN Write Enable 133

07 RDSR2 Read Status Register-2 133

14 ABRD AutoBoot Register Read 133

15 ABWR AutoBoot Register Write 133

16 BRRD Bank Register Read 133

17 BRWR Bank Register Write 133

18 ECCRD ECC Read 133

20 P4E Parameter 8-kB sector Erase (3- or 4-byte address) 133

30 CLSR Clear Status Register - Erase/Program Fail Reset 133

32 QPP Quad Page Program (3- or 4-byte address) 80

35 RDCR Read Configuration Register-1 133

38 QPP Quad Page Program (3- or 4-byte address) 80

41 DLPRD Data Learning Pattern Read 133

42 OTPP OTP Program 133

43 PNVDLR Program NV Data Learning Register 133

60 BE Bulk Erase 133

75 ERSP Erase Suspend 133

85 PGSP Program Suspend 133

90 READ_ID (REMS) Read Electronic Manufacturer Signature 133

Table 47. S79FL256S/S79FL512S Instruction Set (sorted by instruction) (Continued)

11.2 Device ID and Common Flash Interface (ID-CFI) Address Map

11.2.1 Field Definitions

Table 48. Manufacturer and Device ID legacy single byte field. The value is OPN dependent. Table 49. CFI Query Identification String

Table 50. CFI System Interface String Table 51. Device Geometry Definition for 256-Mbit and 512-Mbit Bottom Boot Initial Delivery State

Table 51. Device Geometry Definition for 256-Mbit and 512-Mbit Bottom Boot Initial Delivery State (Continued) Table 52. Device Geometry Definition for 256-Mbit and 512-Mbit Uniform Sector Devices

Table 53. CFI Primary Vendor-Specific Extended Query

needed or not recognized by the software. Table 53. CFI Primary Vendor-Specific Extended Query (Continued) Table 54. CFI Alternate Vendor-Specific Extended Query Header Table 55. CFI Alternate Vendor-Specific Extended Query Parameter 0

Table 56. CFI Alternate Vendor-Specific Extended Query Parameter 80h Address Options Table 55. CFI Alternate Vendor-Specific Extended Query Parameter 0 (Continued) Table 57. CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands

Table 58. CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protection Table 59. CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing Table 60. CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR)

Table 60. CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) (Continued)

Table 61. CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC (DDR)

Table 61. CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC (DDR) (Continued)

reserve space in the ID-CFI map or to force space (pad) to align a following parameter to a required boundary.

11.3 Initial Delivery State

 The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh).  The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased to FFh.  The ID-CFI address space contains the values as defined in the description of the ID-CFI address space.  The Status Register-1 contains 00h (all SR1 bits are cleared to 0’s).  The Configuration Register-1 contains 02h.  The Autoboot register contains 00h.  The Password Register contains FFFFFFFF-FFFFFFFFh.  The ASP Register contents are shown below. Table 62. CFI Alternate Vendor-Specific Extended Query Parameter F0h RFU Table 63. ASP Register Content

Document Number: 002-00518 Rev. *D Page 108 of 111 S79FL256S/S79FL512S

Ordering Information

1. Ordering Informatio n S79FL256S/S79FL512S The ordering part number is formed by a valid combination of the following: Notes: 1. Parameter with 128-kB sectors = A parameter of 32 x 8-kB se ctors with all remaining sectors being 128 kB, with a 512B programming buffer. 2. Uniform 512-kB sectors = All sectors are uniform 512-kB with a 1024B programming buffer. S79FL 256 S DS M F V G 0 0 Packing Type 0 = Tray 1 = Tube 3 = 13” Tape and Reel Model Number (Sector Type) 0 = Parameter 8kB with 128-kB sectors (1) 1 = Uniform 512-kB sectors (2) Model Number (Latency Type, Package Details, RESET#) G = EHPLC, SO footprint with RESET# Temperature Range I = Industrial (–40°C to + 85°C) V = Industrial Plus (–40°C to + 105°C) A = Automotive, AEC-Q100 Grade 3(–40°C to + 85°C) B = Automotive, AEC-Q100 Grade 2 (–40°C to + 105°C) Package Materials F = Lead (Pb)-free Package Type M = 16-pin SO package Speed DS = 80 MHz DDR Device Technology S = 65 nm MirrorBit Process Technology Density 256 = 256 Mbit 512 = 512 Mbit Device Family S79FL Cypress Memory 3.0 Volt-Only, Dual-Quad Serial Peripheral Interface (SPI) Flash Memory

Document Number: 002-00518 Rev. *D Page 109 of 111 S79FL256S/S79FL512S Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations - Automotive Grade / AEC-Q100 The table below lists configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check on newly released combinations. Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products. Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in combination with PPAP. Non–AEC-Q100 grade products are not manufactured or documented in full compliance with ISO/TS-16949 requirements. AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949 compliance. Valid Combinations Base Ordering Part Number Speed Option Package and Temperature Model Number Packing Type Package Marking S79FL256S DS MFI, MFV G0 0, 1, 3 79FL256S + S + (Temp) + F + (Model Number) S79FL512S DS MFI, MFV G0 0, 1, 3 79FL512S + S + (Temp) + F + (Model Number) Valid Combinations Base Ordering Part Number Speed Option Package and Temperature Model Number Packing Type Package Marking S79FL256S DS MFA, MFB G0 0, 1, 3 79FL256S + S + (Temp) + F + (Model Number) S79FL512S DS MFA, MFB G0 0, 1, 3 79FL512S + S + (Temp) + F + (Model Number)

Document Number: 002-00518 Rev. *D Page 110 of 111 S79FL256S/S79FL512S 13. Revision History Document History Page Document Title: S79FL256S/S79FL512S, 256 Mbit (32 MB)/512 Mbit (64 MB), 3 V, Dual-Quad SPI Flash Document Number: 002-00518 Rev. ECN No. Orig. of Change Submission Date Description of Change ** – ANSI 09/25/2014 Initial release. *A 4973702 ANSI 10/20/2015 Updated to Cypress template. *B 5353089 BWHA 08/09/2016 Changed status from Preliminary to Final. Updated Overview: Updated Other Resources: Added Cypress Flash Memory Roadmap. Updated Timing Specifications: Updated AC Test Conditions: Updated Capacitance Characteristics: Updated Table 8: Changed maximum value of CIN parameter from 8 pF to 14 pF. Changed maximum value of COUT parameter from 8 pF to 20 pF. Updated Address Space Maps: Updated Registers: Updated Configuration Register-1 (CR1): Updated Table 20: Updated details in all columns corresponding to Bit 2. Updated Ordering Information S79FL256S/S79FL512S: Updated details corresponding to “0” under “Model Number (Sector Type)” and also updated the corresponding note. Removed Note “EHPLC = Enhanced High Performance Latency Code table”. Updated to new template. Completing Sunset Review. *C 5617675 ECAO 03/10/2017 Updated SOIC 16 Physical Diagram: Updated SO3016 to SS3016. Updated Ordering Information S79FL256S/S79FL512S: Added support for Industrial, Industrial Plus, Automotive AEC-Q100 Grade 2 and 3 temperature range options. Added ECC information. Added Data Integrity information. Updated Cypress logo and Sales page. *D 5962279 AESATMP8 11/09/2017 Updated logo and Copyright.

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