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HyperFlash™ and HyperRAM™ Multi-Chip Package 1.8V/3V Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-03902 Rev. *D Revised February 23, 2017 HyperFlash™ and HyperRAM™ Multi-Chip Package 3 V Distinctive Characteristics ■ HyperFlash™ and HyperRAM™ in Multi-Chip Package (MCP) ❐ 1.8V, 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KS512SC0) ❐ 3.0V, 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KL512SC0) ❐ 3.0V, 256 Mb HyperFlash and 64 Mbit HyperRAM (S71KL256SC0) ❐ FBGA 24-ball, 6  8  1.0 mm package ■ HyperBus Interface ❐ 1.8V I/O, 12 bus signals

  • Differential clock (CK/CK#) ❐ 3.0V I/O, 11 bus signals
  • Single ended clock (CK) ❐ Chip Select (CS#) ❐ 8-bit data bus (DQ[7:0]) ❐ Read-Write Data Strobe (RWDS)
  • Bidirectional Data Strobe/Mask
  • Output at the start of all transactions to indicate refresh latency
  • Output during read transactions as Read Data Strobe
  • Input during write transactions as Write Data Mask (Hyper- RAM only) ■ Optional Signals ❐ Reset ❐ INT# output to generate external interrupt
  • Busy to Ready Transition ❐ RSTO# Output to generate system level Power-On Reset (POR)
  • User configurable RSTO# Low period ■ High Performance ❐ Double-Data Rate (DDR)
  • Two data transfers per clock ❐ Up to 166-MHz clock rate (333 MB/s) at 1.8V VCC ❐ Up to 100-MHz clock rate (200 MB/s) at 3.0V VCC

Document Number: 002-03902 Rev. *D Page 2 of 14 SUPPLEMENT S71KS512SC0 S71KL256SC0 S71KL512SC0

Contents

HyperBus MCP Family with HyperFlash HyperBus MCP — FBGA 24-Ball, Valid Combinations — Automotive Grade /

mation is intended for hardware system designers and software developers of applications, operating systems, or tools. congestion while also maintaining or improving signal integrity over separately packaged memory configurations. combination with HyperRAM 64 Mb (8 Mbyte). HyperBus, HyperFlash, and HyperRAM datasheets. Table 1. Affected Documents/Related Documents

Figure 1. HyperBus MCP Signal Diagram Table 2. Signal Descriptions Note: Single-ended clock is available on 3.0V devices only. the crossing edges of the CK/CK# pair. Note: Differential clock is available on 1.8V devices only. Read-Write Data Strobe: Output data during read transactions are edge aligned with RWDS. Read and Write transactions. indicate that an on-chip event has occurred. INT# is an open-drain output. a weak pull-up, if RESET# is left unconnected it will be pulled up to the High state. RESET# is not connected to the HyperRAM.

Figure 2. HyperBus Connections Including Optional Signals

  1. CK# is for 1.8V devices only.

Figure 3. 24-Ball FBGA, 6 x 8 mm, 5 x 5 Ball Footprint (Top View)

  1. C2 and A3 are chip select (CS#) signals 1 and 2 us ed for HyperFlash and HyperRAM devices respectively.
  2. V SS and VSSQ are internally connected.
  3. CK# (B1) is RFU in 3.0V devices

Figure 4. ELA024 — FBGA 24-Ball 6 x 8 x 1 mm MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION. N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0. POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. "e" REPRESENTS THE SOLDER BALL GRID PITCH. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION9. ALL DIMENSIONS ARE IN MILLIMETERS.

0.00 BSC

1.00 BSC

4.00 BSC

6.00 BSC

8.00 BSC

JEDEC SPECIFICATION NO. REF: N/A10.

Document Number: 002-03902 Rev. *D Page 8 of 14 SUPPLEMENT S71KS512SC0 S71KL256SC0 S71KL512SC0 Electrical Specifications For the general description of the HyperBus interface electrical specifications, refer to the HyperBus Specification. The following section describes HyperFlash device dependent aspects of electrical specifications. Absolute Maximum Ratings Ambient Temperature with Power Applied: 65 °C to +105 °C DC Characteristics Only one memory may have its ch ip select active (Low) at any point in time. For each of the conditions below refer to the Hyper- Flash and HyperRAM datasheets for the most accurate infor- mation: ■ Active core read or write current will be that of the selected device plus the standby current of the non-selected device. But, the added standby current is gener ally not significant as it is less than 300 A. ■ Active IO read current will be that of the selected device. ■ Active clock stop current will be that of the selected device plus the standby current of the non-selected device. But, the added standby current is generally not significant as it is less than 300 A. ■ Program or erase current will be that of the HyperFlash device. Note however, that program and erase operations are long time frame events that extend beyond the duration of a HyperFlash chip select period. Thus, if the HyperRAM is selected for read or write during an on going HyperFlash program or erase operation, the active current will be the sum of the HyperFlash program or erase operation and the HyperRAM read or write current. ■ Standby current, when neither memory is selected and no embedded flash operation is in progress, is the sum of the memory standby currents. ■ Deep Power Down (DPD) curren t, is the sum of the memory DPD currents. ■ Power On Reset (POR) current is the sum of the memory standby currents. ■ Input leakage current is the sum of the memory input leakage currents. For reference purpose, Table 3 aids in the estimation of the above operating conditions current consumption. However, refer to the HyperFlash and HyperRAM datasheets for the most accurate information.

Table 3. 3.0V DC Characteristics (CMOS Compatible)

  1. I CC active while Embedded Algorithm is in progress.
  2. Active Clock Stop Mode enables the lower power mode when the CK signals remain stable for t ACC + 30 ns
  3. Typical I CC values are measured at tAI = 25 °C and VCC = VCCQ = 1.8V/3.0V (not applicable to IDPD for 85 °C and 105 °C).
  1. These values are guaranteed by design and are tested on a sample basis only.
  2. Pin capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VCC, VCCQ are applied and all other pins

(except the pin under test) floating. DQs should be in the High Impedance state.

  1. The capacitance values for the CK, CK#, RWDS and DQx pins must have similar capacitance values to allow for signal propagation time matching in the system. The

capacitance value for CS# is not as critical because there are no critical timings between CS# going active (Low) and data being presented on the DQs bus. Table 3. 3.0V DC Characteristics (CMOS Compatible) (Continued)

  1. I CC active while Embedded Algorithm is in progress.
  2. Active Clock Stop Mode enables the lower power mode when the CK signals remain stable for t
  3. Typical I CC values are measured at tAI = 25 °C and VCC = VCCQ = 1.8V/3.0V (not applicable to IDPD for 85 °C and 105 °C).

Table 4. 1.8V/3.0V Capacitive Characteristics

your local sales representative to confirm availability of specific combinations and to check on newly released combinations.

  1. FBGA package marking omits the leading S7, the package type character and packing type character from the ordering part number from the ordering part number.

Table 5. Valid Standard Combinations

combinations and to check on newly released combinations. Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products. FBGA package marking omits the leading S7, the package type character and packing type character from the ordering part number from the ordering part number. Table 6. Valid Combinations — Automotive Grade / AEC-Q100

Document Number: 002-03902 Rev. *D Page 13 of 14 SUPPLEMENT S71KS512SC0 S71KL256SC0 S71KL512SC0 Document History Page Document Title: S71KS512SC0, S71KL256SC0, S71KL512SC0, HyperFlash™ and HyperRAM™ Multi-Chip Package 1.8V/3V Document Number: 002-03902 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 5023814 MAMC 11/23/2015 Initial release. *A 5188954 RYSU 07/07/2016 Updated HyperBus MCP 3 V Signal Descriptions: Updated Table 2: Updated details in “Description” column corresponding to RESET# pin. Updated HyperBus MCP Block Diagram. Updated Physical Interface: Updated HyperBus MCP — FBGA 24-Ball, 5x5 Array Footprint : Added Note 2. Updated Physical Diagram: Added Figure 4. Updated Electrical Specifications: Updated DC Characteristics: Updated Table 3: Changed typical value of ICC5 parameter from 20 mA to 10 mA. Changed maximum value of ICC5 parameter from 40 mA to 20 mA. Updated Table 4: Updated values of all parameters. Updated to new template. *B 5442136 RYSU 09/27/2016 Updated Document Title to read as “S71KL512SC0, HyperFlash™ and HyperRAM™ Multi-Chip Package 3V”. Removed part number “S71KL256SC0” related information in all instances across the document. Removed 256 Mb density related information in all instances across the document. Updated Ordering Part Numbers: Added Automotive, AEC-Q100 Grade 3 and Automotive, AEC-Q100 Grade 2 Temperature Range details. Removed 128 Mb, 256 Mb details. Updated Valid Combinations - Standard: Removed S71KL256S and its corresponding details. Added Valid Combinations — Automotive Grade / AEC-Q100 . Updated to new template. *C 5560279 RYSU 12/20/2016 Updated Document Title to read as “S71KL256SC0/S71KL512SC0, HyperFlash™ and HyperRAM™ Multi-Chip Package 3 V”. Added part number “S71KL256SC0” related information in all instances across the document. Added 256 Mb density related information in all instances across the document. Updated Electrical Specifications: Updated DC Characteristics: Updated Table 4: Added values corresponding to S71KL256SC0. Updated Ordering Part Numbers: Added 256 Mb details. Updated Valid Combinations - Standard: Added S71KL256S and its corresponding details. Updated Valid Combinations — Automotive Grade / AEC-Q100 : Added S71KL256S and its corresponding details. *D 5635102 SZZX 02/23/2017 Added S71KS512S and its corresponding details. Updated Sales and Copyright information.

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