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Technical content
Features
32bit ARM® Cortex®-R5 CPU Core Clock Maximum clock frequency: 144MHz, 96MHz* DMA controller: 16 channels External interrupt: 16 channels Base timer: 30 channels 32-bit free-run timer: 6 channels 32-bit input capture: 12 channels 32-bit output compare: 12 channels 12-bit A/D converter: 64, 56* channels (2 units total) Real Time Clock Multi-function serial interface: 22, 4* channels, Selectable from UART/CSIO/LIN/I2C CAN-FD(192msb[reception]): 2, 1* channels Exclusion access memory Watchdog timer: 1 channel(SW)+1 channel(HW) CRC generation: 1 channel Secure Hardware Extension General Purpose I/O port: 150, 116* Built-in CR oscillator Debug interface JTAG Debug Port Partial-wakeup function Low Voltage Detector Clock Supervisor Power Supply: 1 power voltage(5V) * Spec for S6J311AHxB, S6J3119HxB, S6J3118HxB Package Example of Reference Plastic・TEQFP176,176pin Product Lineup Part number Parameter S6J311ExxB S6J311DxxB S6J311CxxB S6J311BxxB Main Flash(Byte) 4096K+64K 3072K+64K 2048K+64K 1536K+64K Work Flash(Byte) 112K 112K 112K 112K RAM(Byte) 320K 256K 192K 128K Backup RAM(Byte) 64K 64K 64K 64K Part number Parameter S6J311AHxB S6J3119HxB S6J3118HxB Main Flash(Byte) 1024K+64K 768K+64K 512K+64K Work Flash(Byte) 48K 48K 48K RAM(Byte) 80K 64K 48K Backup RAM(Byte) 8K 8K 8K
Ordering Information
TEQFP(0.5mm pitch), 176pin S6J311DJABSEx0000 S6J311CJABSEx0000 S6J311BJABSEx0000 S6J311EHABSEx0000 Plastic TEQFP(0.5mm pitch), 144pin S6J311DHABSEx0000 S6J311CHABSEx0000 S6J311BHABSEx0000 S6J311AHABSEx0000 Plastic TEQFP(0.5mm pitch), 144pin S6J3119HABSEx0000 S6J3118HABSEx0000 S6J311EJBBSEx0000 Plastic TEQFP(0.5mm pitch), 176pin S6J311DJBBSEx0000 S6J311CJBBSEx0000 S6J311BJBBSEx0000 S6J311EHBBSEx0000 Plastic TEQFP(0.5mm pitch), 144pin S6J311DHBBSEx0000 S6J311CHBBSEx0000 S6J311BHBBSEx0000 S6J311AHBBSEx0000 Plastic TEQFP(0.5mm pitch), 144pin S6J3119HBBSEx0000 S6J3118HBBSEx0000
Document Number: 002-08974 Rev. *A Page 2 of 4 S6J3120 Series Block Diagram Block Diagram of S6J311ExxB,S6J311DxxB,S6J311CxxB,S6J311BxxB C P P Common PERI #0 Group Common PERI #1 Group Common PERI #2 Group Common PERI #0 Group Sys tem Controller(SYSC) SYSC1 Memory & Config Group Core Group (1-Core) Debug Group (CoreSightTM) DAP TCRAM #0 (2bank) 64KB (32KB×2) BootROM 16KB Timing Protection (TPU) #0 Debug I/F (JTAG/SWD) AHB-MAPB-SAPB-M Procceser B0TCM ATCM B1TCM LLPP AXI32-M AHB32AXI-M AXI-S CPU #0 IRC #0
512 Vectors
DMAC Complex #0 - DMAC 16.ch - ReloadTimer 4ch JTAG_SWCLKTCK CLK_DBG Trace Group System SRAM 16KB Wakeup Request #0 ETMTM Debug APB Debug APB ATB AHB2APB (Priviledge Protection) Trace I/F(8Pin) ETB (Trace Buffer) 16KB AHB-64 Security Checker CortexTM -R5F CLK_ATB Flash Group I/F Low Latency Peripheral BusMatrix (LLPBM) Bus Config Group - Bus Performance Counters - Misc Register Module From/To CommonPERI#2 AHB-32 From/To CommonPERI#2 DMA CConfig AXI-64 AHB-32 AXI-64 AXI-64 AHB-32 AHB-32 AHB-32 From/To Flash Group From/To Memor yConfig Grp. Clock divide and distribution Power Domain 2 MCU Config Group ECC-ed RAM I/F Backup RAM 4KB (8+5 bit width RAM x 4) Backup RAM 4KB (8+5 bit width RAM x 4) EICU 16ch Power Domain 6_0 Power Domain 4_0 AHB-32 CLK_SYSC0H AHB-32 State manage (2) CLK_DMA AHB-32 Power Domain 1 (Always on) Power Domain 1 (Always on) EAM AXI-64 CLK_SYSC1 SW-Watchdog CSV(for PLL) High Performance Matrix (HPM) CAN-FD 1ch AHB-32 CLK_HPM2 CLK_LLPBM2 Flash Group TCFLASH #0 1MB + 64KB EEFlash #0 48KB WorkFlash TCF TCF TCF A HB-64 AHB-64 AXI-64 ATCM#0 (Reg & Data) (Reg) (data) From/To Memor yConfig Grp. AXI-64 CLK_CPU CLK_FCLK CLK_CPU CLK_MEMC CLK_HPM CLK_HPM CLK_MEMC CLK_HPM CLK_MEMC CLK_HPM CLK_LLPBM2 CLK_LLPBM CLK_LCP0A CLK_LCP0A CLK_HPM CLK_HPM CLK_HPM2CLK_CPU AXI-64 CLK_CPUCLK_CPUCLK_CPU CLK_MEMC CLK_SYSC1 CLK_LCP CLK_CAN CLK_RAM0H CLK_RAM1H CLK_TRC CLK_CPU CLK_DBG CLK_SHE CLK_SHE BBU BBU BBU BBU CLK_LLPBM2 AHB-32 CLK_LLPBM CLK_LLPBM CLK_LLPBM CLK_LLPBM RAM Base Timer 30ch M.F.S 4ch 32Bit FRT 6ch 32Bit ICU 12ch 32Bit OCU 12ch 12Bit A/DC Unit0×25ch 12Bit A/DC Unit1×31ch Peripheral Bus Bridge Peripheral Bus Bridge Peripheral Bus Bridge CRC 4ch GPIO DMAC Complex #0 (Config) PPU Master (Cnofig) Bus Config Group (Config) H/W Watchdog Reset manage Clock manage CSV PONR State manage Source Clock Timer LVD Fast-CR Slow-CR PLL0 SSCG PLL0 Wakeup-detect RTC Power manage EXT-IRQ 16ch NMI Clock Calibration CLK_CPU AHB-64 AHB-64 CLK_MEMC SHE Group PPU Master From/To CommonPERI#2 CLK_HPM CLK_HPM CLK_SHE CLK_HPM BBU Power Domain 4_1 AHB-32AXI-32 #0 TCRAM (Config) From/To Core-Group CLK_MEMC Power Domain 3 Power Domain 3 From/To PPU-SLAVEs CAN prescal er （CLK_CAN） CLK_COMH
Document Number: 002-08974 Rev. *A Page 3 of 4 S6J3110Series Document History Document Title: S6J3110 Series, 32-bit Microcontroller Traveo Family Fact Sheet Document Number: 002-08974 Revision ECN Orig. of Change Submission Date Description of Change Migrated to Cypress and assigned document number 002-08974. No change to document contents or format. *A 5159031 HIOT 03/04/2016 Updated to Cypress template Added SHE-OFF option and updated revision
Document Number: 002-08974 Rev. *A Page 4 of 4 S6J3110Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Lighting & Power Control cypress.com/powerpsoc Memory cypress.com/memory PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF cypress.com/wireless PSoC® Solutions cypress.com/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/support ARM and Cortex are the trademarks of ARM Limited in the EU and other countries © Cypress Semiconductor Corporation 2014-2016. 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