S6E2C3

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Features

32-bit ARM Cortex-M4F Core  Processor version: r0p1  Up to 200 MHz frequency operation  FPU built-in  Support DSP instructions  Memory protection unit (MPU): improves the reliability of an embedded system  Integrated nested vectored interrupt controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels  24-bit system timer (Sys Tick): system timer for OS task management On-chip Memories  Flash memory This series is based on two independent on-chip flash memories.  Up to 2048 Kbytes  Built-in flash accelerator system with 16 Kbytes trace buffer memory  Read access to flash memory that can be achieved without wait-cycle up to an operating frequency of 72 MHz. Even at the operating frequency more than 72 MHz, an equivalent single cycle access to flash memory can be obtained by the flash accelerator system.  Security function for code protection  SRAM This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to the I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to system bus of Cortex-M4F core.  SRAM0: up to 192 Kbytes  SRAM1: 32 Kbytes  SRAM2: 32 Kbytes External Bus Interface  Supports SRAM, NOR, NAND flash and SDRAM device  Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)  8-/16-/32-bit data width  Up to 25-bit address bus  Supports address/data multiplexing  Supports external RDY function  Supports scramble function  Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units.  Possible to set two kinds of the scramble key Note: It is necessary to use the Cypress provided software library to use the scramble function. USB Interface (Max two Channels) The USB interface is composed of a function and a host.  USB function  USB 2.0 Full-speed supported  Max 6 EndPoint supported

• EndPoint 0 is control transfer
• EndPoint 1, 2 can be selected bulk-transfer, interrupt-transfer or isochronous-transfer
• EndPoint 3 to 5 can select bulk-transfer or interrupt-transfer
• EndPoint 1 to 5 comprise double buffer
• The size of each endpoint is as follows. − Endpoint 0, 2 to 5: 64 byte
• EndPoint 1: 256 byte  USB host  USB2.0 Full-Speed/Low-Speed supported  Bulk-transfer, interrupt-transfer, and isochronous-transfer support  USB Device connected/dis-connected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet length supported  Wake-up function supported

Document Number: 002-04988 Rev.*A Page 2 of 198 S6E2C3 Series Multi-function Serial Interface (Max 16 channels)  Separate 64 byte receive and transmit FIFO buffers for channels 0 to 7.  Operation mode is selectable for each channel from the following:  UART  CSIO (SPI)  LIN  I2C  UART  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detect functions available (parity errors, framing errors, and overrun errors)  CSIO (SPI)  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detect function available  Serial chip select function (ch 6 and ch 7 only)  Supports high-speed SPI (ch 4 and ch 6 only)  Data length 5 to 16-bit  LIN  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/slave mode supported  LIN break field generation (can change to 13- to 16-bit length)  LIN break delimiter generation (can change to 1- to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors)  I2C  Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) supported  Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported DMA Controller (Eight channels) DMA controller has an independent bus, so the CPU and DMA controller can process simultaneously.  Eight independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 GB)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: bytes/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536 DSTC (Descriptor System data Transfer Controller;

256 Channels)

The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor system and, following the specified contents of the descriptor that has already been constructed on the memory, can access directly the memory/peripheral device and perform the data-transfer operation. It supports the software activation, the hardware activation, and the chain activation functions. A/D Converter (Max 32 channels)  12-bit A/D Converter  Successive approximation type  Built-in three units  Conversion time: 0.5 μs at 5 V  Priority conversion available (priority at two levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for priority conversion: 4 steps) D/A Converter (Max 2 Channels)  R-2R type  12-bit resolution Base Timer (Max 16 Channels) Operation mode is selected from the following for each channel:  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals; moreover, the port relocate function is built in. It can set the I/O port to which the peripheral function can be allocated.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in port-relocate function  Up to 120 high-speed general-purpose I/O ports in 144 pin package  Some pins 5V tolerant I/O. See 4. Pin Descriptions and 5. I/O Circuit Type for the corresponding pins.

Document Number: 002-04988 Rev.*A Page 3 of 198 S6E2C3 Series Multi-function Timer (Max three Units) The multi-function timer is composed of the following blocks: Minimum resolution: 5.00 ns  16-bit free-run timer × 3 ch/unit  Input capture × 4 ch/unit  Output compare × 6 ch/unit  A/D activation compare × 6 ch/unit  Waveform generator × 3 ch/unit  16-bit PPG timer × 3 ch/unit The following functions can be used to achieve the motor control:  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (motor emergency stop) interrupt function Real-Time Clock (RTC) The real-time clock can count year, month, day, hour, minute, second, or day of the week from 00 to 99.  Interrupt function with specifying date and time (year/month/day/hour/minute/second/day of the week) is available. This function is also available by specifying only year, month, day, hour, or minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC; Max four Channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. It is also possible to use up/down counter.  The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter) The dual timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the following for each channel:  Free-running  Periodic (= Reload)  One shot Watch Counter The watch counter is used for wake up from low-power consumption mode. It is possible to select the main clock, sub clock, built-in High-speed CR clock, or built-in low-speed CR clock as the clock source.  Interval timer: up to 64 s (max) with a sub clock of 32.768 kHz External Interrupt Controller Unit  External interrupt input pin: Max 32 pins  Include one non-maskable interrupt (NMI) Watchdog Timer (2 Channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs: a "hardware" watchdog and a "software" watchdog. The hardware watchdog timer is clocked by low-speed internal CR oscillator. The hardware watchdog is thus active in any power saving mode except RTC mode and Stop mode. Cyclic Redundancy Check (CRC) Accelerator The CRC accelerator helps to verify data transmission or storage integrity. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 generator polynomial: 0x1021  IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7

Document Number: 002-04988 Rev.*A Page 4 of 198 S6E2C3 Series Programmable Cyclic Redundancy Check (PRGCRC) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16, IEEE-802.3 CRC32 and generating polynomial are supported.  CCITT CRC16 generator polynomial: 0x1021  IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7  Generating polynomial SD Card Interface It is possible to use the SD card that conforms to the following standards.  Part 1 Physical Layer Specification version 3.01  Part E1 SDIO Specification version 3.00  Part A2 SD Host Controller Standard Specification version 3.00  1-bit or 4-bit data bus I2S (Inter-IC Sound Bus) Interface (TX x 1 channel, RX x 1 channel)  Supports three transfer protocols  I2S  Left justified  DSP mode  Separate clock generation block for flexible system integration options  Master/slave mode selectable  RX Only, TX Only or TX and RX simultaneous operation selectable  Word length is programmable from 7-bits to 32 bits  RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66 words x 32-bits)  DMA, interrupts, or polling based data transfer supported High-Speed Quad SPI Up to 66 MHz clock rates for very fast data transfers to and from SPI compatible devices. Up to 256 Mbytes of memory mapped address space.  Single data rate (SDR)  Supports single, dual, and quad data modes  Built-in direct mode and command sequencer mode  Direct mode: Access by use of transmission FIFO/reception FIFO (up to16 word x 32 bit)  Command sequencer mode: Automatic access assigned to external device area. Clock and Reset  Clocks Five clock sources (two external oscillators, two internal CR oscillators, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 48 MHz  Sub clock: 32.768 kHz  High-speed internal CR clock: 4 MHz  Low-speed internal CR clock: 100 kHz  Main PLL Clock  Resets  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timer reset  Low-voltage detector reset  Clock supervisor reset Clock Supervisor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  External OSC clock failure (clock stop) is detected, reset is asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include two-stage monitoring of voltage on the VCC pins. when the voltage falls below the voltage that has been set, the low-voltage detector function generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Low-power Consumption Mode Six low power consumption modes are supported.  Sleep  Timer  RTC  Stop  Deep standby RTC (selectable from with/without RAM retention)  Deep standby stop (selectable from with/without RAM retention)

Document Number: 002-04988 Rev.*A Page 5 of 198 S6E2C3 Series Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used.  RTC  32-kHz oscillation circuit  Power-on circuit  Back up register: 32 bytes  Port circuit Debug  Serial wire JTAG debug port (SWJ-DP)  Embedded trace macrocells (ETM) provide comprehensive debug and trace facilities.  AHB trace macrocells (HTM) Unique ID Unique value of the device (41-bit) is set. Power Supply  Five power supplies  Wide range voltage: VCC = 2.7 V to 5.5 V  Power supply for USB ch 0 I/O: USBVCC0 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used)  Power supply for USB ch 1 I/O: USBVCC1 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used)  Power supply for VBAT: VBAT = 1.65 V to 5.5 V

Document Number: 002-04988 Rev.*A Page 6 of 198 S6E2C3 Series Table of Contents

12.4.6 Operating Conditions of Main PLL (in the Case of Using Built-in High-speed CR Clock

Document Number: 002-04988 Rev.*A Page 7 of 198 S6E2C3 Series

Document Number: 002-04988 Rev.*A Page 8 of 198 S6E2C3 Series 1. Product Lineup Memory Size Product Name S6E2C38H/J/L S6E2C39H/J/L S6E2C3AH/J/L On-chip flash memory 1024 Kbytes 1536 Kbytes 2048 Kbytes On-chip SRAM 128 Kbytes 192 Kbytes 256 Kbytes SRAM0 64 Kbytes 128 Kbytes 192 Kbytes SRAM1 32 Kbytes 32 Kbytes 32 Kbytes SRAM2 32 Kbytes 32 Kbytes 32 Kbytes Function Product Name S6E2C38H0A S6E2C39H0A S6E2C3AH0A S6E2C38J0A S6E2C39J0A S6E2C3AJ0A S6E2C38L0A S6E2C39L0A S6E2C3AL0A Pin count 144 176/192 216 CPU Cortex-M4F, MPU, NVIC 128 ch Freq. 200 MHz Power supply voltage range 2.7V to 5.5V USB2.0 (function/host) 2 ch DMAC 8ch DSTC 256 ch External bus interface Addr: 25-bit (Max), Data: 8-/16-bit CS: 9 (Max), SRAM, NOR flash NAND flash Addr: 25-bit (Max), Data: 8-/16-bit CS: 9 (Max), SRAM, NOR flash , NAND flash SDRAM Addr: 25-bit (Max), Data: 8-/16-/32-bit CS: 9 (Max), SRAM, NOR flash , NAND flash, SDRAM Multi-function serial interface (UART/CSIO/LIN/I2C) 16ch (Max) ch 0 to ch 7：FIFO, ch 8 to ch 15：No FIFO Base timer (PWC/Reload timer/PWM/PPG) 16 ch (Max) MF timer A/D activation compare 6 ch 3 units (Max) Input capture 4 ch Free-run timer 3 ch Output compare 6 ch Waveform generator 3 ch PPG 3 ch SD card interface 1 unit I2S - 1 unit High-speed quad SPI - 1 unit QPRC 4 ch (Max) Dual timer 1 unit Real-time clock 1 unit Watch counter 1 unit CRC accelerator Yes (fixed, programmable) Watchdog timer 1 ch (SW) + 1 ch (HW) External interrupts 32 pins (Max)+ NMI × 1 I/O ports 120 pins (Max) 152 pins (Max) 190 pins (Max) 12-bit A/D converter 24 ch (3 units) 32 ch (3 units) 12-bit D/A converter 2 units (Max) CSV (clock supervisor) Yes LVD (low-voltage detector) 2 ch Built-in CR High-speed 4 MHz (±2%) Low-speed 100 kHz (Typ) Debug function SWJ-DP/ETM/HTM Unique ID Yes

Document Number: 002-04988 Rev.*A Page 9 of 198 S6E2C3 Series Notes: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. − See 12.4.3 Built-In CR Oscillation Characteristics for the accuracy of the built-in CR. 2. Packages Product Name Package S6E2C38H0A S6E2C39H0A S6E2C3AH0A S6E2C38J0A S6E2C39J0A S6E2C3AJ0A S6E2C38L0A S6E2C39L0A S6E2C3AL0A LQFP: LQS144 (0.5-mm pitch)  - - LQFP: LQP176 (0.5-mm pitch) -  - BGA : LBE192 (0.8-mm pitch) -  - LQFP: LQQ216 (0.4-mm pitch) - -  : Supported Note: − See 14. Package Dimensions for detailed information on each package.

Document Number: 002-04988 Rev.*A Page 10 of 198 S6E2C3 Series 3. Pin Assignments LQS144 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. (Top View) VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VCC 1 108 VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_0 2 107 P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_0 3 106 P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_0 4 105 USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_0 5 104 P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_0 6 103 P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_0 7 102 P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_0 8 101 P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_0 9 100 P24/AN29/TIOA13_1/MAD18_0 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 10 99 P25/AN28/INT25_0/MAD17_0 PA9/SOT7_0/IC22_0/MADATA09_0 11 98 P26/MAD16_0 PAA/SCK7_0/IC23_0/MADATA10_0 12 97 P27/AN27/SIN5_0/INT24_0/MAD15_0 PAB/SCS70_0/FRCK2_0/INT03_0/MADATA11_0 13 96 P28/AN26/SOT5_0/MAD14_0 PAC/SCS71_0/TIOB8_0/AIN3_0/MADATA12_0 14 95 P29/AN25/SCK5_0/MAD13_0 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 15 94 P2A/AN24/CTS5_0/MAD12_0 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 16 93 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 17 92 P1E/AN14/TIOA8_1/INT26_1/MAD10_0 P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 18 91 P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 19 90 P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 20 89 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 P32/BIN2_1/INT19_0/S_DATA1_0 21 88 P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P33/FRCK0_0/ZIN2_1/S_DATA0_0 22 87 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P34/IC03_0/INT00_1/S_CLK_0 23 86 P18/AN08/SIN2_0/TIOA3_2/INT10_0 VCC 24 85 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 VSS 25 84 P16/AN06/SOT11_0/TIOA2_2/BIN1_2 P35/IC02_0/INT01_1/S_CMD_0 26 83 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P36/IC01_0/INT02_1/S_DATA3_0 27 82 P14/AN04/SOT6_1 P37/IC00_0/INT03_1/S_DATA2_0 28 81 P13/AN03/SIN6_1/INT25_1 P38/ADTG_2/DTTI0X_0/S_WP_0 29 80 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 30 79 P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 31 78 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 32 77 AVRH P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 33 76 AVRL P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 34 75 AVSS P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 35 74 AVCC VSS 36 73 VCC VCC P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_0 C VSS VCC P7D/SCK1_1/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 P7E/ADTG_7/FRCK1_0/MCSX0_0 INITX P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P73/SOT9_0/TIOB1_0/MAD02_0 P74/SCK9_0/TIOB2_0/MAD03_0 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 P79/SOT6_0/IC11_0/MAD08_0 P7A/SCK6_0/IC12_0/MAD09_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 P7C/DA0/SCS61_0/INT04_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 144

Document Number: 002-04988 Rev.*A Page 11 of 198 S6E2C3 Series LQP176 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. (Top View) VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P64/CTS4_0/RTO25_1/INT29_1 P65/RTO24_1/INT28_1 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P95/RTS5_1/Q_CS0_0 P94/CTS5_1/Q_SCK_0 P93/SCK5_1/INT15_1/Q_IO0_0 P92/SOT5_1/INT14_1/Q_IO1_0 P91/SIN5_1/INT13_1/Q_IO2_0 P90/INT12_1/Q_IO3_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VCC 1 132 VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_0 2 131 P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_0 3 130 P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_0 4 129 USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_0 5 128 P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_0 6 127 P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_0 7 126 P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_0 8 125 P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_0 9 124 P24/AN29/TIOA13_1/MAD18_0 P50/SCS72_0/RTO00_1/TIOA8_2 10 123 P25/AN28/INT25_0/MAD17_0 P51/SCS73_0/RTO01_1/TIOB8_2 11 122 P26/MAD16_0 P52/RTO02_1/TIOA9_2 12 121 P27/AN27/SIN5_0/INT24_0/MAD15_0 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 13 120 P28/AN26/SOT5_0/MAD14_0 PA9/SOT7_0/IC22_0/MADATA09_0 14 119 P29/AN25/SCK5_0/MAD13_0 PAA/SCK7_0/IC23_0/MADATA10_0 15 118 P2A/AN24/CTS5_0/MAD12_0 PAB/SCS70_0/FRCK2_0/INT03_0/MADATA11_0 16 117 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 PAC/SCS71_0/TIOB8_0/AIN3_0/MADATA12_0 17 116 P1E/AN14/TIOA8_1/INT26_1/MAD10_0 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 18 115 PB7/AN23/TIOB12_1/TRACED7 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 19 114 PB6/AN22/SCK8_1/TIOA12_1/TRACED6 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 20 113 PB5/AN21/SOT8_1/TIOB11_1/INT11_1/TRACED5 P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 21 112 PB4/AN20/SIN8_1/TIOA11_1/INT10_1/TRACED4 P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 22 111 P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 23 110 P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P30/TIOA13_2/INT03_2/I2SDI0_0 24 109 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 P31/TIOB13_2/I2SCK0_0 25 108 P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P32/BIN2_1/INT19_0/S_DATA1_0 26 107 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P33/FRCK0_0/ZIN2_1/S_DATA0_0 27 106 P18/AN08/SIN2_0/TIOA3_2/INT10_0 P34/IC03_0/INT00_1/S_CLK_0 28 105 PB3/AN19/SCS62_1/TIOB10_1 VCC 29 104 PB2/AN18/SCS61_1/TIOA10_1/INT09_1 VSS 30 103 PB1/AN17/SCS60_1/TIOB9_1/INT08_1 P35/IC02_0/INT01_1/S_CMD_0 31 102 PB0/AN16/SCK6_1/TIOA9_1 P36/IC01_0/INT02_1/S_DATA3_0 32 101 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 P37/IC00_0/INT03_1/S_DATA2_0 33 100 P16/AN06/SOT11_0/TIOA2_2/BIN1_2 P38/ADTG_2/DTTI0X_0/S_WP_0 34 99 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 35 98 P14/AN04/SOT6_1 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 36 97 P13/AN03/SIN6_1/INT25_1 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 37 96 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 38 95 P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 39 94 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 40 93 AVRH P5D/SIN10_1/TIOB11_2/INT01_2/I2SMCLK0_0 41 92 AVRL P5E/SOT10_1/TIOA12_2/I2SDO0_0 42 91 AVSS P5F/SCK10_1/TIOB12_2/I2SWS0_0 43 90 AVCC VSS 44 89 VCC VCC P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_0 C VSS VCC P7D/SCK1_1/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 P7E/ADTG_7/FRCK1_0/MCSX0_0 INITX P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP PF0/SCS63_0/FRCK1_1/TIOA15_1/INT22_1 PF1/SCS62_0/TIOB15_1/INT23_1 P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P73/SOT9_0/TIOB1_0/MAD02_0 P74/SCK9_0/TIOB2_0/MAD03_0 PF2/RTO10_1/TIOA6_1/MRASX_0 PF3/RTO11_1/TIOB6_1/INT05_1/MCASX_0 PF4/RTO12_1/TIOA7_1/INT06_1/MSDWEX_0 PF5/RTO13_1/TIOB7_1/INT07_1/MCSX8_0 PF6/RTO14_1/TIOA14_1/INT20_1/MSDCKE_0 PF7/RTO15_1/TIOB14_1/INT21_1/MSDCLK_0 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 P79/SOT6_0/IC11_0/MAD08_0 P7A/SCK6_0/IC12_0/MAD09_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 P7C/DA0/SCS61_0/INT04_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 176

Document Number: 002-04988 Rev.*A Page 12 of 198 S6E2C3 Series LQQ216 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. (Top View) VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P64/CTS4_0/RTO25_1/INT29_1 P65/RTO24_1/INT28_1 P66/SIN13_1/RTO23_1/TIOA15_2/INT15_2 P67/SOT13_1/RTO22_1/TIOB15_2 P68/SCK13_1/RTO21_1/TIOA14_2 P69/RTO20_1/TIOB14_2 P6A/DTTI2X_1/TIOA7_2 P6B/SIN14_1/IC20_1/TIOB7_2/INT14_2 P6C/SOT14_1/IC21_1/TIOA6_2 P6D/SCK14_1/IC22_1/TIOB6_2 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P97/TX0_2/INT13_2/Q_CS2_0 P96/RX0_2/INT12_2/Q_CS1_0 P95/RTS5_1/Q_CS0_0 P94/CTS5_1/Q_SCK_0 P93/SCK5_1/INT15_1/Q_IO0_0 P92/SOT5_1/INT14_1/Q_IO1_0 P91/SIN5_1/INT13_1/Q_IO2_0 P90/INT12_1/Q_IO3_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 VCC 1 162 VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_0 2 161 P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_0 3 160 P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_0 4 159 USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_0 5 158 P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_0 6 157 P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_0 7 156 P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_0 8 155 P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_0 9 154 P24/AN29/TIOA13_1/MAD18_0 P50/SCS72_0/RTO00_1/TIOA8_2/MADATA16_0 10 153 P25/AN28/INT25_0/MAD17_0 P51/SCS73_0/RTO01_1/TIOB8_2/MADATA17_0 11 152 P26/MAD16_0 P52/RTO02_1/TIOA9_2/MADATA18_0 12 151 PBF/SIN0_1/ZIN3_2/INT11_2/TRACED15 P53/RTO03_1/TIOB9_2/MADATA19_0 13 150 PBE/SOT0_1/BIN3_2/TRACED14 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 14 149 PBD/SCK0_1/AIN3_2/INT10_2/TRACED13 PA9/SOT7_0/IC22_0/MADATA09_0 15 148 PBC/TRACED12 PAA/SCK7_0/IC23_0/MADATA10_0 16 147 P27/AN27/SIN5_0/INT24_0/MAD15_0 PAB/SCS70_0/FRCK2_0/INT03_0/MADATA11_0 17 146 P28/AN26/SOT5_0/MAD14_0 PAC/SCS71_0/TIOB8_0/AIN3_0/MADATA12_0 18 145 P29/AN25/SCK5_0/MAD13_0 P54/SIN15_1/RTO04_1/TIOA10_2/INT00_2/MADATA20_0 19 144 P2A/AN24/CTS5_0/MAD12_0 P55/SOT15_1/RTO05_1/TIOB10_2/MADATA21_0 20 143 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 P56/SCK15_1/DTTI0X_1/TIOB0_1/MADATA22_0 21 142 P1E/AN14/TIOA8_1/INT26_1/MAD10_0 P57/IC00_1/TIOB1_1/MADATA23_0 22 141 PB7/AN23/TIOB12_1/TRACED7 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 23 140 PB6/AN22/SCK8_1/TIOA12_1/TRACED6 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 24 139 PB5/AN21/SOT8_1/TIOB11_1/INT11_1/TRACED5 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 25 138 PB4/AN20/SIN8_1/TIOA11_1/INT10_1/TRACED4 P58/SIN11_1/IC01_1/TIOB2_1/INT02_2/MADATA24_0 26 137 VCC P59/SOT11_1/IC02_1/TIOB3_1/MADATA25_0 27 136 VSS P5A/SCK11_1/IC03_1/TIOB4_1/MADATA26_0 28 135 P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P5B/FRCK0_1/TIOB5_1/MADATA27_0 29 134 P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 30 133 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 31 132 P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 32 131 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P5C/TIOA11_2/MADATA28_0/RTCCO_1/SUBOUT_1 33 130 P18/AN08/SIN2_0/TIOA3_2/INT10_0 P30/TIOA13_2/INT03_2/MDQM2_0/I2SDI0_0 34 129 PB3/AN19/SCS62_1/TIOB10_1 P31/TIOB13_2/MDQM3_0/I2SCK0_0 35 128 PB2/AN18/SCS61_1/TIOA10_1/INT09_1 P32/BIN2_1/INT19_0/S_DATA1_0 36 127 PB1/AN17/SCS60_1/TIOB9_1/INT08_1 P33/FRCK0_0/ZIN2_1/S_DATA0_0 37 126 PB0/AN16/SCK6_1/TIOA9_1 P34/IC03_0/INT00_1/S_CLK_0 38 125 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 VCC 39 124 P16/AN06/SOT11_0/TIOA2_2/BIN1_2 VSS 40 123 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P35/IC02_0/INT01_1/S_CMD_0 41 122 PBB/SCK9_1/ZIN2_2/TRACED11 P36/IC01_0/INT02_1/S_DATA3_0 42 121 PBA/SOT9_1/BIN2_2/TRACED10 P37/IC00_0/INT03_1/S_DATA2_0 43 120 PB9/SIN9_1/AIN2_2/INT09_2/TRACED9 P38/ADTG_2/DTTI0X_0/S_WP_0 44 119 PB8/ADTG_6/SCS63_1/INT08_2/TRACED8 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 45 118 P14/AN04/SOT6_1 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 46 117 P13/AN03/SIN6_1/INT25_1 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 47 116 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 48 115 P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 49 114 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 50 113 AVRH P5D/SIN10_1/TIOB11_2/INT01_2/MADATA29_0/I2SMCLK0_0 51 112 AVRL P5E/SOT10_1/TIOA12_2/MADATA30_0/I2SDO0_0 52 111 AVSS P5F/SCK10_1/TIOB12_2/MADATA31_0/I2SWS0_0 53 110 AVCC VSS 54 109 VCC 100 101 102 103 104 105 106 107 108 VCC P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_0 C VSS VCC P4A/SIN12_1/AIN0_1/INT04_2 P4B/SOT12_1/BIN0_1 P4C/SCK12_1/ZIN0_1 P4D/SCS72_1/INT05_2 P4E/SCS73_1 P7D/SCK1_1/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 P7E/ADTG_7/FRCK1_0/MCSX0_0 INITX P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP PF0/SCS63_0/FRCK1_1/TIOA15_1/INT22_1 PF1/SCS62_0/TIOB15_1/INT23_1 P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P73/SOT9_0/TIOB1_0/MAD02_0 P74/SCK9_0/TIOB2_0/MAD03_0 PF2/RTO10_1/TIOA6_1/MRASX_0 PF3/RTO11_1/TIOB6_1/INT05_1/MCASX_0 PF4/RTO12_1/TIOA7_1/INT06_1/MSDWEX_0 PF5/RTO13_1/TIOB7_1/INT07_1/MCSX8_0 PF6/RTO14_1/TIOA14_1/INT20_1/MSDCKE_0 PF7/RTO15_1/TIOB14_1/INT21_1/MSDCLK_0 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 PF8/SCS70_1/DTTI1X_1/AIN1_1 PF9/SCS71_1/IC10_1/BIN1_1 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 P79/SOT6_0/IC11_0/MAD08_0 P7A/SCK6_0/IC12_0/MAD09_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 P7C/DA0/SCS61_0/INT04_1 PFA/SCK7_1/IC11_1/ZIN1_1 PFB/SOT7_1/IC12_1/INT07_2 PFC/SIN7_1/IC13_1/INT06_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 216

Document Number: 002-04988 Rev.*A Page 13 of 198 S6E2C3 Series LBE192 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A UDP0 UDM0 USBV CC0 VSS PCD PCB VSS VCC PC8 VSS TCK VCC B VSS PA0 P60 P62 P64 PD1 PCA PC1 P95 P92 TDO TMS TRSTX VSS C VCC PA1 PA2 P61 P63 PD2 PCC PC5 PC0 P93 P90 TDI P20 UDP1 D PA5 PA4 PA6 PA7 PA3 P6E PCE PC6 PC2 P94 P91 P22 P21 UDM1 E VSS P50 P51 P52 PA8 P65 PCF PC7 PC3 P26 P25 P24 P23 USBV CC1 F PA9 PAA PAB PAC PAD PAE PD0 PC9 PC4 P2A P29 P28 P27 PB5 G VSS PAF P08 P09 P0A P30 VSS VSS P1F P1E PB7 PB6 PB4 P1B H VCC P32 P34 P31 VSS P35 VSS VSS P18 PB2 P1D P19 P1C P1A J P33 P39 P38 P37 P36 P71 VSS P74 PB1 PB0 P17 P16 P15 PB3 K P3A P3B P3C P3D PF0 PF1 VSS P73 P75 P79 P14 P12 P11 P13 L P3E P5D P5E P43 P7D P70 VSS P72 PF7 P78 P10 AVRH AVRL VSS M VSS P5F P42 P44 P7E P49 VSS PF3 PF6 P7A P7C AVSS AVCC VCC N VCC P40 P41 P45 INITX P48 VSS PF2 PF4 P77 P7B MD0 MD1 VSS P C VSS VCC X0A X1A VSS VBAT PF5 P76 VSS X0 X1 PFBGA-192

Document Number: 002-04988 Rev.*A Page 14 of 198 S6E2C3 Series 4. Pin Descriptions List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 1 1 1 C1 VCC - - 2 2 2 B2 PA0 G K RTO20_0 (PPG20_0) TIOA8_0 AIN2_0 INT00_0 MADATA00_0 3 3 3 C2 PA1 G I RTO21_0 (PPG20_0) TIOA9_0 BIN2_0 MADATA01_0 4 4 4 C3 PA2 G I RTO22_0 (PPG22_0) TIOA10_0 ZIN2_0 MADATA02_0 5 5 5 D5 PA3 G I RTO23_0 (PPG22_0) TIOA11_0 MADATA03_0 6 6 6 D2 PA4 G I RTO24_0 (PPG24_0) TIOA12_0 MADATA04_0 7 7 7 D1 PA5 G K SIN1_0 RTO25_0 (PPG24_0) TIOA13_0 INT01_0 MADATA05_0 8 8 8 D3 PA6 E I SOT1_0 (SDA1_0)) DTTI2X_0 MADATA06_0 9 9 9 D4 PA7 E I SCK1_0 (SCL1_0) IC20_0 MADATA07_0

Document Number: 002-04988 Rev.*A Page 15 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 10 10 - E2 P50 E I SCS72_0 RTO00_1 (PPG00_1) TIOA8_2 MADATA16_0 11 11 - E3 P51 E I SCS73_0 RTO01_1 (PPG00_1) TIOB8_2 MADATA17_0 12 12 - E4 P52 E I RTO02_1 (PPG02_1) TIOA9_2 MADATA18_0 13 - - - P53 E I RTO03_1 (PPG02_1) TIOB9_2 MADATA19_0 14 13 10 E5 PA8 I Q SIN7_0 IC21_0 INT02_0 WKUP1 MADATA08_0 15 14 11 F1 PA9 N I SOT7_0 (SDA7_0) IC22_0 MADATA09_0 16 15 12 F2 PAA N I SCK7_0 (SCL7_0) IC23_0 MADATA10_0 17 16 13 F3 PAB E K SCS70_0 FRCK2_0 INT03_0 MADATA11_0 18 17 14 F4 PAC E I SCS71_0 TIOB8_0 AIN3_0 MADATA12_0 19 - - - P54 E K SIN15_1 RTO04_1 (PPG04_1) TIOA10_2 INT00_2 MADATA20_0

Document Number: 002-04988 Rev.*A Page 16 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 20 - - - P55 E I SOT15_1 (SDA15_1) RTO05_1 (PPG04_1) TIOB10_2 MADATA21_0 21 - - - P56 E I SCK15_1 (SCL15_1) DTTI0X_1 TIOB0_1 MADATA22_0 22 - - - P57 E I IC00_1 TIOB1_1 MADATA23_0 23 18 15 F5 PAD N I SCK3_0 (SCL3_0) TIOB9_0 BIN3_0 MADATA13_0 24 19 16 F6 PAE N I ADTG_0 SOT3_0 (SDA3_0) TIOB10_0 ZIN3_0 MADATA14_0 25 20 17 G2 PAF I K SIN3_0 TIOB11_0 INT16_0 MADATA15_0 26 - - - P58 E K SIN11_1 IC01_1 TIOB2_1 INT02_2 MADATA24_0 27 - - - P59 E I SOT11_1 (SDA11_1) IC02_1 TIOB3_1 MADATA25_0 28 - - - P5A E I SCK11_1 (SCL11_1) IC03_1 TIOB4_1 MADATA26_0

Document Number: 002-04988 Rev.*A Page 17 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 29 - - - P5B E I FRCK0_1 TIOB5_1 MADATA27_0 30 21 18 G3 P08 E K SIN14_0 TIOB12_0 INT17_0 MDQM0_0 31 22 19 G4 P09 E K SOT14_0 (SDA14_0) TIOB13_0 INT18_0 MDQM1_0 32 23 20 G5 P0A L I ADTG_1 SCK14_0 (SCL14_0) AIN2_1 MCLKOUT_0 33 - - - P5C E I TIOA11_2 MADATA28_0 RTCCO_1 SUBOUT_1 34 24 - G6 P30 E K TIOA13_2 INT03_2 MDQM2_0 I2SDI0_0 35 25 - H4 P31 E I TIOB13_2 MDQM3_0 I2SCK0_0 36 26 21 H2 P32 L K BIN2_1 INT19_0 S_DATA1_0 37 27 22 J1 P33 L I FRCK0_0 ZIN2_1 S_DATA0_0 38 28 23 H3 P34 L K IC03_0 INT00_1 S_CLK_0 39 29 24 H1 VCC - - 40 30 25 H5 VSS - - 41 31 26 H6 P35 L K IC02_0 INT01_1 S_CMD_0

Document Number: 002-04988 Rev.*A Page 18 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 42 32 27 J5 P36 L K IC01_0 INT02_1 S_DATA3_0 43 33 28 J4 P37 L K IC00_0 INT03_1 S_DATA2_0 44 34 29 J3 P38 E I ADTG_2 DTTI0X_0 S_WP_0 45 35 30 J2 P39 G K SIN2_1 RTO00_0 (PPG00_0) TIOA0_1 AIN3_1 INT16_1 S_CD_0 MAD24_0 46 36 31 K1 P3A G K SOT2_1 (SDA2_1) RTO01_0 (PPG00_0) TIOA1_1 BIN3_1 INT17_1 MAD23_0 47 37 32 K2 P3B G K SCK2_1 (SCL2_1) RTO02_0 (PPG02_0) TIOA2_1 ZIN3_1 INT18_1 MAD22_0 MNALE_0 48 38 33 K3 P3C G K SIN13_0 RTO03_0 (PPG02_0) TIOA3_1 INT19_1 MAD21_0 MNCLE_0 49 39 34 K4 P3D G I SOT13_0 (SDA13_0) RTO04_0 (PPG04_0) TIOA4_1 MAD20_0 MNWEX_0

Document Number: 002-04988 Rev.*A Page 19 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 50 40 35 L1 P3E G I SCK13_0 (SCL13_0) RTO05_0 (PPG04_0) TIOA5_1 MAD19_0 MNREX_0 51 41 - L2 P5D E K SIN10_1 TIOB11_2 INT01_2 MADATA29_0 I2SMCLK0_0 52 42 - L3 P5E E I SOT10_1 (SDA10_1) TIOA12_2 MADATA30_0 I2SDO0_0 53 43 - M2 P5F E I SCK10_1 (SCL10_1) TIOB12_2 MADATA31_0 I2SWS0_0 54 44 36 M1 VSS - - 55 45 37 N1 VCC - - 56 46 38 N2 P40 G K SIN3_1 RTO10_0 (PPG10_0) TIOA0_0 AIN0_0 INT23_0 MCSX7_0 57 47 39 N3 P41 G I SOT3_1 (SDA3_1) RTO11_0 (PPG10_0) TIOA1_0 BIN0_0 MCSX6_0 58 48 40 M3 P42 G I SCK3_1 (SCL3_1) RTO12_0 (PPG12_0) TIOA2_0 ZIN0_0 MCSX5_0

Document Number: 002-04988 Rev.*A Page 20 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 59 49 41 L4 P43 G K SIN15_0 RTO13_0 (PPG12_0) TIOA3_0 INT04_0 MCSX4_0 60 50 42 M4 P44 G I SOT15_0 (SDA15_0) RTO14_0 (PPG14_0) TIOA4_0 MCSX3_0 61 51 43 N4 P45 G I SCK15_0 (SCL15_0) RTO15_0 (PPG14_0) TIOA5_0 MCSX2_0 62 52 44 P2 C - - 63 53 45 P3 VSS - - 64 54 46 P4 VCC - - 65 - - - P4A E K SIN12_1 AIN0_1 INT04_2 66 - - - P4B E I SOT12_1 (SDA12_1) BIN0_1 67 - - - P4C E I SCK12_1 (SCL12_1) ZIN0_1 68 - - - P4D E K SCS72_1 INT05_2 69 - - - P4E E I SCS73_1 70 55 47 L5 P7D L Q SCK1_1 (SCL1_1) RX2_0 DTTI1X_0 INT05_0 WKUP2 MCSX1_0 71 56 48 M5 P7E L I ADTG_7 FRCK1_0 MCSX0_0 72 57 49 N5 INITX B C 73 58 50 P5 P46 P S X0A

Document Number: 002-04988 Rev.*A Page 21 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 74 59 51 P6 P47 Q T X1A 75 60 52 P8 VBAT - - 76 61 53 N6 P48 O U VREGCTL 77 62 54 M6 P49 O U VWAKEUP 78 63 - K5 PF0 E K SCS63_0 FRCK1_1 TIOA15_1 INT22_1 79 64 - K6 PF1 E K SCS62_0 TIOB15_1 INT23_1 80 65 55 L6 P70 I K ADTG_8 SIN1_1 INT06_0 MRDY_0 81 66 56 J6 P71 E I SOT1_1 (SDA1_1) MAD00_0 82 67 57 L8 P72 E K SIN9_0 TIOB0_0 INT07_0 MAD01_0 83 68 58 K8 P73 E I SOT9_0 (SDA9_0) TIOB1_0 MAD02_0 84 69 59 J8 P74 E I SCK9_0 (SCL9_0) TIOB2_0 MAD03_0 85 70 - N8 PF2 L I RTO10_1 (PPG10_1) TIOA6_1 MRASX_0 86 71 - M8 PF3 L K RTO11_1 (PPG10_1) TIOB6_1 INT05_1 MCASX_0

Document Number: 002-04988 Rev.*A Page 22 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 87 72 - N9 PF4 L K RTO12_1 (PPG12_1) TIOA7_1 INT06_1 MSDWEX_0 88 73 - P9 PF5 L K RTO13_1 (PPG12_1) TIOB7_1 INT07_1 MCSX8_0 89 74 - M9 PF6 L K RTO14_1 (PPG14_1) TIOA14_1 INT20_1 MSDCKE_0 90 75 - L9 PF7 L K RTO15_1 (PPG14_1) TIOB14_1 INT21_1 MSDCLK_0 91 76 60 K9 P75 E K SIN8_0 TIOB3_0 AIN1_0 INT20_0 MAD04_0 92 77 61 P10 P76 E I SOT8_0 (SDA8_0) TIOB4_0 BIN1_0 MAD05_0 93 78 62 N10 P77 E I SCK8_0 (SCL8_0) TIOB5_0 ZIN1_0 MAD06_0 94 - - - PF8 E I SCS70_1 DTTI1X_1 AIN1_1 95 - - - PF9 E I SCS71_1 IC10_1 BIN1_1 96 79 63 L10 P78 E K SIN6_0 IC10_0 INT21_0 MAD07_0

Document Number: 002-04988 Rev.*A Page 23 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 97 80 64 K10 P79 L I SOT6_0 (SDA6_0) IC11_0 MAD08_0 98 81 65 M10 P7A L I SCK6_0 (SCL6_0) IC12_0 MAD09_0 99 82 66 N11 P7B R J DA1 SCS60_0 IC13_0 INT22_0 100 83 67 M11 P7C R J DA0 SCS61_0 INT04_1 101 - - - PFA E I SCK7_1 (SCL7_1) IC11_1 ZIN1_1 102 - - - PFB E K SOT7_1 (SDA7_1) IC12_1 INT07_2 103 - - - PFC E K SIN7_1 IC13_1 INT06_2 104 84 68 N13 PE0 C E MD1 105 85 69 N12 MD0 J D 106 86 70 P12 PE2 A A X0 107 87 71 P13 PE3 A B X1 108 88 72 N14 VSS - - 109 89 73 M14 VCC - - 110 90 74 M13 AVCC - - 111 91 75 M12 AVSS - - 112 92 76 L13 AVRL - - 113 93 77 L12 AVRH - - 114 94 78 L11 P10 F M AN00 SIN10_0 TIOA0_2 AIN0_2 INT08_0

Document Number: 002-04988 Rev.*A Page 24 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 115 95 79 K13 P11 F L AN01 SOT10_0 (SDA10_0) TIOB0_2 BIN0_2 116 96 80 K12 P12 F L AN02 SCK10_0 (SCL10_0) TIOA1_2 ZIN0_2 117 97 81 K14 P13 F M AN03 SIN6_1 INT25_1 118 98 82 K11 P14 F L AN04 SOT6_1 (SDA6_1) 119 - - - PB8 E O ADTG_6 SCS63_1 INT08_2 TRACED8 120 - - - PB9 E O SIN9_1 AIN2_2 INT09_2 TRACED9 121 - - - PBA E N SOT9_1 (SDA9_1) BIN2_2 TRACED10 122 - - - PBB E N SCK9_1 (SCL9_1) ZIN2_2 TRACED11 123 99 83 J13 P15 F M AN05 SIN11_0 TIOB1_2 AIN1_2 INT09_0 124 100 84 J12 P16 F L AN06 SOT11_0 (SDA11_0) TIOA2_2 BIN1_2

Document Number: 002-04988 Rev.*A Page 25 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 125 101 85 J11 P17 F L AN07 SCK11_0 (SCL11_0) TIOB2_2 ZIN1_2 126 102 - J10 PB0 F L AN16 SCK6_1 (SCL6_1) TIOA9_1 127 103 - J9 PB1 F M AN17 SCS60_1 TIOB9_1 INT08_1 128 104 - H10 PB2 F M AN18 SCS61_1 TIOA10_1 INT09_1 129 105 - J14 PB3 F L AN19 SCS62_1 TIOB10_1 130 106 86 H9 P18 F M AN08 SIN2_0 TIOA3_2 INT10_0 131 107 87 H12 P19 F O AN09 SOT2_0 (SDA2_0) TIOB3_2 INT24_1 TRACECLK 132 108 88 H14 P1A F N AN10 SCK2_0 (SCL2_0) TIOA4_2 TRACED0 133 109 89 G14 P1B F O AN11 SIN12_0 TIOB4_2 INT11_0 TRACED1 134 110 90 H13 P1C F N AN12 SOT12_0 (SDA12_0) TIOA5_2 TRACED2

Document Number: 002-04988 Rev.*A Page 26 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 135 111 91 H11 P1D F N AN13 SCK12_0 (SCL12_0) TIOB5_2 TRACED3 136 - - - VSS - - 137 - - - VCC - - 138 112 - G13 PB4 F O AN20 SIN8_1 TIOA11_1 INT10_1 TRACED4 139 113 - F14 PB5 F O AN21 SOT8_1 (SDA8_1) TIOB11_1 INT11_1 TRACED5 140 114 - G12 PB6 F N AN22 SCK8_1 (SCL8_1) TIOA12_1 TRACED6 141 115 - G11 PB7 F N AN23 TIOB12_1 TRACED7 142 116 92 G10 P1E F M AN14 TIOA8_1 INT26_1 MAD10_0 143 117 93 G9 P1F F M AN15 RTS5_0 TIOB8_1 INT27_1 MAD11_0 144 118 94 F10 P2A F L AN24 CTS5_0 MAD12_0 145 119 95 F11 P29 F L AN25 SCK5_0 (SCL5_0) MAD13_0

Document Number: 002-04988 Rev.*A Page 27 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 146 120 96 F12 P28 F L AN26 SOT5_0 (SDA5_0) MAD14_0 147 121 97 F13 P27 F M AN27 SIN5_0 INT24_0 MAD15_0 148 - - - PBC E N TRACED12 149 - - - PBD E O SCK0_1 (SCL0_1) AIN3_2 INT10_2 TRACED13 150 - - - PBE E N SOT0_1 (SDA0_1) BIN3_2 TRACED14 151 - - - PBF E O SIN0_1 ZIN3_2 INT11_2 TRACED15 152 122 98 E10 P26 E I MAD16_0 153 123 99 E11 P25 F M AN28 INT25_0 MAD17_0 154 124 100 E12 P24 F L AN29 TIOA13_1 MAD18_0 155 125 101 E13 P23 F L UHCONX1 AN30 SCK0_0 (SCL0_0) TIOB13_1 156 126 102 D12 P22 F M AN31 SOT0_0 (SDA0_0) INT26_0 157 127 103 D13 P21 I K ADTG_4 SIN0_0 INT27_0 CROUT_0

Document Number: 002-04988 Rev.*A Page 28 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 158 128 104 C13 P20 I F NMIX WKUP0 159 129 105 E14 USBVCC1 - - 160 130 106 D14 P82 H R UDM1 161 131 107 C14 P83 H R UDP1 162 132 108 B14 VSS - - 163 133 109 A13 VCC - - 164 134 110 B13 P00 E G TRSTX 165 135 111 A12 P01 E G TCK SWCLK 166 136 112 C12 P02 E G TDI 167 137 113 B12 P03 E G TMS SWDIO 168 138 114 B11 P04 E G TDO SWO 169 139 - C11 P90 S K INT12_1 Q_IO3_0 170 140 - D11 P91 S K SIN5_1 INT13_1 Q_IO2_0 171 141 - B10 P92 S K SOT5_1 (SDA5_1) INT14_1 Q_IO1_0 172 142 - C10 P93 S K SCK5_1 (SCL5_1) INT15_1 Q_IO0_0 173 143 - D10 P94 S I CTS5_1 Q_SCK_0 174 144 - B9 P95 S I RTS5_1 Q_CS0_0 175 - - - P96 S K INT12_2 Q_CS1_0 176 - - - P97 S K INT13_2 Q_CS2_0 177 145 115 C9 PC0 K V

Document Number: 002-04988 Rev.*A Page 29 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 178 146 116 B8 PC1 K V TIOB6_0 179 147 117 D9 PC2 K V TIOA6_0 180 148 118 E9 PC3 K V TIOB7_0 181 149 119 F9 PC4 K V TIOA7_0 182 150 120 C8 PC5 K V TIOB14_0 183 151 121 D8 PC6 K V TIOA14_0 184 152 122 E8 PC7 E W INT13_0 CROUT_1 185 153 123 A10 PC8 K V 186 154 124 F8 PC9 K V TIOB15_0 187 155 125 B7 PCA K V TIOA15_0 188 156 126 A9 VCC - - 189 157 127 A8 VSS - - 190 158 128 A7 PCB L W INT28_0 191 159 129 C7 PCC K V 192 160 130 A6 PCD L W SOT4_1 (SDA4_1) INT14_0 193 161 131 D7 PCE L W SIN4_1 INT15_0 194 162 132 E7 PCF L W RTS4_1 INT12_0 195 163 133 F7 PD0 L W INT30_1 196 164 134 B6 PD1 L W INT31_1 197 165 135 C6 PD2 L V CTS4_1 FRCK2_1 198 166 136 D6 P6E E W ADTG_5 SCK4_1 (SCL4_1) IC23_1 INT29_0

Document Number: 002-04988 Rev.*A Page 30 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 199 - - - P6D E I SCK14_1 (SCL14_1) IC22_1 TIOB6_2 200 - - - P6C E I SOT14_1 (SDA14_1) IC21_1 TIOA6_2 201 - - - P6B E K SIN14_1 IC20_1 TIOB7_2 INT14_2 202 - - - P6A E I DTTI2X_1 TIOA7_2 203 - - - P69 E I RTO20_1 (PPG20_1) TIOB14_2 204 - - - P68 E I SCK13_1 (SCL13_0) RTO21_1 (PPG20_1) TIOA14_2 205 - - - P67 E I SOT13_1 (SDA13_1) RTO22_1 (PPG22_1) TIOB15_2 206 - - - P66 E K SIN13_1 RTO23_1 (PPG22_1) TIOA15_2 INT15_2 207 167 - E6 P65 E K RTO24_1 (PPG24_1) INT28_1 208 168 - B5 P64 I K CTS4_0 RTO25_1 (PPG24_1) INT29_1 209 169 137 C5 P63 L K ADTG_3 RTS4_0 INT30_0 MOEX_0

Document Number: 002-04988 Rev.*A Page 31 of 198 S6E2C3 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQQ216 LQP176 LQS144 LBE192 210 170 138 B4 P62 L I SCK4_0 (SCL4_0) MWEX_0 211 171 139 C4 P61 L I UHCONX0 SOT4_0 (SDA4_0) MALE_0 RTCCO_0 SUBOUT_0 212 172 140 B3 P60 I Q SIN4_0 INT31_0 WKUP3 213 173 141 A4 USBVCC0 - - 214 174 142 A3 P80 H R UDM0 215 175 143 A2 P81 H R UDP0 216 176 144 B1 VSS - - - - - E1 - - - - - G1 - - - - - P7 - - - - - P11 - - - - - L14 - - - - - A11 - - - - - A5 - - - - - N7 - - - - - M7 - - - - - L7 - - - - - K7 - - - - - J7 - - -- - - G7 - - - - - H7 - - - - - H8 - - - - - G8 - -

Document Number: 002-04988 Rev.*A Page 32 of 198 S6E2C3 Series Signal Descriptions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 A/D converter ADTG_0 A/D converter external trigger input pin 24 19 16 F6 ADTG_1 32 23 20 G5 ADTG_2 44 34 29 J3 ADTG_3 209 169 137 C5 ADTG_4 157 127 103 D13 ADTG_5 198 166 136 D6 ADTG_6 119 - - - ADTG_7 71 56 48 M5 ADTG_8 80 65 55 L6 AN00 A/D converter analog input pin. ANxx describes A/D converter ch xx. 114 94 78 L11 AN01 115 95 79 K13 AN02 116 96 80 K12 AN03 117 97 81 K14 AN04 118 98 82 K11 AN05 123 99 83 J13 AN06 124 100 84 J12 AN07 125 101 85 J11 AN08 130 106 86 H9 AN09 131 107 87 H12 AN10 132 108 88 H14 AN11 133 109 89 G14 AN12 134 110 90 H13 AN13 135 111 91 H11 AN14 142 116 92 G10 AN15 143 117 93 G9 AN16 126 102 - J10 AN17 127 103 - J9 AN18 128 104 - H10 AN19 129 105 - J14 AN20 138 112 - G13 AN21 139 113 - F14 AN22 140 114 - G12 AN23 141 115 - G11 AN24 144 118 94 F10 AN25 145 119 95 F11 AN26 146 120 96 F12 AN27 147 121 97 F13 AN28 153 123 99 E11 AN29 154 124 100 E12 AN30 155 125 101 E13 AN31 156 126 102 D12

Document Number: 002-04988 Rev.*A Page 33 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Base Timer TIOA0_0 Base Timer ch 0 TIOA pin 56 46 38 N2 TIOA0_1 45 35 30 J2 TIOA0_2 114 94 78 L11 TIOB0_0 Base Timer ch 0 TIOB pin 82 67 57 L8 TIOB0_1 21 - - - TIOB0_2 115 95 79 K13 Base Timer TIOA1_0 Base Timer ch 1 TIOA pin 57 47 39 N3 TIOA1_1 46 36 31 K1 TIOA1_2 116 96 80 K12 TIOB1_0 Base Timer ch 1 TIOB pin 83 68 58 K8 TIOB1_1 22 - - - TIOB1_2 123 99 83 J13 Base Timer TIOA2_0 Base Timer ch 2 TIOA pin 58 48 40 M3 TIOA2_1 47 37 32 K2 TIOA2_2 124 100 84 J12 TIOB2_0 Base Timer ch 2 TIOB pin 84 69 59 J8 TIOB2_1 26 - - - TIOB2_2 125 101 85 J11 Base Timer TIOA3_0 Base Timer ch 3 TIOA pin 59 49 41 L4 TIOA3_1 48 38 33 K3 TIOA3_2 130 106 86 H9 TIOB3_0 Base Timer ch 3 TIOB pin 91 76 60 K9 TIOB3_1 27 - - - TIOB3_2 131 107 87 H12 Base Timer TIOA4_0 Base Timer ch 4 TIOA pin 60 50 42 M4 TIOA4_1 49 39 34 K4 TIOA4_2 132 108 88 H14 TIOB4_0 Base Timer ch 4 TIOB pin 92 77 61 P10 TIOB4_1 28 - - - TIOB4_2 133 109 89 G14 Base Timer TIOA5_0 Base Timer ch 5 TIOA pin 61 51 43 N4 TIOA5_1 50 40 35 L1 TIOA5_2 134 110 90 H13 TIOB5_0 Base Timer ch 5 TIOB pin 93 78 62 N10 TIOB5_1 29 - - - TIOB5_2 135 111 91 H11 Base Timer TIOA6_0 Base Timer ch 6 TIOA pin 179 147 117 D9 TIOA6_1 85 70 - N8 TIOA6_2 200 - - - TIOB6_0 Base Timer ch 6 TIOB pin 178 146 116 B8 TIOB6_1 86 71 - M8 TIOB6_2 199 - - -

Document Number: 002-04988 Rev.*A Page 34 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Base Timer TIOA7_0 Base Timer ch 7 TIOA pin 181 149 119 F9 TIOA7_1 87 72 - N9 TIOA7_2 202 - - - TIOB7_0 Base Timer ch 7 TIOB pin 180 148 118 E9 TIOB7_1 88 73 - P9 TIOB7_2 201 - - - Base Timer TIOA8_0 Base Timer ch 8 TIOA pin 2 2 2 B2 TIOA8_1 142 116 92 G10 TIOA8_2 10 10 - E2 TIOB8_0 Base Timer ch 8 TIOB pin 18 17 14 F4 TIOB8_1 143 117 93 G9 TIOB8_2 11 11 - E3 Base Timer TIOA9_0 Base Timer ch 9 TIOA pin 3 3 3 C2 TIOA9_1 126 102 - J10 TIOA9_2 12 12 - E4 TIOB9_0 Base Timer ch 9 TIOB pin 23 18 15 F5 TIOB9_1 127 103 - J9 TIOB9_2 13 - - - Base Timer TIOA10_0 Base Timer ch 10 TIOA pin 4 4 4 C3 TIOA10_1 128 104 - H10 TIOA10_2 19 - - - TIOB10_0 Base Timer ch 10 TIOB pin 24 19 16 F6 TIOB10_1 129 105 - J14 TIOB10_2 20 - - - Base Timer TIOA11_0 Base Timer ch 11 の TIOA pin 5 5 5 D5 TIOA11_1 138 112 - G13 TIOA11_2 33 - - - TIOB11_0 Base Timer ch 11 TIOB pin 25 20 17 G2 TIOB11_1 139 113 - F14 TIOB11_2 51 41 - L2 Base Timer TIOA12_0 Base Timer ch 12 TIOA pin 6 6 6 D2 TIOA12_1 140 114 - G12 TIOA12_2 52 42 - L3 TIOB12_0 Base Timer ch 12 TIOB pin 30 21 18 G3 TIOB12_1 141 115 - G11 TIOB12_2 53 43 - M2

Document Number: 002-04988 Rev.*A Page 35 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Base Timer TIOA13_0 Base Timer ch 13 TIOA pin 7 7 7 D1 TIOA13_1 154 124 100 E12 TIOA13_2 34 24 - G6 TIOB13_0 Base Timer ch 13 TIOB pin 31 22 19 G4 TIOB13_1 155 125 101 E13 TIOB13_2 35 25 - H4 Base Timer TIOA14_0 Base Timer ch 14 TIOA pin 183 151 121 D8 TIOA14_1 89 74 - M9 TIOA14_2 204 - - - TIOB14_0 Base Timer ch 14 TIOB pin 182 150 120 C8 TIOB14_1 90 75 - L9 TIOB14_2 203 - - - Base Timer TIOA15_0 Base Timer ch 15 TIOA pin 187 155 125 B7 TIOA15_1 78 63 - K5 TIOA15_2 206 - - - TIOB15_0 Base timer ch 15 TIOB pin 186 154 124 F8 TIOB15_1 79 64 - K6 TIOB15_2 205 - - - Debugger SWCLK Serial wire debug interface clock input pin 165 135 111 A12 SWDIO Serial wire debug interface data input/ output pin 167 137 113 B12 SWO Serial wire viewer output pin 168 138 114 B11 TCK JTAG test clock input pin 165 135 111 A12 TDI JTAG test data input pin 166 136 112 C12 TDO JTAG debug data output pin 168 138 114 B11 TMS JTAG test mode state input/output pin 167 137 113 B12 TRACECLK Trace CLK output pin of ETM/HTM 131 107 87 H12 TRACED0 Trace data output pin of ETM/ Trace data output pin of HTM 132 108 88 H14 TRACED1 133 109 89 G14 TRACED2 134 110 90 H13 TRACED3 135 111 91 H11 TRACED4 Trace data output pin of HTM 138 112 - G13 TRACED5 139 113 - F14 TRACED6 140 114 - G12 TRACED7 141 115 - G11 TRACED8 119 - - - TRACED9 120 - - - TRACED10 121 - - - TRACED11 122 - - -

Document Number: 002-04988 Rev.*A Page 36 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Debugger TRACED12 Trace data output pin of HTM 148 - - - TRACED13 149 - - - TRACED14 150 - - - TRACED15 151 - - - TRSTX JTAG test reset Input pin 164 134 110 B13 External bus MAD00_0 External bus interface address bus 81 66 56 J6 MAD01_0 82 67 57 L8 MAD02_0 83 68 58 K8 MAD03_0 84 69 59 J8 MAD04_0 91 76 60 K9 MAD05_0 92 77 61 P10 MAD06_0 93 78 62 N10 MAD07_0 96 79 63 L10 MAD08_0 97 80 64 K10 MAD09_0 98 81 65 M10 MAD10_0 142 116 92 G10 MAD11_0 143 117 93 G9 MAD12_0 144 118 94 F10 MAD13_0 145 119 95 F11 MAD14_0 146 120 96 F12 MAD15_0 147 121 97 F13 MAD16_0 152 122 98 E10 MAD17_0 153 123 99 E11 MAD18_0 154 124 100 E12 MAD19_0 50 40 35 L1 MAD20_0 49 39 34 K4 MAD21_0 48 38 33 K3 MAD22_0 47 37 32 K2 MAD23_0 46 36 31 K1 MAD24_0 45 35 30 J2 MCSX0_0 External bus interface chip select output pin 71 56 48 M5 MCSX1_0 70 55 47 L5 MCSX2_0 61 51 43 N4 MCSX3_0 60 50 42 M4 MCSX4_0 59 49 41 L4 MCSX5_0 58 48 40 M3 MCSX6_0 57 47 39 N3 MCSX7_0 56 46 38 N2 MCSX8_0 88 73 - P9

Document Number: 002-04988 Rev.*A Page 37 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 External bus MADATA00_0 External bus interface data bus (address/data multiplex bus) 2 2 2 B2 MADATA01_0 3 3 3 C2 MADATA02_0 4 4 4 C3 MADATA03_0 5 5 5 D5 MADATA04_0 6 6 6 D2 MADATA05_0 7 7 7 D1 MADATA06_0 8 8 8 D3 MADATA07_0 9 9 9 D4 MADATA08_0 14 13 10 E5 MADATA09_0 15 14 11 F1 MADATA10_0 16 15 12 F2 MADATA11_0 17 16 13 F3 MADATA12_0 18 17 14 F4 MADATA13_0 23 18 15 F5 MADATA14_0 24 19 16 F6 MADATA15_0 25 20 17 G2 MADATA16_0 10 - - - MADATA17_0 11 - - - MADATA18_0 12 - - - MADATA19_0 13 - - - MADATA20_0 19 - - - MADATA21_0 20 - - - MADATA22_0 21 - - - MADATA23_0 22 - - - MADATA24_0 26 - - - MADATA25_0 27 - - - MADATA26_0 28 - - - MADATA27_0 29 - - - MADATA28_0 33 - - - MADATA29_0 51 - - - MADATA30_0 52 - - - MADATA31_0 53 - - - MDQM0_0 External bus interface byte mask signal output pin 30 21 18 G3 MDQM1_0 31 22 19 G4 MDQM2_0 34 - - - MDQM3_0 35 - - - MALE_0 External bus interface address latch enable output signal for multiplex 211 171 139 C4 MRDY_0 External bus interface external RDY input signal 80 65 55 L6

Document Number: 002-04988 Rev.*A Page 38 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 External bus MCLKOUT_0 External bus interface external clock output pin 32 23 20 G5 MNALE_0 External bus interface ALE signal to control NAND flash output pin 47 37 32 K2 MNCLE_0 External bus interface CLE signal to control NAND flash output pin 48 38 33 K3 MNREX_0 External bus interface read enable signal to control NAND flash 50 40 35 L1 MNWEX_0 External bus interface write enable signal to control NAND flash 49 39 34 K4 MOEX_0 External bus interface read enable signal for SRAM 209 169 137 C5 MWEX_0 External bus interface write enable signal for SRAM 210 170 138 B4 MSDCLK_0 SDRAM interface SDRAM clock output pin 90 75 - L9 MSDCKE_0 SDRAM interface SDRAM clock enable pin 89 74 - M9 MRASX_0 SDRAM interface SDRAM column active strobe pin 85 70 - N8 MCASX_0 SDRAM interface SDRAM row active strobe pin 86 71 - M8 MSDWEX_0 SDRAM interface SDRAM write enable pin 87 72 - N9 External interrupt INT00_0 External interrupt request 00 input pin 2 2 2 B2 INT00_1 38 28 23 H3 INT00_2 19 - - - INT01_0 External interrupt request 01 input pin 7 7 7 D1 INT01_1 41 31 26 H6 INT01_2 51 41 - L2 INT02_0 External interrupt request 02 input pin 14 13 10 E5 INT02_1 42 32 27 J5 INT02_2 26 - - - INT03_0 External interrupt request 03 input pin 17 16 13 F3 INT03_1 43 33 28 J4 INT03_2 34 24 - G6 INT04_0 External interrupt request 04 input pin 59 49 41 L4 INT04_1 100 83 67 M11 INT04_2 65 - - - INT05_0 External interrupt request 05 input pin 70 55 47 L5 INT05_1 86 71 - M8 INT05_2 68 - - -

Document Number: 002-04988 Rev.*A Page 39 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 External interrupt INT06_0 External interrupt request 06 input pin 80 65 55 L6 INT06_1 87 72 - N9 INT06_2 103 - - - INT07_0 External interrupt request 07 input pin 82 67 57 L8 INT07_1 88 73 - P9 INT07_2 102 - - - INT08_0 External interrupt request 08 input pin 114 94 78 L11 INT08_1 127 103 - J9 INT08_2 119 - - - INT09_0 External interrupt request 09 input pin 123 99 83 J13 INT09_1 128 104 - H10 INT09_2 120 - - - INT10_0 External interrupt request 10 input pin 130 106 86 H9 INT10_1 138 112 - G13 INT10_2 149 - - - INT11_0 External interrupt request 11 input pin 133 109 89 G14 INT11_1 139 113 - F14 INT11_2 151 - - - INT12_0 External interrupt request 12 input pin 194 162 132 E7 INT12_1 169 139 - C11 INT12_2 175 - - - INT13_0 External interrupt request 13 input pin 184 152 122 E8 INT13_1 170 140 - D11 INT13_2 176 - - - INT14_0 External interrupt request 14 input pin 192 160 130 A6 INT14_1 171 141 - B10 INT14_2 201 - - - INT15_0 External interrupt request 15 input pin 193 161 131 D7 INT15_1 172 142 - C10 INT15_2 206 - - - INT16_0 External interrupt request 16 input pin 25 20 17 G2 INT16_1 45 35 30 J2 INT17_0 External interrupt request 17 input pin 30 21 18 G3 INT17_1 46 36 31 K1 INT18_0 External interrupt request 18 input pin 31 22 19 G4 INT18_1 47 37 32 K2 INT19_0 External interrupt request 19 input pin 36 26 21 H2 INT19_1 48 38 33 K3

Document Number: 002-04988 Rev.*A Page 40 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 External interrupt INT20_0 External interrupt request 20 input pin 91 76 60 K9 INT20_1 89 74 - M9 INT21_0 External interrupt request 21 input pin 96 79 63 L10 INT21_1 90 75 - L9 INT22_0 External interrupt request 22 input pin 99 82 66 N11 INT22_1 78 63 - K5 INT23_0 External interrupt request 23 input pin 56 46 38 N2 INT23_1 79 64 - K6 INT24_0 External interrupt request 24 input pin 147 121 97 F13 INT24_1 131 107 87 H12 INT25_0 External interrupt request 25 input pin 153 123 99 E11 INT25_1 117 97 81 K14 INT26_0 External interrupt request 26 input pin 156 126 102 D12 INT26_1 142 116 92 G10 INT27_0 External interrupt request 27 input pin 157 127 103 D13 INT27_1 143 117 93 G9 INT28_0 External interrupt request 28 input pin 190 158 128 A7 INT28_1 207 167 - E6 INT29_0 External interrupt request 29 input pin 198 166 136 D6 INT29_1 208 168 - B5 INT30_0 External interrupt request 30 input pin 209 169 137 C5 INT30_1 195 163 133 F7 INT31_0 External interrupt request 31 input pin 212 172 140 B3 INT31_1 196 164 134 B6 NMIX Non-maskable interrupt input pin 158 128 104 C13

Document Number: 002-04988 Rev.*A Page 41 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 GPIO P00 General-purpose I/O port 0 164 134 110 B13 P01 165 135 111 A12 P02 166 136 112 C12 P03 167 137 113 B12 P04 168 138 114 B11 P08 30 21 18 G3 P09 31 22 19 G4 P0A 32 23 20 G5 P10 General-purpose I/O port 1 114 94 78 L11 P11 115 95 79 K13 P12 116 96 80 K12 P13 117 97 81 K14 P14 118 98 82 K11 P15 123 99 83 J13 P16 124 100 84 J12 P17 125 101 85 J11 P18 130 106 86 H9 P19 131 107 87 H12 P1A 132 108 88 H14 P1B 133 109 89 G14 P1C 134 110 90 H13 P1D 135 111 91 H11 P1E 142 116 92 G10 P1F 143 117 93 G9 P20 General-purpose I/O port 2 158 128 104 C13 P21 157 127 103 D13 P22 156 126 102 D12 P23 155 125 101 E13 P24 154 124 100 E12 P25 153 123 99 E11 P26 152 122 98 E10 P27 147 121 97 F13 P28 146 120 96 F12 P29 145 119 95 F11 P2A 144 118 94 F10

Document Number: 002-04988 Rev.*A Page 42 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 GPIO P30 General-purpose I/O port 3 34 24 - G6 P31 35 25 - H4 P32 36 26 21 H2 P33 37 27 22 J1 P34 38 28 23 H3 P35 41 31 26 H6 P36 42 32 27 J5 P37 43 33 28 J4 P38 44 34 29 J3 P39 45 35 30 J2 P3A 46 36 31 K1 P3B 47 37 32 K2 P3C 48 38 33 K3 P3D 49 39 34 K4 P3E 50 40 35 L1 P40 General-purpose I/O port 4 56 46 38 N2 P41 57 47 39 N3 P42 58 48 40 M3 P43 59 49 41 L4 P44 60 50 42 M4 P45 61 51 43 N4 P46 73 58 50 P5 P47 74 59 51 P6 P48 76 61 53 N6 P49 77 62 54 M6 P4A 65 - - - P4B 66 - - - P4C 67 - - - P4D 68 - - - P4E 69 - - -

Document Number: 002-04988 Rev.*A Page 43 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 GPIO P50 General-purpose I/O port 5 10 10 - E2 P51 11 11 - E3 P52 12 12 - E4 P53 13 - - - P54 19 - - - P55 20 - - - P56 21 - - - P57 22 - - - P58 26 - - - P59 27 - - - P5A 28 - - - P5B 29 - - - P5C 33 - - - P5D 51 41 - L2 P5E 52 42 - L3 P5F 53 43 - M2 P60 General-purpose I/O port 6 212 172 140 B3 P61 211 171 139 C4 P62 210 170 138 B4 P63 209 169 137 C5 P64 208 168 - B5 P65 207 167 - E6 P66 206 - - - P67 205 - - - P68 204 - - - P69 203 - - - P6A 202 - - - P6B 201 - - - P6C 200 - - - P6D 199 - - - P6E 198 166 136 D6

Document Number: 002-04988 Rev.*A Page 44 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 GPIO P70 General-purpose I/O port 7 80 65 55 L6 P71 81 66 56 J6 P72 82 67 57 L8 P73 83 68 58 K8 P74 84 69 59 J8 P75 91 76 60 K9 P76 92 77 61 P10 P77 93 78 62 N10 P78 96 79 63 L10 P79 97 80 64 K10 P7A 98 81 65 M10 P7B 99 82 66 N11 P7C 100 83 67 M11 P7D 70 55 47 L5 P7E 71 56 48 M5 P80 General-purpose I/O port 8 214 174 142 A3 P81 215 175 143 A2 P82 160 130 106 D14 P83 161 131 107 C14 P90 General-purpose I/O port 9 169 139 - C11 P91 170 140 - D11 P92 171 141 - B10 P93 172 142 - C10 P94 173 143 - D10 P95 174 144 - B9 P96 175 - - - P97 176 - - -

Document Number: 002-04988 Rev.*A Page 45 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 GPIO PA0 General-purpose I/O port A 2 2 2 B2 PA1 3 3 3 C2 PA2 4 4 4 C3 PA3 5 5 5 D5 PA4 6 6 6 D2 PA5 7 7 7 D1 PA6 8 8 8 D3 PA7 9 9 9 D4 PA8 14 13 10 E5 PA9 15 14 11 F1 PAA 16 15 12 F2 PAB 17 16 13 F3 PAC 18 17 14 F4 PAD 23 18 15 F5 PAE 24 19 16 F6 PAF 25 20 17 G2 PB0 General-purpose I/O port B 126 102 - J10 PB1 127 103 - J9 PB2 128 104 - H10 PB3 129 105 - J14 PB4 138 112 - G13 PB5 139 113 - F14 PB6 140 114 - G12 PB7 141 115 - G11 PB8 119 - - - PB9 120 - - - PBA 121 - - - PBB 122 - - - PBC 148 - - - PBD 149 - - - PBE 150 - - - PBF 151 - - -

Document Number: 002-04988 Rev.*A Page 46 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 GPIO PC0 General-purpose I/O port C 177 145 115 C9 PC1 178 146 116 B8 PC2 179 147 117 D9 PC3 180 148 118 E9 PC4 181 149 119 F9 PC5 182 150 120 C8 PC6 183 151 121 D8 PC7 184 152 122 E8 PC8 185 153 123 A10 PC9 186 154 124 F8 PCA 187 155 125 B7 PCB 190 158 128 A7 PCC 191 159 129 C7 PCD 192 160 130 A6 PCE 193 161 131 D7 PCF 194 162 132 E7 PD0 General-purpose I/O port D 195 163 133 F7 PD1 196 164 134 B6 PD2 197 165 135 C6 PE0 General-purpose I/O port E 104 84 68 N13 PE2 106 86 70 P12 PE3 107 87 71 P13 PF0 General-purpose I/O port F 78 63 - K5 PF1 79 64 - K6 PF2 85 70 - N8 PF3 86 71 - M8 PF4 87 72 - N9 PF5 88 73 - P9 PF6 89 74 - M9 PF7 90 75 - L9 PF8 94 - - - PF9 95 - - - PFA 101 - - - PFB 102 - - - PFC 103 - - -

Document Number: 002-04988 Rev.*A Page 47 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Serial SIN0_0 Multi-function serial interface ch 0 input pin 157 127 103 D13 SIN0_1 151 - - - SOT0_0 (SDA0_0) Multi-function serial interface ch 0 output pin This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). 156 126 102 D12 SOT0_1 (SDA0_1) 150 - - - SCK0_0 (SCL0_0) Multi-function serial interface ch 0 clock I/O pin This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4) 155 125 101 E13 SCK0_1 (SCL0_1) 149 - - - Multi- Function Serial SIN1_0 Multi-function serial interface ch 1 input pin 7 7 7 D1 SIN1_1 80 65 55 L6 SOT1_0 (SDA1_0) Multi-function serial interface ch 1 output pin This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). 8 8 8 D3 SOT1_1 (SDA1_1) 81 66 56 J6 SCK1_0 (SCL1_0) Multi-function serial interface ch 1 clock I/O pin This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and as SCL1 when it is used in an I2C (operation mode 4). 9 9 9 D4 SCK1_1 (SCL1_1) 70 55 47 L5 Multi- Function Serial SIN2_0 Multi-function serial interface ch 2 input pin 130 106 86 H9 SIN2_1 45 35 30 J2 SOT2_0 (SDA2_0) Multi-function serial interface ch 2 output pin This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). 131 107 87 H12 SOT2_1 (SDA2_1) 46 36 31 K1 SCK2_0 (SCL2_0) Multi-function serial interface ch 2 clock I/O pin This pin operates as SCK2 when it is used in a CSIO (operation mode 2) and as SCL2 when it is used in an I2C (operation mode 4). 132 108 88 H14 SCK2_1 (SCL2_1) 47 37 32 K2

Document Number: 002-04988 Rev.*A Page 48 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Serial SIN3_0 Multi-function serial interface ch 3 input pin 25 20 17 G2 SIN3_1 56 46 38 N2 SOT3_0 (SDA3_0) Multi-function serial interface ch 3 output pin This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). 24 19 16 F6 SOT3_1 (SDA3_1) 57 47 39 N3 SCK3_0 (SCL3_0) Multi-function serial interface ch 3 clock I/O pin This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). 23 18 15 F5 SCK3_1 (SCL3_1) 58 48 40 M3 Multi- Function Serial SIN4_0 Multi-function serial interface ch 4 input pin 212 172 140 B3 SIN4_1 193 161 131 D7 SOT4_0 (SDA4_0) Multi-function serial interface ch 4 output pin This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). 211 171 139 C4 SOT4_1 (SDA4_1) 192 160 130 A6 SCK4_0 (SCL4_0) Multi-function serial interface ch 4 clock I/O pin This pin operates as SCK4 when it is used in a CSIO (operation mode 2) and as SCL4 when it is used in an I2C (operation mode 4). 210 170 138 B4 SCK4_1 (SCL4_1) 198 166 136 D6 CTS4_0 Multi-function serial interface ch 4 CTS input pin 208 168 - B5 CTS4_1 197 165 135 C6 RTS4_0 Multi-function serial interface ch 4 RTS output pin 209 169 137 C5 RTS4_1 194 162 132 E7

Document Number: 002-04988 Rev.*A Page 49 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Serial SIN5_0 Multi-function serial interface ch 5 input pin 147 121 97 F13 SIN5_1 170 140 - D11 SOT5_0 (SDA5_0) Multi-function serial interface ch 5 output pin This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). 146 120 96 F12 SOT5_1 (SDA5_1) 171 141 - B10 SCK5_0 (SCL5_0) Multi-function serial interface ch 5 clock I/O pin This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4). 145 119 95 F11 SCK5_1 (SCL5_1) 172 142 - C10 CTS5_0 Multi-function serial interface ch 5 CTS input pin 144 118 94 F10 CTS5_1 173 143 - D10 RTS5_0 Multi-function serial interface ch 5 RTS output pin 143 117 93 G9 RTS5_1 174 144 - B9 Multi- Function Serial SIN6_0 Multi-function serial interface ch 6 input pin 96 79 63 L10 SIN6_1 117 97 81 K14 SOT6_0 (SDA6_0) Multi-function serial interface ch 6 output pin This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). 97 80 64 K10 SOT6_1 (SDA6_1) 118 98 82 K11 SCK6_0 (SCL6_0) Multi-function serial interface ch 6 clock I/O pin This pin operates as SCK6 when it is used in a CSIO (operation mode 2) and as SCL6 when it is used in an I2C (operation mode 4). 98 81 65 M10 SCK6_1 (SCL6_1) 126 102 - J10 SCS60_0 Multi-function serial interface ch 6 chip select 0 input/output pin 99 82 66 N11 SCS60_1 127 103 - J9 SCS61_0 Multi-function serial interface ch 6 chip select1 input/output pin 100 83 67 M11 SCS61_1 128 104 - H10 SCS62_0 Multi-function serial interface ch 6 chip select2 input/output pin 79 64 - K6 SCS62_1 129 105 - J14 SCS63_0 Multi-function serial interface ch 6 chip select3 input/output pin 78 63 - K5 SCS63_1 119 - - -

Document Number: 002-04988 Rev.*A Page 50 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Serial SIN7_0 Multi-function serial interface ch 7 input pin 14 13 10 E5 SIN7_1 103 - - - SOT7_0 (SDA7_0) Multi-function serial interface ch 7 output pin This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). 15 14 11 F1 SOT7_1 (SDA7_1) 102 - - - SCK7_0 (SCL7_0) Multi-function serial interface ch 7 clock I/O pin This pin operates as SCK7 when it is used in a CSIO (operation mode 2) and as SCL7 when it is used in an I2C (operation mode 4). 16 15 12 F2 SCK7_1 (SCL7_1) 101 - - - SCS70_0 Multi-function serial interface ch 7 chip select 0 input/output pin 17 16 13 F3 SCS70_1 94 - - - SCS71_0 Multi-function serial interface ch 7 chip select 1 input/output pin 18 17 14 F4 SCS71_1 95 - - - SCS72_0 Multi-function serial interface ch 7 chip select 2 input/output pin 10 10 - E2 SCS72_1 68 - - - SCS73_0 Multi-function serial interface ch 7 chip select 3 input/output pin 11 11 - E3 SCS73_1 69 - - - Multi- Function Serial SIN8_0 Multi-function serial interface ch 8 input pin 91 76 60 K9 SIN8_1 138 112 - G13 SOT8_0 (SDA8_0) Multi-function serial interface ch 8 output pin This pin operates as SOT8 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA8 when it is used in an I2C (operation mode 4). 92 77 61 P10 SOT8_1 (SDA8_1) 139 113 - F14 SCK8_0 (SCL8_0) Multi-function serial interface ch 8 clock I/O pin This pin operates as SCK8 when it is used in a CSIO (operation mode 2) and as SCL8 when it is used in an I2C (operation mode 4). 93 78 62 N10 SCK8_1 (SCL8_1) 140 114 - G12

Document Number: 002-04988 Rev.*A Page 51 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Serial SIN9_0 Multi-function serial interface ch 9 input pin 82 67 57 L8 SIN9_1 120 - - - SOT9_0 (SDA9_0) Multi-function serial interface ch 9 output pin This pin operates as SOT9 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA9 when it is used in an I2C (operation mode 4). 83 68 58 K8 SOT9_1 (SDA9_1) 121 - - - SCK9_0 (SCL9_0) Multi-function serial interface ch 9 clock I/O pin This pin operates as SCK9 when it is used in a CSIO (operation mode 2) and as SCL9 when it is used in an I2C (operation mode 4). 84 69 59 J8 SCK9_1 (SCL9_1) 122 - - - Multi- Function Serial SIN10_0 Multi-function serial interface ch 10 input pin 114 94 78 L11 SIN10_1 51 41 - L2 SOT10_0 (SDA10_0) Multi-function serial interface ch 10 output pin This pin operates as SOT10 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA10 when it is used in an I2C (operation mode 4). 115 95 79 K13 SOT10_1 (SDA10_1) 52 42 - L3 SCK10_0 (SCL10_0) Multi-function serial interface ch 10 clock I/O pin This pin operates as SCK10 when it is used in a CSIO (operation mode 2) and as SCL10 when it is used in an I2C (operation mode 4). 116 96 80 K12 SCK10_1 (SCL10_1) 53 43 - M2 Multi- Function Serial SIN11_0 Multi-function serial interface ch 11 input pin 123 99 83 J13 SIN11_1 26 - - - SOT11_0 (SDA11_0) Multi-function serial interface ch 11 output pin This pin operates as SOT11 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA11 when it is used in an I2C (operation mode 4). 124 100 84 J12 SOT11_1 (SDA11_1) 27 - - - SCK11_0 (SCL11_0) Multi-function serial interface ch 11 clock I/O pin This pin operates as SCK11 when it is used in a CSIO (operation mode 2) and as SCL11 when it is used in an I2C (operation mode 4). 125 101 85 J11 SCK11_1 (SCL11_1) 28 - - -

Document Number: 002-04988 Rev.*A Page 52 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Serial SIN12_0 Multi-function serial interface ch 12 input pin 133 109 89 G14 SIN12_1 65 - - - SOT12_0 (SDA12_0) Multi-function serial interface ch 12 output pin This pin operates as SOT12 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA12 when it is used in an I2C (operation mode 4). 134 110 90 H13 SOT12_1 (SDA12_1) 66 - - - SCK12_0 (SCL12_0) Multi-function serial interface ch 12 clock I/O pin This pin operates as SCK12 when it is used in a CSIO (operation mode 2) and as SCL12 when it is used in an I2C (operation mode 4). 135 111 91 H11 SCK12_1 (SCL12_1) 67 - - - Multi- Function Serial SIN13_0 Multi-function serial interface ch 13 input pin 48 38 33 K3 SIN13_1 206 - - - SOT13_0 (SDA13_0) Multi-function serial interface ch 13 output pin This pin operates as SOT13 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA13 when it is used in an I2C (operation mode 4). 49 39 34 K4 SOT13_1 SCK13_0 (SCL13_0) Multi-function serial interface ch 13 clock I/O pin This pin operates as SCK13 when it is used in a CSIO (operation mode 2) and as SCL13 when it is used in an I2C (operation mode 4). 50 40 35 L1 SCK13_1 Multi- Function Serial SIN14_0 Multi-function serial interface ch 14 input pin 30 21 18 G3 SIN14_1 201 - - - SOT14_0 (SDA14_0) Multi-function serial interface ch 14 output pin This pin operates as SOT14 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA14 when it is used in an I2C (operation mode 4). 31 22 19 G4 SOT14_1 SCK14_0 (SCL14_0) Multi-function serial interface ch 14 clock I/O pin This pin operates as SCK14 when it is used in a CSIO (operation mode 2) and as SCL14 when it is used in an I2C (operation mode 4). 32 23 20 G5 SCK14_1

Document Number: 002-04988 Rev.*A Page 53 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Serial SIN15_0 Multi-function serial interface ch 15 input pin 59 49 41 L4 SIN15_1 19 - - - SOT15_0 (SDA15_0) Multi-function serial interface ch 15 output pin This pin operates as SOT15 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA15 when it is used in an I2C (operation mode 4). 60 50 42 M4 SOT15_1 (SDA15_1) 20 - - - SCK15_0 (SCL15_0) Multi-function serial interface ch 15 clock I/O pin This pin operates as SCK15 when it is used in a CSIO (operation mode 2) and as SCL15 when it is used in an I2C (operation mode 4). 61 51 43 N4 SCK15_1 (SCL15_1) 21 - - -

Document Number: 002-04988 Rev.*A Page 54 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Timer 0 DTTI0X_0 Input signal controlling waveform generator outputs RTO00 to RTO05 of Multi-Function Timer 0. 44 34 29 J3 DTTI0X_1 21 - - - FRCK0_0 16-bit free-run timer ch 0 external clock input pin 37 27 22 J1 FRCK0_1 29 - - - IC00_0 16-bit input capture input pin of Multi-Function Timer 0. ICxx describes channel number. 43 33 28 J4 IC00_1 22 - - - IC01_0 42 32 27 J5 IC01_1 26 - - - IC02_0 41 31 26 H6 IC02_1 27 - - - IC03_0 38 28 23 H3 IC03_1 28 - - - RTO00_0 (PPG00_0) Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 45 35 30 J2 RTO00_1 (PPG00_1) 10 10 - E2 RTO01_0 (PPG00_0) Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 46 36 31 K1 RTO01_1 (PPG00_1) 11 11 - E3 RTO02_0 (PPG02_0) Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 47 37 32 K2 RTO02_1 (PPG02_1) 12 12 - E4 RTO03_0 (PPG02_0) Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 48 38 33 K3 RTO03_1 (PPG02_1) 13 - - - RTO04_0 (PPG04_0) Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 49 39 34 K4 RTO04_1 (PPG04_1) 19 - - - RTO05_0 (PPG04_0) Waveform generator output pin of Multi-Function Timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 50 40 35 L1 RTO05_1 (PPG04_1) 20 - - -

Document Number: 002-04988 Rev.*A Page 55 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Timer 1 DTTI1X_0 Input signal controlling waveform generator outputs RTO10 to RTO15 of Multi-Function Timer 1. 70 55 47 L5 DTTI1X_1 94 - - - FRCK1_0 16-bit free-run timer ch 1 external clock input pin 71 56 48 M5 FRCK1_1 78 63 - K5 IC10_0 16-bit input capture input pin of Multi-Function Timer 1. ICxx describes channel number. 96 79 63 L10 IC10_1 95 - - - IC11_0 97 80 64 K10 IC11_1 101 - - - IC12_0 98 81 65 M10 IC12_1 102 - - - IC13_0 99 82 66 N11 IC13_1 103 - - - RTO10_0 (PPG10_0) Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 56 46 38 N2 RTO10_1 (PPG10_1) 85 70 - N8 RTO11_0 (PPG10_0) Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 57 47 39 N3 RTO11_1 (PPG10_1) 86 71 - M8 RTO12_0 (PPG12_0) Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 58 48 40 M3 RTO12_1 (PPG12_1) 87 72 - N9 RTO13_0 (PPG12_0) Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 59 49 41 L4 RTO13_1 (PPG12_1) 88 73 - P9 RTO14_0 (PPG14_0) Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 60 50 42 M4 RTO14_1 (PPG14_1) 89 74 - M9 RTO15_0 (PPG14_0) Waveform generator output pin of Multi-Function Timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 61 51 43 N4 RTO15_1 (PPG14_1) 90 75 - L9

Document Number: 002-04988 Rev.*A Page 56 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Multi- Function Timer 2 DTTI2X_0 Input signal controlling waveform generator outputs RTO20 to RTO25 of Multi-Function Timer 1. 8 8 8 D3 DTTI2X_1 202 - - - FRCK2_0 16-bit free-run timer ch 2 external clock input pin 17 16 13 F3 FRCK2_1 197 165 135 C6 IC20_0 16-bit input capture input pin of Multi-Function Timer 2. ICxx describes channel number. 9 9 9 D4 IC20_1 201 - - - IC21_0 14 13 10 E5 IC21_1 200 - - - IC22_0 15 14 11 F1 IC22_1 199 - - - IC23_0 16 15 12 F2 IC23_1 198 166 136 D6 RTO20_0 (PPG20_0) Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. 2 2 2 B2 RTO20_1 RTO21_0 (PPG20_0) Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. 3 3 3 C2 RTO21_1 RTO22_0 (PPG22_0) Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. 4 4 4 C3 RTO22_1 RTO23_0 (PPG22_0) Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. 5 5 5 D5 RTO23_1 RTO24_0 (PPG24_0) Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. 6 6 6 D2 RTO24_1 (PPG24_1) 207 167 - E6 RTO25_0 (PPG24_0) Waveform generator output pin of Multi-Function Timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. 7 7 7 D1 RTO25_1 (PPG24_1) 208 168 - B5

Document Number: 002-04988 Rev.*A Page 57 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Quadrature Position/ Revolution Counter AIN0_0 QPRC ch 0 AIN input pin 56 46 38 N2 AIN0_1 65 - - - AIN0_2 114 94 78 L11 BIN0_0 QPRC ch 0 BIN input pin 57 47 39 N3 BIN0_1 66 - - - BIN0_2 115 95 79 K13 ZIN0_0 QPRC ch 0 ZIN input pin 58 48 40 M3 ZIN0_1 67 - - - ZIN0_2 116 96 80 K12 Quadrature Position/ Revolution Counter AIN1_0 QPRC ch 1 AIN input pin 91 76 60 K9 AIN1_1 94 - - - AIN1_2 123 99 83 J13 BIN1_0 QPRC ch 1 BIN input pin 92 77 61 P10 BIN1_1 45 - - - BIN1_2 124 100 84 J12 ZIN1_0 QPRC ch 1 ZIN input pin 93 78 62 N10 ZIN1_1 101 - - - ZIN1_2 125 101 85 J11 Quadrature Position/ Revolution Counter AIN2_0 QPRC ch 2 AIN input pin 2 2 2 B2 AIN2_1 32 23 20 G5 AIN2_2 120 - - - BIN2_0 QPRC ch 2 BIN input pin 3 3 3 C2 BIN2_1 36 26 21 H2 BIN2_2 121 - - - ZIN2_0 QPRC ch 2 ZIN input pin 4 4 4 C3 ZIN2_1 37 27 22 J1 ZIN2_2 122 - - - Quadrature Position/ Revolution Counter AIN3_0 QPRC ch 3 AIN input pin 18 17 14 F4 AIN3_1 45 35 30 J2 AIN3_2 149 - - - BIN3_0 QPRC ch 3 BIN input pin 23 18 15 F5 BIN3_1 46 36 31 K1 BIN3_2 150 - - - ZIN3_0 QPRC ch 3 ZIN input pin 24 19 16 F6 ZIN3_1 47 37 32 K2 ZIN3_2 151 - - -

Document Number: 002-04988 Rev.*A Page 58 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Real-time clock RTCCO_0 0.5 seconds pulse output pin of real-time clock 211 171 139 C4 RTCCO_1 33 - - - SUBOUT_0 Sub-clock output pin 211 171 139 C4 SUBOUT_1 33 - - - USB0 UDM0 USB ch 0 function/host D – pin 214 174 142 A3 UDP0 USB ch 0 function/host D + pin 215 175 143 A2 UHCONX0 USB ch 0 external pull-up control pin 211 171 139 C4 USB1 UDM1 USB ch 1 function/host D – pin 160 130 106 D14 UDP1 USB ch 1 function/host D + pin 161 131 107 C14 UHCONX1 USB ch 1 external pull-up control pin 155 125 101 E13 Low power consump- tion mode WKUP0 Deep standby mode return signal input pin 0 158 128 104 C13 WKUP1 Deep standby mode return signal input pin 1 14 13 10 E5 WKUP2 Deep standby mode return signal input pin 2 70 55 47 L5 WKUP3 Deep standby mode return signal input pin 3 212 172 140 B3 D/A converter DA0 D/A converter ch 0 analog output pin 100 83 67 M11 DA1 D/A converter ch 1 analog output pin 99 82 66 N11 VBAT VREGCTL On-board regulator control pin 76 61 53 N6 VWAKEUP The return signal input pin from a hibernation state 77 62 54 M6 SD I/F S_CLK_0 SD memory card interface SD memory card clock output pin 38 28 23 H3 S_CMD_0 SD memory card interface SD memory card command output 41 31 26 H6 S_DATA1_0 SD memory card interface SD memory card data bus 36 26 21 H2 S_DATA0_0 37 27 22 J1 S_DATA3_0 42 32 27 J5 S_DATA2_0 43 33 28 J4 S_CD_0 SD memory card interface SD memory card detection pin 45 35 30 J2 S_WP_0 SD memory card interface SD memory card write protection 44 34 29 J3

Document Number: 002-04988 Rev.*A Page 59 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 I2S I2SMCLK0_0 I2S external clock pin 51 41 - L2 I2SDO0_0 I2S serial transition data output pin 52 42 - L3 I2SWS0_0 I2S frame synchronization signal pin 53 43 - M2 I2SDI0_0 I2S serial received data input pin 34 24 - G6 I2SCK0_0 I2S bit clock pin 35 25 - H4 High-speed quad SPI Q_SCK_0 SPI clock output pin 173 143 - D10 Q_IO0_0 SPI data input/output pin 172 142 - C10 Q_IO1_0 171 141 - B10 Q_IO2_0 170 140 - D11 Q_IO3_0 169 139 - C11 Q_CS0_0 SPI chip select output pin 174 144 - B9 Q_CS1_0 175 - - - Q_CS2_0 176 - - -

Document Number: 002-04988 Rev.*A Page 60 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Reset INITX External reset Input pin A reset is valid when INITX = L. 72 57 49 N5 Mode MD1 Mode 1 pin During serial programming to flash memory, MD1 = L must be input. 104 84 68 N13 MD0 Mode 0 pin During normal operation, MD0 = L must be input. During serial programming to flash memory, MD0 = H must be input. 105 85 69 N12 Power VCC Power supply pin 1 1 1 C1 39 29 24 H1 55 45 37 N1 64 54 46 P4 109 89 73 M14 137 - - - 163 133 109 A13 188 156 126 A9 USBVCC0 3.3V power supply port for USB I/ 213 173 141 A4 USBVCC1 159 129 105 E14 GND VSS GND pin 40 30 25 H5 54 44 36 M1 63 53 45 P3 108 88 72 N14 136 - - - 162 132 108 B14 189 157 127 A8 216 176 144 B1 - - - E1 - - - G1 - - - P7 - - - P11 - - - L14 - - - A11 - - - A5 - - - N7 - - - M7 - - - K7 - - - J7 - - - G7 - - - H7 - - - H8 - - - G8

Document Number: 002-04988 Rev.*A Page 61 of 198 S6E2C3 Series Module Pin Name Function Pin Number LQQ 216 LQP 176 LQS 144 LBE 192 Clock X0 Main clock (oscillation) input pin 106 86 70 P12 X1 Main clock (oscillation) I/O pin 107 87 71 P13 X0A Sub clock (oscillation) input pin 73 58 50 P5 X1A Sub clock (oscillation) I/O pin 74 59 51 P6 CROUT_0 Built-in High-speed CR-oscillation clock output port 157 127 103 D13 CROUT_1 184 152 122 E8 Analog Power AVCC A/D converter and D/A converter analog power-supply pin 110 90 74 M13 AVRL A/D converter analog reference voltage input pin 112 92 76 L13 AVRH A/D converter analog reference voltage input pin 113 93 77 L12 VBAT Power VBAT VBAT power supply pin Backup power supply (battery etc.) and system power supply 75 60 52 P8 Analog GND AVSS A/D converter and D/A converter GND pin 111 91 75 M12 C pin C Power supply stabilization capacity pin 62 52 44 P2 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.

Document Number: 002-04988 Rev.*A Page 62 of 198 S6E2C3 Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation/GPIO function. When the main oscillation is selected: ・ Oscillation feedback resistor: approximately 1 MΩ ・ Standby mode control When the GPIO is selected: ・ CMOS level output. ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA B ・ CMOS level hysteresis input ・ Pull-up resistor: approximately 50 kΩ P-chP-ch N-ch R R P-chP-ch N-ch Standby mode control Digital input Standby mode control Digital output Digital output Clock input Digital input Standby mode control Pull-up resistor control Pull-up resistor control Digital output Digital output Pull-up resistor Digital input

Document Number: 002-04988 Rev.*A Page 63 of 198 S6E2C3 Series Type Circuit Remarks C ・ Open drain output ・ CMOS level hysteresis input E ・ CMOS level output ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. F ・ CMOS level output ・ CMOS level hysteresis input ・ Input control ・ Analog input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. N-ch P-chP-ch N-ch R P-chP-ch N-ch R Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

Document Number: 002-04988 Rev.*A Page 64 of 198 S6E2C3 Series Type Circuit Remarks G ・ CMOS level output ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -12 mA, IOL = 12 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. H It is possible to select either USB I/O or GPIO function. When the USB I/O is selected: ・ Full-speed, low-speed control When the GPIO is selected: ・ CMOS level output ・ CMOS level hysteresis input ・ Standby mode control ・ IOH = -20.5 mA, IOL = 18.5 mA P-chP-ch N-ch R UDP/Pxx UDM/Pxx Differential Standby mode control Pull-up resistor control Digital input Digital output Digital output GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output USB Full-speed/Low-speed control UDP input Differential input USB/GPIO select UDM input UDM output USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control

Document Number: 002-04988 Rev.*A Page 65 of 198 S6E2C3 Series Type Circuit Remarks I ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ Available to control of PZR registers (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the “FM4 Family Peripheral Manual Main Part (002-04856)”. J CMOS level hysteresis input K ・ CMOS level output ・ TTL level hysteresis input ・ Pull-up resistor control ・Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4mA, IOL = 4mA P-chP-ch N-ch R P-chP-ch N-ch R Standby mode control Pull-up resistor control Digital input Digital output Digital output Mode input Digital output Digital output Pull-up resistor control Digital input Standby mode control

Document Number: 002-04988 Rev.*A Page 66 of 198 S6E2C3 Series Type Circuit Remarks L ・ CMOS level output ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -8 mA, IOL = 8 mA ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. N ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA (GPIO) ・ IOL = 20mA (Fast mode Plus) ・ Available to control of PZR register (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the “FM4 Family Peripheral Manual Main Part (002-04856)”. ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. P-chP-ch N-ch R P-ch N-ch R P-ch N-ch Digital output Digital output Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Pull-up resistor control Fast mode control

Document Number: 002-04988 Rev.*A Page 67 of 198 S6E2C3 Series Type Circuit Remarks O ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ Available to control of PZR register (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the “FM4 Family Peripheral Manual Main Part (002-04856)”. ・ For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part (002-04856).” P ・ CMOS level output ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part (002-04856).” P-ch P-ch N-ch R Digital output Digital output Digital input Pull-up resistor control Digital output Digital output Digital input Pull-up resistor control Standby mode control OSC X0A P-ch P-ch N-ch R

Document Number: 002-04988 Rev.*A Page 68 of 198 S6E2C3 Series Type Circuit Remarks Q It is possible to select the sub oscillation/GPIO function. When the sub oscillation is selected: ・ Oscillation feedback resistor: approximately 10 MΩ When the GPIO is selected: ・ CMOS level output. ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA ・ For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part (002-04856).” R ・ CMOS level output ・ CMOS level hysteresis input ・ Analog output ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -4 mA, IOL = 4 mA (4.5V to 5.5V) ・ IOH = -2 mA, IOL = 2 mA (2.7V to 4.5V) P-ch P-ch N-ch R RX P-ch N-ch R P-ch X1A Digital output Digital output Digital input Pull-up resistor control Standby mode control OSC Standby mode control Clock input Pull-up resistor control Digital input Standby mode control Analog output Digital output Digital output

Document Number: 002-04988 Rev.*A Page 69 of 198 S6E2C3 Series Type Circuit Remarks S ・ CMOS level output ・ (It is possible to select by port drive capability. Select register [PDSR]) ・ CMOS level hysteresis input ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 kΩ ・ IOH = -10 mA, IOL = 10 mA (PDSR = 1) ・ IOH = -4 mA, IOL = 4 mA (PDSR = ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. P-ch P-ch N-ch R Digital output Port Drive Select Digital input Standby mode Control Pull-up resistor control

Document Number: 002-04988 Rev.*A Page 70 of 198 S6E2C3 Series 6. Handling Precautions Every semiconductor device has a characteristic, inherent rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins that connect semiconductor devices to power supply and I/O functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . Such conditions, if present for extended periods of time, can damage the device; therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power-supply pin or ground pin.

Document Number: 002-04988 Rev.*A Page 71 of 198 S6E2C3 Series Latch-Up Semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred milliamps to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design As previously mentioned, all semiconductor devices have inherent rates of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.

Document Number: 002-04988 Rev.*A Page 72 of 198 S6E2C3 Series Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent this, do the following: 1. Avoid exposure to rapid temperature changes, which can cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. 3. When Dry Packages are opened, it is recommended to have humidity between 40% and 70%. 4. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in these aluminum laminate bags for storage. 5. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons, and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, and the use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.

Document Number: 002-04988 Rev.*A Page 73 of 198 S6E2C3 Series

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of static electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive gases, dust, or oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, including cosmic radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, flame CAUTION: Plastic molded devices are flammable and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.

Document Number: 002-04988 Rev.*A Page 74 of 198 S6E2C3 Series 7. Handling Devices Power-Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. All of these pins should be connected externally to the power supply or ground lines, however, in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Be sure to connect the current-supply source with the power pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. A malfunction may occur when the power-supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane, as this is expected to produce stable operation. Evaluate the oscillation introduced by the use of the crystal oscillator by your mount board. Sub Crystal Oscillator The sub-oscillator circuit for devices in this family is low gain to keep current consumption low. To stabilize the oscillation, Cypress recommends a crystal oscillator that meets the following conditions:  Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: approximately 6 pF to 7 pF  Lead type Load capacitance: approximately 6 pF to 7 pF

Document Number: 002-04988 Rev.*A Page 75 of 198 S6E2C3 Series Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Handling When Using Multi-Function Serial Pin as I2C Pin If the application uses the multi-function serial pin as an I2C pin, the P-channel transistor of the digital output must be disabled. I2C pins need to conform to electrical limitations like other pins, however, and avoid connecting to live external systems with the MCU power off. C Pin Devices in this series contain a regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. Some laminated ceramic capacitors have a large capacitance variation due to thermal fluctuation. Please select a capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of the device. A smoothing capacitor of about 4.7 μF would be recommended for this series. Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, the distance between the mode pins and VCC pins or VSS pins is as short as possible, and the connection impedance is low when the pins are pulled up/down such as for switching the pin level and rewriting the flash memory data. This is important to prevent the device from erroneously switching to test mode as a result of noise. Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Set as external clock input Device C VSS CS GND

Document Number: 002-04988 Rev.*A Page 76 of 198 S6E2C3 Series Notes on Power-on Turn power on/off in the sequence shown below or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on: VBAT → VCC → USBVCC0 VBAT → VCC → USBVCC1 VCC → AVCC → AVRH Turning off: USBVCC0 → VCC → VBAT USBVCC1 → VCC → VBAT AVRH → AVCC → VCC Serial Communication There is a possibility of receiving incorrect data as a result of noise or other issues introduced by the serial communication. Take care to design the printed circuit board to minimize noise. Consider the case of introducing error as a result of noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Characteristics within the Product Line The electric characteristics including power consumption, ESD, latch-up, noise, and oscillation differ among members of the product line because chip layout and memory structures are not the same; for example, different sizes, flash versus ROM, etc. If you are switching to a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Pin Doubled as Debug Function The pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK should be used as output only. Do not use as input.

Document Number: 002-04988 Rev.*A Page 77 of 198 S6E2C3 Series 8. Block Diagram Cortex-M4 Core @200 MHz(Max) MainFlash I/F Clock Reset Generator Dual-Timer Watchdog Timer (Hardware) Watch Counter Unit 0 CSV External Interrupt Controller 32-pin + NMI Power-On Reset SRAM0 96/144/192 Kbytes AHB-APB Bridge : APB1 (Max 200 MHz) SRAM1

32 Kbytes

AHB-APB Bridge: APB0(Max 100 MHz) I D Sys CLK S6E2C3AH/J/L, S6E2C39H/J/L, S6E2C38H/J/L AHB-APB Bridge : APB2 (Max 100 MHz) NVIC Watchdog Timer (Software) Security Unit 1 TRSTX,TCK, TDI,TMS TRACEDx, TRACECLK AVCC, AVSS, AVRH, AVRL ANxx TIOAx TIOBx C TDO X0A X1A SCKx SINx SOTx INTx NMIX P0x, P1x, PFx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator CRC Accelerator AHB-AHB Bridge (Slave) ADTGx RTSx CTSx MADx MADATAx MainFlash/DualFlash

2 Mbytes(1M+1M)/

1.5 Mbytes(1M+0.5M)/

1 Mbytes(MainOnly)

16ch. (with FIFO ch.0 to ch.7) HW flow control(ch.4,5) External Bus I/F LVD Multi-layer AHB (Max 200 MHz) TPIU/ETB* ROM Table ETM/HTM*SWJ-DP Main Osc PLL CR 100 kHz LVD Ctrl Base Timer 16-bit 32ch./ 32-bit 16ch. Peripheral Clock Gating Low-speed CR Prescaler RTCCO, SUBOUT Deep Standby Ctrl WKUPx 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. A/D Activation Compare 6ch. 16-bit PPG 3ch. DTTI0X FRCK0 QPRC 4ch.BINx ZINx IC0x RTO0x AINx 12-bit A/D Converter Multi-function Timer × 3 MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX Waveform Generator 3ch. MPUFPU 12-bit D/A Converter 2units SRAM2 (16 Kbytes) USBVCC0 UDP0,UDM0 UHCONX0 S_CLK,S_CMD S_DATAx S_CD,S_WP I2S Clock Ctrl PLL VREGCTL VWAKEUP Unit 2 DAx Real-Time Clock Port Ctrl. Sub Osc VBAT Domain VBAT Domain CR

4 MHz

UDP1,UDM1 UHCONX1 PRG-CRC Accelerator I2SMCLK, I2SWS, I2SCK I2SDI I2SDO Q_SCK, Q_CSx Q_IOx AHB-AHB Bridge (Master) GPIO PIN-Function-Ctrl DMAC 8ch. DSTC Hi-Speed Quad SPI PHY PHY USB2.0 (Host/ Func) USB2.0 (Host/ Func) SD-CARD I/F VBAT DualFlash I/F I2S 1unit

Document Number: 002-04988 Rev.*A Page 78 of 198 S6E2C3 Series 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0x4008_1000 0x4008_0000 Programmable-CRC 0x4007_0000 Reserved 0x4006_F000 GPIO 0x4006_E000 SD-Card I/F 0xFFFF_FFFF 0x4006_D000 Reserved 0x4006_C000 I2S 0xE010_0000 0xE000_0000 0xD000_0000 0x4006_2000 0x4006_1000 DSTC 0x4006_0000 DMAC 0x6000_0000 0x4005_0000 USB ch.1 0x4004_0000 USB ch.0 0x4003_F000 EXT-bus I/F 0x4400_0000 0x4003_E000 Reserved 0x4003_D000 I2S prescaler 0x4200_0000 0x4003_C800 Reserved 0x4003_C100 Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x4000_0000 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x2400_0000 0x4003_8000 MFS 0x4003_7000 Reserved 0x2200_0000 0x4003_6000 USB Clock ctrl 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x200F_0000 0x4003_3000 D/AC 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x2004_8000 0x4002_F000 Reserved 0x2004_0000 SRAM2 0x4002_E000 CR Trim 0x2003_8000 SRAM1 0x2000_0000 Reserved 0x1FFF_0000 SRAM0 0x4002_8000 0x0050_0000 Reserved 0x4002_7000 A/DC 0x0040_0000 Security/CR Trim 0x4002_6000 QPRC 0x4002_5000 Base Timer 0x4002_4000 PPG 0x4002_3000 Reserved 0x0000_0000 0x4002_2000 MFT Unit2 0x4002_1000 MFT Unit1 0x4002_0000 MFT Unit0 0x4001_6000 0x4001_5000 Dual Timer 0x4001_3000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 MainFlash I/F メモリサイズの 詳細は 次項の「●メモリマップ(2)」 を参照してください。 Reserved Cortex-M4 Private Peripherals Peripherals Reserved External Device Area MainFlash Reserved Reserved DualFlash Reserved Reserved Reserved Reg. Area

32 Mbytes

See "Memory Map (2) and (3)" for memory size details.

Document Number: 002-04988 Rev.*A Page 79 of 198 S6E2C3 Series Memory Map (2) * See S6E2CC/S6E2C5/S6E2C4/S6E2C3/S6E2C2/S6E2C1 Series Flash Programming Manual to confirm the detail of flash Memory. S6E2C3AH/J/L S6E2C39H/J/L S6E2C38H/J/L 0x2020_0000 0x2020_0000 0x2020_0000 0x2004_8000 0x2004_8000 0x2004_8000 0x2004_0000 0x2004_0000 0x2004_0000 0x2003_8000 0x2003_8000 0x2003_8000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_0000 0x1FFE_0000 0x1FFD_0000 0x0041_0000 0x0041_0000 0x0041_0000 0x0040_8000 0x0040_8000 0x0040_8000 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security 0x0020_0000 0x0018_0000 SA9-15(#1) (64KBx7) SA8(#1) (32KB) SA8(#1) (32KB) 0x0010_0000 SA4-7(#1) (8KBx4) 0x0010_0000 SA4-7(#1) (8KBx4) 0x0010_0000 SA8(#0) (32KB) SA8(#0) (32KB) SA8(#0) (32KB) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) Reserved Reserved Reserved SRAM2 Reserved Reserved Reserved SRAM0

192 Kbytes

128 Kbytes

64 Kbytes

SA0-3(#1) (8KBx4) MainFlash

40 Kbytes

SA0-3(#1) (8KBx4) MainFlash SA0-3(#1) (8KBx4) MainFlash SA9-23(#1) (64KBx15) MainFlash

2 Mbytes

1 Mbytes

1.5 Mbytes

Document Number: 002-04988 Rev.*A Page 80 of 198 S6E2C3 Series Memory Map (2) During Dual Flash Mode S6E2C3AH/J/L S6E2C39H/J/L S6E2C38H/J/L 0x2020_0000 0x2020_0000 0x2020_0000 0x2018_0000 SA8(#1) (32KB) SA8(#1) (32KB) 0x2010_0000 SA4-7(#1) (8KBx4) 0x2010_0000 SA4-7(#1) (8KBx4) 0x2010_0000 0x200F_8000 SA0-3(#1) (8KBx4) 0x200F_8000 SA0-3(#1) (8KBx4) 0x200F_8000 SA0-3(#1) (8KBx4) 0x2004_8000 0x2004_8000 0x2004_8000 0x2004_0000 0x2004_0000 0x2004_0000 0x2003_8000 0x2003_8000 0x2003_8000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_0000 0x1FFE_0000 0x1FFD_0000 0x0041_0000 0x0041_0000 0x0041_0000 0x0040_8000 0x0040_8000 0x0040_8000 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_2000 CR trimming / HTM 0x0040_2000 CR trimming / HTM 0x0040_2000 CR trimming / HTM 0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security 0x0010_0000 0x0010_0000 0x0010_0000 SA8(#0) (32KB) SA8(#0) (32KB) SA8(#0) (32KB) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) SA9-23(#1) (64KBx15) DualFlash

1 Mbytes +32 Kbytes

512 Kbytes +32 Kbytes

SA9-15(#1) (64KBx7) Reserved Reserved SRAM2 Reserved Reserved Reserved SRAM0

8 Kbytes

Reserved Reserved Reserved SA9-23(#0) (64KBx15) MainFlash SA9-23(#0) (64KBx15) MainFlash SA9-23(#0) (64KBx15) MainFlash

Document Number: 002-04988 Rev.*A Page 81 of 198 S6E2C3 Series Memory Map (3) S6E2C3AH S6E2C3AJ S6E2C3AL 0xD000_0000 0xD000_0000 0xD000_0000 0xC000_0000 0xC000_0000 0xC000_0000 0x8000_0000 0x8000_0000 0x8000_0000 0x7000_0000 0x7000_0000 0x7000_0000 0x6000_0000 0x6000_0000 0x6000_0000 SRAM /NOR Flash Memory /NAND Flash Memory

256 Mbytes

/NOR Flash Memory /NAND Flash Memory /NOR Flash Memory /NAND Flash Memory

Document Number: 002-04988 Rev.*A Page 82 of 198 S6E2C3 Series Peripheral Address Map Start Address End Address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB MainFlash I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/reset control 0x4001_1000 0x4001_1FFF Hardware watchdog timer 0x4001_2000 0x4001_2FFF Software watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-Function Timer unit 0 0x4002_1000 0x4002_1FFF Multi-Function Timer unit 1 0x4002_2000 0x4002_2FFF Multi-Function Timer unit 2 0x4002_3000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base timer 0x4002_6000 0x4002_6FFF Quadrature position/revolution counter 0x4002_7000 0x4002_7FFF A/D converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External interrupt controller 0x4003_1000 0x4003_1FFF Interrupt request batch-read function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF D/A converter 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low voltage detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF USB clock generator 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch counter 0x4003_B000 0x4003_BFFF RTC/port control 0x4003_C000 0x4003_C0FF Low-speed CR prescaler 0x4003_C100 0x4003_C7FF Peripheral clock gating 0x4003_C800 0x4003_CFFF Reserved 0x4003_D000 0x4003_DFFF I2S prescaler 0x4003_E000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External memory interface

Document Number: 002-04988 Rev.*A Page 83 of 198 S6E2C3 Series Start Address End Address Bus Peripherals 0x4004_0000 0x4004_FFFF AHB USB ch 0 0x4005_0000 0x4005_FFFF USB ch 1 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF DSTC register 0x4006_2000 0x4006_BFFF Reserved 0x4006_C000 0x4006_CFFF I2S 0x4006_D000 0x4006_DFFF Reserved 0x4006_E000 0x4006_EFFF SD card I/F 0x4006_F000 0x4006_FFFF GPIO 0x4007_0000 0x4007_FFFF Reserved 0x4008_0000 0x4008_0FFF Programmable-CRC 0x4008_1000 0x41FF_FFFF Reserved 0x200E_0000 0x200E_FFFF Workflash I/F register 0xD000_0000 0xDFFF_FFFF High-speed quad SPI control register

Document Number: 002-04988 Rev.*A Page 84 of 198 S6E2C3 Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings:  INITX = 0 This is the period when the INITX pin is at the L level.  INITX = 1 This is the period when the INITX pin is at the H level.  SPL = 0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL = 1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.  Setting prohibition Prohibition of a setting by specification limitation

Document Number: 002-04988 Rev.*A Page 85 of 198 S6E2C3 Series List of Pin Behavior by Mode State Pin Status Type Function Group Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Deep Standby RTC Mode or Deep Standby Stop mode State Return From Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/interna l input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected Main crystal oscillator input pin/ external main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input Enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/interna l input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/interna l input fixed at 0 Maintain previous state Hi-Z/interna l input fixed at 0 Maintain previous State Main crystal oscillator output pin Hi-Z/ internal input fixed at 0/ or input enable Hi-Z/ internal input fixed at 0 Hi-Z/ internal input fixed at 0 Maintain previous state while oscillator active/ When oscillation stops*1, it will be Hi-Z/ Internal input fixed at 0 C INITX input pin Pull-up/ input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled Pull-up/ Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ input enabled GPIO selected Hi-Z/ input enabled GPIO selected

Document Number: 002-04988 Rev.*A Page 86 of 198 S6E2C3 Series Pin Status Type Function Group Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Deep Standby RTC Mode or Deep Standby Stop mode State Return From Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - F NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z/ WKUP input enabled Maintain previous state Resource other than above selected Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Hi-Z/ internal input fixed at 0 GPIO selected GPIO selected G JTAG selected Hi-Z Pull-up/ input enabled Pull-up/ input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z/ internal input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/ internal input fixed at 0 GPIO selected H JTAG selected Hi-Z Pull-up/ input enabled Pull-up/ input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Setting disabled Setting disabled Setting disabled Hi-Z/Interna l input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/Interna l input fixed at 0 GPIO selected GPIO selected I Resource selected Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Maintain previous state Maintain previous state Hi-Z/Interna l input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected GPIO selected

Document Number: 002-04988 Rev.*A Page 87 of 198 S6E2C3 Series Pin Status Type Function Group Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Deep Standby RTC Mode or Deep Standby Stop mode State Return From Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - J Analog output selected Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Maintain previous state *2 *3 GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected External interrupt enable selected Maintain previous state Maintain previous state Resource other than above selected Hi-Z/interna l input fixed at 0 GPIO selected K External interrupt enable selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Hi-Z/interna l input fixed at 0 GPIO selected L Analog input selected Hi-Z Hi-Z/ internal input fixed at analog input enabled Hi-Z/ internal input fixed at analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/interna l input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected GPIO selected

Document Number: 002-04988 Rev.*A Page 88 of 198 S6E2C3 Series Pin Status Type Function Group Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Deep Standby RTC Mode or Deep Standby Stop mode State Return From Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - M Analog input selected Hi-Z Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled External interrupt enable selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected Resource other than above selected Hi-Z/interna l input fixed at 0 GPIO selected N Analog input selected Hi-Z Hi-Z/ internal input fixed at0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected Resource other than above selected Hi-Z/interna l input fixed at 0 GPIO selected

Document Number: 002-04988 Rev.*A Page 89 of 198 S6E2C3 Series Pin Status Type Function Group Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Deep Standby RTC Mode or Deep Standby Stop mode State Return From Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - O Analog input selected Hi-Z Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected External interrupt enable selected Maintain previous state Resource other than above selected Hi-Z/interna l input fixed at 0 GPIO selected P Analog input selected Hi-Z Hi-Z/ internal input fixed at analog input enabled Hi-Z/ internal input fixed at analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled Hi-Z/ internal input fixed at 0/ analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z/ WKUP input enabled GPIO selected Resource other than above selected Hi-Z/interna l input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected

Document Number: 002-04988 Rev.*A Page 90 of 198 S6E2C3 Series Pin Status Type Function Group Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Deep Standby RTC Mode or Deep Standby Stop mode State Return From Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - Q WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z/ WKUP input enabled WKUP input enabled External interrupt enable selected GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Hi-Z/interna l input fixed at 0 GPIO selected R GPIO selected Hi-Z Hi-Z/ input enabled Hi-Z/ input enabled Maintain previous state Maintain previous state Hi-Z/interna l input fixed at 0 GPIO selected, internal input fixed at 0 Hi-Z/interna l input fixed at 0 GPIO selected USB I/O pin Setting disabled Setting disabled Setting disabled Hi-Z at trans- mission/ input enabled/ internal input fixed at 0 at reception Hi-Z at trans- mission/ input enabled/ internal input fixed at 0 at reception Hi-Z at trans- mission/ input enabled/ internal input fixed at 0 at reception Hi-Z/ input enabled Hi-Z/ input enabled Hi-Z/ input enabled *1: Oscillation is stopped at sub Timer mode, sub CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Maintain previous state at Timer mode. GPIO selected internal input fixed at 0 at RTC mode, Stop mode. *3: Maintain previous state at Timer mode. Hi-Z/internal input fixed at 0 at RTC mode, Stop mode. *4: It shows the case selected by EPFR14.E_SPLC register.

Document Number: 002-04988 Rev.*A Page 91 of 198 S6E2C3 Series List of VBAT Domain Pin Status VBAT Pin Status Type Function Group VBAT Power- On Reset INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Deep Standby RTC mode or Deep Standby Stop mode State Return From Deep Standby Mode State VBAT RTC Mode State Return From VBAT RTC Mode State Power Supply Unstabl e Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 - - ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - - - S GPIO selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Setting prohibition - Sub crystal oscillator input pin/ external sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state Maintain previous state T GPIO selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Setting prohibition - External sub clock input selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Sub crystal oscillator output pin Hi-Z/ internal input fixed at or input enable Maintain previous state Maintain previous state Maintain previous state Maintain previous state/ When oscillation stops, Hi-Z* Maintain previous state/ When oscillation stops, Hi-Z* Maintain previous state/ When oscillation stops, Hi-Z* Maintain previous state/ When oscillation stops, Hi-Z* Maintain previous state Maintain previous state Maintain previous state U Resource selected Hi-Z Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected *: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous state. When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop mode

Document Number: 002-04988 Rev.*A Page 92 of 198 S6E2C3 Series 12. Electrical Characteristics

12.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1,*2 VCC VSS - 0.5 VSS + 6.5 V Power supply voltage (for USB) *1,*3 USBVCC0 VSS - 0.5 VSS + 6.5 V Power supply voltage (for USB) *1,*3 USBVCC1 VSS - 0.5 VSS + 6.5 V Power supply voltage (VBAT) *1 ,*4 VBAT VSS - 0.5 VSS + 6.5 V Analog power supply voltage *1 ,*5 AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage *1 ,*5 AVRH VSS - 0.5 VSS + 6.5 V Input voltage *1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V Except for USB pin VSS - 0.5 USBVCC0 + 0.5 (≤ 6.5 V) V USB ch 0 pin VSS - 0.5 USBVCC1 + 0.5 (≤ 6.5 V) V USB ch 1 pin VSS - 0.5 VSS + 6.5 V 5V tolerant Analog pin input voltage *1 VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5 V) V Output voltage *1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V L level maximum output current *6 IOL - 10 mA 4 mA type 20 mA 8 mA type 10 mA 10 mA type 20 mA 12 mA type 22.4 mA I2C Fm+ L level average output current *7 IOLAV - 4 mA 4 mA type 8 mA 8 mA type 10 mA 10 mA type 12 mA 12 mA type 20 mA I2C Fm+ L level total maximum output current ∑IOL - 100 mA L level total maximum output current*8 ∑IOLAV - 50 mA H level maximum output current *6 IOH - - 10 mA 4 mA type -20 mA 8 mA type - 20 mA 10 mA type - 20 mA 12 mA type H level average output current *7 IOHAV - - 4 mA 4 mA type -8 mA 8 mA type - 10 mA 10 mA type - 12 mA 12 mA type H level total maximum output current ∑IOH - - 100 mA H level total average output current *8 ∑IOHAV - - 50 mA Power consumption PD - 200 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: USBVCC0, USBVCC1 must not drop below VSS - 0.5 V. *4: VBAT must not drop below VSS - 0.5 V. *5: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100-ms period.

Document Number: 002-04988 Rev.*A Page 93 of 198 S6E2C3 Series *8: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100-ms period. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

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12.2 Recommended Operating Conditions

Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 2.7 *7 5.5 V Power supply voltage (for USB ch 0) USBVCC0 - 3.0 3.6 ( ≤VCC) V 2.7 5.5 ( ≤VCC) *2 Power supply voltage (for USB ch 1) USBVCC1 - 3.0 3.6 ( ≤VCC) V 2.7 5.5 ( ≤VCC) *4 Power supply voltage (VBAT) VBAT - 1.65 5.5 V Analog power supply voltage AVCC - 2.7 5.5 V AVCC = VCC Analog reference voltage AVRH - *6 AVCC V AVRL - AVSS AVSS V Operating temperature Junction temperature TJ - - 40 + 125 °C Ambient temperature TA - -40 *5 °C *1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0) *2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80) *3: When P83/UDP1 and P82/UDM1 pins are used as USB (UDP1, UDM1) *4: When P83/UDP1 and P82/UDM1 pins are used as GPIO (P83, P82) *5: The maximum temperature of the ambient temperature (T A) can guarantee a range that does not exceed the junction temperature (TJ). The calculation formula of the ambient temperature (TA) is: TA (Max) = TJ(Max) - Pd(Max) × θJA Pd: Power dissipation (W) θJA: Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage *6: The minimum value of analog reference voltage depends on the value of compare clock cycle (tCCK). See 12.5. 12-bit A/D Converter for the details. *7: For the voltage range between V cc(min) and the low voltage detection reset (VDH), the MCU must be clocked from either the High-speed CR or the low-speed CR.”

Document Number: 002-04988 Rev.*A Page 95 of 198 S6E2C3 Series Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table 12-1 Table for Package Thermal Resistance and Maximum Permissible Power Package Printed Circuit Board Thermal Resistanc e θJA (°C/W) Maximum Permissible Power (mW) TA = +85°C TA = +105°C LQS144 (0.5-mm pitch) Single-layere d both sides 48 833 417 4 layers 33 1212 606 LQP176 (0.5-mm pitch) Single-layere d both sides 45 889 444 4 layers 31 1290 645 LQQ216 (0.4-mm pitch) Single-layere d both sides 46 870 435 4 layers 32 1250 625 LBE192 (0.8-mm pitch) Single-layere d both sides - - - 4 layers 35 1143 571 WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. 3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. 4. Users considering application outside the listed conditions are advised to contact their representatives beforehand.

Document Number: 002-04988 Rev.*A Page 96 of 198 S6E2C3 Series Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: L level output current IOH: H level output current VOL:L level output voltage VOH:H level output voltage ICC is the current drawn by the device. It can be analyzed as follows. ICC = ICC (INT) + ΣICC (IO) ICC (INT): Current drawn by internal logic and memory, etc. through the regulator ΣICC (IO): Sum of current (I/O switching current) drawn by the output pin For ICC (INT), it can be anticipated by (1) Current Rating in 12.3. DC Characteristics (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC (IO) = (CINT + CEXT) × VCC × fSW CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Symbol Conditions Capacitance Value Pin internal load capacitance CINT 4 mA type 1.93 pF 8 mA type 3.45 pF 12 mA type 3.42 pF Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself: Measure current value ICC (Typ) at normal temperature (+25°C). Add maximum leakage current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC (Typ) + ICC (leak_max) Parameter Symbol Conditions Current Value Maximum leakage current at operating ICC (leak_max) TJ = +125°C 79.2 mA TJ = +105°C 39.4 mA TJ = +85°C 26.5 mA

Document Number: 002-04988 Rev.*A Page 97 of 198 S6E2C3 Series Current Explanation Diagram A V ・・・ ・・・ ・・・ V A A Regulator Logic Flash RAM ICC ICC (INT) ΣICC (IO) IOL VOL VOH IOH ICC (IO) Chip VCC CEXT Pd=VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH)) ICC=ICC (INT)＋ΣICC (IO)

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12.3 DC Characteristics

12.3.1 Current Rating

Table 12-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Enabled) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation *7,*8 (PLL)

200 MHz 117 224 mA

192 MHz 113 219 mA

180 MHz 106 211 mA

160 MHz 95 197 mA

144 MHz 86 186 mA

120 MHz 73 169 mA

100 MHz 61 155 mA

80 MHz 50 140 mA

60 MHz 39 126 mA

40 MHz 27 112 mA

20 MHz 16 97 mA

8 MHz 8.7 88.9 mA 4 MHz 6.4 86.1 mA

200 MHz 71 168 mA

192 MHz 68 165 mA

180 MHz 64 159 mA

160 MHz 58 151 mA

144 MHz 52 144 mA

120 MHz 44 134 mA

100 MHz 38 126 mA

80 MHz 31 117 mA

60 MHz 24 109 mA

40 MHz 17 100 mA

20 MHz 10 91 mA

8 MHz 6.3 86.1 mA 4 MHz 5.0 84.5 mA *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 1) *6: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *7: Firmware being executed during data collection for this table is not being accessed from the MainFlash memory.” *8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 99 of 198 S6E2C3 Series Table 14-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation *7,*8 (PLL)

200 MHz 128 236 mA

192 MHz 123 230 mA

180 MHz 116 221 mA

160 MHz 102 205 mA

144 MHz 93 193 mA

120 MHz 79 175 mA

100 MHz 67 161 mA

80 MHz 54 145 mA

60 MHz 42 130 mA

40 MHz 30 115 mA

20 MHz 17 99 mA

8 MHz 9.2 90.0 mA 4 MHz 6.7 86.9 mA

200 MHz 74 170 mA

192 MHz 71 167 mA

180 MHz 67 162 mA

160 MHz 59 152 mA

144 MHz 53 145 mA

120 MHz 45 135 mA

100 MHz 39 127 mA

80 MHz 32 118 mA

60 MHz 25 110 mA

40 MHz 18 101 mA

20 MHz 11 92 mA

8 MHz 6.5 86.8 mA 4 MHz 5.1 85.0 mA *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 0) *6: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) *7: With data access to a MainFlash memory. *8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 100 of 198 S6E2C3 Series Table 12-3 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation *6,*7 (PLL)

72 MHz 71 161 mA

60 MHz 62 150 mA

48 MHz 51 138 mA

36 MHz 40 125 mA

24 MHz 29 112 mA

12 MHz 17 98 mA

8 MHz 13 93 mA

4 MHz 8.4 88.5 mA

72 MHz 46 132 mA

60 MHz 41 125 mA

48 MHz 34 118 mA

36 MHz 27 110 mA

24 MHz 20 102 mA

12 MHz 12 93 mA

8 MHz 9.4 89.7 mA 4 MHz 6.5 86.4 mA *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000) *6: With data access to a MainFlash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 101 of 198 S6E2C3 Series Table 12-4 Typical and Maximum Current Consumption in Normal Operation (Other Than PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation *6, *7 (main oscillation) *5 4 MHz 4.7 84.9 mA When all peripheral clocks are on 3.9 83.8 mA When all peripheral clocks are off Normal operation (built-in High-speed CR) *5 4 MHz 3.0 83.2 mA When all peripheral clocks are on 2.1 82.0 mA When all peripheral clocks are off Normal operation *6, *8 (sub oscillation) *5 32 kHz 0.78 80.37 mA When all peripheral clocks are on 0.77 80.36 mA When all peripheral clocks are off Normal operation (built-in low-speed CR) *5 100 kHz 0.81 80.39 mA When all peripheral clocks are on 0.78 80.38 mA When all peripheral clocks are off *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000) *6: With data access to a MainFlash memory. *7: When using the crystal oscillator of 4 kHz (including the current consumption of the oscillation circuit) *8: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 102 of 198 S6E2C3 Series Table 12-5 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation*5 (PLL)

200 MHz 88 188 mA

192 MHz 85 184 mA

180 MHz 80 178 mA

160 MHz 72 164 mA

144 MHz 65 156 mA

120 MHz 55 144 mA

100 MHz 47 134 mA

80 MHz 38 124 mA

60 MHz 30 114 mA

40 MHz 21 104 mA

20 MHz 12 93 mA

8 MHz 7.4 87.2 mA 4 MHz 5.8 85.2 mA

200 MHz 44 134 mA

192 MHz 42 132 mA

180 MHz 40 129 mA

160 MHz 36 123 mA

144 MHz 33 119 mA

120 MHz 28 113 mA

100 MHz 24 108 mA

80 MHz 20 103 mA

60 MHz 16 98 mA

40 MHz 12 93 mA

20 MHz 7.6 87.6 mA 8 MHz 5.2 84.7 mA 4 MHz 4.4 83.7 mA *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 103 of 198 S6E2C3 Series Table 12-6 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation*5 (PLL)

72 MHz 45 130 mA

60 MHz 38 122 mA

48 MHz 31 114 mA

36 MHz 24 106 mA

24 MHz 18 99 mA

12 MHz 11 91 mA

8 MHz 8.6 88.3 mA 4 MHz 6.3 85.7 mA

72 MHz 20 103 mA

60 MHz 18 99 mA

48 MHz 15 96 mA

36 MHz 12 93 mA

24 MHz 9.1 89.3 mA 12 MHz 6.5 86.1 mA 8 MHz 5.5 84.9 mA 4 MHz 4.6 83.8 mA *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 104 of 198 S6E2C3 Series Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (Other Than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation*5 (main oscillation) 3.4 82.6 mA When all peripheral clocks are on 2.5 81.7 mA When all peripheral clocks are off Sleep operation (built-in High-speed CR) 2.5 81.7 mA When all peripheral clocks are on 1.7 80.9 mA When all peripheral clocks are off Sleep operation*6 (sub oscillation) 32 kHz 0.75 79.97 mA When all peripheral clocks are on 0.74 79.96 mA When all peripheral clocks are off Sleep operation (built-in low-speed CR) 100 kHz 0.79 80.01 mA When all peripheral clocks are on 0.76 79.98 mA When all peripheral clocks are off *1: TA = +25°C, VCC = 3.3 V *2: TJ = +125°C, VCC = 5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 105 of 198 S6E2C3 Series Table 12-8 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode Parameter Symbol Pin Name Conditions Frequency Value Unit Remarks Typ*1 Max*2 Power supply current ICCH VCC Stop mode - TA = +25°C - 27.03 mA *3, *4 TA = +85°C - 39.92 mA *3, *4 TA = +105°C ICCT Timer mode*5 (main oscillation) 4 MHz TA = +25°C - 27.87 mA *3, *4 TA = +85°C - 40.76 mA *3, *4 TA = +105°C Timer mode (built-in High-speed CR) TA = +25°C - 27.42 mA *3, *4 TA = +85°C - 40.31 mA *3, *4 TA = +105°C Timer mode*6 (sub oscillation) 32 kHz TA = +25°C - 27.04 mA *3, *4 TA = +85°C - 39.93 mA *3, *4 TA = +105°C Timer mode (built-in Low-speed CR) 100 kHz TA = +25°C - 27.05 mA *3, *4 TA = +85°C - 39.94 mA *3, *4 TA = +105°C ICCR RTC mode*6 (sub oscillation) 32 kHz TA = +25°C - 27.04 mA *3, *4 TA = +85°C - 39.93 mA *3, *4 TA = +105°C *1: VCC = 3.3V *2: VCC = 5.5V *3: When all ports are fixed *4: When LVD is off *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 106 of 198 S6E2C3 Series Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT Parameter Symbol Pin Name Conditions Frequency Value Unit Remarks Typ*1 Max*2 Power supply current ICCHD VCC Deep Standby Stop mode (When RAM is off) 96 248 µA *3, *4 TA = +25°C - 3009 µA *3, *4 TA = +85°C - 3889 µA *3, *4 TA = +105°C Deep Standby Stop mode (When RAM is on) 106 259 µA *3, *4 TA = +25°C - 3020 µA *3, *4 TA = +85°C - 3900 µA *3, *4 TA = +105°C ICCRD Deep Standby RTC mode*6 (When RAM is off) 32 kHz 96 248 µA *3, *4 TA = +25°C - 3009 µA *3, *4 TA = +85°C - 3889 µA *3, *4 TA = +105°C Deep Standby RTC mode*6 (When RAM is on) 106 259 µA *3, *4 TA = +25°C - 3020 µA *3, *4 TA = +85°C - 3900 µA *3, *4 TA = +105°C ICCVBAT VBAT RTC stop TA = +25°C TA = +85°C TA = +105°C RTC operation*6 1.0 1.8 µA *3, *4 TA = +25°C - 3.2 µA *3, *4 TA = +85°C - 5.1 µA *3, *4 TA = +105°C *1: VCC = 3.3 V *2: VCC = 5.5 V *3: When all ports are fixed *4: When LVD is off *5: When sub oscillation is off *6: When using the crystal oscillator of 32 MHz (including the current consumption of the oscillation circuit)

Document Number: 002-04988 Rev.*A Page 107 of 198 S6E2C3 Series Table 12-10 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/erase Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC At operation - 4 7 µA For occurrence of interrupt MainFlash memory write/erase current ICCFLASH At write/erase - 13.4 15.9 mA *1 *1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power supply current (ICC). Peripheral Current Dissipation Clock system Peripheral Unit Frequency (MHz) Unit Remarks 50 100 200 HCLK GPIO All ports 0.39 0.81 1.56 mA DMAC - 0.99 1.97 3.82 DSTC - 0.73 1.49 2.86 External bus I/F - 0.25 0.48 0.97 SD card I/F - 0.74 1.47 2.90 USB 1 ch 0.48 0.95 1.89 I2S - 0.51 1.02 1.99 High-Speed Quad SPI - 0.48 0.97 1.49 Programmable CRC - 0.05 0.10 0.22 PCLK1 Base timer 4 ch 0.21 0.42 0.83 mA Multi-functional timer/PPG 1 unit/4 ch 0.83 1.65 3.25 Quadrature position/revolution counter 1 unit 0.07 0.13 0.27 A/D converter 1 unit 0.31 0.60 1.17 PCLK2 Multi-function serial 1 ch 0.41 0.81 - mA

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12.3.2 Pin Characteristics

(VCC = USBVCC0 = USBVCC1 = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max H level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 - VCC×0.8 - VCC + 0.3 V MADATAxx VCC > 3.0 V, VCC ≤ 3.6 V, 2.4 - VCC + 0.3 V At External Bus

5 V tolerant input

pin - VCC×0.8 - VSS + 5.5 V Input pin doubled as I2C Fm+ - VCC×0.7 - VSS + 5.5 V TTL Schmitt input pin - 2.0 - VCC+0.3 V L level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 - VSS - 0.3 - VCC×0.2 V pin - VSS - 0.3 - VCC×0.2 V Input pin doubled as I2C Fm+ - VSS - VCC×0.3 V TTL Schmitt input pin - VSS - 0.3 - 0.8 V H level output voltage VOH 4 mA type VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 2 mA 8 mA type VCC ≥ 4.5 V, IOH = - 8 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 4 mA 10 mA type VCC ≥ 4.5 V, IOH = - 10 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 8 mA 12 mA type VCC ≥ 4.5 V, IOH = - 12 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 8 mA The pin doubled as USB I/O USBVCC ≥ 4.5 V, IOH = - 20.5 mA USBVCC - 0.4 - USBVCC V *1 USBVCC < 4.5 V, IOH = - 13.0 mA The pin doubled as I2C Fm+ VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V At GPIO VCC < 4.5 V, IOH = - 3 mA

Document Number: 002-04988 Rev.*A Page 109 of 198 S6E2C3 Series Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max L level output voltage VOL 4 mA type VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA 8 mA type VCC ≥ 4.5 V, IOL = 8 mA VSS - 0.4 V VCC < 4.5 V, IOL = 4 mA 10 mA type VCC ≥ 4.5 V, IOL = 10 mA VSS - 0.4 V VCC < 4.5 V, IOL = 8 mA 12 mA type VCC ≥ 4.5 V, IOL = 12 mA VSS - 0.4 V VCC < 4.5 V, IOL = 8 mA The pin doubled as USB I/O USBVCC ≥ 4.5 V, IOL = 18.5 mA VSS - 0.4 V *1 USBVCC < 4.5 V, IOL = 10.5 mA The pin doubled as I2C Fm+ VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V At GPIO VCC < 4.5 V, IOL = 3 mA VCC ≤ 4.5 V, IOL = 20 mA At I2C Fm+ Input leak current IIL - - - 5 - + 5 μA Pull-up resistor value RPU Pull-up pin VCC ≥ 4.5 V 25 50 100 kΩ VCC < 4.5 V 30 80 200 Input capacitance CIN Other than VCC, USBVCC0, USBVCC1, VBAT, VSS, AVCC, AVSS, AVRH - - 5 15 pF *1: USBVcc0 and USBVcc1 are described as USBVcc.

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12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = -40C to +105C) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥4.5 V 4 48 MHz When crystal oscillator is connected VCC < 4.5 V 4 20 VCC ≥4.5 V 4 48 MHz When using external clock VCC < 4.5 V 4 20 Input clock cycle tCYLH VCC ≥4.5 V 20.83 250 ns When using external clock VCC < 4.5 V 50 250 Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rise time and fall time tCF, tCR - - 5 ns When using external clock Internal operating clock *1 frequency fCC - - - 200 MHz Base clock (HCLK/FCLK) fCP0 - - - 100 MHz APB0bus clock *2 fCP1 - - - 200 MHz APB1bus clock *2 fCP2 - - - 100 MHz APB2bus clock *2 Internal operating clock *1 cycle time tCYCC - - 5 - ns Base clock (HCLK/FCLK) tCYCP0 - - 10 - ns APB0bus clock *2 tCYCP1 - - 5 - ns APB1bus clock *2 tCYCP2 - - 10 - ns APB2bus clock *2 *1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in FM4 Family Peripheral Manual Main Part (002-04856). *2: For more about each APB bus to which each peripheral is connected, see 8. Block Diagram in this data sheet.

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12.4.2 Sub Clock Input Characteristics

(VBAT = 1.65V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Input frequency 1/tCYLL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected * - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock *: For more information about crystal oscillator, see Sub crystal oscillator in 7. Handling Devices.

12.4.3 Built-In CR Oscillation Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH TJ = - 20°C to + 105°C 3.92 4 4.08 MHz When trimming *1 TJ = - 40°C to + 125°C 3.88 4 4.12 TJ = - 40°C to + 125°C 3 4 5 When not trimming Frequency stabilization time tCRWT - - - 30 μs *2 *1: In the case of using the values in CR trimming area of flash memory at shipment for frequency/temperature trimming *2: This is the time to stabilize the frequency of the High-speed CR clock after setting trimming value. During this period, it is able to use the High-speed CR clock as a source clock. Built-In Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz 0.8 × VBAT t CYLL 0.8 × VBAT 0.2 × VBAT 0.2 × VBAT 0.8 × VBAT P WL P WH X0A

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12.4.4 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (lock up time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 13 - 100 multiplier PLL macro oscillation clock frequency fPLLO 200 - 400 MHz Main PLL clock frequency*2 fCLKPLL - - 200 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856).

12.4.5 Operating Conditions of USB PLL・I2S PLL (in the Case of Using Main Clock for Input Clock of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (lock up time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 13 - 100 multiplier PLL macro oscillation clock frequency fPLLO 200 - 400 MHz USB

384 MHz I2S

USB clock frequency *2 fCLKPLL - - 50 MHz After the M frequency division I2S clock frequency *3 fCLKPLL - - 12.288 MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes *2: For more information about USB/Ethernet clock, see Chapter 2-2: USB/Ethernet Clock Generation in FM4 Family Peripheral Manual Communication Macro Part (002-04862). *3: For more information about I2S clock, see Chapter 7-1: I2S Clock Generation in FM4 Family Peripheral Manual Communication Macro Part (002-04862).

Document Number: 002-04988 Rev.*A Page 113 of 198 S6E2C3 Series 12.4.6 Operating Conditions of Main PLL (in the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (lock up time) tLOCK 100 - - µs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 50 - 95 multiplier PLL macro oscillation clock frequency fPLLO 190 - 400 MHz Main PLL clock frequency *2 fCLKPLL - - 200 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part (002-04856). Note: − The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the Main PLL.

12.4.7 Reset Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Reset input time tINITX INITX - 500 - ns

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12.4.8 Power-On Reset Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Power supply rise time TVCCR VCC 0 - ms Power supply shut down time Toff 1 - ms Time until releasing Power-on reset Tprt 0.33 0.60 ms 0.2V VDH_minimum VCC_minimum Tprt Internal RST VCC CPU Operation start RST Active Release TVCCR 0.2V 0.2V Toff Glossary  VCC_minimum: minimum VCC of recommended operating conditions  VDH_minimum: minimum release voltage of low-voltage detection reset See 12.8. Low-Voltage Detection Characteristics.

12.4.9 GPIO Output Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Output frequency tPCYCLE Pxx* VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz *: GPIO is a target. Pxx tPCYCLE

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12.4.10 External Bus Timing

External Bus Clock Output Characteristics Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Output frequency tCYCLE MCLKOUT *1 - 50 *2 MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral Manual Main Part (002-04856). *2: Generate MCLKOUT at setting more than four divisions when the AHB bus clock exceeds 100 MHz. External Bus Signal I/O Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V 0.8 × Vcc0.8 × Vcc tCYCLE VIH VIL VIL VIH VOH VOL VOL VOH MCLK Input signal

Document Number: 002-04988 Rev.*A Page 116 of 198 S6E2C3 Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MOEX Minimum pulse width tOEW MOEX - MCLK×n-3 - ns MCSX↓→Address output delay time tCSL – AV MCSX[7: 0], MOEX↑→Address hold time tOEH - AX MOEX, MAD[24: 0] - 0 MCLK×m+9 ns MCSX↓→ MOEX↓delay time tCSL - OEL MOEX, MCSX[7: 0] - MCLK×m-9 MCLK×m+9 ns MOEX↑→ MCSX↑time tOEH - CSH - 0 MCLK×m+9 ns MCSX↓→ MDQM↓delay time tCSL - RDQML MCSX, MDQM[3: 0] - MCLK×m-9 MCLK×m+9 ns Data set up→MOEX↑ time tDS - OE MOEX, MADATA[31: 0] - 20 - ns MOEX↑→ Data hold time tDH - OE MOEX, MADATA[31: 0] - 0 - ns MWEX Minimum pulse width tWEW MWEX - MCLK×n-3 - ns MWEX↑→Address output delay time tWEH - AX MWEX, MAD[24: 0] - 0 MCLK×m+9 ns MCSX↓→ MWEX↓delay time tCSL - WEL MWEX, MCSX[7: 0] - MCLK×n-9 MCLK×n+9 ns MWEX↑→ MCSX↑delay time tWEH - CSH - 0 MCLK×m+9 ns MCSX↓→ MDQM↓delay time tCSL-WDQML MCSX, MDQM[3: 0] - MCLK×n-9 MCLK×n+9 ns MCSX↓→ Data output time tCSL-DX MCSX, MADATA[31: 0] - MCLK-9 MCLK+9 ns MWEX↑→ Data hold time tWEH - DX MWEX, MADATA[31: 0] - 0 MCLK×m+9 ns Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)

Document Number: 002-04988 Rev.*A Page 117 of 198 S6E2C3 Series Invalid Address tCSL-OEL tCSL-AV RD Address WD tDH-OEtDS-OE tWEH-DX tOEW tOEH-AX tOEH-CSH tWEW tCYCLE tCSL-WEL tCSL-AV tWEH-CSH tWEH-AX tCSL-WDQMLtCSL-RDQML tCSL-DX MCLK MCSX[7: 0] MAD[24: 0] MDQM[1: 0] MWEX MADATA[15: 0] MOEX

Document Number: 002-04988 Rev.*A Page 118 of 198 S6E2C3 Series Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Address delay time tAV MCLK, MAD[24: 0] - 1 9 ns MCSX delay time tCSL MCLK, MCSX[7: 0] - 1 9 ns tCSH - 1 9 ns MOEX delay time tREL MCLK, MOEX - 1 9 ns tREH - 1 9 ns Data set up →MCLK↑ time tDS MCLK, MADATA[31: 0] - 19 - ns MCLK↑→ Data hold time tDH MCLK, MADATA[31: 0] - 0 - ns MWEX delay time tWEL MCLK, MWEX - 1 9 ns tWEH - 1 9 ns MDQM[1: 0] delay time tDQML MCLK, MDQM[3: 0] - 1 9 ns tDQMH - 1 9 ns MCLK↑→ Data output time tODS MCLK, MADATA[31: 0] - MCLK+1 MCLK+18 ns MCLK↑→ Data hold time tOD MCLK, MADATA[31: 0] - 1 18 ns Note: − When the external load capacitance CL = 30 pF Invalid tDQML tREH Address tCSL tAV tREL RD Address WD tDQMH tWEHtWEL tDHtDS tOD tAV tCSH tCYCLE tDQML tDQMH tODS MCLK MCSX[7: 0] MAD[24: 0] MOEX MWEX MADATA[31: 0] MDQM[3: 0]

Document Number: 002-04988 Rev.*A Page 119 of 198 S6E2C3 Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Multiplexed address delay time tALE-CHMADV MALE, MAD[24: 0] - 0 10 ns Multiplexed address hold time tCHMADH - MCLK×n+0 MCLK×n+10 ns Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16) MCLK MCSX[7: 0] MALE MOEX MWEX MADATA[31: 0] MAD [24: 0] MDQM [3: 0]

Document Number: 002-04988 Rev.*A Page 120 of 198 S6E2C3 Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK, MALE - 1 9 tCHAH - 1 9 MCLK↑→Multiplexed address delay time tCHMADV MCLK, MADATA[31: 0] - 1 tOD ns MCLK↑→Multiplexed data output time tCHMADX - 1 tOD ns Note: − When the external load capacitance CL = 30 pF MCLK MCSX[7: 0] MALE MOEX MWEX MADATA[31: 0] MAD [24: 0] MDQM [3: 0]

Document Number: 002-04988 Rev.*A Page 121 of 198 S6E2C3 Series NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MNREX Min pulse width tNREW MNREX - MCLK×n-3 - ns Data set up →MNREX↑time tDS – NRE MNREX, MADATA[31: 0] - 20 - ns MNREX↑→ Data hold time tDH – NRE MNREX, MADATA[31: 0] - 0 - ns MNALE↑→ MNWEX delay time tALEH - NWEL MNALE, MNWEX - MCLK×m-9 MCLK×m+9 ns MNALE↓→ MNWEX delay time tALEL - NWEL MNALE, MNWEX - MCLK×m-9 MCLK×m+9 ns MNCLE↑→ MNWEX delay time tCLEH - NWEL MNCLE, MNWEX - MCLK×m-9 MCLK×m+9 ns MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX - 0 MCLK×m+9 ns MNWEX Min pulse width tNWEW MNWEX - MCLK×n-3 - ns MNWEX↓→ Data output time tNWEL – DV MNWEX, MADATA[31: 0] - -9 9 ns MNWEX↑→ Data hold time tNWEH – DX MNWEX, MADATA[31: 0] - 0 MCLK×m+9 ns Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16) NAND Flash Read MCLK MNREX MADATA[31: 0] Read

Document Number: 002-04988 Rev.*A Page 122 of 198 S6E2C3 Series NAND Flash Address Write NAND Flash Command Write MCLK MNALE MNCLE MADATA[31: 0] MNWEX Write Write MCLK MNALE MNCLE MADATA[31: 0] MNWEX

Document Number: 002-04988 Rev.*A Page 123 of 198 S6E2C3 Series External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MCLK↑ MRDY input setup time tRDYI MCLK, MRDY - 19 - ns  When RDY is input  When RDY is released

• · · Over 2cycle tRDYI 2 cycles tRDYI 0.5×VCC MCLK Original MOEX MWEX MRDY MCLK Extended MOEX MWEX MRDY

Document Number: 002-04988 Rev.*A Page 124 of 198 S6E2C3 Series SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Unit Unit Remarks Min Max Output frequency tCYCSD MSDCLK - - 50 MHz Address delay time tAOSD MSDCLK, MAD[15: 0] - 2 12 ns MSDCLK↑→ Data output delay time tDOSD MSDCLK, MADATA[31: 0] - 2 12 ns MSDCLK↑→ Data output Hi-Z time tDOZSD MSDCLK, MADATA[31: 0] - 2 19.5 ns MDQM[3: 0] delay time tWROSD MSDCLK, MDQM[1: 0] - 1 12 ns MCSX delay time tMCSSD MSDCLK, MCSX8 - 2 12 ns MRASX delay time tRASSD MSDCLK, MRASX - 2 12 ns MCASX delay time tCASSD MSDCLK, MCASX - 2 12 ns MSDWEX delay time tMWESD MSDCLK, MSDWEX - 2 12 ns MSDCKE delay time tCKESD MSDCLK, MSDCKE - 2 12 ns Data set up time tDSSD MSDCLK, MADATA[31: 0] - 19 - ns Data hold time tDHSD MSDCLK, MADATA[31: 0] - 0 - ns Note: − When the external load capacitance CL = 30 pF

Document Number: 002-04988 Rev.*A Page 125 of 198 S6E2C3 Series RD WD MSDCLK MDQM[1:0] MCSX MRASX MCASX MSDWEX MSDCKE MADATA[15:0] Address MADATA[15:0] MAD[24:0] tCYCSD tAOSD tWROSD tMCSSD tRASSD tCASSD tMWESD tCKESD tDOSD tDOZSD tDSSD tDHSD SDRAM Access

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12.4.11 Base Timer Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the base timer is connected, see 8. Block Diagram in this data sheet. tTIWH VIHS VIHS VILS VILS tTIWL tTRGH VIHS VIHS VILS VILS tTRGL ECK TIN TGIN

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12.4.12 CSIO (SPI) Timing

Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 128 of 198 S6E2C3 Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04988 Rev.*A Page 129 of 198 S6E2C3 Series Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 130 of 198 S6E2C3 Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI tSHSL tSLSH VIH tFtR VIH VOH VILVIL VIL VOL VIH VIL VIH VIL tSHOVE tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04988 Rev.*A Page 131 of 198 S6E2C3 Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 132 of 198 S6E2C3 Series MS bit = 0 MS bit = 1 * Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04988 Rev.*A Page 133 of 198 S6E2C3 Series Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number; for example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 134 of 198 S6E2C3 Series MS bit = 0 MS bit = 1 tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI tSHSLtR tSLSH tF tSLOVE VIL VILVIL VIH VIHVIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04988 Rev.*A Page 135 of 198 S6E2C3 Series When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓ setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↓→SCK↓ setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 40 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 136 of 198 S6E2C3 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04988 Rev.*A Page 137 of 198 S6E2C3 Series When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓ setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↓→SCK↓ setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 40 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 138 of 198 S6E2C3 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SOT (SPI=0) SOT (SPI=1) SCK input SOT (SPI=0) SOT (SPI=1) SCS input SCS output SCK output

Document Number: 002-04988 Rev.*A Page 139 of 198 S6E2C3 Series When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↓ setup time tCSSI Internal shift clock operation SCK↑→SCS↓ hold time tCSHI ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↑→SCK↓ setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 140 of 198 S6E2C3 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04988 Rev.*A Page 141 of 198 S6E2C3 Series When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Units Min Max Min Max SCS↑→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↓hold time tCSHI ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↑→SCK↑setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↓hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 142 of 198 S6E2C3 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04988 Rev.*A Page 143 of 198 S6E2C3 Series High-Speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 25 - 25 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 10 + 10 - 10 + 10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 14 - 12.5 - ns 12.5* SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 5 - 2tCYCP - 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 002-04988 Rev.*A Page 144 of 198 S6E2C3 Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04988 Rev.*A Page 145 of 198 S6E2C3 Series High-Speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 25 - 25 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 10 + 10 - 10 + 10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 14 - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 5 - 2tCYCP - 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 002-04988 Rev.*A Page 146 of 198 S6E2C3 Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI tSHSL tSLSH VIH tFtR VIH VOH VILVIL VIL VOL VIH VIL VIH VIL tSHOVE tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04988 Rev.*A Page 147 of 198 S6E2C3 Series High-Speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 25 - 25 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 10 + 10 - 10 + 10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 14 - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 5 - 2tCYCP - 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)

Document Number: 002-04988 Rev.*A Page 148 of 198 S6E2C3 Series MS bit = 0 MS bit = 1 * Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04988 Rev.*A Page 149 of 198 S6E2C3 Series High-Speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 25 - 25 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 10 + 10 - 10 + 10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 14 - 12.5 - ns 12.5* SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 5 - 2tCYCP - 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 − When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)

Document Number: 002-04988 Rev.*A Page 150 of 198 S6E2C3 Series MS bit = 0 MS bit = 1 tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI tSHSLtR tSLSH tF tSLOVE VIL VILVIL VIH VIHVIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04988 Rev.*A Page 151 of 198 S6E2C3 Series When Using High-Speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓ setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI ( *2)+0 ( *2)+20 ( *2)+0 ( *2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↓→SCK↓ setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 152 of 198 S6E2C3 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04988 Rev.*A Page 153 of 198 S6E2C3 Series When Using High-Speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC≥ 4.5 V Unit Min Min Min Max SCS↓→SCK↓ setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI ( *2)+0 ( *2)+20 ( *2)+0 ( *2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↓→SCK↑ setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 154 of 198 S6E2C3 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS intpu SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04988 Rev.*A Page 155 of 198 S6E2C3 Series When Using High-Speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↓ setup time tCSSI Internal shift clock operation SCK↑→SCS↓ hold time tCSHI ( *2)+0 ( *2)+20 ( *2)+0 ( *2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↑→SCK↓ setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 156 of 198 S6E2C3 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04988 Rev.*A Page 157 of 198 S6E2C3 Series When Using High-Speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓ setup time tCSSI Internal shift clock operation SCK↑→SCS↓ hold time tCSHI ( *2)+0 ( *2)+20 ( *2)+0 ( *2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↑→SCK↑ setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. − For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04988 Rev.*A Page 158 of 198 S6E2C3 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04988 Rev.*A Page 159 of 198 S6E2C3 Series External clock (EXT = 1): When in Asynchronous Mode Only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Value Unit Remarks Min Max Serial clock L pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK fall time tF - 5 ns SCK rise time tR - 5 ns tSHSL VIL VIL VIL VIH VIH VIH tR tFtSLSH SCK

Document Number: 002-04988 Rev.*A Page 160 of 198 S6E2C3 Series

12.4.13 External Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTGx - 2tCYCP *1 - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP *1 - ns Waveform generator INT00 to INT31, NMIX - 2tCYCP + 100*1 - ns External interrupt, NMI 500*2 - ns WKUPx - 500*3 - ns Deep standby wake up 1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in Timer mode. For more information about the APB bus number to which the A/D converter, multi-function timer, and external interrupt are connected, see 8. Block Diagram in this data sheet. 2: When in Stop mode, in Timer mode 3: When in Deep Standby RTC mode, in Deep Standby Stop mode

Document Number: 002-04988 Rev.*A Page 161 of 198 S6E2C3 Series

12.4.14 Quadrature Position/Revolution Counter Timing

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40°C to +105°C) Parameter Symbol Conditions Value Unit Min Max AIN pin H width tAHL - 2tCYCP* - ns AIN pin L width tALL - BIN pin H width tBHL - BIN pin L width tBLL - BIN rise time from AIN pin H level tAUBU PC_Mode2 or PC_Mode3 AIN fall time from BIN pin H level tBUAD PC_Mode2 or PC_Mode3 BIN fall time from AIN pin L level tADBD PC_Mode2 or PC_Mode3 AIN rise time from BIN pin L level tBDAU PC_Mode2 or PC_Mode3 AIN rise time from BIN pin H level tBUAU PC_Mode2 or PC_Mode3 BIN fall time from AIN pin H level tAUBD PC_Mode2 or PC_Mode3 AIN fall time from BIN pin L level tBDAD PC_Mode2 or PC_Mode3 BIN rise time from AIN pin L level tADBU PC_Mode2 or PC_Mode3 ZIN pin H width tZHL QCR: CGSC = 0 ZIN pin L width tZLL QCR: CGSC = 0 AIN/BIN rise and fall time from determined ZIN level tZABE QCR: CGSC = 1 Determined ZIN level from AIN/BIN rise and fall time tABEZ QCR: CGSC = 1 *: tCYCP indicates the APB bus clock cycle time except when in Stop mode, in Timer mode. For more information about the APB bus number to which the quadrature position/revolution counter is connected, see "8. Block Diagram" in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

Document Number: 002-04988 Rev.*A Page 162 of 198 S6E2C3 Series BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ZIN

Document Number: 002-04988 Rev.*A Page 163 of 198 S6E2C3 Series ZIN AIN/BIN

Document Number: 002-04988 Rev.*A Page 164 of 198 S6E2C3 Series

12.4.15 I2C Timing

Standard-mode, Fast-mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency fSCL CL = 30 pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns Stop condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between "Stop condition" and "START condition" tBUF 4.7 - 1.3 - μs Noise filter tSP

2 MHz ≤

tCYCP＜40 MHz 2 tCYCP *4 - 2 tCYCP *4 - ns

40 MHz ≤

tCYCP ＜60 MHz 4 tCYCP *4 - 4 tCYCP *4 - ns

60 MHz ≤

tCYCP ＜80 MHz 6 tCYCP *4 - 6 tCYCP *4 - ns

80 MHz ≤

tCYCP ≤100 MHz 8 tCYCP *4 - 8 tCYCP *4 - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal. *3: Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns.” *4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see "8.Block Diagram" in this data sheet. When using Standard-mode, the peripheral bus clock must be set more than 2 MHz. When using Fast-mode, the peripheral bus clock must be set more than 8 MHz. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency.

Document Number: 002-04988 Rev.*A Page 165 of 198 S6E2C3 Series Fast Mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Fast Mode Plus (Fm+)*6 Unit Remarks Min Max SCL clock frequency fSCL CL = 30 pF, R = (Vp/IOL)*1 0 1000 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 0.26 - μs SCL clock L width tLOW 0.5 - μs SCL clock H width tHIGH 0.26 - μs SCL clock frequency tSUSTA 0.26 - μs (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDDAT 0 0.45*2, *3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 50 - ns Stop condition setup time SCL ↑ → SDA ↑ tSUSTO 0.26 - μs Bus free time between "Stop condition" and "START condition" tBUF 0.5 - μs Noise filter tSP tCYCP＜80 MHz 6 tCYCP *4 - ns *5 80 MHz ≤ tCYCP ≤100 MHz 8 tCYCP *4 - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal. *3: The Fast mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns.” *4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see "8.Block Diagram" in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency. *6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See Chapter12: I/O PORT in FM4 Family Peripheral Manual Main Part (002-04856) for the details.

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12.4.16 SD Card Interface Timing

 Clock CLK (All values are referenced to VIH and VIL transition points) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Remarks Min Max Clock frequency Data Transfer Mode fPP S_CLK CCARD ≤ 10 pF (1card) 0 25 MHz Clock frequency Identification Mode fOD S_CLK 0/100 400 kHz Clock low time tWL S_CLK 10 - ns Clock high time tWH S_CLK 10 - ns Clock rise time tTLH S_CLK - 10 ns Clock fall time tTHL S_CLK - 10 ns * 0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.  Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Value Remarks Min Max Input set-up time tISU S_CMD, S_DATA3: 0 CCARD ≤ 10 pF (1card) 5 - ns Input hold time tIH S_CMD, S_DATA3: 0 5 - ns  Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Value Remarks Min Max Output Delay time during Data Transfer Mode tODLY S_CMD, S_DATA3: 0 CCARD ≤ 40 pF (1card) 0 14 ns Output Delay time during Identification Mode tODLY S_CMD, S_DATA3: 0 0 50 ns Default-Speed Mode Notes: − The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. − For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main Part (002-04856). VIL VIL tWL tWH VIH VIH VIH tTHL tTLH tISU VIH VIL VIH VIL tIH VOH VOL VOH VOL tODLY(Max) tODLY(Min) S_CMD, S_DATA3: 0 (Card Output) S_CMD, S_DATA3: 0 (Card Input) S_CLK (SD Clock)

Document Number: 002-04988 Rev.*A Page 167 of 198 S6E2C3 Series High-Speed Mode  Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Remarks Min Max Clock frequency Data Transfer Mode fPP S_CLK CCARD ≤ 10 pF (1 card) 0 50 MHz Clock low time tWL S_CLK 7 - ns Clock high time tWH S_CLK 7 - ns Clock rise time tTLH S_CLK - 3 ns Clock fall time tTHL S_CLK - 3 ns  Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Value Remarks Min Max Input set-up time tISU S_CMD, S_DATA3: 0 CCARD ≤ 10 pF (1 card) 6 - ns Input hold time tIH S_CMD, S_DATA3: 0 2 - ns  Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Value Remarks Min Max Output delay time during data transfer mode tODLY S_CMD, S_DATA3: 0 CL ≤ 40 pF (1 card) 0 14 ns Output hold time tOH S_CMD, S_DATA3: 0 CL ≥ 15 pF (1 card) 2.5 - ns Total system capacitance for each line* CL - 1 card - 40 pF *: In order to satisfy severe timing, host shall drive only one card. High-Speed Mode Notes: − The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. − For more information about clock frequency (fPP), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main Part (002-04856). VIL VIL tWL tWH VIH VIH VIH tTHL tTLH tISU VIH VIL VIH VIL tIH VOH VOL VOH VOL tODLY(Max) tOH(Min) 50%VCC 50%VCC S_CMD, S_DATA3: 0 (Card Output) S_CMD, S_DATA3: 0 (Card Input) S_CLK (SD Clock)

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12.4.17 ETM/ HTM Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Data hold tETMH TRACECLK, TRACED[15: 0] VCC ≥ 4.5 V 2 9 ns VCC ＜4.5 V 2 15 TRACECLK frequency 1/tTRACE TRACECLK VCC ≥ 4.5 V 50 MHz VCC ＜4.5 V 32 MHz TRACECLK clock cycle tTRACE VCC ≥ 4.5 V 20 - ns VCC ＜4.5 V 31.25 - ns Note: − When the external load capacitance CL = 30 pF. HCLK TRACECLK TRACED[15: 0]

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12.4.18 JTAG Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC ＜4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC ＜4.5 V TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V - 25 ns VCC ＜4.5 V - 45 Note: − When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO

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12.4.19 I2S Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Output frequency fMCYC I2SCK - - 12.288 MHz Output clock pulse width tMHW I2SCK - 45 55 % tMLW 45 55 % I2SCK→I2SWS delay time tDFS I2SCK, I2SWS - 0 24.0 ns I2SCK→I2SDO delay time* tDDO I2SCK, I2SDO - 0 24.0 ns I2SDI→I2SCK setup time tHSDI I2SCK, I2SDI - 25.0 - ns I2SDI→I2SCK hold time tHDI - 0 - ns Input signal rise time tFI I2SDI - - 5 ns Input signal fall time tFI - - 5 ns *: Except for the first bit of transmission frame Notes: − When the external load capacitance CL = 20 pF − When I2SWS = 48 kHz, I2MCLK = 256 × I2SWS Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details.

Document Number: 002-04988 Rev.*A Page 171 of 198 S6E2C3 Series Note: − See Chapter7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details of CPOL, FSPH, FSLIN, and SMPL. I2SCK (CPOL=0) tmhw tmlw tmcyc I2SCK (CPOL=1) tdfs tdfs I2SWS (FSPH=0, FSLN=0) tdfs tdfs I2SWS (FSPH=1, FSLN=0) tdfs I2SWS (FSPH=0, FSLN=1) tdfs tdfstdfs I2SWS (FSPH=1, FSLN=1) tddo I2SDO I2SDI (SMPL=0) tsdi thdi tsdi thdi I2SDI (SMPL=1) tsdi thdi I2SDI 0.8×VCC 0.8×VCC 0.2×VCC 0.2×VCC 0.8×VCC tfi tri

Document Number: 002-04988 Rev.*A Page 172 of 198 S6E2C3 Series Slave Mode Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input frequency fSCYC I2SCK - - 12.288 MHz Input clock pulse width tSHW I2SCK - 45 55 % tSLW 45 55 % I2SWS→I2SCK Setup time tSFI I2SCK, I2SWS - 8 - ns I2SWS→I2SCK Hold time tHFI I2SCK, I2SWS - 0 - ns I2SCK↑→I2SDO Delay time*1 tDDO I2SCK, I2SDO - 0 32 ns I2SCK↑→I2SDO Delay time*2 tDFB1 - 0 32 ns I2SDI→I2SCK↓ Setup time tSDI I2SCK, I2SDI - 8 - ns I2SDI→I2SCK↓ Hold time tHDI - 0 - ns Input signal rise time tFI I2SCK, I2SWS, I2SDI - - 5 ns Input signal fall time tFI - - 5 ns *1: Except for the first bit of transmission frame *2: When FSPH bit = 1. Notes: − When the external load capacitance CL = 20 pF − When I2SWS = 48 kHz, I2MCLK = 256×I2SWS Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See Chapter7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details.

Document Number: 002-04988 Rev.*A Page 173 of 198 S6E2C3 Series Notes: − See Chapter7-2: I2S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the details of FSPH, FSLN, SMPL − I2SCK input is selectable polarity by CPOL bit of CNTREG register I2SCK (CPOL=0) tshw tslw tscyc I2SCK (CPOL=1) tsfi thfi I2SWS (FSPH=0, FSLN=0) tsfi thfi I2SWS (FSPH=1, FSLN=0) tsfi I2SWS (FSPH=0, FSLN=1) I2SWS (FSPH=1, FSLN=1) tddo I2SDO I2SDI (SMPL=0) tsdi thdi tsdi thdi I2SDI (SMPL=1) tsdi thdi tsfi tdfb1 I2SCK I2SWS I2SDI 0.8×VCC 0.8×VCC 0.2×VCC 0.2×VCC 0.8×VCC tfi tri

Document Number: 002-04988 Rev.*A Page 174 of 198 S6E2C3 Series I2SMCLK Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input frequency fCHS I2SMCK - - 25 MHz Input clock cycle tCYLHS - - 40 - ns Input clock pulse width - - PWHS/tCYLHS PWLS/tCYLHS 45 55 % When using external clock Input clock rise time and fall time tCFS tCRS - - - 5 ns When using external clock I2SMCLK Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Output frequency fCHS I2SMCK - - 12.288 MHz I2SMCLK 0.8×VCC 0.8×VCC 0.2×VCC 0.2×VCC 0.8×VCC tCFS tCRS PWHS PWLS tCYLHS

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12.4.20 High-Speed Quad SPI Timing

(VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Serial clock frequency tSCYCM Q_SCK_0 CL = 15 pF, VCC = 3.0 to 3.6V - 66 MHz *1 CL = 30 pF - 50 MHz *2 Enabled CS→ CLK Starting Time (mode0/mode2) tOSLSK02 Q_SCK_0, Q_CS0_0, Q_CS1_0, Q_CS2_0 CL = 30 pF 1.5×tSCYCM - 5 - ns Enabled CS→ CLK Starting Time (mode1/mode3) tOSLSK13 tSCYCM - 5 - ns CLK Last→ Disabled CS Time (mode0/mode2) tOSKSL02 tSCYCM - ns CLK Last→ Disabled CS Time (mode1/mode3) tOSKSL13 1.5×tSCYCM - ns SIO Data output time tOSDAT Q_SCK_0, Q_IO0_0, Q_IO1_0, Q_IO2_0, Q_IO3_0 CL = 15 pF, VCC = 3.0 to 3.6V 0 5 ns CL = 30 pF 0 5 SIO Setup tDSSET CL = 30 pF 3 - ns *1 10 - *2 SIO Hold tSDHOLD CL = 30 pF 0.5×tSCYCM - ns *1: When RTM = 1 and mode = 0, 1, 3 *2: When RTM = 1 and mode = 2 or RTM = 0 and mode = 0, 1, 2, 3 Notes: − See Chapter8-3: High-Speed Quad SPI controller in FM4 Family Peripheral Manual Communication Macro Part (002-04862) for the detail of RTM mode. − When using High-Speed Quad SPI, please set PDSR register to set the pin drive capability for VCC = 3V. See Chapter12: I/O Port in FM4 Family Peripheral Manual Main Part (002-04856) for the details.

Document Number: 002-04988 Rev.*A Page 176 of 198 S6E2C3 Series Q_CS0, Q_CS1, Q_CS2 tOSLSK02 tDSSET Q_SCK mode0 mode2 mode1 mode3 tOSLSK13 tSCYCM tOSKSL02 tOSKSL13 input tSDHOLD output tOSDAT Q_IO0, Q_IO1, Q_IO2, Q_IO3

Document Number: 002-04988 Rev.*A Page 177 of 198 S6E2C3 Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral nonlinearity - - - 4.5 - + 4.5 LSB AVRH = 2.7 V to 5.5 V Differential nonlinearity - - - 2.5 - + 2.5 LSB Zero transition voltage VZT ANxx - 15 - + 15 mV Full-scale transition voltage VFST ANxx AVRH – 15 - AVRH + 15 mV AVCC - 15 - AVCC + 15 mV Conversion time - - 0.5*1 - - μs AVCC ≥ 4.5 V Sampling time *2 Ts - 0.15 - 10 μs AVCC ≥ 4.5 V 0.3 - AVCC < 4.5 V Compare clock cycle*3 Tcck - 25 - 1000 ns AVCC ≥ 4.5 V 50 - 1000 AVCC < 4.5 V State transition time to operation permission Tstt - - - 1.0 μs Power supply current (analog + digital) - AVCC - 0.69 0.92 mA A/D 1 unit operation - 1.3 22 μA When A/D stop Reference power supply current (AVRH) - AVRH - 1.1 1.97 mA A/D 1 unit operation AVRH = 5.5 V - 0.3 6.3 μA When A/D stop Analog input capacity CAIN - - - 12.05 pF Analog input resistance RAIN - - - 1.2 kΩ AVCC ≥ 4.5 V 1.8 AVCC < 4.5 V Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 5 μA Analog input voltage - ANxx AVSS - AVRH V AVSS - AVCC V Reference voltage - AVRH 4.5 - AVCC V Tcck ＜ 50 ns 2.7 - AVCC Tcck ≥ 50 ns - AVRL AVSS - AVSS V *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of Ts = 150 ns and Tc = 350 ns (AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog Macro Part (002-04860). The register setting of the A/D converter is reflected by the APB bus clock timing. For more information about the APB bus number to which the A/D converter is connected, see 8. Block Diagram in this data sheet. The sampling and compare clock are set at base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (Tc) is the value of (Equation 2).

Document Number: 002-04988 Rev.*A Page 178 of 198 S6E2C3 Series (Equation 1) Ts ≥ (RAIN + Rext) × CAIN × 9 Ts: Sampling time RAIN: Input resistance of A/D = 1.2 kΩ at 4.5V ≤ AVCC ≤ 5.5V Input resistance of A/D = 1.8 kΩ at 2.7V ≤ AVCC < 4.5V CAIN: Input capacity of A/D = 12.05 pF at 2.7V ≤ AVCC ≤ 5.5V Rext: Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc: Compare time Tcck: Compare clock cycle Rext Rin Cin Analog signal source AN00 to AN31 Analog input pin Comparator RAIN CAIN

Document Number: 002-04988 Rev.*A Page 179 of 198 S6E2C3 Series Definition of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVss AVRH AVss AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

Document Number: 002-04988 Rev.*A Page 180 of 198 S6E2C3 Series 12.6 12-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - DAx - - 12 bit Conversion time tC20 0.56 0.69 0.81 μs Load 20 pF tC100 2.79 3.42 4.06 μs Load 100 pF Integral nonlinearity * INL - 16 - + 16 LSB Differential nonlinearity * DNL - 0.98 - + 1.5 LSB Output voltage offset VOFF - - + 10 mV When setting 0x000 - 20.0 - + 1.4 mV When setting 0xFFF Analog output impedance RO 3.10 3.80 4.50 kΩ D/A operation 2.0 - - MΩ When D/A stop Power supply current * IDDA AVCC 260 330 410 μs D/A 1ch operation AVCC = 3.3 V 400 510 620 μs D/A 1ch operation AVCC = 5.0 V IDSA - - 14 μs When D/A stop *: During no load

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12.7 USB Characteristics

(VCC = AVCC = 2.7V to 5.5V, USBVCC0 = USBVCC1 = 3.0V to 3.6V, VSS = AVSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input characteristics Input H level voltage VIH UDP0/ UDM0, UDP1/ UDM1 - 2.0 USBVCC + 0.3 V *1 Input L level voltage VIL - VSS - 0.3 0.8 V *1 Differential input sensitivity VDI - 0.2 - V *2 Different common mode range VCM - 0.8 2.5 V *2 Output characteristics Output H level voltage VOH External pull-down resistance = 15 kΩ 2.8 3.6 V *3 Output L level voltage VOL External pull-up resistance = 1.5 kΩ 0.0 0.3 V *3 Crossover voltage VCRS - 1.3 2.0 V *4 Rise time tFR Full-Speed 4 20 ns *5 Fall time tFF Full-Speed 4 20 ns *5 Rise/fall time matching tFRFM Full-Speed 90 111.11 % *5 Output impedance ZDRV Full-Speed 28 44 Ω *6 Rise time tLR Low-Speed 75 300 ns *7 Fall time tLF Low-Speed 75 300 ns *7 Rise/fall time matching tLRFM Low-Speed 80 125 % *7 *1: The switching threshold voltage of the single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There is some hysteresis applied to lower noise sensitivity. *2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8V to 2.5V to the local ground reference level. Above voltage range is the common mode input voltage range. Common mode input voltage [V] Minimum differential input sensitivity [V]

Document Number: 002-04988 Rev.*A Page 182 of 198 S6E2C3 Series *3: The output drive capability of the driver is below 0.3 V at low state (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the VSS and 1.5 kΩ load) at high state (VOH). *4: The cross voltage of the external differential output signal (D +/D −) of USB I/O buffer is within 1.3 V to 2.0 V. *5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. VCRS specified range Rise time Falling time

Document Number: 002-04988 Rev.*A Page 183 of 198 S6E2C3 Series *6: USB Full-speed connection is performed via twisted-pair cable shield with 90 Ω ± 15% characteristic impedance (differential mode). USB standard defines that the output impedance of the USB driver must be in the range from 28 Ω to 44 Ω. So, a discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommended value 27 Ω) series resistor Rs. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence.” *7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Note: − See Low-Speed Load (Compliance Load) for conditions of external load. Mount it as external resistance. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Rise time Falling time

Document Number: 002-04988 Rev.*A Page 184 of 198 S6E2C3 Series Low-Speed Load (Upstream Port Load) - Reference 1 Low-Speed Load (Downstream Port Load) - Reference 2 Low-Speed Load (Compliance Load) CL=50pF to 150pF CL=50pF to 150pF CL= 200pF to 600pF CL= 200pF to 600pF CL=200pF to 450pF CL=200pF to 450pF

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12.8 Low-Voltage Detection Characteristics

12.8.1 Low-Voltage Detection Reset

Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL - 2.46 2.55 2.64 V When voltage drops Released voltage VDH - 2.51 2.60 2.69 V When voltage rises

12.8.2 Interrupt of Low-Voltage Detection

Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00111 2.80 2.90 3.00 V When voltage drops Released voltage VDH 2.90 3.00 3.11 V When voltage rises Detected voltage VDL SVHI = 00100 2.99 3.10 3.21 V When voltage drops Released voltage VDH 3.09 3.20 3.31 V When voltage rises Detected voltage VDL SVHI = 01100 3.18 3.30 3.42 V When voltage drops Released voltage VDH 3.28 3.40 3.52 V When voltage rises Detected voltage VDL SVHI = 01111 3.67 3.80 3.93 V When voltage drops Released voltage VDH 3.76 3.90 4.04 V When voltage rises Detected voltage VDL SVHI = 01110 3.76 3.90 4.04 V When voltage drops Released voltage VDH 3.86 4.00 4.14 V When voltage rises Detected voltage VDL SVHI = 01001 4.05 4.20 4.35 V When voltage drops Released voltage VDH 4.15 4.30 4.45 V When voltage rises Detected voltage VDL SVHI = 01000 4.15 4.30 4.45 V When voltage drops Released voltage VDH 4.25 4.40 4.55 V When voltage rises Detected voltage VDL SVHI = 11000 4.25 4.40 4.55 V When voltage drops Released voltage VDH 4.34 4.50 4.66 V When voltage rises LVD stabilization wait time TLVDW - - - 6000×tCYCP * µs *: tCYCP indicates the APB2 bus clock cycle time.

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12.9 MainFlash Memory Write/Erase Characteristics

(VCC = 2.7V to 5.5V) Parameter Value Unit Remarks Min Typ Max Sector erase time Large Sector - 0.7 3.7 s Includes write time prior to internal erase Small Sector - 0.3 1.1 s Half word (16-bit) write time Write cycles < 100 times - 12 100 μs Not including system-level overhead time Write cycles > 100 times 200 Chip erase time* - 13.6 68 s Includes write time prior to internal erase *: It indicates the chip erase time of 1MB MainFlash memory For devices with 1.5 MB or 2 MB of MainFlash memory, two erase cycles are required. See 3.2.2 Command Operating Explanations and 3.3.3 Flash Erase Operation in this product's Flash Programming Manual for the detail. Write Cycles and Data Retention Time Erase/Write Cycles (Cycle) Data Retention Time (Year) 1,000 20* 10,000 10* 100,000 5* *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C).

12.10 Dual Flash Memory Write/Erase Characteristics

It is the same write/erase characteristics as the MainFlash memory. See 3.6 Dual flash mode in this product's Flash Programming Manual for the detail of dual flash mode.

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12.11 Standby Recovery Time

12.11.1 Recovery cause: Interrupt/WKUP

The time from the interrupt occurring to the time of program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tICNT HCLK×1 μs High-speed CR Timer mode Main Timer mode PLL Timer mode 40 80 μs Low-speed CR Timer mode 450 900 μs Sub Timer mode 896 1136 μs RTC mode Stop mode (High-speed CR/Main/PLL Run mode return) 316 581 μs RTC mode Stop mode (Low-speed CR/sub Run mode return) 270 540 μs Deep Standby RTC mode with RAM retention Deep Standby Stop mode with RAM retention 365 667 μs without RAM retention 365 667 μs with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in External Interrupt Recovery*) Ext.INT tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

Document Number: 002-04988 Rev.*A Page 188 of 198 S6E2C3 Series Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*) Internal Resource INT tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each low-power consumption mode. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main Part (002-04856). − The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main Part (002-04856).

Document Number: 002-04988 Rev.*A Page 189 of 198 S6E2C3 Series

12.11.2 Recovery Cause: Reset

The time from reset release to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tRCNT 155 266 µs High-speed CR Timer mode Main Timer mode PLL Timer mode 155 266 µs Low-speed CR Timer mode 315 567 µs Sub Timer mode 315 567 µs RTC mode Stop mode 315 567 µs Deep Standby RTC mode with RAM retention Deep Standby Stop mode with RAM retention 336 667 µs without RAM retention 336 667 µs with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in INITX Recovery) INITX tRCNT Internal RST CPU Operation Start RST Active Release

Document Number: 002-04988 Rev.*A Page 190 of 198 S6E2C3 Series Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*) Internal Resource RST tRCNT Internal RST CPU Operation Start RST Active Release *: Depending on the low-power consumption mode, the reset issue from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each low power consumption mode. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main Part (002-04856). − The recovery process is unique for each operating mode. See Chapter 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main Part (002-04856). − When the power-on reset/low-voltage detection reset, they are not included in the return factor. See 12.4.8 Power-On Reset Timing. − In recovering from reset, CPU changes to High-speed Run mode. In the case of using the main clock and PLL clock, they need further main clock oscillation stabilization wait time and oscillation stabilization wait time of Main PLL clock. − Internal resource reset indicates Watchdog reset and CSV reset.

Document Number: 002-04988 Rev.*A Page 191 of 198 S6E2C3 Series 13. Ordering Information Part number Flash RAM Crypto Voice Package S6E2C38H0AGV20000 1 MB 128 KB N/A N/A Plastic・LQFP (0.5-mm pitch), 144 pin (LQS144) S6E2C39H0AGV20000 1.5 MB 192 KB N/A N/A S6E2C3AH0AGV20000 2 MB 256 KB N/A N/A S6E2C38J0AGV20000 1 MB 128 KB N/A N/A Plastic・LQFP (0.65-mm pitch), 176 pin (LQP176) S6E2C39J0AGV20000 1.5 MB 192 KB N/A N/A S6E2C3AJ0AGV20000 2 MB 256 KB N/A N/A S6E2C38J0AGB10000 1 MB 128 KB N/A N/A Plastic・LQFP (0.8-mm pitch), 192 pin (LBE192) S6E2C39J0AGB10000 1.5 MB 192 KB N/A N/A S6E2C3AJ0AGB10000 2 MB 256 KB N/A N/A S6E2C38L0AGL20000 1 MB 128 KB N/A N/A Plastic・LQFP (0.4-mm pitch), 216 pin (LQQ216) S6E2C39L0AGL20000 1.5 MB 192 KB N/A N/A S6E2C3AL0AGL20000 2 MB 256 KB N/A N/A

Document Number: 002-04988 Rev.*A Page 192 of 198 S6E2C3 Series 14. Package Dimensions Package Type Package Code LQFP 144 LQS 144

Document Number: 002-04988 Rev.*A Page 193 of 198 S6E2C3 Series Package Type Package Code LQFP 176 LQP 176

Document Number: 002-04988 Rev.*A Page 194 of 198 S6E2C3 Series Package Type Package Code LQFP 216 LQQ 216

Document Number: 002-04988 Rev.*A Page 195 of 198 S6E2C3 Series Package Type Package Code PFBGA 192 LBE 192

Document Number: 002-04988 Rev.*A Page 196 of 198 S6E2C3 Series 15. Major Changes Spansion Publication Number: S6E2C3_DS709-00012 Page Section Change Results Revision 0.1 - - Initial release Revision 1.0 2. Features 3. Product Lineup 10. Block Diagram 12. Memory Map Deleted HDM-CEC/Remote Control Receiver. 16-18 5. Pin Assignments Deleted the pins of HDM-CEC/Remote Control Receiver.(CEC0,CEC1) Revised the pin name of I2S. (MI2S*_0→MI2S*0_0) Deleted the pin of IGTRG0_0. 20-71 6. Pin Descriptions Deleted the pins of HDM-CEC/Remote Control Receiver.(CEC0,CEC1) Revised the pin name of I2S. (MI2S*_0→MI2S*0_0) Revised the pin number of PF7 in LQFP216.(91→90) revised the pin number of X1. (73, 58, 50, P5→107, 87, 71, P13) Revised the pin number of X0A. (107, 87, 71, P13→73, 58, 50, P5) 72-79 7. I/O Circuit Type Revised IOH/IOL of Type S.(IOH=-12mA→-10mA, IOL=12mA→ 10mA) Added the case of using I2C in Type E, F, G, L, N, S. 94-101 13. Pin Status In Each CPU State Deleted X and Y in Pin Status Type. 102-103 14.1. Absolute Maximum Ratings Added 10mA type. 104-107 14.2. Recommended Operating Conditions Added AVRL in Analog reference voltage. Revised the leakage current in Maximum leakage current at operating 108-117 14.3.1. Current Rating Revised the maximum current of each category. 118-119 14.3.2. Pin Characteristics Added the characteristic of external bus in H level input voltage (hysteresis input). Added the characteristic of 10 mA type. 122 14.4.5. Operating Conditions of USB PLL・ I2S PLL (in the case of using main clock for input clock of PLL) Revised the maximum of I2S PLL macro oscillation clock frequency. (307.2 MHz→384 MHz) 186 14.5.12-bit A/D Converter Revised the minimum of Sampling time. Revised the characteristic of State transition time to operation permission Added AVRL in Analog reference voltage. 194 14.8.2. Interrupt of Low-Voltage Detection Revised the SVHI values in Conditions NOTE: Please see “Document History” about later revised information.

Document Number: 002-04988 Rev.*A Page 197 of 198 S6E2C3 Series Document History Document Title: S6E2C3 Series 32-bit ARM® Cortex®-M4F, FM4 Microcontroller Document Number: 002-04988 Revision ECN Orig. of Change Submission Date Description of Change ** - AKIH 04/22/2015 New Spec. *A 5126421 HITK 02/05/2016 Company name and layout design change. Added the note of TAP pin. Updated Package Code and Dimensions (LQFP-144, LQFP-176, LQFP-216).

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