Power Management

S6BP401AY2SN1B000

Cypress Semiconductor

Quad Buck DC/DC Converter (DD1 to DD4)

Manufacturer: Cypress Semiconductor

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PDF pages: 38

Technical content

Features

 Quad Buck DC/DC Converter (DD1 to DD4)  VIN Input Range: 4.5V to 5.5V  Switching Frequency  External clock mode: 1.8 MHz to 2.4 MHz  Internal clock mode: 2.0 MHz to 2.2 MHz  Built-in Switching FETs up to 3A  Built-in Output Voltage Setting Resistors  Built-in Compensation Circuits  Dual LDO (LD1, LD2)  VIN Input Voltage Range: 2.97V to 5.5V  Built-in Output Voltage Setting resistors  Power Good Monitor Output for each DC/DC Converters, LDOs  Built-in Windowed Watchdog Timer (WDT)  Under Voltage Lockout (UVLO)  Thermal Shutdown (TSD)  Over Current Protection (OCP)  Over Voltage Protection (OVP)  Independent Enabling for each DC/DC Converters and LDOs  Load-independent Soft-Start  Built-in Discharge Resistors  Small 6 mm × 6 mm QFN-40 Package  AEC-Q100 compliant (Grade-1)

Applications

 Automotive Applications  Advanced Driver Assistance Systems (ADAS)  Camera Systems such as Security Camera  Industrial Applications Block Diagram 1.20V~1.575V / 2A 1.00V~1.275V / 3A 1.20V~2.575V / 2A 3.3V~3.4V / 1A 3.3V~3.4V / 0.2A S6BP401A : PMIC DC/DC converter LDO Power Good Watch Dog

Document Number: 002-03341 Rev.*C Page 2 of 38 S6BP401A More Information Cypress provides a wealth of data at www.cypress.com/pmic to help you to select the right PMIC device for your design, and to help you to quickly and effectively integrate the device into your design. Following is an abbreviated list for S6BP401A:  Overview: Automotive PMIC Portfolio, Automotive PMIC Roadmap  Product Selector:  S6BP401A: 6ch Automotive PMIC for ADAS  Application Notes: Cypress offers S6BP401A application notes. Recommended application notes for getting started with S6BP401A are:  AN98649: How to Design a Power Management Syste m  AN201006: Thermal Considerations and Parameters  Evaluation Kit Operation Manual:  S6SBP401AM2SA1001: Power block for automotive ADAS platform  Related Products:  S6BP201A, S6BP202A, S6BP20 3A: 1ch Buck -Boost Automotive PMIC  S6BP501A, S6BP502A : 3ch Automotive PMIC for Instrument Cluster

Document Number: 002-03341 Rev.*C Page 3 of 38 S6BP401A 1. Typical Application Figure 1-1 Typical Application

Document Number: 002-03341 Rev.*C Page 4 of 38 S6BP401A 2. Pin Configuration Figure 2-1 Pin Configuration PGL2 GND LDO2 PVCCL2 PVCCL1 LDO1 VCC PG1 VREG PG2 PG4 FB1 FB4 PVCC1 PVCC4 LX1 LX4 PGND1 PGND4 PGND2 PGND3 PGND2 LX3 LX2 PVCC3 LX2 FB3 PVCC2 PG3 PVCC2 SYNC WDI RST ENL2 ENL1 EN4 EN3 EN2 EN1 FB2 (Corner Pad) (Corner Pad) (Corner Pad) (Corner Pad)CP1 CP4 CP3CP2 17 18 19 2011 12 13 14 15 16 8 23 9 22 10 21 7 24 Top View 3 28 4 27 5 26 EP (Exposed Pad)6 25 40 39 38 37 36 35 34 33 32 31

Document Number: 002-03341 Rev.*C Page 5 of 38 S6BP401A 3. Pin Functions Table 3-1 Pin Functions Functional Block Pin Number Pin Name I/O Description Pin Setting When Not Being Used DD1 19 EN1 I Enable input terminal of DD1. Ground 30 FB1 I Output voltage feedback terminal of DD1. Ground 33 PG1 O Power good output terminal of DD1. Ground 29 PVCC1 - Power supply terminal of DD1. VCC 28 LX1 O Inductor connect terminal of DD1. Leave pin open 27 PGND1 - Power ground terminal of DD1. Ground DD2 18 EN2 I Enable input terminal of DD2. Ground 20 FB2 I Output voltage feedback terminal of DD2. Ground 31 PG2 O Power good output terminal of DD2. Ground 21, 22 PVCC2 - Power supply terminal of DD2. VCC 23, 24 LX2 O Inductor connect terminal of DD2. Leave pin open 25, 26 PGND2 - Power ground terminal of DD2. Ground DD3 17 EN3 I Enable input terminal of DD3. Ground 9 FB3 I Output voltage feedback terminal of DD3. Ground 10 PG3 O Power good output terminal of DD3. Ground 8 PVCC3 - Power supply terminal of DD3. VCC 7 LX3 O Inductor connect terminal of DD3. Leave pin open 6 PGND3 - Power ground terminal of DD3. Ground DD4 16 EN4 I Enable input terminal of DD4. Ground 2 FB4 I Output voltage feedback terminal of DD4. Ground 1 PG4 O Power good output terminal of DD4. Ground 3 PVCC4 - Power supply terminal of DD4. VCC 4 LX4 O Inductor connect terminal of DD4. Leave pin open 5 PGND4 - Power ground terminal of DD4. Ground LD1 15 ENL1 I Enable input terminal of LD1. Ground 36 PVCCL1 - Power supply terminal of LD1. VCC 35 LDO1 O Output terminal of LD1. Leave pin open LD2 14 ENL2 I Enable input of LD2. Ground 40 PGL2 O Power good output terminal of LD2. Ground 37 PVCCL2 - Power supply terminal of LD2. VCC 38 LDO2 O Output terminal of LD2. Leave pin open WDT 12 WDI I Trigger input terminal of WDT . Ground 13 RST O Reset input terminal of WDT. Ground SYNC 11 SYNC I External clock input terminal. Ground - 34 VCC - Power supply terminal for analog controller. − - 32 VREG O Internal 1.8V supply voltage capacitor terminal. Do NOT supply or load this terminal externally. − - 39 GND - Ground terminal for analog controller. − - EP EP - Exposed pad. Connect to ground plane. − - CP1, CP2, CP3, CP4 CP - Corner pad for reinforcing attachment to a board. Connect to ground plane. −

Document Number: 002-03341 Rev.*C Page 6 of 38 S6BP401A 4. Preset Output Voltage Table 4-1 Preset Output Voltage (Buck DC/DC Converter) Channel Preset Output Voltage [V] Soft-start Time [ms] Maximum Output Current [mA] Under Voltage Threshold [%] Over Voltage Threshold [%] DD1 1.200 1.200 2000 94.0 106.0 1.225 1.225 1.250 1.250 1.275 1.275 1.300 1.300 1.325 1.325 1.500 1.500 1.525 1.525 1.550 1.550 1.575 1.575 DD2 1.000 1.000 3000 94.0 106.0 1.025 1.025 1.050 1.050 1.075 1.075 1.100 1.100 1.125 1.125 1.150 1.150 1.175 1.175 1.200 1.200 1.225 1.225 1.250 1.250 1.275 1.275 DD3 1.200 1.200 2000 95.2 106.0 1.225 1.225 1.250 1.250 1.275 1.275 1.500 1.500 1.525 1.525 1.550 1.550 1.575 1.575 1.800 1.800 1.825 1.825 1.850 1.850 1.875 1.875 2.500 2.500 2.525 2.525 2.550 2.550 2.575 2.575 DD4 3.300 3.300 1000 95.5 106.0 3.325 3.325 3.350 3.350 3.375 3.375 3.400 3.400 Notes: − Soft-start time values are at fOSC = 2.1 MHz − Refer to Chapter 8 for the minimum or maximum values of output voltage, under voltage threshold and over voltage threshold.

Document Number: 002-03341 Rev.*C Page 7 of 38 S6BP401A Table 4-2 Preset Output Voltage (LDO) Channel Preset Output Voltage [V] Soft-start Time [ms] Maximum Output Current [mA] Under Voltage Threshold [%] Over Voltage Threshold [%] LD1 3.300 3.300 200 94.0 106.0 3.325 3.325 3.350 3.350 3.375 3.375 3.400 3.400 LD2 1.200 1.200 500 94.0 106.0 1.225 1.225 1.250 1.250 1.275 1.275 1.800 1.800 1.825 1.825 1.850 1.850 1.875 1.875 2.800 2.800 2.825 2.825 2.850 2.850 2.875 2.875 Notes: − Soft-start time values are at fOSC = 2.1 MHz − Refer to Chapter 8 for the minimum or maximum values of output voltage, under voltage threshold and over voltage threshold.

Document Number: 002-03341 Rev.*C Page 8 of 38 S6BP401A 5. Architecture Block Diagram Figure 5-1 Architechture Block Diagram Error Amplifier Slope Compensation PWM Logic Control PWM Comparator Current Sense Anti- Shoot Through Low Priority en1 Voltage Reference Power Good Monitor Peak Current Comparator FB1 PVCC1 LX1 PGND1 << DD1 >> PGND2 PVCC2 LX2 Discharge ss1 clk pg1 Error Amplifier Slope Compensation PWM Logic Control PWM Comparator Current Sense Anti- Shoot Through Low Priority en2 Voltage Reference Power Good Monitor Peak Current Comparator FB2 PVCC2 LX2 PGND2 << DD2 >> Discharge ss2 clk pg2 Error Amplifier Slope Compensation PWM Logic Control PWM Comparator Current Sense Anti- Shoot Through Low Priority en3 Voltage Reference Power Good Monitor Peak Current Comparator FB3 PVCC3 LX3 PGND3 << DD3 >> Discharge ss3 clk pg3 Error Amplifier Slope Compensation PWM Logic Control PWM Comparator Current Sense Anti- Shoot Through Low Priority en4 Voltage Reference Power Good Monitor Peak Current Comparator FB4 PVCC4 LX4 PGND4 << DD4 >> Discharge ss4 clk pg4

Document Number: 002-03341 Rev.*C Page 9 of 38 S6BP401A EN1 EN2 EN3 EN4 ENL1 ENL2 SYNC VCC VREG GND PG1 PG2 PG3 PG4 RST Control Logic pg1 pg2 pg3 pg4 Watchdog Timer pgl1 Oscillator with Synchronization clk Thermal Shutdown Under Voltage Lockout clk en1 en2 en3 en4 enl1 enl2 Soft-Start Control ss1 ss2 ss3 ss4 ssl1 enl2 Linear Regulator VCC VCC << Main Control >> << Power Good monitor Output >> << Watchdog Timer >> WDI clk Power Good Monitor PVCCL1Low Priority Voltage Reference Power Good Monitor LDO1 << LDO1 >> Discharge enl1 ssl1 pgl1 PVCCL2Low Priority Voltage Reference Power Good Monitor LDO2 << LDO2 >> Discharge enl2 ssl2 pgl2 PGL2 pgl2

Document Number: 002-03341 Rev.*C Page 10 of 38 S6BP401A 6. Absolute Maximum Ratings Table 6-1 Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Min Max Power supply voltage VVCC VCC -0.3 +6.9 V VPVCC PVCC1, PVCC2, PVCC3, PVCC4 -0.3 +6.9 V VPVCCL PVCCL1, PVCCL2 -0.3 +6.9 V Input voltage VEN EN1, EN2, EN3, EN4, ENL1, ENL2 -0.3 +6.9 V VWDI WDI -0.3 +6.9 V VSYNC SYNC -0.3 +6.9 V VFB FB1, FB2, FB3, FB4 -0.3 +6.9 V VPG PG1, PG2, PG3, PG4, PGL2 -0.3 +6.9 V VRST RST -0.3 +6.9 V LX voltage VLX LX1, LX2, LX3, LX4 -0.3 +6.9 V Voltage difference VPVCC-VCC PVCC1 -VCC, PVCC2-VCC, PVCC3-VCC, PVCC4-VCC -0.3 +0.3 V VPGND-GND PGND1-GND, PGND2-GND, PGND3-GND, PGND4-GND -0.3 +0.3 V VPVCC-LX PVCC1-LX1, PVCC2-LX2, PVCC3-LX3, PVCC4-LX4 -0.3 +6.9 V VVCC-INPUT VCC-EN1, VCC-EN2, VCC-EN3, VCC-EN4, VCC-EN1L, VCC-EN2L, VCC-WDI, VCC-SYNC, VCC-FB1, VCC-FB2, VCC-FB3, VCC-FB4 -0.3 +6.9 V Power dissipation PD TA ≤ + 25°C, Thermal resistance (θJA): 18°C /W (*1) - 6940 mW Junction temperature TJ - -40 +150 °C Storage temperature TSTG - -55 +150 °C *1: When the IC is mounted on 76.2 mm × 114.3 mm four-layer epoxy board. IC is mounted on a four-layer epoxy board, which terminal bias, and the IC’s thermal pad is connected to the epoxy board. WARNING 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Figure 6-1 Maximum Power Dissipation - Operating Ambient Temperature Characteristics 1000 2000 3000 4000 5000 6000 7000 8000 -60 -40 -20 0 20 40 60 80 100 120 140 Maximum Power dissipation PD [mW] Ambient Temperature TA [°C]

Document Number: 002-03341 Rev.*C Page 11 of 38 S6BP401A 7. Recommended Operating Conditions Table 7-1 Recommended Operating Conditions Parameter Symbol Condition Value Unit Min Typ Max Power supply voltage VVCC VCC +4.5 +5.0 +5.5 V VPVCC PVCC1, PVCC2, PVCC3, PVCC4 - VVCC - V VPVCCL PVCCL1, PVCCL2 +2.97 +5.0 VVCC V Input voltage VEN EN1, EN2, EN3, EN4, ENL1, ENL2 0 - VVCC V VWDI WDI 0 - VVCC V VSYNC SYNC 0 - VVCC V VFB FB1, FB2, FB3, FB4 0 - VVCC V VPG PG1, PG2, PG3, PG4, PGL2 0 - +5.5 V VRST RST 0 - +5.5 V Operating ambient temperature TA - -40 +25 +125 °C WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Document Number: 002-03341 Rev.*C Page 12 of 38 S6BP401A 8. Electrical Characteristics VVCC = VPVCC = 5.0V, VPVCCL = 5.0V, TA = TJ = -40 to +125 °C, unless otherwise noted. Typical values are at TA = +25 °C. Table 8-1 Electrical Characteristics Parameter Symbol Condition Value Unit Min Typ Max Supply Current Shutdown current IVCCS VCC PIN, VEN1 = VEN2 = VEN3 = VEN4 = VENL1 = VENL2 = 0V - 1 10 µA UVLO: Under Voltage Lockout (VCC) Threshold voltage VUVLOF VVCC falling, UVLO stop voltage 3.80 3.95 4.10 V Hysteresis VUVHYS - 0.27 0.30 0.33 V TSD: Thermal Shutdown Shutdown temperature TTSD Temperature rising - 165 (*1) - °C Hysteresis TTSDHYS - - 10 (*1) - °C Enable Inputs (EN1, EN2, EN3, EN4, ENL1, ENL2) Input high voltage VIHEN - 2.0 - VVCC V Input low voltage VILEN - 0 - 0.4 V Input current IIHEN VEN = 5.0V 33 50 100 µA Pull down resistance RPDEN - 50 100 150 kΩ Internal Linear Regulator Output (VREG) Output voltage VVREG VVCC = 5.0V 1.74 1.80 1.86 V Maximum output current IVREG VVCC = 5.0V 5 - - mA Over voltage lockout threshold VVREGOVR VVREG rising, Power fail 1.86 1.92 1.98 V VVREGOVF VVREG falling, Power good 1.81 1.87 1.93 V Under voltage lockout threshold VVREGUVR VVREG rising, Power good 1.67 1.73 1.79 V VVREGUVF VVREG falling, Power fail 1.62 1.68 1.74 V Oscillator Switching frequency fOSC - 2.0 2.1 2.2 MHz Synchronization Input (SYNC) Input high voltage VIHSYNC - 2.0 - VVCC V Input Low voltage VILSYNC - 0 - 0.4 V Input current IIHSYNC VEN = 5.0V 33 50 100 µA Pull down resistance RPDSYNC - 50 100 150 kΩ Input frequency fSYNC - 1.8 2.1 2.4 MHz Switching frequency fOSC - - fSYNC - MHz

Document Number: 002-03341 Rev.*C Page 13 of 38 S6BP401A Parameter Symbol Condition Value Unit Min Typ Max Power Good Monitor (PG1, PG2, PGL2) Over voltage threshold VPGOV Ratio of power fail threshold to VOUT1, VOUT2, VOUTL2 rising 104.5 106.0 107.5 % Over voltage hysteresis VPGOVHYS - 0.5 1.0 1.5 % Under voltage threshold VPGUV Ratio of power fail threshold to VOUT1, VOUT2, VOUT3 falling 92.5 94.0 95.5 % Under voltage hysteresis VPGUVHYS - 0.5 1.0 1.5 % Leakage current ILEAKPG VPG = 5.0V - - 1 µA Output low voltage VOLPG IPG = 3 mA - 0.15 0.30 V Propagation time TPPG 5% outside of the threshold, Power fail - 4 (*1) 8 (*1) µs Power-on reset time TRPG Power good 8 10 12 ms Power Good Monitor (PG3) Over voltage threshold VPGOV Ratio of power fail threshold to VOUT3 rising 104.5 106.0 107.5 % Over voltage hysteresis VPGOVHYS - 0.5 1.0 1.5 % Under voltage threshold VPGUV Ratio of power fail threshold to VOUT3 falling 93.7 95.2 96.7 % Under voltage hysteresis VPGUVHYS - 0.5 1.0 1.5 % Leakage current ILEAKPG VPG = 5.0V - - 1 µA Output low voltage VOLPG IPG = 3 mA - 0.15 0.30 V Propagation time TPPG 5% outside of the threshold, Power fail - 4 (*1) 8 (*1) µs Power-on reset time TRPG Power good 8 10 12 ms Power Good Monitor (PG4) Over voltage threshold VPGOV Ratio of power fail threshold to VOUT4 rising 104.5 106.0 107.5 % Over voltage hysteresis VPGOVHYS - 0.5 1.0 1.5 % Under voltage threshold VPGUV Ratio of power fail threshold to VOUT4 falling 94.0 95.5 97.0 % Under voltage hysteresis VPGUVHYS - 0.5 1.0 1.5 % Leakage current ILEAKPG VPG = 5.0V - - 1 µA Output low voltage VOLPG IPG = 3 mA - 0.15 0.30 V Propagation time TPPG 5% outside of the threshold, Power fail - 4 (*1) 8 (*1) µs Power-on reset time TRPG Power good 8 10 12 ms Reset (RST) Over voltage threshold VRSOV Ratio of power fail threshold to VOUTL1 rising 104.5 106.0 107.5 % Over voltage hysteresis VRSOVHYS - 0.5 1.0 1.5 % Under voltage threshold VRSUV Ratio of power fail threshold to VOUTL1 falling 92.5 94.0 95.5 % Under voltage hysteresis VRSUVHYS - 0.5 1.0 1.5 % Leakage current ILEAKRST VRST = 5.0V - - 1 µA Output low voltage VOLRST IPG = 3 mA - 0.15 0.30 V Propagation time TPRST 5% outside of the threshold, Power fail - 4 (*1) 8 (*1) µs Power-on reset time TRD Power good 25.6 32.0 38.4 ms

Document Number: 002-03341 Rev.*C Page 14 of 38 S6BP401A Parameter Symbol Condition Value Unit Min Typ Max Watchdog Timer (WDI) Watchdog sampling time TSAM - 0.40 0.50 0.60 ms Ignore window time TIW - 25.6 32.0 38.4 ms Open window time TOW - 25.6 32.0 38.4 ms Long open window time TLOW - 102.4 128.0 153.6 ms Closed window time TCW - 25.6 32.0 38.4 ms Window watchdog trigger time TWD - 38.4 48 51.2 ms Input high voltage VIHWDI - 2.0 - VVCC V Input low voltage VILWDI - 0 - 0.4 V Input current IIHWDI VWDI = 5.0V 33 50 100 µA Pull down resistance RPDWDI - 50 100 150 kΩ DD1: Buck DC/DC Converter Output voltage accuracy VOUT1 VVCC = 5.0V, IOUT1 = 10 mA -1.8 0 +1.8 % DC regulation VREG1 VVCC = VPVCC1 = 4.5 to 5.5V, FB1 input resistance RFB1 VFB1 = 2.0V 95 190 285 kΩ Switching FET ON resistance RONHS1 ILX1 = 20 mA (PVCC1 to LX1) - 100 190 mΩ RONLS1 ILX1 = -20 mA (LX1 to PGND1) - 65 125 mΩ Switching FET leakage current ILEAK1 IPVCC1 = 5.0V - 1 10 µA Maximum output current IOUT1 L = 1.5 µH 2 (*1) - - A LX1 peak current limit ILIMIT1 L = 1.5 µH 2.5 (*1) - - A Over voltage protection threshold VOVP1 VOUT1 rising, Switching termination threshold 125.0 130.0 135.0 % Over voltage protection hysteresis VOVPHYS1 - 2.0 5.0 8.0 % FB1 discharge resistance RDIS1 - 160 400 640 Ω Soft-start time coefficient TCOESS1 TSS1 = VOUT1 x TCOESS1 0.9 1.0 1.1 ms/V DD2: Buck DC/DC Converter Output voltage accuracy VOUT2 VVCC = 5.0V, IOUT2 = 10 mA -1.8 0 +1.8 % DC regulation VREG2 VVCC = VPVCC2 = 4.5 to 5.5V FB2 input resistance RFB2 VFB2 = 2.0V 95 190 285 kΩ Switching FET ON resistance RONHS2 ILX2 = 20 mA (PVCC2 to LX2) - 85 165 mΩ RONLS2 ILX2 = -20 mA (LX2 to PGND2) - 55 105 mΩ Switching FET leakage current ILEAK2 IPVCC2 = 5.0V - 1 10 µA Maximum output current IOUT2 L = 1.5 µH 3 (*1) - - A LX2 peak current limit ILIMIT2 L = 1.5 µH 3.5 (*1) - - A Over voltage protection threshold VOVP2 VOUT2 rising, Switching termination threshold 125.0 130.0 135.0 % Over voltage protection hysteresis VOVPHYS2 - 2.0 5.0 8.0 % FB2 discharge resistance RDIS2 - 160 400 640 Ω Soft-start time coefficient TCOESS2 TSS2 = VOUT2 x TCOESS2 0.9 1.0 1.1 ms/V

Document Number: 002-03341 Rev.*C Page 15 of 38 S6BP401A Parameter Symbol Condition Value Unit Min Typ Max DD3: Buck DC/DC Converter Output voltage accuracy VOUT3 VVCC = 5.0V, IOUT3 = 10 mA -1.8 0 +1.8 % DC regulation VREG3 VVCC = VPVCC3 = 4.5 to 5.5V, FB3 input resistance RFB3 VFB3 = 2.0V 95 190 285 kΩ Switching FET ON resistance RONHS3 ILX3 = 20 mA (PVCC3 to LX3) - 100 190 mΩ RONLS3 ILX3 = -20 mA (LX3 to PGND3) - 65 125 mΩ Switching FET leakage current ILEAK3 IPVCC3 = 5.0V - 1 10 µA Maximum output current IOUT3 L = 1.5 µH 2 (*1) - - A LX3 peak current limit ILIMIT3 L = 1.5 µH 2.5 (*1) - - A Over voltage protection threshold VOVP3 VOUT3 rising, Switching termination threshold 125.0 130.0 135.0 % Over voltage protection hysteresis VOVPHYS3 - 2.0 5.0 8.0 % FB3 discharge resistance RDIS3 - 160 400 640 Ω Soft-start time coefficient TCOESS3 TSS3 = VOUT3 × TCOESS3 0.9 1.0 1.1 ms/V DD4: Buck DC/DC Converter Output voltage accuracy VOUT4 VVCC = 5.0V, IOUT4 = 10 mA -1.8 0 +1.8 % DC regulation VREG4 VVCC = VPVCC4 = 4.5 to 5.5V, FB4 input resistance RFB4 VFB4 = 2.0V 95 190 285 kΩ Switching FET ON resistance RONHS4 ILX4 = 20 mA (PVCC4 to LX4) - 100 190 mΩ RONLS4 ILX4 = -20 mA (LX4 to PGND4) - 65 125 mΩ Switching FET leakage current ILEAK4 IPVCC4 = 5.0V - 1 10 µA Maximum output current IOUT4 L = 1.5 µH 1 (*1) - - A LX4 peak current limit ILIMIT4 L = 1.5 µH 1.5 (*1) - - A Over voltage protection threshold VOVP4 VOUT4 rising, Switching termination threshold 125.0 130.0 135.0 % Over voltage protection hysteresis VOVPHYS4 - 2.0 5.0 8.0 % FB4 discharge resistance RDIS4 - 160 400 640 Ω Soft-start time coefficient TCOESS4 TSS4 = VOUT4 × TCOESS4 0.9 1.0 1.1 ms/V

Document Number: 002-03341 Rev.*C Page 16 of 38 S6BP401A Parameter Symbol Condition Value Unit Min Typ Max LD1: LDO Regulator Output voltage accuracy VOUTL1 VVCC = 5.0V, IOUTL1 = 10 mA -1.8 0 +1.8 % DC regulation VREGL1 VVCC = 4.5 to 5.5V, VPVCCL1 = 2.97 to VVCC IOUTL1 = 0 to IOUTL1 -15 (*1) 0 +5 (*1) mV Output FET leakage current ILEAKL1 IPVCCL1=5.0V - 1 10 µA Maximum output current IOUTL1 VPVCCL1 - VOUTL1 ≥ 1.6V 200 (*1) - - mA 0.17V ≤ VPVCCL1 - VOUTL1 < 1.6V 100 (*1) - - mA Output current limit ILIMITL1 VPVCCL1 - VOUTL1 ≥ 1.6V 210 (*1) - - mA 0.17V ≤ VPVCCL1 - VOUTL1 < 1.6V 105 (*1) - - mA LDO1 discharge resistance RDISL1 - 160 400 640 Ω Soft-start time coefficient TCOESSL1 TSSL1 = VOUTL1 × TCOESSL1 0.9 1.0 1.1 ms/V LD2: LDO Regulator Output voltage accuracy VOUTL2 VVCC = 5.0V, IOUTL2 = 10 mA -1.8 0 +1.8 % DC regulation VREGL2 VVCC = 4.5 to 5.5V, VPVCCL2 = 2.97 to VVCC IOUTL2 = 0 to IOUTL2 -15 (*1) 0 +5 (*1) mV Output FET leakage current ILEAKL2 IPVCCL2=5.0V - 1 10 µA Maximum output current IOUTL2 VPVCCL2 - VOUTL2 ≥ 1.6V 500 (*1) - - mA 0.17V ≤ VPVCCL2 - VOUTL2 < 1.6V 400 (*1) - - mA Output current limit ILIMITL2 VPVCCL2 - VOUTL2 ≥ 1.6V 525 (*1) - - mA 0.17V ≤ VPVCCL2 - VOUTL2 < 1.6V 420 (*1) - - mA LDO2 discharge resistance RDISL2 - 160 400 640 Ω Soft-start time coefficient TCOESSL2 TSSL2 = VOUTL2 × TCOESSL2 0.9 1.0 1.1 ms/V *1: The electrical characteristic is ensured by statistical characterization and indirect tests.

Document Number: 002-03341 Rev.*C Page 17 of 38 S6BP401A 9. Operating Mode List Table 9-1 shows the operation list of S6BP401A. Table 9-1 Operation Mode List Condition Operating Block TJ SYNC ENL1 EN1/ EN2/ EN3/ EN4/ ENL2 Chip Control VREG LDO Watch- dog Trigger Monitor Freq. Sync. LD1 DD1/ DD2/ DD3/ DD4/ LD2 < TTSD L or H L L OFF OFF OFF OFF OFF OFF < TTSD L or H L H ON ON OFF OFF OFF ON < TTSD L or H H L ON ON ON OFF ON OFF < TTSD L or H H H ON ON ON OFF ON ON < TTSD clock L L OFF OFF OFF OFF OFF OFF < TTSD clock L H ON ON OFF ON OFF ON < TTSD clock H L ON ON ON ON ON OFF < TTSD clock H H ON ON ON ON ON ON ≥ TTSD L or H L L OFF OFF OFF OFF OFF OFF ≥ TTSD L or H L H ON ON OFF OFF OFF OFF ≥ TTSD L or H H L ON ON OFF OFF OFF OFF ≥ TTSD L or H H H ON ON OFF OFF OFF OFF ≥ TTSD clock L L OFF OFF OFF OFF OFF OFF ≥ TTSD clock L H ON ON OFF OFF OFF OFF ≥ TTSD clock H L ON ON OFF OFF OFF OFF ≥ TTSD clock H H ON ON OFF OFF OFF OFF

Document Number: 002-03341 Rev.*C Page 18 of 38 S6BP401A 10. Function

10.1 Turning ON and OFF Sequence

When all of the enable input terminals (EN1, EN2, EN3, EN4, ENL1 and ENL2) are “Low”, the device is in shutdown state. When any one or more than one of them go “High,” the device is initialized, then the internal linear regulator (VREG) starts generating 1.8V internal supply voltage. After that, each DC/DC converters and LDOs state is transitioned to the state which can be started. In order for the device to start, the VCC terminal voltage must be higher than the under-voltage lockout threshold (VUVLOF + VUVHYS). Figure 10-1 depicts the turning-on and off sequence where the enable signals are connected to VCC. Figure 10-2 depicts that where the enable signals are respectively controlled after the IC is powered. Figure 10-1 Turning ON and OFF Sequence (where EN1 and ENL1 are Connected to VCC) *1: Given that the system employs the same external parts with those specified in “11. Application Circuit Example”. Time VRST VVREG VOUTL1 VOUT1 VPGUV+VPGUVHYS VENL1 VEN1 VVCC VRSUV+VRSUVHYS Initialization (TYP:1ms) TRD VUVLOF TYP:40.5ms(*1) 10% 10% TYP:0.92ms(*1) VUVLOF + VUVHYS

Document Number: 002-03341 Rev.*C Page 19 of 38 S6BP401A Figure 10-2 Turning ON and OFF Sequence (where EN1 and ENL1 are Respectively Controlled) *1: Given that the system employs the same external parts with those specified in “11. Application Circuit Example”. Time VRST VVREG VOUTL1 VOUT1 VPGUV+VPGUVHYS VENL1 VEN1 VVCC VRSUV+VRSUVHYS Initialization (TYP:1ms) TRD Initialization (TYP:1ms) 10% 10% TYP:40.5ms(*1) TYP:0.92ms(*1) VUVLOF + VUVHYS

Document Number: 002-03341 Rev.*C Page 20 of 38 S6BP401A

10.2 Over Current Protection

The over current protection of the DC/DC converters detects the inductor peak current with on-resistance of Internal high side switching FET. If the DC/DC converter is over current state, the corresponding output voltage is decreased. If the device returns from over current state, the output voltage is target voltage. Each LDOs equips foldback current limiter in order to prevent the IC itself from being damaged or destroyed. The curve of output current and output voltage in over current state is shown in the Figure 10-3. Figure 10-3 LDO Foldback Over Current Protection Characteristic

10.3 Over Voltage Protection

The over voltage protection of the DC/DC converters detects the output voltage. If the DC/DC converter is over voltage state, the corresponding channel stops switching and inductor connecting terminal (LX1, LX2, LX3, LX4) is held at high impedance. If the device returns from over voltage state, the channel returns switching automatically. Figure 10-4 Over Voltage Protection Timing Chart Current Voltage IOUTL1 IOUTL2 ILIMITL1 ILIMITL2 VOUTL1 VOUTL2 ISL1 ISL2 Time VPG1,VPG2, VPG3,VPG4 TRPG TPPG VEN1,VEN2, VEN3,VEN4 VOUT1,VOUT2, VOUT3,VOUT4 TRPG VPGOVHYS VPGOV Hi-Z ON LX1, LX2, LX3, LX4 Discharge OFF Switching Hi-Z Switching VOVP1, VOVP2, VOVP3, VOVP4 VOVPHYS1, VOVPHYS2, VOVPHYS3, VOVPHYS4

Document Number: 002-03341 Rev.*C Page 21 of 38 S6BP401A

10.4 Thermal Shutdown (TSD)

If the junction temperature reaches +165°C, all DC/DC converters and LDOs stop outputting voltage. Then the discharge operation is carried out to discharge the output capacitor (The discharge operation continues until the state of the thermal shutdown released.) When the junction temperature drops below +155°C, the soft-starters activate regulators and start generating voltage gradually if the enable is "High." Figure 10-5 Thermal Shutdown Timing Chart

10.5 Under Voltage Lockout (UVLO)

If the VCC terminal voltage (VVCC) drops below the lower UVLO threshold (VUVLOF), all DC/DC converters (DD1, DD2, DD3, DD4), LDOs (LD1, LD2), windowed watchdog timer (WDT) and the internal linear regulator (VREG) stop working. When the VCC terminal voltage (VVCC) is raised higher than the higher UVLO threshold (VUVLOF + VUVHYS), the device returns automatically.

10.6 Soft-Start Operation

S6BP401A equips load-independent soft-start function in order to prevent the DC/DC converters and LDOs from having rush current at the start-up. The soft-start timing is shown in the Figure 10-6, and is given by the following equation; 𝑇𝑆𝑆 = 𝑉𝑂𝑈𝑇 ×𝑇𝐶𝑂𝐸𝑆𝑆, where TSS [ms] : Soft-start time VOUT [V] : Output voltage (VOUT1, VOUT2, VOUT3, VOUT4, VOUTL1, VOUTL2) TCOESS [ms/V] : Soft-start time coefficient (TCOESS1, TCOESS2, TCOESS3, TCOESS4, TCOESSL1, TCOESSL2) 165 deg. 155 deg.TJ VEN1 VOUT1 Time Soft-Start Soft-Start

Document Number: 002-03341 Rev.*C Page 22 of 38 S6BP401A Figure 10-6 Soft-Start Operation Timing Chart

10.7 Discharge Operation

When an enable signal goes “Low”, the corresponding output capacitor is discharged by the internal discharge resistor and the output voltage is decreased gradually. Note that the discharge time is not consistent: it depends on the output load current. As for a DC/DC converter, the output capacitor is discharged from FB1, FB2, FB3 and FB4 terminal to PGND1, PGND2, PGND3 and PGND4 terminal respectively. As for a LDO, the output capacitor is dis-charged from LDO1, LDO2 terminal to GND terminal. The discharge time required to decrease the output voltage by 90% without any explicit load given by the following equation; 𝑇𝐷𝐼𝑆 = 2.3×𝑅𝐷𝐼𝑆 ×𝐶𝑂𝑈𝑇, where TDIS [ms] : Discharge time RDIS [kΩ] : Discharge resistance (RDIS1, RDIS2, RDIS3, RDIS4, RDISL1, RDISL2) COUT [µF] : Output capacitor Figure 10-7 Discharge Diagram (DC/DC Converter) enable Error Amp. PWM Control Power Supply PVCC1,PVCC2, PVCC3,PVCC4 LX1,LX2, LX3,LX4 PGND1,PGND2, PGND3,PGND4 FB1,FB2, FB3,FB4 RDIS1, RDIS2, RDIS3, RDIS4 VEN VOUT Time TSS=VOUT (1)×TCOESS VOUT (1) VOUT (2) VOUT (3) TSS=VOUT (2)×TCOESS TSS=VOUT (3)×TCOESS

Document Number: 002-03341 Rev.*C Page 23 of 38 S6BP401A Figure 10-8 Discharge Diagram (LDO)

10.8 Power Good Monitor and Reset Function

Each DC/DC converters and LDOs has power good function to indicate whether the output voltage is in the expected range. The Table 10-1 describes the power good pin names and their functions of each DC/DC converters and LDOs. The Figure 10-9 and Figure 10-10 depict power-good timing chart. Table 10-1 Power Good Monitor and Reset Function Pin List Channel Pin Name Description DD1 PG1 Enabling DD1 is followed by rising of the DD1 output voltage (VOUT1). Once VOUT1 reaches within the power good range (VPGUV + VPGUVHYS < VOUT1 < VPGOV – VPGOVHYS), the power good monitor output (PG1 terminal) changes its state from “Low” to “Open” after a power-on-reset time (TRPG). When VOUT1 is out of the power good range (VOUT1 ≤ VPGUV or VOUT1 ≥ VPGOV), PG1 terminal changes its state from “Open” to “Low” after the propagation delay (TPPG). The glitch within TPPG does not affect the power good monitor output. DD2 PG2 Enabling DD2 is followed by rising of the DD2 output voltage (VOUT2). Once VOUT2 reaches within the power good range (VPGUV + VPGUVHYS < VOUT2 < VPGOV – VPGOVHYS), the power good monitor output (PG2 terminal) changes its state from “Low” to “Open” after a power-on-reset time (TRPG). When VOUT2 is out of the power good range (VOUT2 ≤ VPGUV or VOUT2 ≥ VPGOV), PG2 terminal changes its state from “Open” to “Low” after the propagation delay (TPPG). The glitch within TPPG does not affect the power good monitor output. DD3 PG3 Enabling DD3 is followed by rising of the DD3 output voltage (VOUT3). Once VOUT3 reaches within the power good range (VPGUV + VPGUVHYS < VOUT3 < VPGOV – VPGOVHYS), the power good monitor output (PG3 terminal) changes its state from “Low” to “Open” after a power-on-reset time (TRPG). When VOUT3 is out of the power good range (VOUT3 ≤ VPGUV or VOUT3 ≥ VPGOV), PG3 terminal changes its state from “Open” to “Low” after the propagation delay (TPPG). The glitch within TPPG does not affect the power good monitor output. DD4 PG4 Enabling DD4 is followed by rising of the DD4 output voltage (VOUT4). Once VOUT4 reaches within the power good range (VPGUV + VPGUVHYS < VOUT4 < VPGOV – VPGOVHYS), the power good monitor output (PG4 terminal) changes its state from “Low” to “Open” after a power-on-reset time (TRPG). When VOUT4 is out of the power good range (VOUT4 ≤ VPGUV or VOUT4 ≥ VPGOV), PG4 terminal changes its state from “Open” to “Low” after the propagation delay (TPPG). The glitch within TPPG does not affect the power good monitor output. enable Power Supply PVCCL1,PVCCL2 LDO1,LDO2 RDISL1, RDISL2

Document Number: 002-03341 Rev.*C Page 25 of 38 S6BP401A

10.9 Watchdog Timer

S6BP401A employs a digital windowed watchdog timer. The digital windowed watchdog timer starts monitoring trigger signal, when the LD1 output voltage (VOUTL1) reaches the power good level after enabling LD1. Figure 10-11 shows the state diagram of the digital watchdog timer. There are six states in the diagram. In the normal operation, the state is expected to move back and forth between “CW” and “OW”, At first, as described in the section 10.8, enabling LD1 brings “RESET” state, and the “RESET” state is kept for the “Reset Time (TRD)” outputting “Low” from RST terminal. In the second, after TRD in the “RESET” state, the state will transition to “Ignore Window (IW)”, and let RST terminal be “Open”. The “IW” state will be elapsed in the “Ignore Window Time (TIW.)” In the third, after elapsing, the state will transition will transition to “Long Open Window (LOW)” state, and let RST terminal be “Open.” In this state, a trigger signal is expected to be input: if an input trigger arrives, the state will immediately transition to the “Closed Window (CW)” state. Without an input trigger in the “Long Open Window Time (TLOW,)” the state will be elapsed and will transition to “RESET” state. In the “CW” state, a trigger signal is expected NOT to be input: if an input trigger arrives, the state will immediately transition to the “RESET” state. Without an input trigger in the “Closed Window Time (TCW,)” the state will be elapsed and will transition to “Open Window (OW)” state. In the “OW” state, a trigger signal is expected NOT to be input: if an input trigger arrives, the state will immediately transition to the “RESET” state. Without an input trigger in the “Open Window Time (TOW,)” the state will be elapsed and will transition to “Closed Window (CW)” state. In any states above, a power failure of LD1 will cause a transition to “OFF” state, and output “Low” from RST terminal until LD1 goes well. Figure 10-11 Watchdog Timer State Diagram OFF RST=Low Reset RST=Low IW RST=open Long OW RST=open OW RST=open CW RST=open LD1 power failLD1 power fail LD1 power fail Trigger LD1 power fail No Trigger (TOW timeout) Trigger No Trigger (TCW timeout) LD1 power good TRD timeout TIW timeout Trigger No Trigger (TLOW timeout) LD1 power fail

Document Number: 002-03341 Rev.*C Page 27 of 38 S6BP401A Figure 10-14 De-glitch of Window Watchdog Trigger Pulse Window Time Closed Window Open Window Closed Window TOWTCW TCW TSAM H H L L H H L L H H L L H H L L : Sampling point Valid Valid Not ValidNot Valid Watchdog Trigger Pulse L H L L H H L HNot Valid Not Valid

Document Number: 002-03341 Rev.*C Page 28 of 38 S6BP401A

10.10 Internal Linear Regulator Output (VREG)

S6BP401A equips a 1.8V linear regulator as the power source for its internal circuit. A low ESR 1.0µF ceramic capacitor should be connected from VREG pin to GND. VREG is not designed to supply to external load. Unless the VREG terminal voltage is in the range between the over voltage lockout level VVREGOVR and the under voltage lockout level VVREGUVF, S6BP401A considers it abnormal and halts all DC/DC converters, LDOs and windowed watchdog timer. When the VREG terminal voltage returns to the power good voltage range (VVREGUVR ≤ VVREG ≤ VVREGOVF), S6BP401A returns the DC/DC converters, LDOs and window watchdog timer to the normal mode. Soft-start circuits of each regulator gradually generates supply voltage as described in the section 10.6. Figure 10-15 VREG OVLO/UVLO Timing Chart VVREG Time VVREGUVF VVREGOVR VVREGOVF VVREGUVR VEN1,VEN2, VEN3,VEN4, VENL1,VENL2 VOUT1 Soft-Start Soft-StartSoft-Start VOUT2 Soft-Start Soft-StartSoft-Start VOUT3 Soft-Start Soft-StartSoft-Start VOUT4 Soft-Start Soft-StartSoft-Start VOUTL1 Soft-Start Soft-StartSoft-Start VOUTL2 Soft-Start Soft-StartSoft-Start Initialization Initialization Initialization

Document Number: 002-03341 Rev.*C Page 29 of 38 S6BP401A 11. Application Circuit Example Figure 11-1 Application Circuit Example PVCC1 29 LX1 28 PGND1 27 PVCC2a 21PVCC2b 22 LX2a 23LX2b 24 PGND2a 25PGND2b 26 PVCC3 8 LX3 7 PGND3 6 PVCC4 3 LX4 4 PGND4 5 PVCCL1 36 LDO1 35 PVCCL2 37 LDO2 38 PG1 33 PG2 31 PG3 10 PG4 1 PGL2 40 RST 13 WDI 12 FB130 FB220 FB39 FB42 EN119 EN218 EN317 EN416 ENL115 ENL214 VCC34 VREG32 SYNC11 GND39 EP41 CP142 CP243 CP344 CP445 S6BP401A VIN VIN VIN VIN VIN VIN VOUT1 VOUT2 VOUT3 VOUT4 VOUTL1 VOUTL2 VOUT1 VOUT2 VOUT3 VOUT4 RST WDI VOUTL1 or VIN VOUT4 or VIN R10 C31 C15 C21 C27 C28 C30 C33 C34 C16 C17 C22 C23 C10 PG1 PG2 PG3 PG4 PGL2 EN1 EN2 EN3 EN4 ENL1 ENL2 VOUT1 VOUT2 VOUT3 VOUT4 VOUTL1 VOUTL2 VIN GND

Document Number: 002-03341 Rev.*C Page 30 of 38 S6BP401A Table 11-1 Parts list Symbol Parts Part number Specifications Vendor C1 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C2 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C3 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C7 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C8 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C9 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C10 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C15 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C16 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C17 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C21 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C22 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C23 Ceramic Capacitor CGA6P1X7R1C226M250AC 22 µF TDK C27 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK C28 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK C30 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK C31 Ceramic Capacitor CGA5L1X7R1C106K160AC 10 µF TDK C33 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK C34 Ceramic Capacitor CGA3E1X7R1C105M080AC 1 µF TDK L1 Inductor CLF6045T-1R5N-D 1.5 µH TDK L2 Inductor CLF6045T-1R5N-D 1.5 µH TDK L3 Inductor CLF6045T-1R5N-D 1.5 µH TDK L4 Inductor CLF6045T-1R5N-D 1.5 µH TDK R5 Resistor RG1608P-473-B 47 kΩ SSM R6 Resistor RG1608P-473-B 47 kΩ SSM R7 Resistor RG1608P-473-B 47 kΩ SSM R8 Resistor RG1608P-473-B 47 kΩ SSM R9 Resistor RG1608P-473-B 47 kΩ SSM R10 Resistor RG1608P-473-B 47 kΩ SSM TDK : TDK Corporation SSM : SUSUMU CO., LTD.

Document Number: 002-03341 Rev.*C Page 31 of 38 S6BP401A 12. Reference Data The followings are the reference data measured under the conditions shown in ”11. Application Circuit Example”. Figure 12-1 DC/DC Converter DD1 Efficiency [%] IOUT1 [A] 100 S6BP401AGraph002 DD1 Efficiency vs IOUT1 VVCC = VPVCC1 = 5.0V 10.10.010.001 Preset output voltage = 1.250V TA = +25oC TA = －40oC TA = +125oC VOUT1 [V] IOUT1 [A] 1.200 2.0 S6BP401AGraph003 1.230 DD1 Load Regulation VVCC = VPVCC1 = 5.0V 1.220 1.210 1.240 1.250 1.260 1.270 1.280 Preset output voltage = 1.250V 1.61.20.2 0.6 TA = +125oC TA = +25oC TA = －40oC VVCC = VPVCC1 = 5.0V, TA = +25oC, Preset output voltage = 1.250V 10 µs/div S6BP401AGraph008 IOUT1

2 A/div

DD1 Load Transient Response VPG1 10V/div VOUT1 20 mV/div Offset 1.250V 10 µs/div S6BP401AGraph0081 IOUT1 DD1 Load Transient Response VPG1 10V/div VOUT1 20 mV/div Offset 1.250V VVCC = VPVCC1 = 5.0V, TA = +25oC, Preset output voltage = 1.250V TA = +25oC TA = －40oC DD2 Efficiency [%] IOUT2 [A] 100 S6BP401AGraph011 DD2 Efficiency vs IOUT2 VVCC = VPVCC2 = 5.0V 10.10.010.001 Preset output voltage = 1.125V TA = +125oC VOUT1 [V] IOUT2 [A] 1.080 3.0 S6BP401AGraph012 1.110 DD2 Load Regulation VVCC = VPVCC2 = 5.0V 1.100 1.090 1.120 1.130 1.140 1.150 1.160 Preset output voltage = 1.125V TA = +125oC TA = +25oC TA = －40oC VVCC = VPVCC2 = 5.0V, TA = +25oC, Preset output voltage = 1.125V 10 µs/div S6BP401AGraph017 IOUT2 DD2 Load Transient Response VPG2 10V/div VOUT2 20 mV/div Offset 1.125V 10 µs/div S6BP401AGraph0171 IOUT2 DD2 Load Transient Response VPG2 10V/div VOUT2 20 mV/div Offset 1.125V VVCC = VPVCC2 = 5.0V, TA = +25oC, Preset output voltage = 1.125V TA = +25oC TA = －40oC DD3 Efficiency [%] IOUT3 [A] 100 S6BP401AGraph020 DD3 Efficiency vs IOUT3 VVCC = VPVCC3 = 5.0V 10.10.010.001 Preset output voltage = 2.550V TA = +125oC

Document Number: 002-03341 Rev.*C Page 32 of 38 S6BP401A VOUT3 [V] IOUT3 [A] 2.500 2.0 S6BP401AGraph021 2.530 DD3 Load Regulation VVCC = VPVCC3 = 5.0V 2.520 2.510 2.540 2.550 2.560 2.570 2.580 Preset output voltage = 2.550V 1.4 1.80.4 0.6 TA = +125oC TA = +25oC TA = －40oC VVCC = VPVCC3 = 5.0V, TA = +25oC, Preset output voltage = 2.550V 10 µs/div S6BP401AGraph026 IOUT3 DD3 Load Transient Response VPG3 10V/div VOUT3 50 mV/div Offset 2.550V 10 µs/div S6BP401AGraph0261 IOUT3 DD3 Load Transient Response VPG3 10V/div VOUT3 50 mV/div Offset 2.550V VVCC = VPVCC3 = 5.0V, TA = +25oC, Preset output voltage = 2.550V DD4 Efficiency [%] IOUT4 [A] 100 S6BP401AGraph029 DD4 Efficiency vs IOUT4 VVCC = VPVCC4 = 5.0V 10.10.010.001 Preset output voltage = 3.375V TA = +125oC TA = +25oC TA = －40oC VOUT4 [V] IOUT4 [A] 3.320 1.0 S6BP401AGraph030 3.350 DD4 Load Regulation VVCC = VPVCC4 = 5.0V 3.340 3.330 3.360 3.370 3.380 3.390 3.400 0.60.50.30.10 TA = +125oC TA = +25oC TA = －40oC Preset output voltage = 3.375V VVCC = VPVCC4 = 5.0V, TA = +25oC, Preset output voltage = 3.375V 10 µs/div S6BP401AGraph035 IOUT4

1 A/div

DD4 Load Transient Response VPG4 10V/div VOUT4 50 mV/div Offset 3.375V 10 µs/div S6BP401AGraph0351 IOUT4 DD4 Load Transient Response VPG4 10V/div VOUT4 50 mV/div Offset 3.375V VVCC = VPVCC4 = 5.0V, TA = +25oC, Preset output voltage = 3.375V fOSC [MHz] 2.00 S6BP401AGraph0531 fOSC vs VVCC 2.04 2.08 2.16 VVCC [V] 2.06 2.02 2.10 2.12 2.14 TA = －40oC TA = +25oC TA = +125oC

Document Number: 002-03341 Rev.*C Page 33 of 38 S6BP401A Figure 12-2 LDO regulator VOUTL1 [V] IOUTL1 [A] 3.300 0.2 S6BP401AGraph038 3.330 LD1 Load Regulation VVCC = VPVCCL1 = 5.0V 3.320 3.310 3.340 3.350 3.360 3.370 3.380 0.10.050 0.15 TA = +25oC TA = －40oC TA = +125oC Preset output voltage = 3.325V VVCC = VPVCCL1 = 5.0V, TA = +25oC, Preset output voltage = 3.325V 10 µs/div S6BP401AGraph043 IOUTL1

0.2 A/div

LD1 Load Transient Response VRST 10V/div VOUTL1 50 mV/div Offset 3.325 400 µs/div S6BP401AGraph0431 IOUTL1 LD1 Load Transient Response VRST 10V/div VOUTL1 50 mV/div Offset 3.325V VVCC = VPVCCL1 = 5.0V, TA = +25oC, Preset output voltage = 3.325V VOUTL2 [V] IOUTL2 [A] 2.770 0.5 S6BP401AGraph045 2.800 LD2 Load Regulation VVCC = VPVCCL2 = 5.0V 2.790 2.780 2.810 2.820 2.830 2.840 2.850 0.30.10 0.4 TA = +25oC TA = －40oC TA = +125oC Preset output voltage =2.800V 0.2 VVCC = VPVCCL2 = 5.0V, TA = +25oC, Preset output voltage = 2.800V 10 µs/div S6BP401AGraph050 IOUTL2

0.5 A/div

LD2 Load Transient Response VPGL2 10V/div VOUTL2 20 mV/div Offset 2.800V 400 µs/div S6BP401AGraph0501 IOUTL2 LD2 Load Transient Response VPGL2 10V/div VOUTL2 20 mV/div Offset 2.800V VVCC = VPVCCL2 = 5.0V, TA = +25oC, Preset output voltage = 2.800V

Document Number: 002-03341 Rev.*C Page 34 of 38 S6BP401A 13. Ordering Information Table 13-1 Ordering information Part Number (MPN) (*1) Output Voltage [V] Package DD1 DD2 DD3 DD4 LD1 LD2 Plastic, QFN (0.50 mm pitch), 40-pin (VND040) MPN: Marketing Part Number *1: Please contact our sales division for the output voltage combination not mentioned in this table. Part Numbering Conventions These ICs follow the part numbering convention described in the following table. Each single-character is alphanumeric (0, 1, 2, …, 9, A, B, …, Z) unless stated otherwise. The part numbers are defined as follows. S 6B P 4 0 1 A XX S N1 B 0 0 0 Fixed on 000 Packing: B = 13 inch Tape and Reel Package: N1 = QFN, Pd-PPF/Low-Halogen Reliability Grade: S = 10 ppm Preset Condition Revision: A = 1st Revision Product ID: 01 Topology: 4 = Switch-Mode Power Supply Product Type: P = Power Management IC Product Class: 6B = Automotive Analog Company ID: S = Cypress

Document Number: 002-03341 Rev.*C Page 35 of 38 S6BP401A 14. Package Dimensions

Document Number: 002-03341 Rev.*C Page 36 of 38 S6BP401A 15. Major Changes Spansion Publication Number: S6BP401A_DS405-00024 Page Section Change Results Revision 0.1 (February 19, 2015) - - Initial release NOTE: Please see “Document History” about later revised information. Document History Document Title: S6BP401A Power Management IC for Automotive ADAS Platform Document Number: 002-03341 Revision ECN Orig. of Change Submission Date Description of Change ** 4922113 YMAE 09/16/2015 New Spec. Updated Ordering Information *A 5085035 HIXT 01/14/2016 Updated “3. Pin Functions” Updated “6. Absolute Maximum Ratings” Updated “7. Recommended Operating Conditions” Added “Development Support” Added “12. Reference Data” Updated “13. Ordering Information” *B 5160391 HIXT 03/04/2016 Added “AEC-Q100 compliant (Grade-1)” in “Features” Added the following values in “8. Electrical Characteristics” Supply Current IVCCS: Max value UVLO: Under Voltage Lockout (VCC) VUVHYS: Min and Max values Enable Inputs (EN1, EN2, EN3, EN4, ENL1, ENL2) IIHEN: Min and Max values Synchronization Input (SYNC) IIHSYNC: Min and Max values Power Good Monitor (PG1, PG2, PG3, PG4, PGL2, RST) VPGOVHYS: Min and Max values VPGUVHYS: Min and Max values Watchdog Timer (WDI) TWD: Min and Max values IIHWDI: Min and Max values DD1: Buck DC/DC Converter RFB1: Min and Max values RONHS1: Max values RONLS1: Max values ILEAK1: Max value VOVPHYS1: Min and Max values RDIS1: Min and Max values TCOESS1: Min and Max values DD2: Buck DC/DC Converter RFB2: Min and Max values RONHS2: Max values RONLS2: Max values

Document Number: 002-03341 Rev.*C Page 37 of 38 S6BP401A Revision ECN Orig. of Change Submission Date Description of Change *B 5160391 HIXT 03/04/2016 ILEAK2: Max value VOVPHYS2: Min and Max values RDIS2: Min and Max values TCOESS2: Min and Max values DD3: Buck DC/DC Converter RFB3: Min and Max values RONHS3: Max values RONLS3: Max values ILEAK3: Max value VOVPHYS3: Min and Max values RDIS3: Min and Max values TCOESS3: Min and Max values DD4: Buck DC/DC Converter RFB4: Min and Max values RONHS4: Max values RONLS4: Max values ILEAK4: Max value VOVPHYS4: Min and Max values RDIS4: Min and Max values TCOESS4: Min and Max values LD1: LDO Regulator ILEAKL1: Max value RDISL1: Min and Max values TCOESSL1: Min and Max values LD2: LDO Regulator ILEAKL2: Max value RDISL2: Min and Max values TCOESSL2: Min and Max values Updated the following values in “8. Electrical Characteristics” DD1: Buck DC/DC Converter RONHS1: Typ value RONLS1: Typ value DD2: Buck DC/DC Converter RONHS2: Typ value RONLS2: Typ value DD3: Buck DC/DC Converter RONHS3: Typ value RONLS3: Typ value DD4: Buck DC/DC Converter RONHS4: Typ value RONLS4: Typ value Delete the following values in “8. Electrical Characteristics” Updated “Figure 10-1” and “Figure 10-2” Updated “10.5 Under Voltage Lockout (UVLO)” Added a part number, S6BP401AL2SN1B000, in “Table 13-1”. Corrected an error in “Table 13-1”. from S6BP401AW1SN1B000 to S6BP401AW0SN1B000 *C 5396389 HIXT 08/09/2016 Deleted “Development Support” and added “More Information” Added “S6BP401AY2SN1B000” to “Table 13-1 Ordering information”

Document Number: 002-03341 Rev.*C August 9, 2016 Page 38 of 38 S6BP401A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Lighting & Power Control cypress.com/powerpsoc Memory cypress.com/memory PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF cypress.com/wireless PSoC® Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training | Components Technical Support cypress.com/support ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. © Cypress Semiconductor Corporation, 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non -exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for S oftware provided in source code f orm, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organiza tion, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through reselle rs and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for u se with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICUL AR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to thi s document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design inform ation or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the ope ration of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (incl uding resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses whe re the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical comp onent is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall ind emnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ -USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brand s may be claimed as property of their respective owners.

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