S6BP202A5JST2B00A

S6BP202A CYPRESS | Alldatasheet

Document overview

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• PDF pages: 20

Technical content

Datasheet sections

• 8.1 Block Description
• 8.2 Protection Function Table
• 10.1 Setting the Operation Conditions

Features

 Wide input voltage range: 2.5V to 42V  Selectable output voltage (factory settable):  Wide operating frequency range: 200 kHz to 2.1 MHz  External synchronized clock range: 200 kHz to 400 kHz  SYNC function (factory settable)  SYNC_IN: External clock input (Unless inputting clock, this IC operates by internal clock )  SYNC_OUT: Internal clock output  Super-high efficiency by PFM operation (When setting MODE pin to a low level )  Automatic PWM/PFM switching operation and fixed PWM operation are selectable by MODE pin  Built-in switching FET  Synchronous current mode architecture  Shutdown current: Lower than 1 µA  Quiescent current: 20 µA  Power Good Monitor  Output voltage monitoring by window comparator  Power-on reset time (factory settable): 7 µs, 14 ms  Soft start time without load dependence: 0.9 ms (When switching frequency = 2.1 MHz)  Enhanced protection functions  Input UVLO  Output UVP (factory settable): 92.0%, 95.5%  Output OVP (factory settable): 108.0%, 104.5%  Output OVC  Thermal shutdown  Small ETSSOP16 package (exposed PAD): 5 mm × 6.4 mm  AEC-Q100 compliant (Grade-1)

Applications

 Instrument cluster  Advanced driver assistance systems (ADAS)  Gateway module  Automotive applications  Industrial applications Block Diagram Buck- Boost DC/DC Converter

2.1 MHz

5V LDO, Enable OSC, External SYNC Protection Battery 2.5-42V Enable Power Good PWM/PFM External Clock for Frequency Setting Synchronization / Switch GND S6BP202A 5V / 2.4A Internal Clock Output

Document Number: 002-08496 Rev. *D Page 2 of 20 S6BP202A More Information Cypress provides a wealth of data at www.cypress.com/pmic to help you to select the right PMIC device for your design, and to help you to quickly and effectively integrate the device into your design. Following is an abbreviated list for S6BP202A.  Overview: Automotive PMIC Portfolio, Automotive PMIC Roadmap  Product Selector:  S6BP202A: 1-Ch Buck -Boost Automotive PMIC  Application Notes: Cypress offers S6BP202A application notes. Recommended application notes for getting started with S6BP202A are:  AN99497: Designing a Power Management System with S6BP201A, S6BP202A, and S6BP203A  AN201006: Thermal Considerations and Parameters  Evaluation Kit Operation Manual:  S6SBP202A1FVA1001: Power block of automotive instrument cluster  Related Products:  S6BP201A, S6BP203A: 1-Ch Buck -Boost Automotive PMIC  S6BP401A: 6-Ch Automotive PMIC for ADAS  S6BP501A, S6BP502A : 3-Ch Automotive PMIC for Instrument Cluster

Document Number: 002-08496 Rev. *D Page 4 of 20 S6BP202A 1. Product Lineup The VOUT output voltage, SYNC function, VOUT UVP threshold, VOUT OVP threshold, power-on reset time of this product are set at the factory shipment. To order a product, select an item from the product lineup blow. Part Number (MPN) Order Code VOUT Output Voltage [V] SYNC Function VOUT UVP Threshold [%] VOUT OVP Threshold [%] Power-on Reset Time[s] Falling (Typ) Rising(Typ) Rising (Typ) Falling (Typ) S6BP202A1BST2B00A 1B 5.000 SYNC_IN 92.0 93.0 108.0 107.0 7.0µ S6BP202A1CST2B00A 1C SYNC_OUT S6BP202A1DST2B00A 1D SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A1EST2B00A 1E SYNC_OUT S6BP202A1FST2B00A 1F SYNC_IN 92.0 93.0 108.0 107.0 14.0m S6BP202A1GST2B00A 1G SYNC_OUT S6BP202A1HST2B00A 1H SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A1JST2B00A 1J SYNC_OUT S6BP202A2BST2B00A 2B 5.050 SYNC_IN 92.0 93.0 108.0 107.0 7.0µ S6BP202A2CST2B00A 2C SYNC_OUT S6BP202A2DST2B00A 2D SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A2EST2B00A 2E SYNC_OUT S6BP202A2FST2B00A 2F SYNC_IN 92.0 93.0 108.0 107.0 14.0m S6BP202A2GST2B00A 2G SYNC_OUT S6BP202A2HST2B00A 2H SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A2JST2B00A 2J SYNC_OUT S6BP202A3BST2B00A 3B 5.075 SYNC_IN 92.0 93.0 108.0 107.0 7.0µ S6BP202A3CST2B00A 3C SYNC_OUT S6BP202A3DST2B00A 3D SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A3EST2B00A 3E SYNC_OUT S6BP202A3FST2B00A 3F SYNC_IN 92.0 93.0 108.0 107.0 14.0m S6BP202A3GST2B00A 3G SYNC_OUT S6BP202A3HST2B00A 3H SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A3JST2B00A 3J SYNC_OUT S6BP202A4BST2B00A 4B 5.100 SYNC_IN 92.0 93.0 108.0 107.0 7.0µ S6BP202A4CST2B00A 4C SYNC_OUT S6BP202A4DST2B00A 4D SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A4EST2B00A 4E SYNC_OUT S6BP202A4FST2B00A 4F SYNC_IN 92.0 93.0 108.0 107.0 14.0m S6BP202A4GST2B00A 4G SYNC_OUT S6BP202A4HST2B00A 4H SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A4JST2B00A 4J SYNC_OUT S6BP202A5BST2B00A 5B 5.125 SYNC_IN 92.0 93.0 108.0 107.0 7.0µ S6BP202A5CST2B00A 5C SYNC_OUT S6BP202A5DST2B00A 5D SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A5EST2B00A 5E SYNC_OUT S6BP202A5FST2B00A 5F SYNC_IN 92.0 93.0 108.0 107.0 14.0m S6BP202A5GST2B00A 5G SYNC_OUT S6BP202A5HST2B00A 5H SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A5JST2B00A 5J SYNC_OUT S6BP202A6BST2B00A 6B 5.150 SYNC_IN 92.0 93.0 108.0 107.0 7.0µ S6BP202A6CST2B00A 6C SYNC_OUT S6BP202A6DST2B00A 6D SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A6EST2B00A 6E SYNC_OUT S6BP202A6FST2B00A 6F SYNC_IN 92.0 93.0 108.0 107.0 14.0m S6BP202A6GST2B00A 6G SYNC_OUT S6BP202A6HST2B00A 6H SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A6JST2B00A 6J SYNC_OUT

Document Number: 002-08496 Rev. *D Page 5 of 20 S6BP202A Part Number (MPN) Order Code VOUT Output Voltage [V] SYNC Function VOUT UVP Threshold [%] VOUT OVP Threshold [%] Power-on Reset Time[s] Falling (Typ) Rising(Typ) Rising (Typ) Falling (Typ) S6BP202A7BST2B00A 7B 5.200 SYNC_IN 92.0 93.0 108.0 107.0 7.0µ S6BP202A7CST2B00A 7C SYNC_OUT S6BP202A7DST2B00A 7D SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A7EST2B00A 7E SYNC_OUT S6BP202A7FST2B00A 7F SYNC_IN 92.0 93.0 108.0 107.0 14.0m S6BP202A7GST2B00A 7G SYNC_OUT S6BP202A7HST2B00A 7H SYNC_IN 95.5 96.5 104.5 103.5 S6BP202A7JST2B00A 7J SYNC_OUT MPN: Marketing Part Number 2. Pin Assignment Figure 2-1 Pin Assignment (Top view) EP: GND PGND1 LX1 PVIN BST VIN ENA MODE VCC PGND2 LX2 VOUT FB RT SYNC PG GND (SEC016) 3. Pin Descriptions Table 3-1 Pin Descriptions Pin No. Pin Name I/O Description

1 PGND1 − GND pin for built-in switching FET

2 LX1 O Inductor connection pin

3 PVIN I Power supply pin for PWM controller and switching FETs

4 BST I BST(Boost) capacitor connection pin

5 VIN I Power supply pin

6 ENA I DC/DC converter enable pin

7 MODE I PWM/PFM operation control pin

8 VCC O VCC capacitor connection pin. LDO output pin of Internal reference voltage

9 GND − GND pin

10 PG O Open drain output pin for power good. When being used, connect PG pin to VCC pin or VOUT pin. When not being used, leave PG pin open.

11 SYNC I/O External clock input pin / Internal clock output pin

For the SYNC pin setting, refer to "10.1 Setting the Operation Conditions"

12 RT O Timing resistor connection pin for internal clock (switching frequency)

For the resistance, refer to "10.1 Setting the Operation Conditions"

13 FB I Output voltage feedback pin

14 VOUT O DC/DC converter output pin

15 LX2 O Inductor connection output pin.

16 PGND2 − GND pin for built-in switching FET

EP GND − GND pin

Document Number: 002-08496 Rev. *D Page 6 of 20 S6BP202A Figure 3-1 I/O Pin Equivalent Circuit Diagram <VIN pin, PVIN pin> 5VIN 16PGND2 3PVIN 9GND 1PGND1 <LX1 pin, BST pin> 3PVIN 1PGND1 8VCC

4 BST

2 LX1

<VOUT pin, LX2 pin> 16PGND2

14 VOUT

15 LX2

<VCC pin> 9GND 13 FB

8 VCC

<FB pin> 13FB 9GND <PG pin> 9GND 10 PG <ENA pin> 5VIN 6ENA 9GND <MODE pin> 8VCC 7MODE 9GND <SYNC pin> 8VCC 11SYNC 9GND <RT pin> 8VCC 9GND 12 RT

Document Number: 002-08496 Rev. *D Page 7 of 20 S6BP202A 4. Architecture Block Diagram Figure 4-1 Architecture Block Diagram SYNC BGR5V LDO VIN UVLO TSD LS Slope Boost Mode Pulse PWM Logic Bypass SW VCC UVLO OSC VIN5 ENA6 GND9 ck 13FB VOUT14VOUT 15LX2 FB VIN LS ck ICMP PFMCMP VCC PGND11 PG 12RT 8VCC High Side FET2 Low Side FET2 16PGND2 Low Side FET1 High Side FET1 BST4 LX12 PVIN3 VIN SYNC MODE 11SYNC 7MODE ErrAMP 10PG Buck-Boost DC/DC Converter

Document Number: 002-08496 Rev. *D Page 8 of 20 S6BP202A 5. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Min Max Power supply voltage (*1) VVIN VIN pin −0.3 +48.0 V VPVIN PVIN pin −0.3 +48.0 V VVCC VCC pin −0.3 +6.9 V Terminal voltage(*1) VBST BST pin −0.3 +48.0 V VLX1 LX1 pin −2.0 +48.0 V VLX2 LX2 pin −2.0 +6.9 V VFB FB pin −0.3 VVCC V VRT RT pin −0.3 VVCC V VMODE MODE pin −0.3 VVCC V VSYNC SYNC pin −0.3 VVCC V VENA ENA pin −0.3 +48.0 V VPG PG pin −0.3 +6.9 V Difference voltage(*1) VBST-LX Between BST–LX1 pins −0.3 +6.9 V VGND Between GND–PGND1 pins, Between GND–PGND2 pins −0.3 +0.3 V PG output current IPG PG pin −3 0 mA Power dissipation (*1) PD Ta ≤ ±25°C 0 3324 (*2) mW Storage temperature TSTG − −55 +150 °C *1: When PGND1 = PGND2 = GND = 0V *2: When the product is mounted on 76.2 mm × 114.3 mm, four-layer FR-4 board Warning: 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. 6. Recommended Operating Conditions Parameter Symbol Condition Value Unit Min Typ Max Power supply voltage (*1) VVIN VIN pin At start-up 5.0 12.0 42.0 V After start-up 2.5 12.0 42.0 V Terminal voltage (*1) VBST BST pin 0.0 − 47.5 V VLX1 LX1 pin −1.0 +12.0 +42.0 V VLX2 LX2 pin −1.0 − +5.5 V VFB FB pin 0.0 − 5.5 V VMODE MODE pin 0.0 − 5.5 V VSYNC SYNC pin 0.0 − 5.5 V VENA ENA pin 0.0 12.0 42.0 V VPG PG pin 0.0 − 5.5 V Difference voltage(*1) VBST-LX1 Between BST−LX1 pins 0.0 − 5.5 V VGND Between GND−PGND1 pins,Between GND−PGND2 pins −0.05 0.00 +0.05 V PG output current IPG PG pin (sink current) 0 − 1 mA BST capacitance CBST Between BST−LX1 pins 0.068 0.100 0.470 µF VCC capacitance CVCC Between VCC−GND pins 2.2 4.7 10.0 µF Timing resistance RRT Between RT−GND pins. When using internal clock 22 − 270 kΩ Operating ambient Temperature Ta − −40 +25 +125 °C *1: When PGND1 = PGND2 = GND = 0V Warning: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Document Number: 002-08496 Rev. *D Page 9 of 20 S6BP202A 7. Electrical Characteristics VIN=PVIN=12V, ENA=5V (Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.) Parameter Symbol Condition Value Unit Min Typ Max Buck-boost DC/DC converter Block VOUT output voltage VVOUT IVOUT = 0A, When VVOUT = 5.000 (*1) 4.925 5.000 5.075 V IVOUT = 0A, When VVOUT = 5.050 (*1) 4.975 5.050 5.125 V IVOUT = 0A, When VVOUT = 5.075 (*1) 4.999 5.075 5.151 V IVOUT = 0A, When VVOUT = 5.100 (*1) 5.024 5.100 5.176 V IVOUT = 0A, When VVOUT = 5.125 (*1) 5.048 5.125 5.201 V IVOUT = 0A, When VVOUT = 5.150 (*1) 5.073 5.150 5.227 V IVOUT = 0A, When VVOUT = 5.200 (*1) 5.122 5.200 5.278 V FB input resistance RFB EN = 0V, Ta = +25°C 3.84 4.80 5.76 MΩ Switching FET on-resistance RHSIDEFET1 LX1 = −30 mA (Between PVIN−LX1) − 150 − mΩ RLSIDEFET1 LX1 = 30 mA (Between LX1−PGND1) − 150 − mΩ RHSIDEFET2 LX2 = −30 mA (Between VOUT−LX2) − 150 − mΩ RLSIDEFET2 LX2 = 30 mA (Between LX2−PGND2) − 150 − mΩ switching FET leakage current ILEAK − − − 5 µA Soft-start time TSS RRT = 22 kΩ 0.855 0.9 0.945 ms Maximum output current IVOUT PVIN ≥ 7.5V, Ta = 25 °C 2.4 (*2) − − A Current limit ILIMT PVIN = 12V, L = 2.2 µH 2.4 (*2) − − A 5V LDO block VCC output voltage VVCC VIN = 12V 4.9 5.0 5.1 V VIN UVLO block VIN UVLO falling threshold VUVLOVINHL VIN input voltage when falling 2.30 2.40 2.50 V VIN UVLO rising threshold VUVLOVINLH VIN input voltage when rising 4.55 4.75 4.95 V VCC UVLO block VCC UVLO falling threshold VUVLOVCCHL VCC input voltage when falling 2.30 2.40 2.50 V VCC UVLO rising threshold VUVLOVCCLH VCC input voltage when rising 4.55 4.75 4.95 V ENA pin Enable condition VENA Enable voltage range 1.10 − VVIN V VDSB Disable voltage range 0.0 − 0.2 V ENA input current IENA VENA = 12V − 1 3 µA MODE pin MODE input voltage VMODE_L Automatic PWM/PFM switching 0.0 − 0.4 V VMODE_H Fixed PWM operation 2.0 − VVOUT V MODE Input current IMODE MODE = 5.0V − 5 10 µA OSC block Switching frequency (SYNC output frequency) FOSC RRT = 22kΩ 2.0 2.1 2.2 MHz RRT = 270kΩ 180 200 220 kHz SYNC block (SYNC_IN/ SYNC_OUT) SYNC input threshold VSYNC_L When selecting SYNC_IN (*1) 0.0 − 0.4 V VSYNC_H When selecting SYNC_IN (*1) 2.0 − VVOUT V SYNC input frequency VSYNC_L When selecting SYNC_IN (*1) 200 − 400 kHz SYNC input duty ratio VSYNC_H When selecting SYNC_IN (*1) +20 +50 +80 % SYNC output frequency FOUTPUT When selecting SYNC_OUT (*1) − FOSC − Hz SYNC output duty ratio FOUTDUTY When selecting SYNC_OUT (*1) +40 +50 +60 % SYNC leakage current ILKSYNC VSYNC = 5.0V, When selecting SYNC_IN (*1) − 5 10 µA PG block (UVP , OVP) VOUT UVP falling threshold PGUVPHL Falling threshold for VOUT output voltage setting (*1) 90.5 92.0 93.5 % 94.0 95.5 97.0 % VOUT UVP rising threshold PGUVPLH Rising threshold for VOUT output voltage setting (*1) 91.5 93.0 94.5 % 95.0 96.5 98.0 % VOUT OVP rising threshold PGOVPLH Rising threshold for VOUT output voltage setting (*1) 106.5 108.0 109.5 % 103.0 104.5 106.0 % VOUT OVP falling threshold PGOVPHL Falling threshold for VOUT output voltage setting (*1) 105.5 107.0 108.5 % 102.0 103.5 105.0 % Leak current ILKPG VPWRGD = 5.0V, VENA = 0V 0 − 1 µA Low level output voltage VOLPG IPGSINK = 1 mA 0.025 0.05 0.15 V Delay time at abnormal detection TPPG At power shutdown − 7(*2) 12(*2) µs Power-on reset time (*1) TRPG At power good − 7(*2) 12(*2) µs 9.1 14.0 18.9 ms

Document Number: 002-08496 Rev. *D Page 10 of 20 S6BP202A Parameter Symbol Condition Value Unit Min Typ Max Thermal shutdown block (TSD) Shutdown temperature TTSDH − − 165 (*2) − °C TTSDL Hysteresis − 10 (*2) − °C Supply current Shutdown current IVINSDN VIN input current, VENA = 0V − 1 5 µA Quiescent current IVINQ VIN input current, VENA = 12V, IVOUT = 0A, MODE/SYNC/PG Pins = OPEN − 20 40 µA *1: Refer to "1. Product Lineup" *2: The electrical characteristic is ensured by statistical characterization and indirect tests. 8. Functional Description

8.1 Block Description

Input Under Voltage Lockout (Input UVLO) The input UVLO is the function that prevents a malfunction of this IC from the following status, and protects poststage devices.  Transitional state at start -up  Momentary drop of power supply voltage To prevent such a malfunction, this protection monitors the VIN input voltage and VCC voltage. When either VIN or VCC voltage falls to the UVLO falling threshold, 2.4V (Typ), or lower, the IC stops the VOUT voltage output and becomes UVLO status. When both VIN and VCC voltages reach the UVLO rising threshold, 4.75V (Typ), or higher, the IC is released from the UVLO state and returns to the normal operation. Output Under Voltage Protection (Output UVP) The output UVP is the function that monitors the voltage drop of the VOUT pin and notifies by the PG pin. When the output voltage falls to the UVP falling threshold (PGUVPHL) for the output voltage setting or lower, the PG voltage is fixed to the low level. The IC becomes the UVP status, but the switching operation is maintained under the UVP status. When the output voltage once again reaches the UVP rising threshold (PGUVPLH) for the output voltage setting or higher, the IC is released from the UVP state and the PG voltage is fixed to the high level. Output Over Voltage Protection (Output OVP) The output OVP is the function that monitors the voltage rise of the VOUT pin and stops the switching operations, which protects poststage devices from overvoltage. Also, the VOUT state is notified by the PG pin. When the output voltage rises to the OVP falling threshold (PGOVPLH) for the output voltage setting or higher, the PG voltage is fixed to the low level. The IC becomes the OVP status, and the switching operations of the high-Side FETs are stopped. When the output voltage once again falls to the OVP falling threshold (PGOVPHL) for the output voltage setting or lower, the IC is released from the OVP state and resumes the switching operations. The PG voltage is fixed to the high level again. Output Over Current Protection (Output OCP) The output OCP is the function that limits the excessive current load and protects poststage devices. Thermal Shutdown (TSD) The TSD is the function that protects the IC from heat-destruction. When the junction temperature reaches +165°C (Typ), the high-side and low-side switching FET are turned off and the IC becomes the TSD status. When the junction temperature once again falls to +155°C (Typ) or lower, the IC is released from the TSD state and restarts the power supply.

Document Number: 002-08496 Rev. *D Page 11 of 20 S6BP202A

8.2 Protection Function Table

The following table shows the state of each pin when each protection function operates. Table 8-1 Protection Function Table Function ENA Pin Setting PG Pin Output DC/DC Converter Operation Remarks Shutdown operation L Hi-Z (*1) Shutdown It is recommended to connect PG pin to VCC pin or VOUT pin via a pull-up resistor. When setting ENA pin to a low level, Both VCC pin and VOUT pin voltages drop to 0V. Therefore, PG pin outputs 0V. Nominal operation H Hi-Z (*1) Switching − Input under voltage protection (Input UVLO) H L Shutdown After releasing UVLO state, this IC is automatically reset with soft start. Output under voltage protection (Output UVP) H L Switching − Output over voltage protection (Output OVP) H L Shutdown − Output over current protection (Output OCP) H L Switching OCP operates to drop the output voltage. Thermal shutdown (TSD) H L Shutdown After releasing TSD state, this IC is automatically reset with soft start. *1: PG pin is formed as an open drain structure. The internal MOSFET is in the OFF state.

Document Number: 002-08496 Rev. *D Page 12 of 20 S6BP202A 9. Application Circuit Example and Parts list Figure 9-1 Application Circuit Example RRT EP VOUT VCC VIN 22 kΩ CVCC 4.7 μF CVIN 0.1 μF PVIN LLX 2.2 μH CBST 0.1 μF VIN CPVIN 10 μF CVOUT_1 22 μF VCC or VOUT VOUT MODE SYNC ENA PG VOUT CVOUT_2 22 μF FOSC = 2.1 MHz When selecting “VOUT output voltage = 5.0V” VIN VCC FB MODE SYNC ENA RT GND GND BST LX1 LX2 VOUT PGND1 PGND2 PG S6BP202A RPG 1 MΩ Table 9-1 Parts List Symbol Item Value Part Number Vendor Package Size (W×L×H[mm]) Remarks CVIN, CBST Ceramic capacitor 0.1 μF CGA2B3X7R1H104K050BB TDK 1.0×0.5×0.5 X7R, Rated voltage: 50 Vdc CPVIN Ceramic capacitor 10 μF CGA9N3X7R1H106K230KB TDK 5.7×5.0×2.3 X7R, Rated voltage: 50 Vdc CVCC Ceramic capacitor 4.7 μF CGA4J3X7R1C475K125AB TDK 2.0×1.25×1.25 X7R, Rated voltage: 16 Vdc CVOUT_1, CVOUT_2 Ceramic capacitor 22 μF CGA6P1X7R1C226M250AC TDK 3.2×2.5×2.5 X7R, Rated voltage: 16 Vdc RRT Resistor 22 kΩ RK73H1JTTD2202F KOA 0.8×1.6×0.45 − RPG Resistor 1 MΩ RK73H1JTTD1004F KOA 0.8×1.6×0.45 − TDK: TDK Corporation KOA: KOA Corporation

Document Number: 002-08496 Rev. *D Page 13 of 20 S6BP202A 10. Application Note

10.1 Setting the Operation Conditions

Operation State of DC/DC Convertor When Selecting SYNC_IN The operation stage of DC/CD converter is set by both MODE pin and SYNC pin. Table 10-1 Operation State of DC/DC Convertor When Selecting SYNC_IN MODE Pin SYNC Pin (Signal Input) Operation State of DC/DC Convertor L (*3) L (*3) Automatic PWM/PFM switching operation from an internal clock External clock input (*5) Fixed PWM operation with synchronizing signal from an external clock (*2) H (*4) Prohibition of use (*1) H (*4) L (*3) Fixed PWM operation from an internal clock External clock input (*5) Fixed PWM operation with synchronizing signal from an external clock (*2) H (*4) Prohibition of use (*1) *1: When selecting SYNC_IN and setting SYNC pin to a high level, the quiescent current (IVINQ) is increased. *2: Set the timing resistance (RRT) to 330 kΩ. *3: Apply the GND1 or GND2 voltage. *4: Apply the VOUT voltage. *5: Apply the VOUT voltage at a high level. Apply the GND1 or GND2 voltage at a low level Operation State of DC/DC Convertor When Selecting SYNC_OUT When selecting SYNC_OUT, the phase of SYNC clock output is shifted from an internal clock. Table 10-2 Operation State of DC/DC Convertor When Selecting SYNC_OUT MODE Pin SYNC Pin Operation State of DC/DC Convertor L (*1) Internal clock output Fixed PWM operation from an internal clock H (*2) *1: Apply the GND1 or GND2 voltage. *2: Apply the VOUT voltage. Setting of Switching Frequency (Internal Clock) The switching frequency (internal clock) can be set by RT resistor, which value is the timing resistance (RRT), connected to RT pin. Set the timing resistance in a range within the following graph Figure 10-1 FOSC vs RRT Measured Characteristic FOSC vs RRT Measured Characteristic FOSC [MHz] RRT [kΩ] 0.0 2.5 400 0.5 100 S6BP202AGraph001 1.0 1.5 2.0 200 300

Document Number: 002-08496 Rev. *D Page 14 of 20 S6BP202A The reference value can be calculated by the following formula. FOSC[Hz] ≈ 1 RRT×21.7×10−12 FOSC : Switching frequency [Hz] RRT : Timing resistance [Ω] Setting of Soft-start Time The Soft-start time is determined by the timing resistance (RRT), the value of the resistor connected to RT pin. TSS[s] = 1 FOSC ×2×1024 TSS : Soft-start time [s] FOSC : Switching frequency [Hz] Consideration of VOUT Maximum Output Current Make sure the VOUT maximum output current in a range within the following graph. Figure 10-2 IVOUT vs VVIN IVOUT vs VVIN IVOUT [A] VVIN [V] 0.0 3.0 0.5 S6BP202AGraph002 1.0 1.5 2.0 2 3 4 5 6 7 8 10 119 2.5 Ta=+25oC, FOSC=2.1MHz Ta=+125oC, FOSC=2.1MHz

Document Number: 002-08496 Rev. *D Page 15 of 20 S6BP202A 11. Reference Data The followings are the reference data measured under the conditions shown in ”9. Application Circuit Example and Parts list”. Efficiency [%] Load Current [A] 100 S6BP202AGraph004-1 Efficiency (Fixed PWM) 10.10.001 VVIN = 2.5 V VVIN = 4.5 V VVIN = 42 V 0.01 LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25oC, VVIN = 12 V Efficiency [%] Load Current [A] 100 S6BP202AGraph004-2 Efficiency (Automatic PWM/PFM) 10.10.001 VVIN = 42 V VVIN = 12 V VVIN = 4.5 V VVIN = 2.5 V 0.01 LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25oC, Load Current [A] 2.5 S6BP202AGraph005 Load Regulation (Fixed PWM) 2.01.51.00.50 TA = +125 oC TA = +25 oC TA = －40 oC LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVIN = 12V, VVOUT = 5 V, FOSC = 2.1 MHz set, VVOUT [V] 4.92 4.98 4.96 4.94 5.00 5.04 5.06 5.08 5.02 VVIN [V] S6BP202AGraph006 Line Regulation (Fixed PWM) 352515100 TA = +125 oC, Load Current = 1.5 A 5 20 30 40 LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25 oC, Load Current = 2.4 A TA = －40 oC, Load Current = 2.4 A VVOUT [V] 4.92 4.98 4.96 4.94 5.00 5.04 5.06 5.08 5.02 IVINQ [µA] IVINQ vs VVIN (Automatic PWM/PFM) 100 120 140 TA = －40oC VVIN [V] S6BP202AGraph008-1 45100 20 25 405 15 30 35 TA = +25oC TA = +125oC LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVOUT = 5 V, Load Current = 0 A, FOSC = 2.1 MHz set, 2 ms/div ENA

5 V/div

2 A/div

TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF S6BP202AGraph009-2 Automatic PWM/PFMAutomatic PWM/PFM VVIN = 12 V, VVOUT = 5 V, Load Current = 0 A, FOSC = 2.1 MHz set, TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVIN = 12 V, VVOUT = 5 V, Load Current = 0 A, FOSC = 2.1 MHz set,

Document Number: 002-08496 Rev. *D Page 16 of 20 S6BP202A S6BP202AGraph010-2 200 µs/div Load Transient Response S6BP202AGraph010-1 200 µs/div VOUT 200 mV/div Load Current

1 A/div

Automatic PWM/PFMAutomatic PWM/PFM Load Transient Response AC-Coupled / 10 µs / 10 µs LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVIN = 12 V, VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25oC, Load Current LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVIN = 12 V, VVOUT = 5 V, FOSC = 2.1 MHz set, TA = +25oC, 0 A 2.4 A 2.4 A 0 A S6BP202AGraph011-2 1 ms/div VIN

10 V/div

Cold Crank Line Transient Response Load Dump Line Transient Response AC-Coupled Automatic PWM/PFM S6BP202AGraph011-1 4 ms/div VIN

2 V/div

2.5 V 6 V

/ 1 ms / 1 ms 11 V 2.5 V VVOUT = 5 V, Load Current = 0.2 A, FOSC = 2.1 MHz set, TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVOUT = 5 V, Load Current = 2.4 A, FOSC = 2.1 MHz set, TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF

40 V 11 V

/ 1 ms

11 V 40 V

/ 1 ms 10 ms/div S6BP202AGraph012-2 Ripple Waveform 1 µs/div S6BP202AGraph012-1 LX1 Automatic PWM/PFM Automatic PWM/PFM AC-Coupled VVIN = 12 V, VVOUT = 5 V, Load Current = 2.4 A, FOSC = 2.1 MHz set, TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF VVIN = 12 V, VVOUT = 5 V, Load Current = 0 A, FOSC = 2.1 MHz set, TA = +25oC, LLX = 2.2 µH, CVOUT_1 = CVOUT_2 = 22 µF

Document Number: 002-08496 Rev. *D Page 17 of 20 S6BP202A 12. Usage Precaution Printed circuit board ground lines should be set up with consideration for common impedance. Take appropriate measures against static electricity.  Containers for semiconductor materials should have anti−static protection or be made of conductive material.  After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.  Work platforms, tools, and instruments should be properly grounded .  Working personnel should be grounded with resistance of 250 k Ω to 1 M Ω in s erial body and ground . Do not apply negative voltages. The use of negative voltages below −0.3 V may make the parasitic transistor activated to the LSI, and can cause malfunctions. 13. RoHS Compliance Information This product has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). 14. Ordering Information Table 14-1 Ordering Information Order Code Part Number (MPN) (*1) Package 1F S6BP202A1FST2B00A Plastic ETSSOP16 (0.65 mm pitch), 16-pin (Package Code: SEC016) 1G S6BP202A1GST2B00A 4F S6BP202A4FST2B00A 7F S6BP202A7FST2B00A MPN: Marketing Part Number *1: Please contact our sales division for the part numbers (refer to "1. Product Lineup") not mentioned in this table. Figure 14-1 Ordering Part Number Definitions S 6B P 2 0 2 A XX S T2 B 0 0A Fixed on 00A Packing: B = 13 inch Tape and Reel Package: T2 = ETSSOP, Pure Sn / Low-Halogen Reliability Grade: S = 10 ppm Preset Condition (Order Code): See “Product Lineup” Revision: A = 1st Revision Product ID: 02 Topology: 2 = Switch-Mode Power Supply (Integrated FET) Product Type: P = Power Management IC Product Class: 6B = Automotive Analog Company ID: S = Cypress

Document Number: 002-08496 Rev. *D Page 18 of 20 S6BP202A 15. Package Dimensions 002-10769 Rev. **

Document Number: 002-08496 Rev. *D Page 19 of 20 S6BP202A 16. Major Changes Spansion Publication Number: S6BP202A_DS405-00027 Page Section Change Results Preliminary 0.1 − − Initial release Preliminary 0.2 1 Cover page The sentences of the "Notice to Readers" were changed from "the contents of Full Production" to "the contents of Preliminary". 13 10. Electrical Characteristics "(TSD)" was added in the table of "10. Electrical Characteristics". NOTE: Please see “Document History” about later revised information. Document History Document Title: S6BP202A, ASSP , 42V, 2.4A, Synchronous Buck-boost DC/DC Converter IC Document Number: 002-08496 Revision ECN Orig. of Change Submission Date Description of Change ** − HIXT 09/04/2015 New Spec. *A 5056149 HIXT 12/18/2015 Added Block Diagram Added Figure 15-1 Updated 16. Package Dimensions *B 5164343 HIXT 03/08/2016 Added “AEC-Q100 compliant (Grade-1)” in Features Added Figure 3-1 I/O Pin Equivalent Circuit Diagram The followings in 7. Electrical Characteristics were updated. The parameter name of IVOUT was changed from ”VOUT output voltage” to “Maximum output current” The max values of IVOUT were moved to the min column. Added 11. Development Support Added 12. Reference Data Deleted the ES part number from Table 15-1 *C 5839054 MASG 07/31/2017 Adapted Cypress new logo. *D 5909405 HIXT 10/13/2017 Updated to the Cypress naming and format Updated “TSSOP”  “ETSSOP” in Features, Table 14-1 and Figure 14-1 Updated 15 Package Dimensions Added More Information Deleted “11. Development Support” (Moved to More Information) Changed the suffix of the Part Number from “000” to “00A” in 1. Product Lineup Table 14-1 and Figure 14-1

Document Number: 002-08496 Rev. *D October 13, 2017 Page 20 of 20 S6BP202A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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