S6AP111A28

S6AP111A28 CYPRESS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 51

Technical content

Datasheet sections

• 8.1 Bottom Detection Comparator System
• 8.3 Under Voltage Lockout Protection Circuit Block (UVLO)
• 8.4 Soft Start/Discharge Block (Soft Start, Discharge)
• 8.5 ON/OFF Time Generator Block (tON Generator)
• 8.9 Thermal Shutdown Protection Block (TSD)
• 8.10 DAC Block (DAC)
• 8.11 Output Block (DRV1 and 2)
• 8.12 Boost Circuit Block (CB1 and 2)
• 8.14 Control Block (CTL)
• 8.15 Table of Protection Functions
• 12.1 Setting Operating Conditions
• 12.2 Selecting Parts
• 12.3 Layout

Features

 High efficiency: 96% (maximum)  High accuracy reference voltage: +/-0.7% (+25°C)  Input voltage range: 6V to 28V  Output voltage setting range: 0.75V to 5.5V  CH1 reference voltage with built-in variable function  Built-in boost switch  Over voltage protection function  Under voltage protection function  Over current detection function  Built-in soft start circuit: 1.4 ms (typical)  Built-in discharge control circuit  Built-in synchronous rectification type output steps for Nch MOS FET  Standby current: 0 A (typical)  Small package: TSSOP-24

Applications

 Industrial equipment  Multi-function printers  Storage devices  Servers and PCs

Document Number: 002-08491 Rev.*C Page 3 of 51 S6AP111A28 1. Pin Assignment Figure 1-1. Pin Assignment (Top View) (STI024) DRVH1 : 1 24 : LX1 CB1 : 2 23 : DRVL1 CTL1 : 3 22 : PGND1 VO1 : 4 21 : ILIM1 FB1 : 5 20 : VCC GND : 6 19 : VB DAC0 : 7 18 : VREF FB2 : 8 17 : DAC1 VO2 : 9 16 : ILIM2 CTL2 : 10 15 : PGND2 CB2 : 11 14 : DRVL2 DRVH2 : 12 13 : LX2

Document Number: 002-08491 Rev.*C Page 4 of 51 S6AP111A28 2. Pin Descriptions Table 2-1. Pin Descriptions Pin Number Pin Name I/O Function Description 1 DRVH1 O CH1 output pin for external high side FET gate drive. 2 CB1 - CH1 bootstrap capacitor connection pin. 3 CTL1 I CH1 control pin. 4 VO1 I CH1 input pin for DC/DC output voltage. 5 FB1 I CH1 feedback pin for DC/DC output voltage. 6 GND - Ground pin. 7 DAC0 I CH1 DAC input pin for change the internal reference voltage. 8 FB2 I CH2 feedback pin for DC/DC output voltage. 9 VO2 I CH2 input pin for DC/DC output voltage. 10 CTL2 I CH2 control pin. 11 CB2 - CH2 bootstrap capacitor connection pin. 12 DRVH2 O CH2 output pin for external high side FET drive. 13 LX2 - CH2 inductor and external high side FET source connection pin. 14 DRVL2 O CH2 output pin for external synchronous rectification-side FET gate drive. 15 PGND2 - Ground pin for CH2 output circuit. 16 ILIM2 I CH2 over current detection level setting voltage input pin. 17 DAC1 I CH1 DAC input pin for change the internal reference voltage. 18 VREF O Control circuit bias output pin. 19 VB O Output circuit bias output pin. 20 VCC I Power supply pin for the reference voltage and control circuit. 21 ILIM1 I CH1 over current detection level setting voltage input pin. 22 PGND1 O Ground pin for CH1 output circuit. 23 DRVL1 O CH1 output pin for external synchronous rectification-side FET gate drive. 24 LX1 - CH1 inductor and external high side FET source connection pin.

Document Number: 002-08491 Rev.*C Page 5 of 51 S6AP111A28 3. Block Diagram Figure 3-1. Block Diagram (24PIN) VREF (4.55V) VCC VOUT1 Drv-1 Drv-2 <Error Comp.> INTREF1 x 1.15V (5.2V) 19 VB PGND1 CB1 DRVH1 DRVL1 LX1 GND Drive Logic tON Generator 4VO1 FB1 INTREF1 SS1 R S Q VO1 VCC <OVP Comp.> <UVP Comp.> INTREF1 x 0.7V ovp_q1 uvp_q1 18UVLO VIN (6.0V ~ 28V) VOUT1 LX1 PGND1 <ILIM Comp.> ILIM1 10uA H:UVLO release delay delay R S Q R S Q ovp_q2uvp_q2 VOUT2 PGND2 CB2 DRVH2 DRVL2 LX2 ILIM2 <CH1> <CH2> 9VO2 FB2 VOUT2 DAC DAC0 DAC1 INTREF1 103 CTL2CTL1 SS Logic SS1 SS2 CTL1 CTL2 /CTL1 UVP,TSD bias TSD uvlo /UVP,/TSD (H:active) VREF Reg. VB Reg.CTL <RS-FF> <RS-Latch> <RS-Latch>

Document Number: 002-08491 Rev.*C Page 6 of 51 S6AP111A28 4. Absolute Maximum Ratings Parameter Symbol Condition Rating Min Max Unit Power supply voltage VVCC - -0.3 +36 V CB pin input voltage VCB CB1 and 2 pins -0.3 +42 V LX pin input voltage VLX LX1 and 2 pins -2.0 +36 V Voltage between CB and LX VCBLX - -0.3 +6.9 V Control input voltage VI CTL1 and 2 pins -0.3 +30 V Input voltage VFB FB1 and 2 pins -0.3 +6.9 V VVO VO1 and 2 pins -0.3 +6.9 V VILIM ILIM 1 and 2 pins -0.3 +6.9 V VDAC DAC 0 and 1 pins -0.3 +6.9 V Power Dissipation*1 PD Ta  +25°C 0 1333 mW Storage temperature TSTG - -55 +125 °C *1: Given that the IC is mounted on four-layer FR-4 board. WARNING: 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

Document Number: 002-08491 Rev.*C Page 7 of 51 S6AP111A28 5. Recommended Operating Conditions Parameter Symbol Condition Value Unit Min Typ Max Power supply voltage VVCC - 6 - 28 V CB pin input voltage VCB - - - VVCC +VB V CTL pin input voltage VI CTL1 and 2 pins 0 - 28 V Input voltage VFB FB1 and 2 pins 0 - VREF V VVO VO1 and 2 pins 0 - VB V VILIM ILIM1 and 2 pins 30 - 200 mV VDAC DAC0 and 1 pins 0 - VB V Peak output current IOUT DRVH1 and 2 pins, DRVL1 and 2 pins Duty  5% (t = 1/fOSCxDuty) -1200 - +1200 mA CB pin capacity CCB - - 0.1 1.0 F Bias voltage output capacity CVB - - 2.2 10 F Reference voltage output capacity CREF - - 1.0 4.7 F Operating ambient temperature Ta - -40 +25 +85 °C WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Document Number: 002-08491 Rev.*C Page 8 of 51 S6AP111A28 6. Electrical Characteristics VCC = 12V, CTL1,2 = 5V, Ta = +25°C, unless otherwise noted. Parameter Symbol Condition Value Unit Min Typ Max Bias Voltage Block [ VB Reg. ] Output voltage VVB - 5.04 5.20 5.36 V Input stability LINE VCC = 6V to 28V - 10 100 mV Load stability LOAD VB = 0A to -1 mA - 10 100 mV Short circuit output current IOS VB = 0V -220 -140 -100 mA Bias Voltage Block [ VREF Reg. ] VREF output voltage VVREF VREF pin 4.45 4.55 4.65 V Under Voltage Lock Out Protection [ UVLO ] UVLO VB Threshold voltage VTLH VB pin 3.9 4.2 4.5 V VTHL VB pin 3.3 3.6 3.9 V Hysteresis width VH VB pin - 0.6(*1) - V UVLO VREF Threshold voltage VTLH VREF pin 3.5 3.8 4.1 V VTHL VREF pin 3.3 3.6 3.9 V Hysteresis width VH VREF pin - 0.2(*1) - V Soft start/Discharge Block [ Soft-Start, Discharge ] Soft start time tSS FB1, 2 = 0.735V 0.9 1.4 1.9 ms Electrical discharge resistance RD CTL1,2 = 0V, VO1, 2 = 0.5V - 35 70 Ω Discharge end voltage VO CTL1,2 = 0V, VO1, 2 pins 0.1 0.2 0.3 V ON/OFF Time Generator Block [ tON Generator ] ON time tON1 VCC = 12V, VO1 = 1.2V 320 400 480 ns tON2 VCC = 12V, VO2 = 1.8V 320 400 480 ns Minimum ON time tONMIN VCC = 12V, VO1, 2 = 0V - 140 170 ns Minimum OFF time tOFFMIN - - 380 560 ns Error Comparison Block [ Error Comp. ] Threshold voltage [Ch1] VTH11 DAC1, DAC0 = 0,0 DC threshold 0.797 0.802 0.807 V VTH12 DAC1, DAC0 = 0,1 DC threshold 0.829 0.834 0.839 V VTH13 DAC1, DAC0 = 1,0 DC threshold 0.862 0.867 0.872 V VTH14 DAC1, DAC0 = 1,1 DC threshold 0.765 0.770 0.775 V Threshold voltage [Ch2] VTH2 DC threshold 0.768 0.773 0.778 V FB pin input current IFB FB1, 2 = 0.8V -0.1 0 0.1 A VO pin input current IVO VO1, 2 = 2V - 20 29 A

Document Number: 002-08491 Rev.*C Page 9 of 51 S6AP111A28 Parameter Symbol Condition Min Typ Max Unit Over voltage Protection Circuit Block [ OVP Comp. ] Over voltage detecting voltage VOVP Error Comp. input INTREF 1.11 INTREF 1.15 INTREF 1.19 V Over voltage detection delay time tOVP - - 50(*1) - s Under voltage Protection Circuit Block [ UVP Comp. ] Under voltage detecting voltage VUVP Error Comp. input INTREF 0.65 INTREF 0.70 INTREF 0.75 V Under voltage detection delay time tUVP - 1.2(*1) 1.7(*1) 2.2(*1) ms Thermal shutdown Protection Circuit Block [ TSD ] Protection temperature TTSDH - - +150(*1) - °C TTSDL - - +125(*1) - °C DAC Block [ DAC ] DAC input "H" condition VIH DAC1, DAC0 pins 2.64 - VB V DAC input "L" condition VIL DAC1, DAC0 pins 0 - 0.66 V Output Block [ DRV ] High side output on resistance ROH DRVH1, 2 = -100 mA - 5 7 Ω ROL DRVH1, 2 = 100 mA - 1.5 2.5 Ω Low side output on resistance ROH DRVL1, 2 = -100 mA - 4 6 Ω ROL DRVL1, 2 = 100 mA - 1 2 Ω Output source current ISOURCE LX1, 2 = 0V, CB1, 2 = VB DRVH1, 2 = 2.5 DUTY  5% - -0.4(*1) - A LX1, 2 = 0V, CB1, 2 = VB DRVL1, 2 = 2.5V DUTY  5% - -0.5(*1) - A Output sink current ISINK LX1, 2 = 0V, CB1, 2 = VB DRVH1, 2 = 2.5V DUTY  5% - 0.7(*1) - A LX1, 2 = 0V, CB1, 2 = VB DRVL1, 2 = 2.5V DUTY  5% - 0.9(*1) - A Deadtime TD LX1, 2 = 0V, BST1, 2 = VB - 30(*1) - ns Boost switch on resistance RBST IVB = 30 mA - 30 40 Ω Leakage current ILEAK CB1, 2 = 33.2V, LX1, 2 = 28V - 0.1 1 A

Document Number: 002-08491 Rev.*C Page 10 of 51 S6AP111A28 Parameter Symbol Condition Min Typ Max Unit Over Current Detection Block [ Current Sense ] ILIM pin source current IILIM ILIM1, 2 = 0.1V -12.5 -10 -8.3 A ILIM pin source current Temperature slope TILIM - - 4200(*1) - ppm /°C Overcurrent detection offset voltage VOFFILIM ILIMx − (PGNDx−LXx) PGNDx − LX = 60 mV -20 0 20 mV Overcurrent detection Setting range VILIM ILIM input 30 - 200 mV Control Block [ CTL1, 2 ] On condition VON CTL1,2 pin 2 - 28 V Off condition VOFF CTL1,2 pin 0 - 0.8 V Hysteresis width VH CTL1,2 pin - 0.4(*1) - V Input current ICTLH CTL1,2 = 5V - 25 40 A ICTLL CTL1,2 = 0V - 0 1 A All Devices Standby current ICCS VCC = 12V, CTL1,2 = 0V - 0 10 A Power supply current ICC VCC = 12V, LX1, 2 = 0V, FB1, 2 = 1.0V - 1.3 1.8 mA *1: This parameter is not be specified. This should be used as a reference to support designing the circuits.

Document Number: 002-08491 Rev.*C Page 11 of 51 S6AP111A28 7. Typical Characteristics 5.0 5.1 5.2 5.3 5.4 -50 -40 -30 -20 -10 0 VB bias voltage VVB (V) VB bias output current IVB (mA) Ta=+25℃ VCC=6V VCC=12V VCC=28V 500 1000 1500 2000 Power dissipation PD (mW) Operating ambient temperature Ta (°C) 1333 -40 +85 5.00 5.04 5.08 5.12 5.16 5.20 5.24 5.28 5.32 5.36 5.40 VB bias voltage VVB (V) Operating ambient temperature Ta (°C) VCC=12V IVB=0A 5.00 5.04 5.08 5.12 5.16 5.20 5.24 5.28 5.32 5.36 5.40 0 5 10 15 20 25 30 VB bias voltage VVB (V) Input voltage VCC (V) Ta=+25℃ IVB=0A 0.829 0.830 0.831 0.832 0.833 0.834 0.835 0.836 0.837 0.838 0.839 Error Comp. Threshold voltage VTH (V) Operating ambient temperature Ta (°C) DAC1,DAC0=0,1 Error Comp. Threshold voltage12 VTH12 (V) 0.797 0.798 0.799 0.800 0.801 0.802 0.803 0.804 0.805 0.806 0.807 Error Comp. Threshold voltage VTH (V) Operating ambient temperature Ta (°C) DAC1,DAC0=0,0 Error Comp. Threshold voltage11 VTH11 (V) VB bias voltage vs. VB bias output current Power dissipation vs. Operating ambient temperature VB bias voltage vs. Operating ambient temperature VB bias voltage vs. Input voltage Error Comp. Threshold voltage (VTH11) vs. Operating ambient temperature Error Comp. Threshold voltage (VTH12) vs. Operating ambient temperature

Document Number: 002-08491 Rev.*C Page 12 of 51 S6AP111A28 -14.0 -13.0 -12.0 -11.0 -10.0 -9.0 -8.0 -7.0 -6.0 ILIM pin current IILIM (uA) Operating ambient temperature Ta (°C) 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 DRVH1 on time tON1 (ns) Operating ambient temperature Ta (°C) VCC=12V VO1=1.2V 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 DRVH2 on time tON2 (ns) Operating ambient temperature Ta (°C) VCC=12V VO2=1.8V 0.768 0.769 0.770 0.771 0.772 0.773 0.774 0.775 0.776 0.777 0.778 Error Comp. Threshold voltage VTH (V) Operating ambient temperature Ta (°C) Error Comp. Threshold voltage2 VTH2 (V) 0.765 0.766 0.767 0.768 0.769 0.770 0.771 0.772 0.773 0.774 0.775 Error Comp. Threshold voltage VTH (V) Operating ambient temperature Ta (°C) DAC1,DAC0=1,1 Error Comp. Threshold voltage14 VTH14 (V) 0.862 0.863 0.864 0.865 0.866 0.867 0.868 0.869 0.870 0.871 0.872 Error Comp. Threshold voltage VTH (V) Operating ambient temperature Ta (°C) DAC1,DAC0=1,0 Error Comp. Threshold voltage13 VTH13 (V) ILIM pin current vs. Operating ambient temperature DRVH1 on time vs. Operating ambient temperature DRVH2 on time vs. Operating ambient temperature Error Comp. Threshold voltage (VTH13) vs. Operating ambient temperature Error Comp. Threshold voltage (VTH14) vs. Operating ambient temperature Error Comp. Threshold voltage (VTH2) vs. Operating ambient temperature

Document Number: 002-08491 Rev.*C Page 13 of 51 S6AP111A28 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 5 10 15 20 25 30 DRVH1 on time tON1 (ns) Input voltage VCC (V) Ta=+25℃ VO1=1.2V 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 5 10 15 20 25 30 DRVH2 on time tON2 (ns) Input voltage VCC (V) Ta=+25℃ VO2=1.8V 100 150 200 250 Minimum on time tONMIN1 (ns) Operating ambient temperature Ta (°C) VCC=12V VO1,2=0V 100 150 200 250 5 10 15 20 25 30 Minimum on time tONMIN (ns) Input voltage VCC (V) Ta=+25℃ VO1,2=0V 200 250 300 350 400 450 500 550 600 5 10 15 20 25 30 Minmum off time tOFFMIN(ns) Input voltage VCC (V) Ta=+25℃ 200 250 300 350 400 450 500 550 600 Mimimum off time tOFFMIN (ns) Operating ambient temperature Ta (°C) VCC=12V DRVH1 on time vs. Input voltage DRVH2 on time vs. input voltage Minimum on time vs. Operating ambient temperature Minimum on time vs. Input voltage Minimum off time vs. Input voltage Minimum off time vs. Operating ambient temper ature

Document Number: 002-08491 Rev.*C Page 14 of 51 S6AP111A28 Dead time (ns) Operating ambient temperature Ta (°C) LX1,2=0V CB1,2=VBtD1 tD2 Boost switch on resistance RBST (Ω) Operating ambient temperature Ta (°C) Dead time vs. Operating ambient temperature tD1：period from DRVL off to DRVH on tD2：period from DRVH off to DRVL on Boost switch on resistance vs. Operating ambient temperature

Document Number: 002-08491 Rev.*C Page 15 of 51 S6AP111A28 8. Function Description

8.1 Bottom Detection Comparator System

The bottom detection comparator system for low output voltage ripple determines the ON time (tON) using the input voltage (VIN) and output voltage (VOUT) and holds the ON state for a specified period. During the OFF period, the reference voltage (INTREF) is compared with the feedback voltage (FB) using the error comparator (Error Comp.). When the feedback voltage (FB) is below the reference voltage (INTREF), RS-FF is set and the ON period starts again. Switching is repeated as described above. Error Comp. is used to compare the reference voltage (INTREF) with the feedback voltage (FB) to control the off time in order to stabilize the output voltage. This system adds the inductor current slope detected during the synchronous rectification period (tOFF) to the reference voltage (INTREF), and generates an output voltage slope in the IC during the OFF period, which is essential for the bottom detection comparator system. This enables the stable control operations under the low output voltage ripple conditions. Figure 8-1. Circuit Diagram Figure 8-2. Bottom Detecting Operation DRVL Bias tON Generator Drive Logic VIN IL S VOUT Bias Reg. Lo-side Drive FB RS-FF <Error Cmp.> R Q Hi-side Drive RS out VINVOUT tON Vref INTREF DRVH Slope Detector tON tOFF IL t DRVH FB INTREF

Document Number: 002-08491 Rev.*C Page 16 of 51 S6AP111A28 8.2 Bias Voltage Block [ VB Reg., VREF Reg. ] VB Reg. generates 5.2V (typical) bias voltage from the VCC pin voltage for the control, output, and boost circuits. When either or both of the CTL1 or CTL2 pins (pins 3 and 10) are set to the “H” level, the system is restored from the standby state to supply the bias voltage from the VB pin (pin 19). VREF Reg. generates a temperature compensating stable voltage of 4.55 V (typical) from the VREF pin (pin 18) which is used as the reference voltage in the IC and the bias power supply for the control circuit.

8.3 Under Voltage Lockout Protection Circuit Block (UVLO)

A transitional state or an instantaneous drop when the bias voltage (VVB) for the control circuit starts will evoke malfunction of the IC and will cause system destruction or degradation. To avoid this sort of malfunction, the under voltage lockout protection detects a voltage drop in the VB pin (pin 19) and fixes the DRVH1 pin (pin 1), DRVH2 pin (pin 12), DRVL1 pin (pin 23), and DRVL2 pin (pin 14) to Level "L." The system recovers when the VB pin voltage exceeds the 4.2V threshold voltage (typical) of the under voltage lockout protection circuit.

8.4 Soft Start/Discharge Block (Soft Start, Discharge)

The soft start block is a circuit that prevents inrush current when powering on the IC. When the CTL1 pin (pin 3) and CTL2 pin (pin 10) are set to Level "H," the reference voltage (SS1) for the CH1 error comparator and the reference voltage (SS2) for the CH2 error comparator start to increase in the soft start circuit built in to the IC. The reference voltages SS1 and SS2 increase linearly until the INTREF1 and INTREF2 voltages with the formula in Figure 10-3(tss1 and tss2). The system soft starts independent of the DC/DC convertor output load because the DC/DC convertor output increase with the same slope of the reference voltage. From the time that the soft start commences until the initial switching commences, the low side FET stays OFF. The low side FET is allowed to come on after high side FET switching commences. When the CTL1 pin (pin 3) and CTL2 pin (pin 10) are set to Level "L," the output capacitor discharges based on the FET(RON≈35Ω) for the discharge built in to the IC. When the VO1 pin (pin 4) and VO2 pin (pin 9) voltage becomes less than 0.2 V (typical) as a result of output capacitor discharge, the IC shuts down and transitions to standby. In addition, the discharge function operates both after under voltage protection circuit block (UVP Comp.) latch setting and after thermal shutdown protection circuit block (TSD) over temperature detection.

Document Number: 002-08491 Rev.*C Page 17 of 51 S6AP111A28 Figure 8-3. Example Timing Chart for Soft Start/Discharge Channel DAC0 DAC1 tss1 CH1 0V 0V 1.5 ms typ VB 0V 1.6 ms typ 0V VB 1.7 ms typ VB VB 1.5 ms typ Channel DAC0 DAC1 tss2 CH2 - - 1.5 ms typ tss1,2 is calculated using the following formula. 735021 . V)ms(tss)ms(,tss INTREF tss1,2: Soft start time of DC/DC converter CH1,2 tss: Soft start time ( 1.4 ms typical ), which is specified at "6. Electrical Characteristics " INTREF: Internal reference voltage (DC threshold) [V] , which is referred at " VTH in 6. Electrical Characteristics "

Document Number: 002-08491 Rev.*C Page 18 of 51 S6AP111A28

8.5 ON/OFF Time Generator Block (tON Generator)

The ON/OFF time generator block (tON Generator) has a built-in capacitor for timing setting and a resistor for timing setting and generates ON time which depends on input voltage and output voltage, and a minimum 380 ns (typical) OFF time. The ON time is set from the voltage value for VCC pin (pin 20), input pin VO1 (pin 4) and the VO2 pin (pin 9) for the output voltage for each channel, using the following formula. To avoid beats from frequency discrepancies between both channels, the CH2 frequency is set to 1.5 times the CH1 frequency. kHzfV VnstV VWhen OSC VCC VO ON VCC 1  kHzfV VnstV VWhen OSC VCC VO ON VCC 2  The ON time is set so that it does not become less than the minimum 140 ns (typical). Therefore, when a soft start commences or when the input/output voltage ratio is small, the ON time operates at a minimum of 140 ns (typical). )(140)(),035.0( 1 1 typicaltnstV VWhen ONMINON VCC VO  )(140)(,)052.0( 2 2 typicaltnstV VWhen ONMINON VCC VO  8.6 Error Comparison Block (Error Comp.) The error comparison block (Error Comp.) detects the bottom value of the output voltage ripple in the DC/DC converter. You can set the output voltage flexibily(0.75V to 5.5V) by connecting an external output voltage setting resistor to FB1 (pin 5) and FB2 (pin 8). 8.7 Over Voltage Protection Circuit Block (OVP Comp.) This function stops the output voltage when the DC/DC output voltage has increased, and protects devices connected to the output. This function compares the voltage that is 1.15 times (typical) the INTREF internal reference voltage with the feedback voltage that is input in the FB1 pin (pin 5) and the FB2 pin (pin 8). If the feedback voltage is found to be at least 50 s (typical) higher, the RS latch is set, the DRVH1 pin (pin 1) and DRVH2 pin (pin 12) are set to Level "L", and the DRVL1 pin (pin 23) and DRVL2 pin (pin 14) are set to Level "H." The voltage output stops because these operations fix the high side FET to the off state and the low side FET to the on state for both channels of the DC/DC converter. Further, there is 5% (typical) hysteresis in the threshold for the over voltage protection operation to avoid malfunction of the over voltage protection function.

Document Number: 002-08491 Rev.*C Page 19 of 51 S6AP111A28 Figure 8-4. Example Timing Chart for the Over Voltage Protection Operation The over voltage protection state is released (the RS latch for over voltage protection is reset) under either of the following conditions.  UVLO detection in the stop sequence after setting both the CTL1 pin (pin 3) and CTL2 pin (pin 10) to Level "L".  UVLO detection in VCC power-off  Thermal shutdown protection function (TSD) detection. DRVH1 DRVL1 VO1 VO2 INTREF x1.15 50µs (typical) FB1 FB2 INTREF INTREF Output voltage setting value CTL1,2 VB UVLO VTHL Less than 50µs (typical) Cancellation of over-voltage protection state by CTL=”L” Standby DRVH2 DRVL2 INTREF x1.10 Output voltage setting value

Document Number: 002-08491 Rev.*C Page 20 of 51 S6AP111A28 8.8 Under Voltage Protection Circuit Block (UVP Comp.) This function stops the output voltage when the DC/DC output voltage has decreased, and protects devices connected to the output. This function compares the voltage that is 0.7 times (typical) the INTREF internal reference voltage with the feedback voltage that is input in the FB1 pin (pin 5) and the FB2 pin (pin 8). If the feedback voltage is found to be at least 1.7 ms (typical) lower, the RS latch is set, the DRVH1 pin (pin 1) and DRVH2 pin (pin 12) are set to Level "L", and the DRVL1 pin (pin 23) and DRVL2 pin (pin 14) are set to Level "L." In addition, when the latch is set for under voltage protection, the discharge function built in to the IC starts at the same time and voltage output stops for both channels. Further, there is 5% (typical) hysteresis in the threshold for the under voltage protection operation to avoid malfunction of the under voltage protection function. Figure 8-5. Example Timing Chart for the Under Voltage Protection Operation The under voltage protection state is released (the RS latch for under voltage protection is reset) under either of the following conditions. DRVH1 DRVL1 VO1 VO2 INTREF x0.70 FB1 FB2 INTREF INTREF Output voltage setting value CTL1,2 VB Less than 1.7 ms (typical) 1.7 ms (typical) DRVH2 DRVL2 Cancellation of under-voltage protection State by CTLCTL=”L” UVLO VTHL Standby INTREF x0.75 Output voltage setting value

Document Number: 002-08491 Rev.*C Page 21 of 51 S6AP111A28  UVLO detection in the stop sequence after setting both the CTL1 pin (pin 3) and CTL2 pin (pin 10) to Level "L".  UVLO detection in VCC power-off  Thermal shutdown protection function (TSD) detection.

8.9 Thermal Shutdown Protection Block (TSD)

The thermal shutdown protection block (TSD) provides a function that prevents the IC from thermal damage. If the junction temperature of the thermal shutdown protection circuit reaches +150°C, the DRVH1 pin (pin 1) and DRVH2 pin (pin 12) are set to the “L” level, and the DRVL1 pin (pin 23 ) and DRVL2 pin (pin 14) are set to the “L” level, and switching stops. In addition, the discharge function that is built in to the IC runs, and voltage output for both channels stops. If the junction temperature drops to +125°C, the soft start is reactivated (restored automatically). TSD detection is +150°C, but operations above the absolute maximum rating for the storage temperature (+125°C) are not guaranteed.

8.10 DAC Block (DAC)

You can change the reference voltage (INTREF1) for the CH1 error comparison block and the output voltage for the DC/DC converter by inputting an external 0V or VB pin voltage in the DAC0 pin (pin 7) and DAC1 pin (pin 17). Table 8-1. Reference Voltage Settings DAC0 DAC1 CH1 Reference Voltage (INTREF1) 0V 0V 0.802V typ VB 0V 0.834V typ 0V VB 0.867V typ VB VB 0.770V typ

8.11 Output Block (DRV1 and 2)

The output circuit is configured in CMOS format for both of the high side and the low side, and can drive an external Nch MOS FET. The output block for the high side FET supplies power from the built-in boost circuit, and the output block for the low side FET supplies power from the VB. This circuit prevents through-current by monitoring the gate voltages of the high side and low side FETs and controlling the timing of turning on one FET until the other FET is off. The sink ON resistance of the output circuit is a low 1Ω (typical), and the self turn on margin for the low side FET is improved.

8.12 Boost Circuit Block (CB1 and 2)

The boost circuit is needed high side FET in a case using Nch MOS FET.Efficiency improvement and/or reduction in parts cost can be expected of High side FET by using Nch MOSFET. The boost circuit is formed a boost charge pump block which consists of the built-in switch for bootstraps and the condenser connected between CB pin and the LX pin. Then the condenser is charged through built-in switch from VB. The boosted power supply for gate drives of high side FET. The boost circuit has a built-in boost switch that eliminates the boost voltage (voltage between the CB pin and LX pin) loss of the forward voltage (Vf) that existed in older boost diodes. Therefore further efficiency improvement and reduction in parts cost can be expected more than a diode system.

Document Number: 002-08491 Rev.*C Page 22 of 51 S6AP111A28 Figure 8-6. Output Block and Boost Circuit Block 8.13 Over Current Detection Block (ILIM Comp.) This function limits the output current when it has increased, and protects devices connected to the output. It compares the difference in voltage between the PGND1 pin (pin 22) and the LX1 pin (pin 24) and the ILIM1 pin (pin 21) voltage, and the difference in voltage between the PGND2 pin (pin 15) and LX2 pin (pin 13) and the ILIM2 pin (pin 16) voltage during the synchronous rectification period, and performs over current detection in every cycle. The high side FET stays off until the difference in voltage between PGNDx and LXx is lower than the ILIMx pin voltage, and turns on after it becomes lower. This is how over current protection is performed. This protection operation drops the output voltage. For the difference in voltage between PGNDx and LXx during the synchronous rectification period, the low side FET on resistance is sense resistance, and the inductor current is the sensed voltage waveform. A 10 A (typical) IILIM current is supplied from the ILIMx pin, so you can set any over current limit value by connecting resistance to the ILIMx pin. For the IILIM current, a temperature slope of 4200ppm/°C is set to compensate for the temperature dependence characteristics of the low side FET on resistance.

8.14 Control Block (CTL)

Turn CH1 on or off using the CTL1 pin (pin 3) and turn the CH2 on or off using the CTL2 pin (pin 10). Setting both CTL1 and 2 to Level "L" at the same time puts it in standby (the power supply current during standby is a maximum of 10 A). Table 8-2. Control Functions CTL1 CTL2 DC/DC Converter (CH1) DC/DC Converter (CH2) L L OFF OFF H L ON OFF L H OFF ON H H ON ON DRVLx VBDrive Logic VIN IL VOUT Bias Reg. Lo-side Drive Hi-side Drive DRVHx CBx LXx VB DRVLx Boost SW x: Each channel number

Document Number: 002-08491 Rev.*C Page 23 of 51 S6AP111A28

8.15 Table of Protection Functions

The following table shows the state of the DRVH1 and 2 pins (pins 1 and 12) and the DRVL1 and 2 pins (pins 23 and 14) when each protection function is in operation. Table 8-3. Protection Functions Protection function Detection condition Output of each pin during detection DC/DC output drop state VB DRVHx DRVLx Under voltage lockout protection (UVLO) VVB < 3.6V - L L Natural electric discharge Under voltage protection (UVP) VFBx < INTREFx × 0.7 V 5.2V L L Electrical discharge by discharge function Over voltage protection (OVP) VFBx > INTREFx × 1.15 V 5.2V L H 0V clamping Over current protection (ILIM) VPGNDx – VLXx > VILIMx 5.2V switching switching Dropped by the set current value Thermal shutdown protection (TSD) Tj > +150°C 5.2V L L Electrical discharge by discharge function Control (CTL) CTLx : H → L (VOx > 0.2V) 5.2V L L Electrical discharge by discharge function

Document Number: 002-08491 Rev.*C Page 24 of 51 S6AP111A28 9. I/O Pin Equivalent Circuit Diagram VCC GND CTL1 CTL2 VB GND ILIM1 ILIM2 PGND1 PGND2 VO1 VO2 GND VB GND VB DAC0 GND VB DAC1 ESD protection element ESD protection element VB GND FB1 FB2 FB1, FB2 pins CTL1, CTL2 pins ILIM1, ILIM2 pins VO1, VO2 pins DAC0 pin DAC1 pin

Document Number: 002-08491 Rev.*C Page 25 of 51 S6AP111A28 CB1 CB2 LX1 LX2 DRVH1 DRVH2 VB PGND1 PGND2 VB PGND1 PGND2 DRVL1 DRVL2 VCC GND PGND1 PGND2 GND VB VCC VREF VB DRVH1, DRVH2, CB1, CB2, LX1, LX2 pins DRVL1, DRVL2 pins VB pin VREF pin VCC, GND, PGND1, PGND2 pins

Document Number: 002-08491 Rev.*C Page 26 of 51 S6AP111A28 10. Example Application Circuit Figure 10-1. Circuit Diagram VCC FB1 VREF VB CB1 DRVH1 VO1 DAC0 DAC1 GND ILIM1 PGND1 DRVL1 LX1 CTL1 FB2 VO2 CTL2 CB2 DRVH2 LX2 DRVL2 PGND2 ILIM2 G D1S1 G D1S1 VIN DAC0 VOUT1-5 VOUT1-4 VOUT1-3 VOUT1-2 VOUT1-1 VOUT1-6 DAC1 CTL1 CTL2 G D1S1 G D1S1 VIN VOUT2-5 VOUT2-4 VOUT2-3 VOUT2-2 VOUT2-1 VOUT2-6 VB VB PatternShort PatternShort PatternShort VOUT1s PatternShort VOUT2s PGND5 PGND6 PGND7 PGND8 PGND9 PGND10 PGND11 PGND12 PGND13 PGND14 PGND15 PGND16 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN VB VIN PGND1 PGND2 PGND3 PGND4 C2-1 2 1 C4-1 2 1 C1-1 Q13 1 5 Q23 1 5 C2-2 C1-2 NMT C10 R1-1 R1-2R2 R5NMT C11 R3-1 R3-2R4 C3-1 Q33 1 5 1 5 C4-2 C3-2 JP7 JP8 NMT NMT JP1JP2 NMT R13 NMT C13 R12 NMT C12 NMT

Document Number: 002-08491 Rev.*C Page 27 of 51 S6AP111A28 11. Part List Table 11-1. Parts List No. Component Item Parts Number Vendor Value Remarks

1 M1 PMIC S6AP111A28GT1B000 CYPRESS - -

2 L1 Inductor MPLC1040L4R7 KEMET 4.7µH 8A 3 L2 Inductor MPLC1040L4R7 KEMET 4.7µH 8A

4 Q1 FET FDMC8015L FAIRCHILD - 40V, 7A

5 Q2 FET FDMC8327L FAIRCHILD - 40V, 12A

6 Q3 FET FDMC8015L FAIRCHILD - 40V, 7A

7 Q4 FET FDMC8327L FAIRCHILD - 40V, 12A

8 C1-1 Ceramic Capacitor C3216X5R1V226M160AC TDK 22μF 35V

9 C1-2 Ceramic Capacitor C1608CH1H102J TDK 0.001μF 50V 10 C2-1 Ceramic Capacitor 6TPE150MF PANASONIC 150μF 6.3V 11 C2-2 Ceramic Capacitor C1608CH1H102J TDK 0.001μF 50V

12 C3-1 Ceramic Capacitor C3216X5R1V226M160AC TDK 22μF 35V

13 C3-2 Ceramic Capacitor C1608CH1H102J TDK 0.001μF 50V 14 C4-1 Ceramic Capacitor 6TPE150MF PANASONIC 150μF 6.3V 15 C4-2 Ceramic Capacitor C1608CH1H102J TDK 0.001μF 50V 16 C5 Ceramic Capacitor C1608X5R1H104K080AA TDK 0.1μF 50V 17 C6 Ceramic Capacitor C1608X5R1H104K080AA TDK 0.1μF 50V 18 C7 Ceramic Capacitor C1608X5R1H104K080AA TDK 0.1μF 50V 19 C8 Ceramic Capacitor C1608X5R1C225K TDK 2.2μF 16V

20 C9 Ceramic Capacitor C1608X5R1H105K080AB TDK 1μF 50V

21 C10,C11,C12,C13 Ceramic Capacitor C1608CH1H102J TDK 0.001μF NMT 22 R1-1 Chip Resistor RR0816P-201-D SUSUMU 0.2kΩ -

23 R1-2 Chip Resistor RR0816P-333-D SUSUMU 33 kΩ -

24 R2 Chip Resistor RR0816P-103-D SUSUMU 10 kΩ -

25 R3-1 Chip Resistor RR0816P-432-D SUSUMU 4.3 kΩ -

26 R3-2 Chip Resistor RR0816P-513-D SUSUMU 51 kΩ -

27 R4 Chip Resistor RR0816P-103-D SUSUMU 10 kΩ -

28 R5 Chip Resistor RR0816P-103-D SUSUMU 10 kΩ -

29 R6 Chip Resistor RR0816P-103-D SUSUMU 10 kΩ -

30 R7,R8 Chip Resistor RR0816P-103-D SUSUMU 10 kΩ NMT

31 R12,R13 Chip Resistor RK73H2ATTD10R0F SUSUMU 10 Ω NMT

32 JP1,JP2,JP7,JP8 Jumper - - - Pattern short

PGND, VOUT1, VOUT1a,VIN, CTL1, DAC0 Terminal 90131-0770 molex - 2 × 10pin header PGND, VOUT2, VOUT2a,VIN, CTL2, DAC1 Terminal 90131-0770 molex - 2 × 10pin header

Document Number: 002-08491 Rev.*C Page 28 of 51 S6AP111A28 NMT: No mount. These components are compliant with RoHS, and please ask each vendor for details if necessary. CYPRESS : CYPRESS Semiconductor Corp. KEMET : KEMET Electronics Corporation FAIRCHILD : Fairchild Semiconductor Corp. TDK : TDK Corporation PANASONIC : Panasonic Corporation SUSUMU : SUSUMU Co., Ltd. molex : Molex Japan Co., Ltd.

Document Number: 002-08491 Rev.*C Page 29 of 51 S6AP111A28 LOUT ΔIESRΔV  12. Application Note

12.1 Setting Operating Conditions

Setting the Output Voltage You can set the output voltage by adjusting the R1 and R2 resistance ratio. The output voltage is calculated using the following formula. ΔV)R)t 102.800-(1ΔI0.01840.0100-(INTREFR2 R2R1V OUT ON_Sync OFF OSCIN OOIN L V V L V-VΔI f UTUT  , INOSC OUTIN OFF Vf )V-(Vt  INTREF : Internal reference voltage (DC threshold) [V] VOUT : Output settings voltage [V] VIN : Power supply voltage [V] ΔVOUT : Output ripple voltage value [V] tOFF : Off time [s] RON_Sync : ON resistance of low side FET [Ω] ΔIL : Ripple current peak-to-peak value of inductor [A] ESR : Series resistance element of output capacitor [Ω] L : Inductor value [H] fOSC : Switching frequency [Hz] Select a total resistor value (R1+R2) of up to 100 kΩ for the setting output resistor. Figure 12-1. FB Connection Connecting the Feedback Capacitor The IC internally generates the output voltage slope during the OFF period to stabilize the switching frequency, but it is also effective to apply output ripple voltage to the FB pin. This is achieved by adding capacitors (CFB) to the R1 in parallel. Applying a ripple voltage value to the FB terminals is more effective than high output voltage conditions that decrease it based on the R1 and R2 ratio. When selecting which capacitors to add, use the following formula. 212 )21(10 RRf RRC OSC FB    CFB : Feedback capacitor capacitance [F] R1,R2 : Output voltage setting resistance [Ω] fOSC : Switching frequency [Hz] VOUTx FBx VOx x: Each channel number

Document Number: 002-08491 Rev.*C Page 31 of 51 S6AP111A28 Maintaining a Difference between the Minimum Input and Output Voltage Stable switching control is performed in this IC, so the minimum OFF time is set, but if the difference between the input and output is small, and the input voltage is less than the voltage value shown in the formula below, the output voltage is reduced. For this reason, you should maintain the difference between the minimum input voltages. 1.4ft))R(RDCI(V -V V))R(RDCI(V V OSCOFFM INNON_SyncOUT_M AXOUTOUT OUTON_M ainOUT_M AXOUT IN_M IN  VIN_MIN : Input voltage [V] VOUT : Output settings voltage [V] IOUT_MAX : Maximum load current value [A] RON_Main : High side FET ON resistance [Ω] RON_Sync : ON resistance of low side FET [Ω] RDC : Inductor direct current resistance [Ω] fOSC : Switching frequency setting value [Hz] tOFFMINN : Normal minimum OFF time (maximum value) [s] Slope Voltage To ensure a stable switching cycle, maintain a slope voltage of at least 15 mV. Calculate the slope voltage using the following formula. OSCIN ON_SyncOUTOUTIN Slope fVL RV)V-(V V  VSlope : Slope voltage [V] VIN : Power supply voltage [V] VOUT : Output settings voltage [V] fOSC : Switching frequency [Hz] RON_Sync : ON resistance of low-side FET [Ω] L : Inductor value [H] Setting the Over Current Detection Value The over current detection value can be set by adjusting the over current detection setting resistor that is connected to the ILIM pin. Calculate the resistor value from the following formula. LIM_SOURCE L LIMON_Sync LIM I ΔI-(IR R RLIM : Over current detection value setting resistor [Ω] ILIM : Over current detection value [A] ILIM_SOURCE : ILIM pin source current [A] ΔIL : Ripple current peak-to-peak value of inductor [A] RON_Sync : ON resistance of low side FET [Ω]

Document Number: 002-08491 Rev.*C Page 33 of 51 S6AP111A28 Power Dissipation and Thermal Design This is a high efficiency IC so power dissipation and thermal design do not need to be investigated in most cases, but they do need to be investigated when using the IC at a high power supply voltage, high oscillator frequency, high load, and high temperature. Calculate the internal IC loss from the following formula. )fQfQ(IVP OSC2G_Total2OSC1G_Total1CCCCIC  PIC : IC internal loss [W] VCC : Power supply voltage (VIN) [V] ICC : Power supply current [A] (1.8mA Max) QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C] QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C] fOSC1 : CH1 Switching frequency [Hz] fOSC2 : CH2 Switching frequency [Hz] Calculate the junction temperature (Tj) from the following formula. ICjaaj PTT  Tj : Junction temperature [°C] (+125°C Max) Ta : Ambient temperature [°C] θja : TSSOP-24P package thermal resistance (75°C/W) PIC : IC internal loss [W] Pin Processing when Only Using a Single Channel This IC is a 2ch DC/DC converter control IC, but you can also use it as a 1ch DC/DC converter using the following processing for pins from unused channels. Figure 12-6. Pin Processing x: Unused channel No. “Open” “Open” “Open” CTLx ILIMx FBx VOx LXx DRVHx DRVLx CBx

Document Number: 002-08491 Rev.*C Page 34 of 51 S6AP111A28

12.2 Selecting Parts

Selection of smoothing inductor The inductor value selects the value that the ripple current peak-to-peak value of the inductor is 50% or less of the maximum load current as a rough standard. Calculate the inductor value in this case by the following formula. OSCIN UTO OUT_MAX UTOIN fILOR L V VV-V L : Inductor value [H] Iout_max : Maximum load current [A] LOR : Ripple current peak-to-peak value of inductor/Maximum load current ratio (= 0.5) VIN : Power supply voltage [V] VOUT : Output setting voltage [V] fOSC : Switching frequency [Hz] It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric current that flows to the inductor is a rated value or less. Calculate the maximum current value of the inductor by the following formula. IIL L OUT_MAXMAX I ILMAX : Maximum current value of inductor [A] IOUT_MAX : Maximum load current [A] ΔIL : Ripple current peak-to-peak value of inductor [A] L : Inductor value [H] VIN : Power supply voltage [V] VOUT : Output setting voltage [V] fOSC : Switching frequency [Hz] Figure 12-7. Maximum Output Current Setting Inductor current Time ΔIL IOUT_MAX ILMAX

Document Number: 002-08491 Rev.*C Page 35 of 51 S6AP111A28 Selection of Switching FET If selecting the high-side FET so that the value of the high-side FET conduction loss and the high-side FET switching loss is same, the loss is effectively decreased. Confirm that the high-side FET loss is within the rating value. SW_MainRON_MainMainFET PPP  PMainFET : High-side FET loss [W] PRON_Main : High-side FET conduction loss [W] PSW_Main : High-side FET switching loss [W] High-side FET conduction loss ON_Main IN UTO OUT_MAXRON_Main RV VIP  2 PRON_Main : High-side FET conduction loss [W] IOUT_MAX : Maximum load current [A] VIN : Power supply voltage [V] VOUT : Output voltage [V] RON_Main : ON resistance of high-side FET [Ω] The high-side FET switching loss can be calculated roughly by the following formula. SWOUT_M AXOSCINSW_M ain QIfVP  96.1 PSW_Main : Switching loss [W] VIN : Power supply voltage [V] fOSC : Switching frequency [Hz] IOUT_MAX : Maximum load current [A] QSW : Amount of high-side FET gate switch electric charge [C] Select the ON resistance of low-side FET from the range below. )II( L LIM Sync_ON L Sy nc_ON I .R  10 , L Sy nc_ON I .R  0150 RON_Sync : ON resistance of low-side FET [Ω] ΔIL : Ripple current peak-to-peak value of inductor [A] ILIM : Over current detection value [A]

Document Number: 002-08491 Rev.*C Page 36 of 51 S6AP111A28 If the formula above has been already satisfied and then a low ON resistance FET as possible is used for the low-side FET, the loss is effectively decreased. Especially, it works dramatically in the low on duty mode. The loss of the low-side FET can be calculated by the following formula. on_Sy nc IN UTO OUT_MAXRon_Sy ncSy ncFET R)V V-(1IPP  2 PSyncFET : Low-side FET loss [W] PRon_Sync : Low-side FET conduction loss [W] IOUT_MAX : Maximum load current [A] VIN : Power supply voltage [V] VOUT : Output voltage [V] RON_Sync : ON resistance of low-side FET [Ω] Turn-on and turn-off voltage of the low-side FET is generally small and the switching loss is small enough to ignore, so that is omitted here. Especially, when turning on the high-side FET under the high power supply voltage condition, the rush-current might be generated by according to self-turn-on of the low-side FET. The parasitic capacitor value of the low-side FET needs to satisfy the following conditions. IN iss rss TH_Sy nc VC CV  VTH_Sync : Threshold voltage of low-side FET [V] Crss : Parasitic feedback capacitance of low-side FET [F] Ciss : Parasitic input capacitance of low-side FET [F] VIN : Power supply voltage [V] Also approaches of adding a capacitor close between the gate source pins of the low-side FET or adding resistor between the CB pin and the boost capacitor, and so on are effective as a countermeasure of the self-turn-on(adding resistor between the CB pin and the boost capacitor is also effective to adjust turn-on time of the high-side FET). This device monitors the gate voltage of the switching FET and optimizes the dead time. If the dumping resistor is inserted among DRVH, DRVL and the switching FET gate to adjust turn-on and turn-off time of the switching FET, this function might malfunction. In this device, resistor should not be connected among the DRVH pin, the DRVL pin of IC and the switching FET gate, and should be connected by low impedance as possible. The gate drive power of the switching FET is supplied from LDO (VB) of IC inside. Select switching FET so that the total amount of the switching FET electric charge for 2 channels (QG_Total1, QG_Total2) satisfies the following formula.

21 OSCG_Total2OSCG_Total1MAX_VB fQfQI 

IVB_MAX : VB load current upper limit value (see the following graph) [A] QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C] QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C] fOSC1 : CH1 Switching frequency [Hz] fOSC2 : CH2 Switching frequency [Hz]

Document Number: 002-08491 Rev.*C Page 37 of 51 S6AP111A28 Moreover, select the total quantity of the high-side FET electric charge as a guide that does not exceed the total quantity of the high-side FET electric charge upper limit value shown below. 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 6 8 10 12 14 16 18 20 22 24 26 28 VB load current upper limit value [A] VIN [V] 100 120 140 160 6 8 10 12 14 16 18 20 22 24 26 28 The total quantity upper limit of electric charge of the high-side FET QG_MAX[nC] Power supply voltage VIN[V] CH1 upper limit CH2 upper limit

Document Number: 002-08491 Rev.*C Page 38 of 51 S6AP111A28 Whether the mean current value that flows to switching FET is a rated value or less of switching FET is judged. Each rating value for the switching FET can be calculated roughly by the following formula. DII MAX_OUT_MainD  )D(II MAX_OUT_Sy ncD  1 ID_Main : High-side FET drain current [A] ID_Sync : Low-side FET drain current [A] IOUT_MAX : Maximum load current [A] D : On-duty INDSS VV  VDSS : Voltage between the high-side FET drain and source and the low-side FET drain and source [V] VIN : Power supply voltage [V] Selection of fly-back diode This device is improved by adding the fly-back diode when the conversion efficiency improvement or the suppression of the low-side FET fever is desired, although those are unnecessary to execute normally. The effect is achieved in the condition where the switching frequency is high or output voltage is lower. Select schottky barrier diode (SBD) that the forward current is as small as possible. In this DC/DC control IC, the period for the electric current flow into fly-back diode is limited to dead time period because the synchronous rectification system is adopted. (as for the dead time, see “Output Block” in “ELECTRICAL CHARACTERISTICS”). Each rating for the fly-back diode can be calculated by the following formula. )tt(fII DDOSCOUT_MAXD 21  ID : Forward current rating of SBD [A] IOUT_MAX : Maximum load current [A] fOSC : Switching frequency [Hz] tD1 : Dead time period from DRVL off to DRVH on [s] tD2 : Dead time period from DRVH off to DRVL on [s] L OUT_MAXFSM III  IFSM : Peak forward surge current ratings of SBD [A] IOUT_MAX : Maximum load current [A] ΔIL : Ripple current peak-to-peak value of inductor [A] INFly_R VV  VR_Fly : Reverse voltage of fly-back diode direct current [V] VIN : Power supply voltage [V]

Document Number: 002-08491 Rev.*C Page 39 of 51 S6AP111A28 Selection of input capacitor Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor cannot support. The ripple voltage is generated in the power supply voltage by the switching operation of DC/DC. Calculate the lower bound of input capacitor according to an allowable ripple voltage. Calculate the ripple voltage of the power supply from the following formula. ΔI(IESRfV V C IΔV LOUT_M AX OSCIN OUT IN OUT_M AX ΔVIN : Power supply ripple voltage peak-to-peak value [V] IOUT_MAX : Maximum load current value [A] CIN : Input capacitor value [F] VIN : Power supply voltage [V] VOUT : Output setting voltage [V] fOSC : Switching frequency [Hz] ESR : Series resistance component of input capacitor [Ω] ΔIL : Ripple current peak-to-peak value of inductor [A] Capacitor has frequency characteristic, the temperature characteristic, and the bias voltage characteristic, etc.The effective capacitor value might become extremely small depending on the use conditions. Note the effective capacitor value in the use conditions. Calculate ratings of the input capacitor by the following formula: INCIN VV  VCIN : Withstand voltage of the input capacitor [V] VIN : Power supply voltage [V] IN OUTINOUT OMAX V )V-V(VIIrms  Irms : Allowable ripple current of input capacitor (effective value) [A] IOMAX : Maximum load current value [A] VIN : Power supply voltage [V] VOUT : Output setting voltage [V]

Document Number: 002-08491 Rev.*C Page 40 of 51 S6AP111A28 Selection of output capacitor A certain level of ESR is required for stable operation of this IC. Use a tantalum capacitor or polymer capacitor as the output capacitor. If using a ceramic capacitor with low ESR, a resistor should be connected in series with it to increase ESR equivalently. Calculate the output capacitor value by the following formula as a guide. ESRC OSC OUT f  4 COUT : Output capacitor value [F] fOSC : Switching frequency [Hz] ESR : Series resistance of output capacitor [Ω] Moreover, the output capacitor values are also derived from the allowable amount of overshoot and undershoot. The following formula is represented as the worst condition in which the shift time for a sudden load change is 0s. The output capacitor value allow a smaller amount than the value calculated by the following formula when a longer shift time. OVER_OUTOUT OUT UTO VV LIC   2 …Overshoot condition )tfVVV(VV )tfVV(LIC MIN_OFFOSCINOUTINUNDER_OUTOUT MIN_OFFOSCINOUTOUT …Undershoot condition COUT : Output capacitor value [F] ΔVOUT_OVER : Allowable amount of output voltage overshoot [V] ΔVOUT_UNDER : Allowable amount of output voltage undershoot [V] ΔlOUT : Current difference in sudden load change [A] L : Inductor value [H] VIN : Power supply voltage [V] VOUT : Output setting voltage [V] fOSC : Switching frequency [Hz] tOFF_MIN : Minimum off time The capacitor has frequency, operating temperature, and bias voltage characteristics, etc. Therefore, it must be noted that its effective capacitor value may be significantly smaller, depending on the use conditions. OUTCOUT VV  VCOUT : Withstand voltage of the output capacitor [V] VOUT : Output voltage [V] L RMS II  IRMS : Allowable ripple current of output capacitor (effective value) [A] ΔlL : Ripple current peak-to-peak value of inductor [A]

Document Number: 002-08491 Rev.*C Page 41 of 51 S6AP111A28 When connecting resistance in series configuration while a ceramic capacitor is in use, the resistor rating is calculated by the following formula. L ESR IESRP  PESR : Power dissipation of resistor [W] ESR : Resistor value [Ω] ΔIL : Ripple current peak-to-peak value of inductor [A] Selection of bootstrap capacitor To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. 0.1 μF is assumed to be standard, however, it is necessary to adjust it when the high-side FET QG is big. Consider the capacitor value calculated by the following formula as the lowest value for the bootstrap capacitor and select a thing anymore. GBST QC 10 CBST : Bootstrap capacitor value [F] QG : Total quantity of charge for the high-side FET gate [C] Calculate ratings of the bootstrap capacitor by the following formula: BCBST VV  VCBST : Withstand voltage of the bootstrap capacitor [V] VB : VB voltage [V] VB pin capacitor 2.2 μF is assumed to be a standard, and when QG of switching FET used is large, it is necessary to adjust it. To suppress the ripple voltage by the switching FET gate drive, consider the capacitor value calculated by the following formula as the lowest value for VB capacitor and select a thing anymore. )Q(Q50C G_Total2G_Total1VB  CVB : VB pin capacitor value [F] QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C] QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C] Calculate ratings of the VB pin capacitor by the following formula: BCVB VV  VCVB : Withstand voltage of the VB pin capacitor [V] VB : VB voltage [V]

Document Number: 002-08491 Rev.*C Page 42 of 51 S6AP111A28

12.3 Layout

Consider the following points in your layout.  Try to provide a ground plane on the IC mounting surface. Try not to pass the heavy current path through the ground of around IC.  Try to connect the switching system parts on the surface and avoid connecting via the through-hole as much as possible.  Provide through-holes close to GND pins for switching system parts, and connect them to the inner ground plane.  Pay particular attention to the loop composed of the input capacitor (CVCC), switching FET, and flyback diode (SBD), and make the current loop as small as possible.  Place the bootstrap capacitor (CBOOT1, CBOOT2) as close as possible to the IC CBx and LXx pins.  A large electric current will instantaneously flow in the net of the DRVHx and DRVLx pins connected to the switching FET gate. Make the wiring as short as possible and aim for a wire width of approximately 0.8 mm.  Place the bypass capacitors (CVCC, CVB, CVREF) that connect to the VCC, VB, and VREF as close to the pins as possible. In addition, connect the GND pin for the bypass capacitor to the inner ground plane through the nearest through-hole.  In order to provide the IC with more accurate feedback on the ripple voltage that is generated by the output capacitor ESR, individually pull the feedback wires connected to the VOx pins of this IC from the closest possible output capacitor pins. The wires connected to the VOx and FBx pins are sensitive to noise. Try to keep these wires as far away from switching system parts as possible. In addition, place the output voltage setting resistors that are connected to these wires as close to the IC as possible. Make the FB pin wire as short as possible. In addition, for the inner layer right under the mounting location, provide a ground plane that has minimal ripple and spike noises, or provide a power plane if possible.

Document Number: 002-08491 Rev.*C Page 43 of 51 S6AP111A28

Document Number: 002-08491 Rev.*C Page 44 of 51 S6AP111A28 13. Reference Data 100 0 1 2 3 4 5 6 Conversion Efficiency η (%) Load Current IOUT1(A) 100 0 1 2 3 4 5 6 Conversion Efficiency η (%) Load Current IOUT2(A) 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 0 2 4 6 Output Voltage VOUT2 (V) Load Current IOUT2(A) 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 0 1 2 3 4 5 6 Output Voltage VOUT1 (V) Load Current IOUT1(A) 100 150 200 250 300 350 400 0 1 2 3 4 5 6 Switching Frequency fosc1 (kHz) Load Current IOUT1(A) 250 300 350 400 450 500 550 0 1 2 3 4 5 6 Switching Frequency fosc2 (kHz) Load Current IOUT2(A) VIN=24V VOUT1=3.3V VIN=24V VOUT2=5.0V VIN=24V VIN=24V VIN=24V VOUT1=3.3V VIN=24V VOUT2=5.0V Conversion Efficiency vs. Load Current Conversion Efficiency vs. Load Current Output Voltage vs. Load Current Output Voltage vs. Load Current Switching Frequency vs. Load Current Switching Frequency vs. Load Current

Document Number: 002-08491 Rev.*C Page 45 of 51 S6AP111A28 VOUT1 50mV/div 20µs/div IOUT1 2A/div VIN=24V, VOUT1=3.3V, IOUT1=0A↔3A(1A/µs) VOUT2 50mV/div 20µs/div IOUT2 2A/div VIN=24V, VOUT2=5V, IOUT2=0A↔3A(1A/µs) Normal operation VOUT1 2V/div 400µs/div IOUT1 10A/div LX2 50V/div Over current protection operation Under voltage protection operation VIN=24V, VOUT1=3.3V Normal operation VOUT2 2V/div 400µs/div IOUT2 10A/div LX2 50V/div Over current protection operation Under voltage protection operation VIN=24V, VOUT2=5V 4µs/div VOUT1 20mV/div VIN=24V, VOUT1=3.3V, IOUT1=6A 4µs/div VOUT2 20mV/div VIN=24V, VOUT2=5V, IOUT2=6A Output Ripple Waveform Load Sudden Change Waveform Output Over Current Waveform

Document Number: 002-08491 Rev.*C Page 46 of 51 S6AP111A28 400µs/div CTL1,CTL2 5V/div VOUT1 2V/div VOUT2 2V/div VIN=24V, VOUT1=3.3V, VOUT2=5V, IOUT1,2=0A 4ms/div CTL1,CTL2 5V/div VOUT2 2V/div VOUT1 2V/div VIN=24V, VOUT1=3.3V, VOUT2=5V, IOUT1,2=0A 400µs/div CTL1 5V/div VOUT1 2V/div LX1 20V/div VIN=24V, VOUT1=3.3V, IOUT1=0A 4ms/div CTL1 5V/div VOUT1 2V/div LX1 20V/div VIN=24V, VOUT1=3.3V, IOUT1=0A 400µs/div CTL2 5V/div VOUT2 2V/div LX2 20V/div VIN=24V, VOUT2=5V, IOUT2=0A 4ms/div CTL2 5V/div VOUT2 2V/div LX2 20V/div VIN=24V, VOUT2=5V, IOUT2=0A Startup, Shutdown Waveform

Document Number: 002-08491 Rev.*C Page 47 of 51 S6AP111A28 14. Usage Precaution Printed circuit board ground lines should be set up with consideration for common impedance. Take appropriate measures against static electricity.  Containers for semiconductor materials should have anti−static protection or be made of conductive material.  After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.  Work platforms, tools, and instruments should be properly grounded.  Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground. Do not apply negative voltages. The use of negative voltages below −0.3 V may make the parasitic transistor activated to the LSI, and can cause malfunctions. 15. RoHS Compliance Information This product has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). 16. Ordering Information Part Number (MPN) Package S6AP111A28GT1B000 Plastic TSSOP (0.65 mm pitch), 24-pin (STI024) MPN: Marketing Part Number Figure 16-1 Ordering Part Number Definitions S 6A P 1 1 1 A 2 8 G T1 B 0 0 0 Fixed on 000 Packing: B = B type: 13 inch Tape and Reel Package: T1 = TSSOP, Sn-Bi / Low-Halogen Reliability Grade: G = 100 ppm Preset Condition: 28 Revision: A = 1st Revision Product ID: 11 Topology: 1 = Switch-Mode Power Supply (External FET) Product Type: P = Power Management IC Product Class: 6A = Consumer Analog Company ID: S = Cypress

Document Number: 002-08491 Rev.*C Page 48 of 51 S6AP111A28 17. Package Dimensions 002-14046 Rev. **

Document Number: 002-08491 Rev.*C Page 49 of 51 S6AP111A28 18. Major Changes Spansion Publication Number: S6AP111A28_DS405-00025 Page Section Change Results Revision 0.1 - - Initial release Revision 1.0 - - Preliminary → Full Production 16 10.5 ON/OFF Time Generator Block (tON Generator) Description is changed : the CH2 ON time is set to 1/1.5 times the CH1 ON time  the CH2 frequency is set to 1.5 times the CH1 frequency 26,27 11.2 Layout Description and picture is updated Revision 2.0 9 Absolute Maximum Ratings VO1 and 2 added. 10 Recommended Operating Conditions VO1 and 2 added. time are added. 14 to 17 Typical Characteristics Create new. 22 Function Description Figure 11.4 modified. 23 Function Description Figure 11.5 modified.

24 Function Description Boost circuit Block (CB1 and 2) create new

27,28 I/O Pin Equivalent Circuit Diagram Create new. 29 Example Application Circuit Create new. 30,31 Part List Create new. 37 to 44 Application Note Selecting parts create new. NOTE: Please see “Document History” about later revised information.

Document Number: 002-08491 Rev.*C Page 50 of 51 S6AP111A28 Document History Document Title: S6AP111A28 2ch DC/DC Converter IC with PWM Synchronous Rectification Document Number: 002-08491 Revision ECN Orig. of Change Submission Date Description of Change ** - TAOA 08/31/2015 Migrated to Cypress and assigned document number 002-08491. No change to document contents or format. *A 5135372 TAOA 02/16/2016 Updated to Cypress format. *B 5641426 HIXT 02/24/2017 Updated Pin Assignment: Change the package name from FPT-24P-M10 to STI024 Added Usage Precaution Added RoHS Compliance Information Added Ordering Information Updated Package Dimensions: Updated to Cypress format *C 5785669 MASG 06/26/2017 Adapted Cypress new logo.

Document Number: 002-08491 Rev.*C June 26, 2017 Page 51 of 51 S6AP111A28 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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