S6AE101A

S6AE101A CYPRESS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 23

Technical content

Datasheet sections

• 7.1 Power Supply Control
• 7.2 Power Gating
• 7.3 Discharge
• 7.4 Over Voltage Protection (OVP Block)
• 9.1 Setting the Operation Conditions
• 9.2 PCB Layout

Features

 Input power selection control: Solar cell or primary battery  Operated by solar cells without the need for primary batteries  Storage of energy from power supply to storage capacitors  Output power gating control, output voltage regulation  Operation input voltage range  Solar cell power : 2.0V to 5.5V  Primary battery power : 2.0V to 5.5V  Adjustable output voltage range : 1.1V to 5.2V  Low-consumption current : 250 nA  Minimum input power at startup : 1.2 µW  Input overv oltage protection : 5.4V  Compact SON-10 package : 3 mm×3 mm

Applications

 Energy harvesting power system with a very small solar cell  Bluetooth® Smart sensor  Wireless HVAC sensor  Wireless lighting control  Security system  Smart home / Building / Industrial wireless sensor Block Diagram Multiplexer Control Block Power Gating Switch Storage Control Over Voltage Protection S6AE101A Voltage Reference Circuit Battery (Optional) Solar Cell System Load

Document Number: 002-08493 Rev. *B Page 3 of 23 S6AE101A 1. Pin Assignment Figure 1-1 Pin Assignment (TOP VIEW) VBAT 4 7

10 VSTORE1

N.C. SET_VOUTL SET_VOUTH SET_VOUTFBAGND VOUT1 (VNE010) 2. Pin Descriptions Table 2-1 Pin Descriptions Pin No. Pin Name I/O Description 1 N.C − Non connection pin (Leave this pin open)

2 VINT O Internal circuit storage output pin

3 VBAT I Primary battery input pin (when being not used, leave this pin open )

4 VDD I Solar cell input pin (when being not used, leave this pin open )

5 AGND − Ground pin.

6 SET_VOUTFB O Reference voltage output pin (for connecting resistor)

7 SET_VOUTH I VOUT1 output voltage setting pin (for connecting resistor)

8 SET_VOUTL I VOUT1 output voltage setting pin (for connecting resistor)

9 VOUT1 O Output voltage pin

10 VSTORE1 O Storage output pin

Figure 2-1 I/O Pin Equivalent Circuit Diagram VSTORE1 VINT VBAT VDD AGND VOUT1 AGND VINT AGND SET_VOUTFB VINT AGND SET_VOUTL SET_VOUTH

Document Number: 002-08493 Rev. *B Page 4 of 23 S6AE101A 3. Architecture Block Diagram Figure 3-1 Architecture Block Diagram Primary Battery Solar Cell AGND SET_VOUTH SET_VOUTL SET_VOUTFB VSTORE1 VBAT Discharge VDD Power supply for internal circuit to system Load Power supply block VINT VOUT1 SW1 SW2 SW7 SW9 1.15V VSTORE1 Control VINT SW4 OVP block VINT 1.15V

Document Number: 002-08493 Rev. *B Page 5 of 23 S6AE101A 4. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Min Max Power supply voltage (*1) VMAX VDD, VBAT pin −0.3 +6.9 V Signal input voltage(*1) VINPUTMAX SET_VOUTH, SET_VOUTL pin −0.3 VVDD V VDD slew rate VSLOPE VDD pin − 0.1 mV/µs Power dissipation (*1) PD Ta ≤+ 25°C − 1200 (*2) mW Storage temperature TSTG − −55 +125 °C *1: When GND=0V *2: θja (wind speed 0m/s): +58°C/W Warning: 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings.Do not exceed any of these ratings. 5. Recommended Operating Conditions Parameter Symbol Condition Value Unit Min Typ Max Power supply voltage 1 (*1) VVDD VDD pin 2.0 3.3 5.5 V Power supply voltage 2 (*1) VVBAT VBAT pin 2.0 3.0 5.5 V Signal input voltage (*1) VINPUT SET_VOUTH, SET_VOUTL pin − − VINT pin voltage V VOUT1 setting resistance RVOUT Sum of R1, R2, R3 10 − 50 MΩ VDD capacitance C1 VDD pin 10 − − µF VINT capacitance C2 VINT pin 1 − − µF VSTORE1 capacitance C3 VSTORE1 pin 100 − − µF VOUT maximum setting voltage VSYSH VSTORE1 pin 1.3 − 5.2 V VOUT minimum setting voltage VSYSL VSTORE1 pin VSYSH ≥ 1.7V 1.1 − VSYSH × 0.90 V VSYSH < 1.7V 1.1 − VSYSH × 0.85 V Operating ambient temperature Ta − −40 − +85 °C *1: When GND = 0V Warning: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Document Number: 002-08493 Rev. *B Page 6 of 23 S6AE101A 6. Electrical Characteristics The electrical characteristics excluding the effect of external resistors and external capacitors are shown in below. Table 6-1 Electrical Characteristics (System Overall) (Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.) Parameter Symbol Condition Value Unit Min Typ Max Minimum Input power in start-up WSTART VDD pin, Ta = +25°C, VVOUTH setting =3V, By applying 0.4 µA to VDD, when VOUT1 reaches 3V × 95% after the point when VDD reaches 3V. − − 1.2 µW Consumption current 1 IQIN1 VDD pin input current, VDD=3V, Open VBAT pin, SW2 = OFF, Ta = +25°C, SET_VOUTFB resistance = 50 MΩ, VOUT1 Load = 0 mA − 250 390 nA Power detection voltage VDETH VDD, VBAT ,VINT pin 1.0 1.4 2.0 V Power undetection voltage VDETL VDD, VBAT ,VINT pin 0.9 1.3 1.9 V Power detection hysteresis VDETHYS VDD, VBAT ,VINT pin − 0.1 − V VOUT maximum voltage VVOUTH VSTORE1 pin, VOUT1 Load=0 mA VSYSH ≥ 2V VSYSH×0.950 VSYSH VSYSH×1.050 V VSYSH < 2V VSYSH×0.935 VSYSH VSYSH×1.065 V Input power reconnect voltage VVOUTM VSTORE1 pin, VOUT1 Load=0 mA VSYSH ≥ 2V VVOUTH ×0.90250 VVOUTH × 0.95 VVOUTH × 0.99750 V VSYSH < 2V VVOUTH ×0.88825 VVOUTH × 0.95 VVOUTH ×1.01175 V VOUT minimum voltage VVOUTL VSTORE1 pin, VOUT1 Load=0 mA VSYSL ≥ 2V VSYSL×0.950 VSYSL VSYSL×1.050 V VSYSL < 2V VSYSL×0.935 VSYSL VSYSL×1.065 V OVP detection voltage VOVPH VDD pin 5.2 5.4 5.5 V OVP release voltage VOVPL VDD pin 5.1 5.3 5.4 V OVP detection hysteresis VOVPHYS VDD pin − 0.1 − V OVP protection current IOVP VDD pin input current 6 − − mA Table 6-2 Electrical Characteristics (Switch) VDD ≥ 3V, VBAT ≥ 3V, VINT ≥ 3V, VVOUTL ≥ 3V, VSTORE1 ≥ VVOUTL (Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.) Parameter Symbol Condition Value Unit Min Typ Max On resistance 1 RON1 SW1, In connection of VSTORE1 pin and VOUT1 pin − 1.5 2.5 Ω On resistance 2 RON2 SW2, In connection of VDD pin and VSTORE1 pin − 5 10 kΩ On resistance 4 RON4 SW4, In connection of VDD pin and VSTORE1 pin − 5 10 kΩ Discharge resistance RDIS VOUT1 pin − 1 2 kΩ

Document Number: 002-08493 Rev. *B Page 7 of 23 S6AE101A 7. Functional Description

7.1 Power Supply Control

This IC can operate by two input power supplies, namely, the solar cell voltage VDD and the primary battery voltage VBAT. The voltages at the VDD pin and VBAT pin are monitored, and selection control of the input power supply is performed based on this voltage state (Figure 7-1). The input power (solar cell or primary battery) is temporarily stored to a capacitor connected to the VSTORE1 pin. When the voltage of the VSTORE1 pin reaches a certain threshold value or higher, the power switching switch (SW1) connects VSTORE1 and VOUT1. Table 7-1 Input Power Supply Selection Control VDD Voltage (Solar Cell) VBAT Voltage (Primary Battery) Operation VDETH (1.55V) or higher VDETH (1.55V) or higher VDD input power supply is performed VDETL (1.45V) or less VDD input power supply is performed VDETL (1.45V) or less VDETH (1.55V) or higher VBAT input power supply is performed VDETL (1.45V) or less All paths are disconnected Figure 7-1 Input Power Selection Control [V] VDD VDD VDETH VDETL time VBAT input VDETH VDETL VBAT [V] operation VDD input operation VBAT VBAT input operation VBAT time VDD VBAT VDD Input Operation Disconnection of All Paths Disconnection of All Paths (a) Switching Between VDD Input and VBAT Input (b) Switching Between VDD Input and Disconnection of All Paths VDD

Document Number: 002-08493 Rev. *B Page 8 of 23 S6AE101A 1. VDD input voltage operation This section describes operation when the VDD pin is set as the input power (Figure 7-2). [1] When the voltage of the VDD pin reaches the power detection voltage (VDETH = 1.55V) or higher, the switch (SW2) connects VDD and VSTORE1 (path S1). Also, when the voltage of the VDD pin falls to the power undetection voltage (VDETL = 1.45V) or less, SW2 disconnects the path S1. [2] When the voltage of the VSTORE1 pin reaches the threshold value (VVOUTH) or higher that was set by the SET_VOUTH pin, SW2 disconnects the path S1. Also, the VOUT switch (SW1) connects VSTORE1 and VOUT1 (path S2). [3] When the voltage of the VSTORE1 pin falls to the input power reconnect voltage (VVOUTM) or less, SW2 connects the path S1 (path S1+S2). [4] In addition, when the voltage falls to the threshold value (VVOUTL) or less that was set by the SET_VOUTL pin, SW1 disconnects the path S2. [5] When SW1 disconnects the path S2, the discharge function is activated.

Document Number: 002-08493 Rev. *B Page 9 of 23 S6AE101A Figure 7-2 VDD Pin Input Power Operation Solar Cell VDD VOUT1 VSTORE1 SW2 MCU + RF SW1S6AE101A SW7 VINTS1 VDD VINT VSTORE1 time VOUT1 VOUT1 Load SW1 SW2 SW7 on on offoff off off off on on on off on on VDD VINT VVOUTH VVOUTM VVOUTL S1 S2 S1 S2 S1S2 VDETL VDETH [1] [2] [3] [4] [5][V] [V] [V] VDETH(VDD) VDETH(VINT) Open Voltage of Solar Cell VVOUTH VVOUTM VVOUTH VVOUTL VVOUTM VVOUTH VVOUTM VVOUTH VDETL VDETH [mA] (a) Internal Operation Diagram (b) Operation Sequence on off

Document Number: 002-08493 Rev. *B Page 10 of 23 S6AE101A 2. VBAT input voltage operation This section describes operation when the VBAT pin is set as the input power (Figure 10-3). [1] When the voltage of the VBAT pin reaches the power detection voltage (VDETH = 1.55V) or higher, the switch (SW2) connects VBAT and VSTORE1 (path S3). Also, when the voltage of the VDD pin falls to the power undetection voltage (VDETL = 1.45V) or less, SW4 disconnects the path S3. [2] When the voltage of the VSTORE1 pin reaches the threshold value (VVOUTH) or higher that was set by the SET_VOUTH pin, SW4 disconnects the path S3. Also, the VOUT switch (SW1) connects VSTORE1 and VOUT1 (path S2). [3] When the voltage of the VSTORE1 pin falls to the input power reconnect voltage (VVOUTM) or less, SW4 connects the path S3 (path S3+S2). [4] In addition, when the voltage falls to the threshold value (VVOUTL) or less that was set by the SET_VOUTL pin, SW1 disconnects the path S2. [5] When SW1 disconnects the path S2, the discharge function is activated.

Document Number: 002-08493 Rev. *B Page 11 of 23 S6AE101A Figure 7-3 VBAT Pin Input Power Operation VBAT VOUT1 VSTORE1 SW4 MCU + RF SW1S6AE101A SW9 VINT Primary Battery VBAT VINT VSTORE1 VOUT1 VOUT1 Load SW1 SW4 SW9 on on offoff off off off on on on off on VBAT VINT VVOUTH VVOUTM VVOUTL S3 S2 S3 S2 S3S2 VDETL VDETH [1] [2] [3] [4] [5][V] (a) Internal Operation Diagram VDETH(VDD) VDETH(VINT) VVOUTH VVOUTM VVOUTH VVOUTL VVOUTM VVOUTH VVOUTM VVOUTH VVOUTL [V] [V] [mA] (b) Operation Sequence time on off

Document Number: 002-08493 Rev. *B Page 12 of 23 S6AE101A 3. Input power supply switching This section describes the input power switching operation (Figure 7-4). [1] If the voltages of the VDD pin and VBAT pin increase from a state where both are less than the power detection voltage (VDETH = 1.55V) so that the voltage of the VDD pin reaches the power detection voltage (VDETH = 1.55V) or higher, and operation switches to VDD input power operation back from the stage of disconnecting all paths. [2] When the voltage of the VBAT pin increases to the power detection voltage (VDETH = 1.55V) or higher, if the power from the solar cell is reduced, and when the voltage of the VDD pin falls to the power undetection voltage (VDETL = 1.45V) or less, operation switches from VDD input power operation to VBAT input power operation. [3] When the amount of power supplied from the solar cell increases, and the voltage of the VDD pin reaches the power detection voltage (VDETH = 1.55V) or higher, operation switches back to VDD input power operation. After switching, operation is performed based on VDD input power operation.

Document Number: 002-08493 Rev. *B Page 13 of 23 S6AE101A Figure 7-4 Input Power Switching VBAT SW4 SW9 Solar Cell VDD VOUT1 VSTORE1 SW2 MCU + RF SW1 SW7 VINT S6AE101A VDD VINT VSTORE1 VOUT1 VOUT1 Load SW1 SW2 SW7 onoff off off off on on on on off VDD VINT S1 S2 SW4 SW9 on off off off on on on on off VVOUTH VVOUTM VVOUTL S3 S2 + S VDETL VDETH VBAT VDETL VDETH [1] [2] VINT VDD Operation Stop VDD Input Operation VBAT Input Operation off off time VDD Input Operation VDD off off on on on off [3] (a) Internal Operation Diagram Primary Battery [V] [V] [V] [V] [mA] (b) Operation Sequence time Open Voltage of Solar Cell VDETH VDETH (VINT) VVOUTH VVOUTM VVOUTH VVOUTL VVOUTM VVOUTH VVOUTM VVOUTH (VDD,VBAT) VDETL (VDD) VVOUTM VVOUTL VDETH (VDD) VVOUTH

Document Number: 002-08493 Rev. *B Page 14 of 23 S6AE101A

7.2 Power Gating

This IC has a power gating function for the external system. Once it is detected that the voltage of the VSTORE1 pin has reached the VOUT maximum voltage (VVOUTH), the VSTORE1 pin and VOUT pin are connected by an internal switch until the VOUT minimum voltage (VVOUTL) is reached. Figure 7-5 Power Gating Operation VSTORE1 SW1 ON SW1 OFFSW1 OFF VVOUTH VVOUTL [V] VOUT1 [V] time

7.3 Discharge

This IC includes a VOUT1 pin discharge function. When SW1 disconnects the VSTORE1 and VOUT1 path, the discharge circuit is activated between the VOUT1 pin and GND. The power of the VOUT1 pin is discharged to the GND level.

7.4 Over Voltage Protection (OVP Block)

This IC includes an input overvoltage protection (OVP) function for the VDD pin voltage. When the VDD pin voltage reaches the OVP detection voltage (VOVPH=5.4V) or higher, the OVP current (IOVP) from the VDD pin is drawn in for limiting the increase in the VDD pin voltage for preventing damage to the IC. Also, when the OVP release voltage (VOVPL=5.3V) or less is reached, drawing-in of the OVP current is stopped. Figure 7-6 OVP Operation VOVPH VOVPL IOVP [V] [mA] VDD IOVP time Open Voltage of Solar Cell

Document Number: 002-08493 Rev. *B Page 15 of 23 S6AE101A 8. Application Circuit Example and Parts list Figure 8-1 Application Circuit Example S6AE101A Primary Battery Solar Battery MCU + RF AGND SET_VOUTH SET_VOUTL SET_VOUTFB VOUT1 VSTORE1 VBAT VDD VINT Table 8-1 Parts List Symbol Item Value Remarks C1 Ceramic capacitor 10 μF − C2 Ceramic capacitor 1 μF − C3 Ceramic capacitor 100 μF − R1 Resistor 6.8 MΩ (*1) − R2 Resistor 2.7 MΩ (*1) − R3 Resistor 9.1 MΩ (*1) − D1 Diode − − *1: Setting of VOUT maximum voltage: VVOUTH ≈ 3.3V, VOUT minimum voltage: VVOUTL ≈ 2.6V.

Document Number: 002-08493 Rev. *B Page 16 of 23 S6AE101A 9. Application Note

9.1 Setting the Operation Conditions

Setting of output voltage (VOUT1) The resistor connecting the SET_VOUTH pin and SET_VOUTL pin can be changed to set the VOUT1 output voltage of this IC. This is because the VOUT maximum voltage (VVOUTH) and VOUT minimum voltage (VVOUTL) are set based on the connected resistance. The SET_VOUTFB pin outputs a reference voltage for setting the VOUT maximum voltage and VOUT minimum voltage. Resistor voltage division can be performed on this reference voltage outside the IC for creating a voltage applied to the SET_VOUTH pin and SET_VOUTL pin. Figure 9-1 Setting of output voltage (VOUT1) SET_VOUTH SET_VOUTL SET_VOUTFB S6AE101A The VOUT maximum voltage (VVOUTH) and VOUT minimum voltage (VVOUTL) can be calculated using the formulas below. VOUT maximum voltage VVOUTH[V] = 57.5×(R2+R3) 11.1×(R1+R2+R3) VOUT minimum voltage VVOUTL[V] = 57.5×R3 11.1×(R1+R2+R3) The characteristics when the total value for R1, R2, and R3 is from 10 MΩ to 50 MΩ are shown in "6. Electrical Characteristics".

Document Number: 002-08493 Rev. *B Page 17 of 23 S6AE101A

9.2 PCB Layout

Take into account the following points when designing the layout.  Try to route the wiring for the diode (D1) and input capacitor (C1) for connecting the solar cell on the top layer as m uch as possible, and avoid implementing a connection using a through hole.  For the AGND pin of S6AE101A, provide a through hole nearby, and connect it to the GND plane.  Locate the capacitor (C2) for the internal power as near as possible to the VINT pin.  Locate the resistors (R1, R2, R3) for setting the output voltage in a grid -type configuration with small loops, and locat e them as near as possible to each pin (SET_VOUTFB, SET_VOUTH, SET_VOUTL) . Also, removing the GND plane under the parts can be effective in preventing malfunctions due to the leakage current.  To prevent a leakage current, locate and route the storage capacitor (C3) as far as possible from patterns that are dif ferent from the electrical potential of VSTORE1 (such as the GND li ne). Generally, the insulation resistor of printed cir cuit boards is extremely high, and normally, the passing of leakage current through the board does not pose a proble m. However, in certain rare cases, the surface of the board may have a low insulation resistance, and when using th ese boards, a leakage current that cannot be ignored may occur. Figure 9-2 PCB Layout Example Top Layer GND Layer Battery Input Solar Input VOUT Through Hole Remove Solid Pattern C2C1D1 N.C. VINT VBAT VDD AGND VSTORE1 VOUT1 SET_VOUTL SET_VOUTH SET_VOUTFB 10. Development Support This IC has a set of documentation, such as application notes, development tools, and online resources to assist you during your development process. Visit www.cypress.com/energy-harvesting to find out more.

Document Number: 002-08493 Rev. *B Page 18 of 23 S6AE101A 11. Reference Data For the circuit diagram of the reference data, Refer to "Figure 8-1 Application Circuit Example". Figure 11-1 Reference Data IQIN1 [nA] VVDD [V] 600 100 S6AE101AGraph001 IQIN1 vs VVDD VBAT voltage = 0V, SW2 = OFF, RVOUT = 50 MΩ 2.0 TA = －40oC TA = +25oC TA = +95oC 200 300 400 500 VVOUTH = 1.3V, VVOUTL = 1.1V Temp. [oC] S6AE101AGraph017-1 －40 100－20 0 20 40 60 80 VVDD = 3V RON1 [Ω] 0.4 1.8 0.6 0.8 1.0 1.2 1.4 1.6 RON1 vs Temp. Temp. [oC] S6AE101AGraph018-1 －40 100－20 0 20 40 60 80 VVDD = 3V RDIS [kΩ] 0.8 1.4 0.9 1.0 1.1 1.2 1.3 RDIS vs Temp. VDD voltage [V] Temp. [oC] 1.0 2.0 S6AE101AGraph004 VDETH, VDETL (of VDD) vs Temp. －40 100－20 0 20 40 60 80 VDETH 1.9 VDETL 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 VBAT voltage [V] Temp. [oC] 1.0 2.0 S6AE101AGraph005 VDETH, VDETL (of VBAT) vs Temp. －40 100－20 0 20 40 60 80 VDETH 1.9 VDETL 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 VINT voltage [V] Temp. [oC] 1.0 2.0 S6AE101AGraph006 VDETH, VDETL (of VINT) vs Temp. －40 100－20 0 20 40 60 80 VDETH 1.9 VDETL 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 10 s/div S6AE101AGraph020 10 s/div S6AE101AGraph019 VDD

2 V/div

VVOUTH = 5.2V, VVOUTL = 4.68V VVOUTH = 5.2V, VVOUTL = 4.68V VDD current = 0A 4 µA, VOUT1 current = 1 µA, C3 = 100 µF, VDD Input Power Supply VDD TA=+25oCTA=+25oC VDD current = 4 µA 0A, VOUT1 current = 1 µA, C3 = 100 µF,

Document Number: 002-08493 Rev. *B Page 19 of 23 S6AE101A 10 s/div S6AE101AGraph022 1 s/div S6AE101AGraph021 VVOUTH = 5.2V, VVOUTL = 4.68V VVOUTH = 5.2V, VVOUTL = 4.68V TA=+25oC VDD Input Power Supply VDD Input Power Supply VDD VDD current = 40 µA 0A, VOUT1 current = 10 µA, C3 =100µF,VDD current = 0A 40 µA, VOUT1 current = 10 µA, C3 =100µF, TA=+25oC 0.4 s/div S6AE101AGraph028 0.4 s/div S6AE101AGraph027 VDD

4 V/div

0.5 V/div

VDD & VBAT Input Power Supply VDD & VBAT Input Power Supply VVOUTH = 1.3V, VVOUTL = 1.1V VOUT1 current = 10 µA, C3 = 100 µF, TA= +25oC, VVOUTH = 1.3V, VVOUTL = 1.1V VDD voltage = 0V 5.5V, VBAT voltage = 2V VOUT1 current = 10 µA, C3 = 100 µF, TA= +25oC, VDD voltage = 5.5V 0V, VBAT voltage = 2V VDD 0.4 s/div VDD 0.4 s/div VDD & VBAT Input Power Supply VDD & VBAT Input Power Supply VVOUTH = 1.3V, VVOUTL = 1.1V VVOUTH = 1.3V, VVOUTL = 1.1V VOUT1 current = 10 µA, C3 = 100 µF, TA= +25oC, VDD voltage = 0V 2V, VBAT voltage = 5.5V VOUT1 current = 10 µA, C3 = 100 µF, TA= +25oC, VDD voltage = 2V 0V, VBAT voltage = 5.5V VDD

Document Number: 002-08493 Rev. *B Page 20 of 23 S6AE101A 12. Usage Precaution Printed circuit board ground lines should be set up with consideration for common impedance. Take appropriate measures against static electricity.  Containers for semiconductor materials should have anti−static protection or be made of conductive material.  After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.  Work platforms, tools, and instruments should be properly grounded .  Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground . Do not apply negative voltages. The use of negative voltages below −0.3 V may make the parasitic transistor activated to the LSI, and can cause malfunctions. 13. RoHS Compliance Information This product has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). 14. Ordering Information Table 14-1 Ordering Part Number Part number (MPN) Package S6AE101A0DGNAB000 10-pin plastic SON (0.5mm pitch) (VNE010) MPN: Marketing Part Number Figure 14-1 Ordering Part Number Definitions S 6A E 1 0 1 A 0D G NA B 0 0 0 Fixed on 000 Packing: B = 13 inch Tape and Reel (ER) Package: NA = SON, Pd-PPF/Low-Halogen Reliability Grade: Preset Condition Revision: A = 1st Revision Product ID: 01 Topology: 1 = Buck Power Supply Product Type: E = Energy Harvesting PMIC Product Class: 6A = Consumer Analog Company ID: S = Cypress G = 100 ppm (Commercial Sample)

Document Number: 002-08493 Rev. *B Page 21 of 23 S6AE101A 15. Package Dimensions

Document Number: 002-08493 Rev. *B Page 22 of 23 S6AE101A 16. Major Changes Spansion Publication Number: S6AE101A_DS405-00026 Page Section Change Results Preliminary 0.1 − − Initial release NOTE: Please see “Document History” about later revised information. Document History Document Title: S6AE101A Energy Harvesting PMIC for Wireless Sensor Node Document Number: 002-08493 Revision ECN Orig. of Change Submission Date Description of Change ** − TAOA 04/27/2015 New Spec. *A 5054369 TAOA 12/17/2015 Added Block Diagram Updated 5. Recommended Operating Conditions Updated 6. Electrical Characteristics Updated Table 8-1 Parts List Updated 9.1 Setting the Operation Conditions: Changed the formulas for the VOUT maximum voltage and VOUT minimum voltage. *B 5103619 HIXT 01/25/2016 Added Figure 2-1 I/O Pin Equivalent Circuit Diagram Updated Figure 3-1 Architecture Block Diagram Added 10. Development Support Added 11. Reference Data

Document Number: 002-08493 Rev. *B January 25, 2016 Page 23 of 23 S6AE101A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless Spansion Products cypress.com/spansionproducts PSoC® Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support Cypress, the Cypress logo, Spansion ®, the Spansion logo, MirrorBit ®, MirrorBit® EclipseTM, ORNANDTM, Easy DesignSim TM, TraveoTM and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2015-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsi bility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license und er patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life -support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The in clusion of Cypress products in life -support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and s ubject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in supp ort of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress doe s not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be exp ected to result in significant injury to the user. The inclusion of Cypress’ product in a life -support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.