S34ML02G1

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Technical content

Datasheet sections

• 1.1 Logic Diagram
• 1.2 Connection Diagram
• 1.3 Pin Description
• 1.4 Block Diagram
• 1.5 Array Organization
• 1.6 Addressing
• 1.7 Mode Selection
• 2.1 Command Input
• 2.2 Address Input
• 2.3 Data Input
• 2.4 Data Output
• 2.5 Write Protect
• 2.6 Standby
• 3.1 Page Read
• 3.2 Page Program
• 3.3 Multiplane Program
• 3.4 Page Reprogram
• 3.5 Block Erase
• 3.6 Multiplane Block Erase
• 3.7 Copy Back Program
• 3.8 EDC Operation — S34ML 02G1 and S34ML04G1
• 3.9 Read Status Register
• 3.10 Read Status Enhanced
• 3.11 Read Status Register Field Definition
• 3.12 Reset
• 3.13 Read Cache
• 3.14 Cache Program
• 3.15 Multiplane Cache Program
• 3.16 Read ID
• 3.17 Read ID2
• 3.18 Read ONFI Signature
• 3.19 Read Parameter Page
• 3.20 One-Time Programmable (OTP) Entry
• 4.1 Data Protection and Power On / Off Sequence
• 4.2 Ready/Busy
• 4.3 Write Protect Operation
• 5.1 Valid Blocks
• 5.2 Absolute Maximum Ratings
• 5.4 AC Test Conditions
• 5.5 AC Characteristics
• 5.6 DC Characteristics
• 5.7 Pin Capacitance
• 5.8 Thermal Resistance
• 5.9 Program / Erase Characteri stics
• 6.1 Command Latch Cycle
• 6.2 Address Latch C ycle
• 6.3 Data Input Cycle Timing
• 6.4 Data Output Cycle Timing
• 6.5 Data Output Cycle Timing
• 6.6 Page Read Operation
• 6.8 Page Read Operation Timing with CE# Don’t Care
• 6.9 Page Program Operation
• 6.10 Page Program Operation Timing
• 6.11 Page Program Operation with Random Data Input
• 6.12 Random Data Output In a Page
• 6.13 Multiplane Page Program Operation
• 6.14 Block Erase Operation
• 6.15 Multiplane Block Erase
• 6.16 Copy Back Read with Optional Data Readout
• 6.17 Copy Back Program Operation
• 6.18 Multiplane Copy Back Program
• 6.19 Read Status Register Timing
• 6.20 Read Status Enhanced Timing
• 6.21 Reset Operation Timing
• 6.22 Read Cache
• 6.23 Cache Program
• 6.24 Multiplane Cache Program
• 6.25 Read ID Operation Timing
• 6.26 Read ID2 Operation Timing
• 6.27 Read ONFI Signature Timing
• 6.28 Read Parameter Page Timing
• 6.29 OTP Entry Timing
• 6.30 Power On and Data Protection Timing
• 6.31 WP# Handling
• 7.1 Physical Diagram
• 9.1 System Bad Block Replacement
• 9.2 Bad Block Management

1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash

Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-00676 Rev. *V Revised March 20, 2018 Distinctive Characteristics ■ Density ❐ 1 Gb/ 2 Gb / 4 Gb ■ Architecture ❐ Input / Output Bus Width: 8-bits / 16-bits ❐ Page size:

• x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area
• x16 = 1056 (1024 + 32) words; 32 words is spare area ❐ Block size: 64 Pages
• x8 = 128 KB + 4 KB
• x16 = 64k + 2k words ❐ Plane size:
• 1 Gb / 2 Gb: 1024 Blocks per Plane x8 = 128 MB + 4 MB x16 = 64M + 2M words Gb: 2048 Blocks per Plane x8 = 256 MB+ 8 MB x16 = 128M + 4M words ❐ Device size:
• 1 Gb: 1 Plane per Device or 128 MB
• 2 Gb: 2 Planes per Device or 256 MB
• 4 Gb: 2 Planes per Device or 512 MB ■ NAND flash interface ❐ Open NAND Flash Interface (ONFI) 1.0 compliant ❐ Address, Data and Commands multiplexed ■ Supply voltage ❐ 3.3-V device: Vcc = 2.7 V ~ 3.6 V ■ Security ❐ One Time Programmable (OTP) area ❐ Hardware program/erase disabled during power transition ■ Additional features ❐ 2 Gb and 4 Gb parts support Multiplane Program and Erase commands ❐ Supports Copy Back Program ❐ 2 Gb and 4 Gb parts support Multiplane Copy Back Program ❐ Supports Read Cache ■ Electronic signature ❐ Manufacturer ID: 01h ■ Operating temperature ❐ Industrial: -40 °C to 85 °C ❐ Automotive: -40 °C to 105 °C Performance ■ Page Read / Program ❐ Random access: 25 µs (Max) ❐ Sequential access: 25 ns (Min) ❐ Program time / Multiplane Program time: 200 µs (Typ) ■ Block Erase (S34ML01G1) ❐ Block Erase time: 2.0 ms (Typ) ■ Block Erase / Multiplane Erase (S34ML02G1, S34ML04G1) ❐ Block Erase time: 3.5 ms (Typ) ■ Reliability ❐ 100,000 Program / Erase cycles (Typ) (with 1 bit ECC per 528 bytes (x8) or 264 words (x16)) ❐ 10 Year Data retention (Typ) ❐ For one plane structure (1-Gb density)
• Block zero is valid and will be valid for at least 1,000 program-erase cycles with ECC ❐ For two plane structures (2-Gb and 4-Gb densities)
• Blocks zero and one are valid and will be valid for at least 1,000 program-erase cycles with ECC ■ Package options ❐ Lead Free and Low Halogen ❐ 48-Pin TSOP 12  20  1.2 mm ❐ 63-Ball BGA 9  11  1 mm

Document Number: 002-00676 Rev. *V Page 3 of 71 S34ML01G1 S34ML02G1 S34ML04G1

Document Number: 002-00676 Rev. *V Page 4 of 71 S34ML01G1 S34ML02G1 S34ML04G1 1. General Description The Cypress S34ML01G1, S34ML02G1, and S34ML04G1 series is offered with a 3.3-V VCC power supply, and with ×8 or ×16 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for ×8 is (2048 + 64 spare) bytes; for ×16 (1024 + 32) words. Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory. The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device by a microcontroller, since the CE# transitions do not stop the read operation. The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load the data in a cache register while the previous data is transferred to the I/O buffers to be read. Like all other 2-kB page NAND flash devices, a program operation typically writes 2112 bytes (×8), or 1056 words (×16) in 200 µs and an erase operation can typically be performed in 2 ms (S34ML01G1) on a 128-kB block (×8) or 64-kword block (×16). In addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%. In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of the footprint. Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins. The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required, and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase operations. The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a single pull-up resistor. In a system with multiple memories the R/B# pins can be connected all together to provide a global status signal. The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The Copy Back operation automatically executes embedded error detection operation: 1-bit error out of every 528 bytes (×8) or 256 words (×16) can be detected. With this feature it is no longer necessary to use an external mechanism to detect Copy Back operation errors. Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed. In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data using the cache register. The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram re-programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the second plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during re-program operations. Note: The S34ML01G1 device does not support EDC.

data sheet. For more details, contact your nearest Cypress sales office.

1.1 Logic Diagram

Figure 1. Logic Diagram Table 1. Product List Table 2. Signal Names

1.2 Connection Diagram

Figure 2. 48-Pin TSOP1 Contact ×8, ×16 Devices

1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.

Figure 3. 63-BGA Contact, ×8 Device (Balls Down, Top View)

1. These pins should be c onnected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.

Figure 4. 63-BGA Contact, ×16 Device (Balls Down, Top View)

1.3 Pin Description

1. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB

track widths must be sufficient to carry the currents required during program and erase operations.

1. An internal voltage detector disables all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions.

Table 3. Pin Description CE# Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory. WE# Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#. tREA after the falling edge of RE# which also increments the internal column address counter by one. R/B# Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory. prevents the insertion of Commands when VCC is less than VLKO.

1.4 Block Diagram

Figure 5. Functional Block Diagram

1024 Mbit + 32 Mbit (1 Gb Device)Program Erase

4096 Mbit + 128 Mbit (4 Gb Device)

1.5 Array Organization

Figure 6. Array Organization — ×8 Figure 7. Array Organization — ×16

1 Page = (2k + 64) bytes

1 Block = (2k + 64) bytes x 64 pages

1 Plane = (128k + 4k) bytes x 1024 Blocks

2 Gb and 4 Gb devices have two Planes

1 Page = (1k + 32) words

1 Block = (1k + 32) words x 64 pages

1 Plane = (64k + 2k) words x 1024 Blocks

1.6 Addressing

1.6.1 S34ML01G1

1. CAx = Column Address bit.
2. Block address concatenated with page address = actual page ad dress, also known as the row address.
3. I/O[15:8] are not used during the addressing sequence and sho uld be driven Low.

1.6.2 S34ML02G1

Table 4. Address Cycle Map — 1 Gb Device Table 5. Address Cycle Map — 2 Gb Device

1. CAx = Column Address bit.
2. PLA0 = Plane Address bit zero.
3. BAx = Block Address bit.
4. Block address concatenated with page address and plane address = actual page address, also known as the row address.
5. I/O[15:8] are not used during the addressing sequence and should be driven Low.

1.6.3 S34ML04G1

1. CAx = Column Address bit.
2. PLA0 = Plane Address bit zero.
3. BAx = Block Address bit.
4. Block address concatenated with page address and plane address = actual page address, also known as the row address.
5. I/O[15:8] are not used during the addressing sequence and should be driven Low.

Table 6. Address Cycle Map — 4 Gb Device

1.7 Mode Selection

1. X can be VIL or VIH. High= Logic level high. Low = Logic level low.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. During Busy Time in Read, RE# must be held high to prevent unintended data out.

Table 7. Mode Selection

Document Number: 002-00676 Rev. *V Page 13 of 71 S34ML01G1 S34ML02G1 S34ML04G1 2. Bus Operation There are six standard bus operations that control the device: Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. (See Table 7.) Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory and do not affect bus operations.

2.1 Command Input

The Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be high. See Figure 12 on page 38 and Table 20 on page 35 for details of the timing requirements. Command codes are always applied on I/O7:0 regardless of the bus configuration (×8 or ×16).

2.2 Address Input

The Address Input bus operation allows the insertion of the memory address. For the S34ML02G1 and S34ML04G1 devices, five write cycles are needed to input the addresses. For the S34ML01G1, four write cycles are needed to input the addresses. If necessary, a 5th dummy address cycle can be issued to S34ML01G1, which will be ignored by the NAND device without causing problems. Addresses are accepted with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be high. See Figure 13 on page 38 and Table 20 on page 35 for details of the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus configuration (×8 or ×16). Refer to Table 4 through Table 6 on page 11 for more detailed information.

2.3 Data Input

The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serial and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable high, and Write Protect high and latched on the rising edge of Write Enable. See Figure 14 on page 39 and Table 20 on page 35 for details of the timing requirements.

2.4 Data Output

The Data Output bus operation allows data to be read from the memory array and to check the Status Register content, the EDC register content, and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low, Write Enable high, Address Latch Enable low, and Command Latch Enable low. See Figure 15 on page 39 and Table 20 on page 35 for details of the timings requirements.

2.5 Write Protect

The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify operations do not start and the content of the memory is not altered. The Write Protect pin is not latched by Write Enable to ensure the protection even during power up.

2.6 Standby

In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.

Table 8. Command Set

Document Number: 002-00676 Rev. *V Page 15 of 71 S34ML01G1 S34ML02G1 S34ML04G1

3.1 Page Read

Page Read is initiated by writing 00h and 30h to the command register along with five address cycles (four or five cycles for S34ML01G1). Two types of operations are available: random read and serial page read. Random read mode is enabled when the page address is changed. All data within the selected page are transferred to the data registers. The system controller may detect the completion of this data transfer (tR) by analyzing the output of the R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25 ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE# signal makes the device output the data, starting from the selected column address up to the last column address. The device may output random data in a page instead of the sequential data by writing Random Data Output command. The column address of next data, which is going to be out, may be changed to the address that follows Random Data Output command. Random Data Output can be performed as many times as needed. After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation. Any operation other than read or Random Data Output causes the device to exit read mode. See Figure 6.1 on page 40 and Figure 21 on page 43 as references.

3.2 Page Program

A page program cycle consists of a serial data loading period in which up to 2112 bytes (×8) or 1056 words (×16) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs (four cycles for S34ML01G1) and then serial data. The words other than those to be programmed do not need to be loaded. The device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to the address that follows the Random Data Input command (85h). Random Data Input may be performed as many times as needed. The Page Program confirm command (10h) initiates the programming process. The internal write state controller automatically executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register. The system controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read Status command mode until another valid command is written to the command register. F i g u r e6 . 2 o np a g e4 2 and Figure 20 on page 43 detail the sequence. The device is programmable by page, but it also allows multiple partial page programming of a word or consecutive bytes up to 2112 bytes (×8) or 1056 words (×16) in a single page program cycle. The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number indicated in Table 23 on page 37. Pages may be programmed in any order within a block. Users who use “EDC check” (for S34ML02G1 and S34ML04G1 only) in copy back must comply with some limitations related to data handling during one page program sequence. Refer to Section 3.8 on page 19 for details. If a Page Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.

3.3 Multiplane Program — S 34ML02G1 and S34ML04G1

must be in the 2nd plane (PLA0 = 1). The Program Confirm command (10h) starts parallel programming of both pages. Status Register will be set. Refer to Section 3.9 on page 21 for further info. indicated in Table 23 on page 37. Pages may be programmed in any order within a block.

3.4 Page Reprogram — S34ML02G1 and S34ML04G1

Page Program may result in a fail, which can be detected by Read Status Register. In this event, the host may call Page Reprogram. cycle, as described in Figure 8. Figure 8. Page Reprogram

before program confirm ‘10h’, as described in Figure 9. Figure 9. Page Reprogram with Data Manipulation of how many times it is done in a page. executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks. controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.

Document Number: 002-00676 Rev. *V Page 18 of 71 S34ML01G1 S34ML02G1 S34ML04G1

3.5 Block Erase

The Block Erase operation is done on a block basis. Block address loading is accomplished in three cycles (two cycles for S34ML01G1) initiated by an Erase Setup command (60h). Only the block address bits are valid while the page address bits are ignored. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by the execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase verify. Once the erase process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register. The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O0) may be checked. Figure 24 on page 45 details the sequence. If a Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted block is erased under continuous power conditions before that block can be trusted for further programming and reading operations.

3.6 Multiplane Block Erase — S34ML02G1 and S34ML04G1

Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane. The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. In this case, multiplane erase does not need any Dummy Busy Time between 1st and 2nd block insertion. See Table 23 on page 37 for performance information. For the Multiplane Block Erase operation, the address of the first block must be within the first plane (PLA0 = 0) and the address of the second block in the second plane (PLA0 = 1). See Figure 25 on page 45 for a description of the legacy protocol. In this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 26 on page 46 describes the sequences using the ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status Register command is also available during Dummy Busy time (tDBSY). In case of failure in either erase, the fail bit of the Status Register will be set. Refer to Section 3.9 on page 21 for further information. If a Multiplane Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted blocks are erased under continuous power conditions before those blocks can be trusted for further programming and reading operations.

3.7 Copy Back Program

The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved. The benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also needs to be copied to the newly assigned free block. The operation for performing a copy back is a sequential execution of page-read (without mandatory serial access) and Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the address of the source page moves the whole page of data into the internal data register. As soon as the device returns to the Ready state, optional data read-out is allowed by toggling RE# (see Figure 27 on page 46), or the Copy Back Program command (85h) with the address cycles of the destination page may be written. The Program Confirm command (10h) is required to actually begin programming. The source and the destination pages in the Copy Back Program sequence must belong to the same device plane (same PLA0 for S34ML02G1 and S34ML04G1). Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the device to meet the program time (tPROG) specification. Copy Back Program may not meet this specification when copying from an odd address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page (target page). The data input cycle for modifying a portion or multiple distinct portions of the source page is allowed as shown in Figure 28 on page 46. As noted in Section 1. on page 4 the device may include an automatic EDC (for S34ML02G1 and S34ML04G1) check during the copy back operation, to detect single bit errors in EDC units contained within the source page. More details on EDC operation and limitations related to data input handling during one Copy Back Program sequence are available in Section 3.8 on page 19.

Document Number: 002-00676 Rev. *V Page 19 of 71 S34ML01G1 S34ML02G1 S34ML04G1 If a Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.

3.7.1 Multiplane Copy Back Progr am — S34ML02G1 and S34ML04G1

The device supports Multiplane Copy Back Program with exactly the same sequence and limitations as the Page Program. Multiplane Copy Back Program must be preceded by two single page Copy Back Read command sequences (1st page must be read from the 1st plane and 2nd page from the 2nd plane). Multiplane Copy Back cannot cross plane boundaries — the contents of the source page of one device plane can be copied only to a destination page of the same plane. EDC check is available also for Multiplane Copy Back Program only for S34ML02G1 and S34ML04G1. When “EDC check” is used in copy back, it must comply with some limitations related to data handling during one Multiplane Copy Back Program sequence. Please refer to Section 3.8 on page 19 for details on EDC operation. The Multiplane Copy Back Program sequence represented in Figure 29 on page 47 shows the legacy protocol. In this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 30 on page 47 describes the sequence using the ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. If a Multiplane Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks.

3.7.2 Special Read for Copy B ack — S34ML02G1 and S34ML04G1

The S34ML02G1 and S34ML04G1 devices support Special Read for Copy Back. If Copy Back Read (described in Section 3.7 and Section 3.7.1 on page 19) is triggered with confirm command ‘36h’ instead ‘35h’, Copy Back Read from target page(s) will be executed with an increased internal (VPASS) voltage. This special feature is used in order to minimize the number of read errors due to over-program or read disturb — it shall be used only if ECC read errors have occurred in the source page using Page Read or Copy Back Read sequences. Excluding the Copy Back Read confirm command, all other features described in Section 3.7 and Section 3.7.1 for standard copy back remain valid (including the figures referred to in those sections).

3.8 EDC Operation — S34ML02G1 and S34ML04G1

Error Detection Code check is a feature that can be used during the copy back operation (both single and multiplane) to detect single bit errors occurring in the source page(s). Note: The S34ML01G1 device does not support EDC.  EDC check allows detection of up to 1 single bit error every 528 bytes, where each 528 byte group is composed of 512 bytes of main array and 16 bytes of spare area (see Table 10 and Table 11 on page 21). The described 528-byte area is called an “EDC unit.”  In the ×16 device, EDC allows detection of up to 1 single bit error every 264 words, where each 264 word group is composed by 256 words of main array and 8 words of spare area see Table 10 and Table 11 on page 21). The described 264-word area is called “EDC unit.” EDC results can be checked through a specific Read EDC register command, available only after issuing a Copy Back Program or a Multiplane Copy Back Program. The EDC register can be queried during the copy back program busy time (tPROG). For the “EDC check” feature to operate correctly, specific conditions on data input handling apply for program operations.

cannot be written to any column address more than once before the program is initiated. the EDC check is possible only if the whole EDC unit is modified during one Copy Back Program sequence. data insertion in each column address of the EDC unit must not exceed 1. If you use copy back without EDC check, none of the limitations described above apply. can execute a Page Read operation in order to correct a single bit error with external ECC software or hardware.

3.8.1 Read EDC Status Register — S34ML02G1 and S34ML04G1

the case of multiplane copy back, it is not possible to know which of the two read operations caused the error. Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last. Table 9. EDC Register Coding

0 Pass / Fail Pass: 0; Fail: 1

1 EDC status No error: 0; Error: 1

2 EDC validity Invalid: 0; Valid: 1

5 Ready / Busy Busy: 0; Ready: 1

6 Ready / Busy Busy: 0; Ready: 1

7 Write Protect Protect ed: 0; Not Protected: 1

3.9 Read Status Register

status value related to the outcome of the operation in the two planes according to the following table. In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it. during a random read cycle, the read command (00h) must be issued before starting read cycles. Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack configurations (single CE#). “Read Status Enhanced” shall be used instead. Table 10. Page Organization in EDC Units Table 11. Page Organization in EDC Units by Address Table 12. Read Status Definition

3.10 Read Status Enhanced — S34ML02G1 and S34ML04G1

Read Status Enhanced is used to retrieve the status value for a previous operation in the specified plane. command sequence in order to retrieve the status of the die and the plane of interest. The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.

3.11 Read Status Register Field Definition

3.12 Reset

Table 13. Status Register Coding

0 Pass / Fail Pass / Fail NA NA Pass / Fail

1 NA NA NA NA Pass / Fail

5 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Internal Data Operation Active: 0

6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy

7 Write Protect Write Protect NA NA Write Protect Protected: 0

Document Number: 002-00676 Rev. *V Page 23 of 71 S34ML01G1 S34ML02G1 S34ML04G1

3.13 Read Cache

Read Cache can be used to increase the read operation speed, as defined in Section 3.1 on page 15, and it cannot cross a block boundary. As soon as the user starts to read one page, the device automatically loads the next page into the cache register. Serial data output may be executed while data in the memory is read into the cache register. Read Cache is initiated by the Page Read sequence (00-30h) on a page M. After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6 switches to high), two command sequences can be used to continue read cache:  Read Cache (command ‘31h’ only): once the command is latched into the command register (see Figure 35 on page 49), device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the data register to the cache register. At the end of this phase, the cache register data can be output by toggling RE# while the next page (page address M+1) is read from the memory array into the data register.  Read Cache Enhanced (sequence ‘00h’ <page N address> ‘31’): once the command is latched into the command register (see Figure 36 on page 50), device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the data register to the cache register. At the end of this phase, cache register data can be output by toggling RE# while page N is read from the memory array into the data register. Note: The S34ML01G1 device does not support Read Cache Enhanced. Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command sequences. If serial data output time of one page exceeds random access time (tR), the random access time of the next page is hidden by data downloading of the previous page. On the other hand, if 31h is issued prior to completing the random access to the next page, the device will stay busy as long as needed to complete random access to this page, transfer its contents into the cache register, and trigger the random access to the following page. To terminate the Read Cache operation, 3Fh command should be issued (see Figure 37 on page 50). This command transfers data from the data register to the cache register without issuing next page read. During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh, Read SR, or Reset (FFh). To carry out other operations, Read Cache must be terminated by the Read Cache End command (3Fh) or the device must be reset by issuing FFh. Read Status command (70h) may be issued to check the status of the different registers and the busy/ready status of the cached read operations.  The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data.  The status bit I/O5 can be used to determine when the cell reading of the current data register contents is complete. Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is toggled to output the data of a given page, the first output data is related to the first byte of the page (column address 00h). Random Data Output command can be used to switch column address.

Document Number: 002-00676 Rev. *V Page 24 of 71 S34ML01G1 S34ML02G1 S34ML04G1

3.14 Cache Program

Cache Program can improve the program throughput by using the cache register. The Cache Program operation cannot cross a block boundary. The cache register allows new data to be input while the previous data that was transferred to the data register is programmed into the memory array. After the serial data input command (80h) is loaded to the command register, followed by five cycles of address, a full or partial page of data is latched into the cache register. Once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data register for cell programming. At this time the device remains in the Busy state for a short time (tCBSYW). After all data of the cache register is transferred into the data register, the device returns to the Ready state and allows loading the next data into the cache register through another Cache Program command sequence (80h-15h). The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to the data register. Cell programming the data of the data register and loading of the next data into the cache register is consequently processed through a pipeline model. In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming of current data register contents is complete; till this moment the device will stay in a busy state (tCBSYW). Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the pass/fail status of the cached program operations.  The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.  The status bit I/O5 can be used to determine when the cell programming of the current data register contents is complete.  The Cache Program error bit I/O1 can be used to identify if the previous page (page N-1) has been successfully programmed or not in a Cache Program operation. The status bit is valid upon I/O6 status bit changing to 1.  The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while programming page N. The status bit is valid upon I/O5 status bit changing to 1. I/O1 may be read together with I/O0. If the system monitors the progress of the operation only with R/B#, the last page of the target program sequence must be programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is finished before starting any other operation. See Table 13 on page 22 and Figure 38 on page 50 for more details. If a Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks.

Document Number: 002-00676 Rev. *V Page 25 of 71 S34ML01G1 S34ML02G1 S34ML04G1

3.15 Multiplane Cache Program — S34ML02G1 and S34ML04G1

The Multiplane Cache Program enables high program throughput by programming two pages in parallel, while exploiting the data and cache registers of both planes to implement cache. The command sequence can be summarized as follows:  Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within 1st plane (PLA0 = 0). The data of 1st page other than those to be programmed do not need to be loaded. The device supports Random Data Input exactly like Page Program operation.  The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY).  Once device returns to ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be within 2nd plane (PLA0 = 1). The data of 2nd page other than those to be programmed do not need to be loaded.  Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command register, the data in the cache registers is transferred into the data registers for cell programming. At this time the device remains in the Busy state for a short time (tCBSYW). After all data from the cache registers are transferred into the data registers, the device returns to the Ready state, and allows loading the next data into the cache register through another Cache Program command sequence. complete programming the current data register contents, and transferring the new data from the cache registers. The sequence to The Multiplane Cache Program is available only within two paired blocks in separate planes. Figure 39 on page 51 shows the legacy protocol for the Multiplane Cache Program operation. In this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 40 on page 52 shows the ONFI protocol for the Multiplane Cache Program operation. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user opts for 70h, Read Status Register will provide “global” information about the operation in the two planes.  I/O6 indicates when both cache registers are ready to accept new data.  I/O5 indicates when the cell programming of the current data registers is complete.  I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not. This status bit is valid upon I/O6 status bit changing to 1.  I/O0 identifies if any error has been detected by the program/erase controller while programming the two pages N. This status bit is valid upon I/O5 status bit changing to 1. See Table 13 on page 22 for more details. If the system monitors the progress of the operation only with R/B#, the last pages of the target program sequence must be programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is finished before starting any other operation. Refer to Section 3.9 on page 21 for further information. If a Multiplane Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks.

3.16 Read ID

before Read Status command (0x70). Table 14. Read ID for Supported Configurations

2 Gb 01h DAh 90h 95h 44h

4 Gb 01h DCh 90h 95h 54h

2 Gb 01h CAh 90h D5h 44h

4 Gb 01h CCh 90h D5h 54h

Table 15. Read ID Bytes 3rd Internal chip number, cell type, etc.

Table 16. Read ID Byte 3 Description

Document Number: 002-00676 Rev. *V Page 28 of 71 S34ML01G1 S34ML02G1 S34ML04G1 5th ID Data Table 3.2 Read ID Byte 4 Description — S34ML02G1 and S34ML04G1 Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Page Size (without spare area) 1 kB 2 kB 4 kB 8 kB 0 0 0 1 1 0 1 1 Block Size (without spare area) 64 kB 128 kB 256 kB 512 kB 0 0 0 1 1 0 1 1 Spare Area Size (byte / 512 byte) Serial Access Time 50 ns / 30 ns 25 ns Reserved Reserved Organization ×8 0 ×16 1 Table 3.3 Read ID Byte 5 Description — S34ML02G1 and S34ML04G1 Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Plane Number 0 0 0 1 1 0 1 1 Plane Size (without spare area) 64 Mb 128 Mb 256 Mb 512 Mb 1 Gb 2 Gb 4 Gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 Reserved 0 0 0

Document Number: 002-00676 Rev. *V Page 29 of 71 S34ML01G1 S34ML02G1 S34ML04G1

3.17 Read ID2

The device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command register, followed by address inputs, followed by command 30h. The address for S34ML01G1 will be 00h-02h-02h-00h. The address for S34ML02G1 and S34ML04G1 will be 00h-02h-02h-00h-00h. The ID2 data can then be read from the device by pulsing RE#. The command register remains in Read ID2 mode until further commands are issued to it. Figure 42 on page 53 shows the Read ID2 command sequence. Read ID2 values are all 0xFs, unless specific values are requested when ordering from Cypress.

3.18 Read ONFI Signature

To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i.e. it is not valid to enter an address of 00h and read 36 bytes to get the ONFI signature). The ONFI signature is the ASCII encoding of 'ONFI' where 'O' = 4Fh, 'N' = 4Eh, 'F' = 46h, and 'I' = 49h. Reading beyond four bytes yields indeterminate values. Figure 43 on page 54 shows the operation sequence.

3.19 Read Parameter Page

The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an address input of 00h. The host may monitor the R/B# pin or wait for the maximum data transfer time (tR) before reading the Parameter Page data. The command register remains in Parameter Page mode until further commands are issued to it. If the Status Register is read to determine when the data is ready, the Read Command (00h) must be issued before starting read cycles. Figure 44 on page 54 shows the operation sequence, while Table 3.4 explains the parameter fields. For ×16 devices, the upper eight I/Os are not used and are 0xFF. Note: For 41nm 2Gb/4Gb Cypress NAND, for a particular condition, the Read Parameter Page command does not give the correct values. To overcome this issue, the host must issue a Reset command before the Read Parameter Page command. Issuance of Reset before the Read Parameter Page command will provide the correct values and will not output 00h values. This does not apply to 48nm 1Gb. Table 3.4 Parameter Page Description Byte O/M Description Values Revision Information and Features Block 0-3 M Parameter page signature Byte 0: 4Fh, “O” Byte 1: 4Eh, “N” Byte 2: 46h, “F” Byte 3: 49h, “I” 4Fh, 4Eh, 46h, 49h 4-5 M Revision number 2-15 Reserved (0) 1 1 = supports ONFI version 1.0

0 Reserved (0)

02h, 00h 6-7 M Features supported 5-15 Reserved (0) 4 1 = supports odd to even page Copyback 3 1 = supports interleaved operations 2 1 = supports non-sequential page programming 1 1 = supports multiple LUN operations 0 1 = supports 16-bit data bus width S34ML01G100 (×8): 14h, 00h S34ML02G100 (×8): 1Ch, 00h S34ML04G100 (×8): 1Ch, 00h S34ML01G104 (×16): 15h, 00h S34ML02G104 (×16): 1Dh, 00h S34ML04G104 (×16): 1Dh, 00h 8-9 M Optional commands supported 6-15 Reserved (0) 5 1 = supports Read Unique ID 4 1 = supports Copyback 3 1 = supports Read Status Enhanced 2 1 = supports Get Features and Set Features 1 1 = supports Read Cache commands 0 1 = supports Page Cache Program command S34ML01G1: 13h, 00h S34ML02G1: 1Bh, 00h S34ML04G1: 1Bh, 00h 10-31 Reserved (0) 00h Manufacturer Information Block

Document Number: 002-00676 Rev. *V Page 30 of 71 S34ML01G1 S34ML02G1 S34ML04G1 32-43 M Device manufacturer (12 ASCII characters) 53h, 50h, 41h, 4Eh, 53h, 49h, 4Fh, 4Eh, 20h, 20h, 20h, 20h 44-63 M Device model (20 ASCII characters) S34ML01G1: 53h, 33h, 34h, 4Dh, 4Ch, 30h, 31h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h S34ML02G1: 53h, 33h, 34h, 4Dh, 4Ch, 30h, 32h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h S34ML04G1: 53h, 33h, 34h, 4Dh, 4Ch, 30h, 34h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h

64 M JEDEC manufacturer ID 01h

67-79 Reserved (0) 00h Memory Organization Block 80-83 M Number of data bytes per page 00h, 08h, 00h, 00h 84-85 M Number of spare bytes per page 40h, 00h 86-89 M Number of data bytes per partial page 00h, 02h, 00h, 00 h 90-91 M Number of spare bytes per partial page 10h, 00h 92-95 M Number of pages per block 40h, 00h, 00h, 00h 96-99 M Number of blocks per logical unit (LUN) S34ML01G1: 00h, 04h, 00h, 00h S34ML02G1: 00h, 08h, 00h, 00h S34ML04G1: 00h, 10h, 00h, 00h

100 M Number of logical units (LUNs) 01h

S34ML01G1: 22h S34ML02G1: 23h S34ML04G1: 23h

102 M Number of bits per cell 01h

103-104 M Bad blocks maximum per LUN S34ML01G1: 14h, 00h S34ML02G1: 28h, 00h S34ML04G1: 50h, 00h 105-106 M Block endurance 01h, 05h

107 M Guaranteed valid blocks at beginning of target 01h

108-109 M Block endurance for guaranteed valid blocks 01h, 03h

110 M Number of programs per page 04h

Partial programming attributes 5-7 Reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 Reserved 0 1 = partial page programming has constraints 00h

112 M Number of bits ECC correctability 01h

Number of interleaved address bits 4-7 Reserved (0) 0-3 Number of interleaved address bits S34ML01G1: 00h S34ML02G1: 01h S34ML04G1: 01h 114 O Interleaved operation attributes 4-7 Reserved (0)

3 Address restrictions for program cache

2 1 = program cache supported 1 1 = no block address restrictions

0 Overlapped / concurrent interleaving support

S34ML01G1: 00h S34ML02G1: 04h S34ML04G1: 04h 115-127 Reserved (0) 00h Electrical Parameters Block Table 3.4 Parameter Page Description (Continued) Byte O/M Description Values

Document Number: 002-00676 Rev. *V Page 31 of 71 S34ML01G1 S34ML02G1 S34ML04G1 Note 24. O” Stands for Optional, “M” for Mandatory.

3.20 One-Time Program mable (OTP) Entry

The device contains a one-time programmable (OTP) area, which is accessed by writing 29h-17h-04h-19h to the command register. The device is then ready to accept Page Read and Page Program commands (refer to Page Read and Page Program on page 15). The OTP area is of a single erase block size (64 pages), and hence only row addresses between 00h and 3Fh are allowed. The host must issue the Reset command (refer to Reset on page 22) to exit the OTP area and access the normal flash array. The Block Erase command is not allowed in the OTP area. Refer to Figure 45 on page 54 for more detail on the OTP Entry command sequence. Note: The OTP feature in the S34ML01G1 does not have non-volatile protection.

128 M I/O pin capacitance 0Ah

6-15 Reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 1Fh, 00h 131-132 O Program cache timing mode support 6-15 Reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0 1Fh, 00h 133-134 M t PROG Maximum page program time (µs) BCh, 02h 135-136 M t BERS Maximum block erase time (µs) S34ML01G1: B8h, 0Bh S34ML02G1: 10h, 27h S34ML04G1: 10h, 27h 137-138 M t R Maximum page read time (µs) 19h, 00h 139-140 M t CCS Minimum Change Column setup time (ns) 64h, 00h 141-163 Reserved (0) 00h Vendor Block 164-165 M Vendor specific Revision number 00h 166-253 Vendor specific 00h 254-255 M Integrity CRC S34ML01G100 (×8): FFh, 63h S34ML02G100 (×8): 3Bh, C5h S34ML04G100 (×8): 45h, 8Eh S34ML01G104 (×16): 8Dh, 15h S34ML02G104 (×16): 49h, B3h S34ML04G104 (×16): 37h, F8h Redundant Parameter Pages 256-511 M Value of bytes 0-255 Repeat Value of bytes 0-255 512-767 M Value of bytes 0-255 Repeat Value of bytes 0-255 768+ O Additional redundant parameter pages FFh Table 3.4 Parameter Page Description (Continued) Byte O/M Description Values

Document Number: 002-00676 Rev. *V Page 32 of 71 S34ML01G1 S34ML02G1 S34ML04G1 4. Signal Descriptions

4.1 Data Protection and Power On / Off Sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever VCC is below about 1.8V. The power-up and power-down sequence is shown in Figure 46 on page 55. The Ready/Busy signal shall be valid within 100 µs after the power supplies have reached the minimum values (as specified on), and shall return to one within 5 ms (max). During this busy time, the device executes the initialization process (cam reading), and dissipates a current ICC0 (30 mA max), in addition, it disregards all commands excluding Read Status Register (70h). At the end of this busy time, the device defaults into “read setup”, thus if the user decides to issue a page read command, the 00h command may be skipped. The WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100 µs is required before the internal circuit gets ready for any command sequences as shown in Figure 46 on page 55. The two-step command sequence for program/erase provides additional software protection.

4.2 Ready/Busy

The Ready/Busy output provides a method of indicating the completion of a page program, erase, copyback, or read completion. The R/B# pin is normally high and goes to low when the device is busy (after a reset, read, program, or erase operation). It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B# outputs to be Or-tied. Because the pull-up resistor value is related to tr (R/B#) and the current drain during busy (ibusy), and output load capacitance is related to tf an appropriate value can be obtained with the reference chart shown in Figure 10. For example, for a particular system with 20 pF of output load, tf from VCC to VOL at 10% to 90% will be 10 ns, whereas for a particular load of 50 pF, Cypress measured it to be 20 ns as shown in Figure 10.

Figure 10. Ready/Busy Pin Electrical Application

4.3 Write Protect Operation

I/O7 value will be related to the WP# value. Refer to Table 13 on page 22 for more information on device status. Figure 47 and Figure 48 on page 55. Figure 11. WP# Low Timing Requirements during Program/Erase Command Sequence Rp(max) is determined by maximum permissible limit of tr.

1. Electrical C haracteristics

5.1 Valid Blocks

5.2 Absolute Maximum Ratings

1. Except for the rating “Operating Temperature Range”, stresses above those listed in the table Absolute Maximum Ratings “Absolute Maximum Ratings” may cause

sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

1. Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions.
2. Maximum Voltage may overshoot to VCC+2.0V during transition and for less than 20 ns during transitions.

5.3 Recommended Operating Conditions

5.4 AC Test Conditions

Table 17. Valid Blocks Table 18. Recommended Operating Conditions Table 19. AC Test Conditions

5.5 AC Characteristics

1. The time to Ready depends on the value of the pull-up resistor tied to R/B# pin.
2. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5 µs.
3. CE# low to high or RE# low to high can be at different times and produce three cases. Depending on which signal comes high first, either tCOH or tRHOH will be met.
4. During data output, tCEA depends partly on tCR (CE# low to RE# low). If tCR exceeds the minimum value specified, then the maximum time for tCEA may also be exceeded

Table 20. AC Characteristics

5.6 DC Characteristics

1. All VCC pins, and VSS pins respectively, are shorted together.
2. Values listed in this table refer to the complete voltage range for VCC and to a single device in case of device stacking.
3. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.
4. Standby current measurement can be performed after the device has completed the initialization process at power up. Refer to Section 4.1 for more details.

5.7 Pin Capacitance

1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].

Table 21. Pin Capacitance (TA = 25°C, f=1.0 MHz)

5.8 Thermal Resistance

1. Test conditions follow standard methods and procedures for measuring thermal impedance in accordance with EIA/JESD51.

5.9 Program / Erase Characteristics

1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed (VCC = 3.3V, 25°C).
2. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the device to meet the program

page) or from an even address page (source page) to an odd address page (target page). Table 22. Thermal Resistance Table 23. Program / Erase Characteristics

6.1 Command Latch Cycle

Command Latch Enable High, Address Latch Enable low, and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/ erase) the Write Protect pin must be high. Figure 12. Command Latch Cycle

6.2 Address Latch Cycle

operation (write/ erase) the Write Protect pin must be high. Figure 13. Address Latch Cycle

6.3 Data Input Cycle Timing

Enable High, and Write Protect High and latched on the rising edge of Write Enable. Figure 14. Input Data Latch Cycle

6.4 Data Output Cycle Timing (C LE=L, WE#=H, ALE=L, WP#=H)

Figure 15. Data Output Cycle Timing

1. Transition is measured at ± 200 mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3. tRHOH starts to be valid when frequency is lower than 33 MHz.

6.5 Data Output Cycle Timing (ED O Type, CLE=L, WE#=H, ALE=L)

Figure 16. Data Output Cycle Timing (EDO)

1. Transition is measured at ± 200 mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3. tRLOH is valid when frequency is higher than 33 MHz.
4. tRHOH starts to be valid when frequency is lower than 33 MHz.

6.6 Page Read Operation

1. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page buffer.

6.7 Page Read Operation (Interrupted by CE#)

Figure 17. Page Read Operation Interrupted by CE#

6.8 Page Read Operation Timing with CE# Don’t Care

Figure 18. Page Read Operation Timing with CE# Don’t Care

6.9 Page Program Operation

1. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.

6.10 Page Program Operation Timing with CE# Don’t Care

Figure 19. Page Program Operation Timing with CE# Don’t Care

6.11 Page Program Operat ion with Random Data Input

Figure 20. Random Data Input

1. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
2. For EDC operation only one Random Data Input is allowed at each EDC Unit.

6.12 Random Data Output In a Page

Figure 21. Random Data Output

6.13 Multiplane Page Program Opera tion — S34ML02G1 and S34ML04G1

Figure 22. Multiplane Page Program

1. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
2. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.

Figure 23. Multiplane Page Program (ONFI 1.0 Protocol)

1. C1A-C2A Column address for page A. C1A is the least significant byte.
2. R1A-R3A Row address for page A. R1A is the least significant byte.
3. D0A-DnA Data to program for page A.
4. C1B-C2B Column address for page B. C1B is the least significant byte.
5. R1B-R3B Row address for page B. R1B is the least significant byte.
6. D0B-DnB Data to program for page B.
7. The block address bits must be the same except for the bit(s) that select the plane.

6.14 Block Erase Operation

Figure 24. Block Erase Operation (Erase One Block)

6.15 Multiplane Block Erase — S34ML02G1 and S34ML04G1

Figure 25. Multiplane Block Erase

1. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.

Figure 26. Multiplane Block Erase (ONFI 1.0 Protocol)

1. R1A-R3A Row address for block on plane 0. R1A is the least significant byte.
2. R1B-R3B Row address for block on plane 1. R1B is the least significant byte.
3. The block address bits must be the same except for the bit(s) that select the plane.

6.16 Copy Back Read with Optional Data Readout

Figure 27. Copy Back Read with Optional Data Readout

6.17 Copy Back Program Operat ion With Random Data Input

Figure 28. Copy Back Program with Random Data Input

6.18 Multiplane Copy Back Progr am — S34ML02G1 and S34ML04G1

Figure 29. Multiplane Copy Back Program

1. Copy Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
3. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.

Figure 30. Multiplane Copy Back Program (ONFI 1.0 Protocol)

1. C1A-C2A Column address for page A. C1A is the least significant byte.
2. R1A-R3A Row address for page A. R1A is the least significant byte.
3. C1B-C2B Column address for page B. C1B is the least significant byte.
4. R1B-R3B Row address for page B. R1B is the least significant byte.
5. The block address bits must be the same except for the bit(s) that select the plane.

6.19 Read Status Register Timing

Figure 31. Status / EDC Read Cycle

6.20 Read Status Enhanced Timing

Figure 32. Read Status Enhanced Timing

6.21 Reset Operation Timing

Figure 33. Reset Operation Timing

6.22 Read Cache

Figure 34. Read Cache Operation Timing Figure 35. “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation

1 Dout 31h Dout

1 Dout31h Dout

1 Dout

Figure 36. “Random” Read Cache Timing, Start (and Continuation) of Cache Operation Figure 37. Read Cache Timing, End Of Cache Operation

6.23 Cache Program

Figure 38. Cache Program

6.24 Multiplane Cache Program — S34ML02G1 and S34ML04G1

Figure 39. Multiplane Cache Program

1. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
2. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.

Figure 40. Multiplane Cache Program (ONFI 1.0 Protocol)

1. The block address bits must be the same except for the bit(s) that select the plane.
2. Read Status register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.

6.25 Read ID Operation Timing

Figure 41. Read ID Operation Timing

6.26 Read ID2 Operation Timing

Figure 42. Read ID2 Operation Timing

1. 4-cycle address is shown for the S34ML01G1. For S34ML02G1 and S34ML04G1, insert an additional address cycle of 00h.
2. If Status Register polling is used to determine completion of the Read ID2 operation, the Read Command (00h) must be issued before ID2 data can be read from the flash.

4 Gb Device

4 Cycle Address 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle

6.27 Read ONFI Signature Timing

Figure 43. ONFI Signature Timing

6.28 Read Parameter Page Timing

Figure 44. Read Parameter Page Timing

1. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page buffer.

6.29 OTP Entry Timing

Figure 45. OTP Entry Timing

6.30 Power On and Data Protection Timing

Figure 46. Power On and Data Protection Timing

6.31 WP# Handling

Figure 47. Program Enabling / Disabling Through WP# Handling Figure 48. Erase Enabling / Disabling Through WP# Handling

7.1 Physical Diagram

Figure 49. TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline

1. DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994).

1. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
2. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
3. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

1. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD

PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.

1. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX. FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm.

1. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10mm AND 0.25mm FROM THE LEAD TIP.

1. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM
2. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

Figure 50. VBM063 — 63-Pin BGA, 11 mm x 9 mm Package

1. DIMENSIONING AND TOLERANCING METHODS PER
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE

BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C. SOLDER BALL IN THE OUTER ROW. THE OUTER ROW “SD” OR “SE” = 0. THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.

1. "+" INDICATES THE THEORETICAL CENTER OF

9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

9.1 System Bad Block Replacement

Figure 54 for the recommended procedure to follow if an error occurs during an operation. Figure 54. Bad Block Replacement

1. An error occurs on the Nth page of Block A during a program operation.
2. Data in Block A is copied to the same location in Block B, which is a valid block.
3. The Nth page of block A, which is in controller buffer memory, is copied into the Nth page of Block B.
4. Bad block table should be updated to prevent from erasing or programming Block A.

Table 24. Block Failure

9.2 Bad Block Management

be written to that block.The 1st block, which is placed on 00h block address is guaranteed to be a valid block. Figure 55. Bad Block Management Flowchart

1. Check for FFh at the 1st byte in the spare area of the 1st, 2nd, and last pages.

Document Number: 002-00676 Rev. *V Page 61 of 71 S34ML01G1 S34ML02G1 S34ML04G1 10. Ordering Information The ordering part number is formed by a valid combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Notes 85. BGA package marking omits the leading “S34” and the Packing Type designator from the ordering part number. 86. A, V, B: 4G ×16 (04 in bus width) available, but for other ×16 versions contact factory. S34ML 04G 1 00 T F I 00 0 Packing Type 0 = Tray 3 = 13” Tape and Reel Model Number 00 = Standard Interface / ONFI (×8) 00 = Standard Interface (×16) 01 = ONFI (×16) Temperature Range I = Industrial (–40°C to + 85°C) A = Industrial with AECQ-100 and GT Grade (-40˚C to +85˚C) V = Industrial Plus (–40°C to + 105°C) B = Industrial Plus with AECQ-100 and GT Grade (-40˚C to +105˚C) Materials Set F = Lead (Pb)-free H = Lead (Pb)-free and Low Halogen Package B = BGA T = TSOP Bus Width 00 = ×8 NAND, single die 04 = ×16 NAND, single die Technology 1 = Cypress NAND Revision 1 (4x nm) Density 01G = 1 Gb 02G = 2 Gb 04G = 4 Gb Device Family S34ML - 3V Cypress SLC NAND Flash Memory for Embedded Valid Combinations Device Family Density Technology Bus Width Package Type Temperature Range Additional Ordering Options Packing Type Package

Description

1 00, 04 TF, BH I A, V, B [86] 00, 01 0, 3 TSOP, BGA [85]02G 04G

Document Number: 002-00676 Rev. *V Page 62 of 71 S34ML01G1 S34ML02G1 S34ML04G1 11. Document History Page Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change ** – XILA 04/16/2012 Initial release *A – XILA 05/04/2012 Global: Removed Spansion Confidential designation Read Status Enhanced: Updated text Command Set: Updated table: Command Set Read ID: Updated table: Read ID for Supported Configurations Legacy Read ID: Removed section heading: Legacy Read ID Valid Blocks: Updated table: Valid Blocks *B – XILA 05/23/2012 Global: Changed Cache Read to Read Cache General Description: Updated text Block Diagram: Combined three block diagrams into one Addressing: Updated Address Cycle Map tables Mode Selection: Updated table: Busy Time in Read; updated note Command Set: Updated table Added ‘Supported in S34ML01G1’ column Copy Back Program: Updated text Multiplane Copy Back Program: Updated text Special Read for Copy Back: Updated text Read EDC Status Register: Updated text Read ID: Read ID Byte 4 Description — S34ML01G1 table: changed Number of I/O to Spare Area Size (byte / 512 byte) Absolute Maximum Ratings: Updated Input or Output Voltage and Supply Voltage rows Program / Erase Characteristics: Updated table *C – XILA 05/24/2012 Performance: Updated Performance section Read ID: Updated Read ID for Supported Configurations table Modified tables: Read ID Byte 3 Description, Read ID Byte 4 Description – S34ML01G1, Read ID Byte 4 Description – S34ML02G1 and S34ML04G1, Read ID Byte 5 Description – S34ML02G1 and S34ML04G1 AC Test Conditions: Updated table

Document Number: 002-00676 Rev. *V Page 63 of 71 S34ML01G1 S34ML02G1 S34ML04G1 *D – XILA 05/31/2012 Global: Data Sheet designation updated from Advance Information to Preliminary Distinctive Characteristics/Performance: Updated Distinctive Characteristics and Performance section Pin Description: Updated Pin Description table Addressing: Updated Address Cycle Map — 1 Gb Device table Updated Address Cycle Map — 2 Gb Device table Updated Address Cycle Map — 4 Gb Device table Command Set: Updated Command Set table *E – XILA 07/13/2012 Performance: Corrected Page Read/Program - Sequential access: from 25ns (Max) to 25 ns (Min) Connection Diagram: Corrected figure: 48-Pin TSOP1 Contact x8 Device Mode Selection: Mode selection table: corrected Busy Time in Read, WE# from High to X; corrected Notes Command Set: Command Set table: added ONFI, Extended Read Status, and Read ID2 commands Note that all ONFI information is in the Advanced Information designation Copy Back Program: Updated section Multiplane Copy Back Program — S34ML02G1 and S34ML04G1: Updated section Read ID2: Added section Read ONFI Signature: Added Section Note that all ONFI information is in the Advanced Information designation Read Parameter Page: Added section Note that all ONFI information is in the Advanced Information designation One-Time Programmable (OTP) Entry: Added section Note that all ONFI information is in the Advanced Information designation Program/Erase Characteristics: Added note to table Timing Diagrams: Rearranged section Added timing diagrams: Multiplane Block Erase (ONFI 1.0 Protocol), Multiplane Cache Program (ONFI 1.0 Protocol), Read ID2 Operation Timing, ONFI Signature Timing, Read Parameter Page Timing, Read ID2 Operation Timing, OTP Entry Timing Updated timing diagrams: Page Read Operation (Read One Page), Page Read Operation Intercepted by CE#, Page Read Operation Timing with CE# Don’t Care, Page Program Operation, Page Program Operation Timing with CE# Don’t Care, Random Data Input, Random Data Output, Multiplane Page Program, Block Erase Operation (Erase One Block), Reset Operation Timing, Read Cache Operation Timing, Cache Program, Multiplane Cache Program, Read ID Operation Timing Note that all ONFI information is in the Advanced Information designation 11. Document History Page (Continued) Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00676 Rev. *V Page 64 of 71 S34ML01G1 S34ML02G1 S34ML04G1 *F – XILA 07/23/2012 Command Set: Command Set table: changed Read ONFI Signature to ‘Yes’ for Supported on S34ML01G1 Read Parameter Page: Parameter Page Description table: changed Byte 254-255 Values Valid Blocks: Valid Blocks table: removed Note 1 and Note 3 DC Characteristics: DC Characteristics and Operating Conditions table: corrected Output low voltage Test Conditions corrected Output low current (R/B#) Typ and Max values *G – XILA 08/02/2012 Global: Note that all ONFI information is now in the Preliminary designation Read Parameter Page: Parameter Page Description table: updated values for bytes 6-7, 108-109, 254- 255 Physical Interface: Added TSOP (2 CE 8 Gb) diagram Added BGA diagram Ordering Information: Updated data Appendix A: Added Errata *H – XILA 08/29/2012 Global: Removed 8 Gb data Added x16 I/O bus width data *I – XILA 09/06/2012 Connection Diagram: 48-Pin TSOP1 Contact x8, x16 Devices figure: corrected pinouts 63-VFBGA Contact, x16 Device (Balls Down, Top View) figure: corrected pinouts, removed note Command Set: Reorganized section AC Characteristics: Corrected TALS Min and TDS Min 11. Document History Page (Continued) Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00676 Rev. *V Page 65 of 71 S34ML01G1 S34ML02G1 S34ML04G1 *J – XILA 10/01/2012 Addressing Address Cycle Map -1 Gb Device: corrected data Address Cycle Map -2 Gb Device: corrected data Address Cycle Map -4 Gb Device: corrected data Multiplane Program -S34ML02G1 and S34ML04G: Added text Block Erase Added text Multiplane Block Erase -S34ML02G1 and S34ML04G1: Added text Copy Back Program: Added text Multiplane Copy Back Program — S34ML02G1 and S34ML04G: Added text Multiplane Cache Program — S34ML02G1 and S34ML04G1: Added text Read Parameter Page: Parameter Page Description table: corrected Electrical Parameters Block values for bytes 129-130 and bytes 131- 132 corrected Vendor Block values for bytes 254-255 Multiplane Page Program Operation — S34ML02G1 and S34ML04G1: Added note to Multiplane Page Program figure Added note to Multiplane Page Program (ONFI 1.0 Protocol) figure Multiplane Block Erase — S34ML02G1 and S34ML04G1: Added note to Multiplane Block Erase figure Updated note to Multiplane Block Erase (ONFI 1.0 Protocol) figure Multiplane Copy Back Program — S34ML02G1 and S34ML04G1: Added note to Multiplane Copy Back Program figure Multiplane Copy Back Program (ONFI 1.0 Protocol) figure: corrected IOx values Updated note Multiplane Cache Program — S34ML02G1 and S34ML04G1: Added note to Multiplane Cache Program figure Multiplane Cache Program (ONFI 1.0 Protocol) figure: removed address values from RY/BY# changed IOx value from F1h to 70h updated note AC Characteristics: AC Characteristics table: added CE# access time *K – XILA 11/02/2012 Global: Data Sheet designation updated from Preliminary to Full Production Absolute Maximum Ratings: Added note Ordering Information: Valid Combinations table: added to Additional Ordering Options 11. Document History Page (Continued) Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00676 Rev. *V Page 66 of 71 S34ML01G1 S34ML02G1 S34ML04G1 *L – XILA 12/19/2012 Command Set: Added Page Reprogram command Changed ReadID2 to be “Supported on S34ML01G1” Page Reprogram: Moved section Added paragraph Copy Back Program: Added paragraph Reset: Updated paragraph ReadID2: Updated paragraph Read Parameter Page: Parameter Page Description table: fixed Values of Bytes 6-7 and 254-255 fixed Description of Bytes 129-130 and 131-132 DC Characteristics: DC Characteristics and Operating Conditions table: Power-On Reset Current (S34ML01G1): removed row Operating Current: removed ICC1: tRC = tRC (min); ICC2: removed Cache (S34ML01G1) Input Leakage Current: removed VIN = 0 to VCC (max) Output Leakage Current: removed VOUT = 0 to VCC (max) Output High Voltage: removed IOH = -100 µA, IOH = 100 µA, and IOH = 400 µA rows Output Low Voltage: removed IOL = -100 µA row Output Low Current (R/B#): removed VOL = 0.1V row AC Characteristics: AC Characteristics table: added note Page Read Operation: Page Read Operation (Read One Page) figure: added note Read ID2 Operation Timing: Read ID2 Operation Timing figure: replaced tWHR with tR and added R/B# timing signal added note Bad Block Management: Added text Bad Block Management Flowchart: updated note 11. Document History Page (Continued) Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00676 Rev. *V Page 67 of 71 S34ML01G1 S34ML02G1 S34ML04G1 *M – XILA 02/28/2013 Command Set: Command Set table: removed ‘Nth Page’ entries Page Program: Added paragraph Multiplane Program — S34ML02G1 and S34ML04G1: Added paragraph Page Reprogram — S34ML02G1 and S34ML04G1: Added paragraph Block Erase: Added paragraph Multiplane Block Erase — S34ML02G1 and S34ML04G1: Added paragraph Copy Back Program: Added paragraph Multiplane Copy Back Program — S34ML02G1 and S34ML04G1: Added paragraph Cache Program — S34ML02G1 and S34ML04G: Added paragraph Multiplane Cache Program — S34ML02G1 and S34ML04G1 Added paragraph Read Parameter Page: Added paragraph Electrical Characteristics: Valid Blocks table: updated table AC Characteristics: AC Characteristics table: corrected Min value for tCLS and Max value for tCEA Read Status Cycle Timing: status / EDC Read Cycle figure: removed Note *N – XILA 03/07/2013 Ready/Busy: Updated section Corrected Ready/Busy Pin Electrical Application figure 11. Document History Page (Continued) Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00676 Rev. *V Page 68 of 71 S34ML01G1 S34ML02G1 S34ML04G1 *O – XILA 08/09/2013 Distinctive Characteristics: Security -removed Serial number (unique ID) Operating Temperature: removed Commercial and Extended temperatures Performance: Updated Reliability General Description: Updated section Removed bullet: Serial number (unique identifier) Addressing: Appended Note in all Address Cycle Map tables Added text to Bus Cycle column in all Address Cycle Map tables Mode Selection: Updated Mode Selection table Command Set: Command Set table: updated Acceptable Command during Busy column Changed status of Cache Program (End) and Cache Program (Start) / (Continue) to ‘Supported on S34ML01G1’ Page Read: Updated section Page Program: Changed sentence “In addition, pages must be sequentially programmed within a block.” to “Pages may be programmed in any order within a block.” Multiplane Program — S34ML02G1 and S34ML04G1: Changed sentence “In addition, pages must be programmed sequentially within a block.” to “Pages may be programmed in any order within a block.” Page Reprogram — S34ML02G1 and S34ML04G1: Corrected Page Reprogram figure Corrected Page Reprogram with Data Manipulation figure Copy Back Program: Updated section Read Status Enhanced — S34ML02G1 and S34ML04G1: Updated section Read Status Register Field Definition: Updated Status Register Coding table Cache Program: Removed S34ML02G1 and S34ML04G1 from heading Read ID: Read ID Bytes: updated Description Read Parameter Page: Parameter Page Description table: corrected Values for Bytes 8-9 and 254-255 Absolute Maximum Ratings: Updated Absolute Maximum Ratings table Multiplane Page Program Operation — S34ML02G1 and S34ML04G1: Updated Multiplane Page Program figure Updated Multiplane Page Program (ONFI 1.0 Protocol) Copy Back Read with Optional Data Readout: Corrected Copy Back Read with Optional Data Readout figure Copy Back Program Operation With Random Data Input: Updated Copy Back Program Operation With Random Data Input figure Read Status Register Timing: Removed Read Status Enhanced Cycle figure Read Status Enhanced Timing: Removed Read Status Timing figure 11. Document History Page (Continued) Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00676 Rev. *V Page 69 of 71 S34ML01G1 S34ML02G1 S34ML04G1 *O (Cont’d) – XILA 08/09/2013 Read Cache: Updated Read Cache Operation Timing figure Removed Cache Timing heading Cache Program: Updated Cache Program figure Multiplane Cache Program — S34ML02G1 and S34ML04G1: Updated Multiplane Cache Program figure Updated Multiplane Cache Program (ONFI 1.0 Protocol) figure Read Parameter Page Timing: Added Note to Read Parameter Page Timing figure One-Time Programmable (OTP) Entry: Added Note stating that the OTP feature in the S34ML01G1 does not have non- volatile protection Electrical Characteristics: Absolute Maximum Ratings table: removed Ambient Operating Temperature (Commercial Temperature Range) and Ambient Operating Temperature (Extended Temperature Range) Physical Interface: Updated figures: TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline VBM063 — 63-Pin BGA, 11 mm x 9 mm Package System Interface: Updated Read Operation with CE# Don't Care figure Ordering Information: Updated Materials Set: H = Low Halogen to H = Lead (Pb)-free and Low Halogen Added Note to Valid Combinations table *P – XILA 02/10/2014 Distinctive Characteristics: Operating Temperature: Added Automotive Read ID: Updated section Ordering Information: Temperature Range: Added A, V, B Valid Combinations: Temperature Range: Added A, V, B *Q 4963050 XILA 11/02/2015 Updated to Cypress template. *R 5160512 XILA 04/25/2016 Updated Command Set: Updated Read Parameter Page: Updated description. Updated Electrical Characteristics: Added Recommended Operating Conditions. Updated DC Characteristics: Replaced “VCC supply Voltage (erase and program lockout)” with “Erase and Program Lockout voltage” in “Parameter” column corresponding to VLKO. Updated Ordering Information: Updated details under Temperature Range. Updated to new template. *S 5409174 XILA 08/30/2016 Updated Performance: Updated details under “Reliability”. *T 5738855 GNKK 05/16/2017 Updated the Cypress logo and copyright information. 11. Document History Page (Continued) Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00676 Rev. *V Page 70 of 71 S34ML01G1 S34ML02G1 S34ML04G1 *U 5995650 MNAD 12/21/2017 Updated Electrical Characteristics: Added Thermal Resistance. Updated Timing Diagrams: Updated Multiplane Cache Program — S34ML02G1 and S34ML04G1: Updated Figure 39 on page 51. Updated to new template. *V 6104589 MNAD 03/20/2018 No technical updates. Completing Sunset Review. 11. Document History Page (Continued) Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded Document Number: 002-00676 Rev. ECN No. Orig. of Change Submission Date Description of Change

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