S323DB11UI

AM29DS323D_06 AMD | Alldatasheet

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This product has been retired and is not recommended for designs. Please contact a Spansion repre- sentative for alternates. The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29DS323D Data Sheet RETIRED PRODUCT Publication Number 23480 Revision A Amendment 5 Issue Date October 10, 2006

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 23480 Rev: A Amendment: 5 Issue Date: October 10, 2006 Am29DS323D

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations ■ Multiple bank architectures — Two devices available with different bank sizes (refer to Table 3) ■ Secured Silicon (Secured Silicon) Sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed — 64 Kbyte sector size ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero ■ Package options — 48-ball FBGA — 48-pin TSOP ■ Top or bottom boot block ■ Manufactured on 0.23 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast 110 ns — Program time: 13 µs/word typical; with Accelerate function, 7 µs/word typical ■ Ultra low power consumption (typical values) — 1 mA active read current at 1 MHz — 5 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 Year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming and erasing, enabling EEPROM emulation — Eases sector erase limitations ■ Supports Common Flash Memory Interface (CFI) ■ Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to reading array data ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function provides accelerated program times ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system This product has been retired and is not recommended for designs. Please contact a Spansion representative for alternates.

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The Am29DS323D family consists of 32 megabit, 1.8 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the stan- dard 1.8 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 110 and 120 ns. The devices are offered in an 48-ball FBGA package. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus con- tention issues. The device requires only a single 1.8 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. Am29DS323D Features The Secured Silicon (SecSi) Sector is an additional

64 Kbyte sector capable of being permanently locked

by AMD or customers. The Secured Silicon Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked , and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The Se- cured Silicon Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the Se- cured Silicon Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes.

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Speed Option Standard Voltage Range: V CC = 1.8–2.2 V 110 120 Max Access Time (ns) 110 120 CE# Access (ns) 110 120 OE# Access (ns) 50 50 VCC VSS Upper Bank AddressA0–A20 RESET# WE# CE# BYTE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ0–DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address OE# BYTE# Status Control A0–A20 A0–A20 A0–A20A0–A20 DQ0–DQ15 DQ0–DQ15

October 10, 2006 23480A5 Am29DS323D 5 DATA SHEET CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP

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Special Handling Instructions for FBGA Package Special handling is requir ed for Flash Memory prod- ucts in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. C2 D2 E2 F2 G2 H2 C1 D1 E1 F1 G1 H1 C3 D3 E3 F3 G3 H3 C4 D4 E4 F4 G4 H4 C5 D5 E5 F5 G5 H5 C6 D6 E6 F6 G6 H6 A2 B2 A1 B1 A3 B3 A4 B4 A5 B5 A6 B6 DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 48-Ball FBGA Top View, Balls Facing Down

October 10, 2006 23480A5 Am29DS323D 7 DATA SHEET PIN DESCRIPTION A0–A20 = 21 Addresses DQ0–DQ14 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write Protect/ Acceleration Pin RESET# = Hardware Reset Pin, Active Low BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy Output V CC = 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V SS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A20 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con- firm availability of specific valid combinations and to check on newly released combinations. Am29DS323D T 110 WM I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) WM = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 12 mm package (FBD048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29DS323D

32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages Order Number Am29DS323DT110, Am29DS323DB110 EI Am29DS323DT120, Am29DS323DB120 Valid Combinations for FBGA Packages Order Number Package Marking Am29DS323DT110, Am29DS323DB110 WMI S323DT11U, S323DB11U I Am29DS323DT120, Am29DS323DB120 S323DT12U, S323DB12U

each of these operations in further detail. Table 1. Am29DS323D Device Bus Operations

1. Addresses are A20:A0 in word mode (BYTE# = V

IH), A20:A-1 in byte mode (BYTE# = VIL).

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. used as an input for the LSB (A-1) address function. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V H X High-Z High-Z High-Z

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addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Memory Array Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. I CC1 in the DC Characteris- tics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 3–6 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section cont ains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow fast er manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated program- ming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and I CC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not read ing or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC +

data is latched and always available to the system. automatic sleep mode current specification. rameters and to Figure 14 for the timing diagram. Table 2. Am29DS323D Device Bank Divisions

64 Kbyte/32 Kword

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Table 3. Top Boot Sector Addresses (Am29DS32xDT)

Table 4. Secured Silicon Sector Addresses for Top Boot Devices Table 3. Top Boot Sector Addresses (Am29DS32xDT) (Continued)

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Table 5. Bottom Boot Sector Addresses (Am29DS32xDB)

are A20 and A19 for Am29DS323DB. Table 6. Secured Silicon Sector Addresses for Bottom Boot Devices Table 5. Bottom Boot Sector Addresses (Am29DS32xDB) (Continued)

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accessed in-system through the command register. ID (9.0 V to 11.0 V) on address pin A9. Table 7. In addition, when verifying sector protection, shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. mand Sequence section for more information. Table 7. Am29DS323D Autoselect Codes (High Voltage Method) Sector Address, X = Don’t care.

Table 8. Top Boot Sector/Sector Block Addresses Table 9. Bottom Boot Sector/Sector Block

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equipment requires V ID on address pin A9 and OE#. written for earlier 1.8 volt-only AMD flash devices. Contact an AMD representative for further details. The device is shipped with all sectors unprotected. AMD representative for details. a top-boot-configured device. sectors were last set to be protected or unprotected. tor/Sector Block Protection and Unprotection”. Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected (If WP#/ACC = V IL,

outermost boot sectors will remain protected).

1. All previously protected sectors are protected once

Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

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Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identifica- tion through an Electronic Serial Number (ESN). The Secured Silicon Sector is 64 Kbytes in length, and uses a Secured Silicon Sector Indicator Bit to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which pre- vents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the Secured Silicon Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable versio n is shipped with the unprotected, allowing customers to utilize the that sec- tor in any manner they choose. The customer-lockable version has the Secured Silicon Sector Indicator Bit permanently set to a “0.” Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable de- vices from being used to replace devices that are factory locked. The system accesses the Secured Silicon Sector through a command sequence (see “Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence”). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation contin ues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device re- verts to sending commands to the boot sectors instead of the Secured Silicon sector. Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the fac- tory. The Secured Silicon Sector cannot be modified in any way. The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot de- vice the starting address of the ESN will be at ad- dresses 1F83C0h–1F83C7h in word mode (or addresses 3F0780h–3F078Fh in byte mode). Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the permanently locked. Contact an AMD representative for details on using AMD’s Express- Flash service. Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory If the security feature is not required, the Secured S ili- con Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. The Secured Silicon Sector can be read, programmed, and erased as often as re- quired. The Secured Silic on Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Fig- ure 2, except that RESET# may be at either V IH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. ■ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then use the alter- nate method of sector protection described in the “Sector/Sector Block Protection and Unprotection”. Once the Secured Silicon Sector is locked and veri- fied, the system must write the Exit Secured Silicon Sector Region command sequence to return to read- ing and writing the remainder of the array. The Secured Silicon Sector protection must be used with caution since, once pr otected, there is no proce- dure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise.

or WE# do not initiate a write cycle. cally reset to reading array data on power-up. interfaces for long-term compatibility. system must write the reset command. device to the autoselect mode. representative for copies of these documents. Table 10. CFI Query Identification String

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Table 11. System Interface String Table 12. Device Geometry Definition

Table 13. Primary Vendor-Specific Extended Query The number of sectors in Bank 2 is device dependent.

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Writing specific address and data commands or se- quences into the command register initiates device operations. Table 14 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- quence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Memory Array Read-Only Operations table pro- vides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the bank to which the system was writin g to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an aut oselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 14 shows the address and data requirements. This method is an alternative to that shown in Table 7, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. Th is is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read at any address within the same bank any number of times without ini- tiating another autoselect command sequence. The fol- lowing table describes the hex address requirements for the various autoselect functions, and the resulting data. BA represents the bank address, and SA repre- sents the sector address. * For byte mode, ignore data output bits D8–DQ15. Description Word Address Byte Address Read Data* Maufacturer ID (BA) + 00 (BA) + 00 01 Device ID (BA) + 01 (BA) + 02 22B7 (top boot) 22B8 (bottom boot) Sector Block Protect Verify (SA) + 02 (SA) + 04 00 (unlocked), 01 (locked) Secured Silicon Sector Factory Protect (BA) + 03 (BA) + 06 85 (factory locked) 05 (not factory locked)

October 10, 2006 23480A5 Am29DS323D 25 DATA SHEET The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The system can access the Secured Silicon Sector re- gion by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the sys- tem issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal op- eration. Table 14 shows the address and data requirements for both command sequences. See also “Secured Silicon Sector Flash Memory Region” for fur- ther information. Note that a hardware reset (RESET#=V IL) will reset the device to reading array data. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program command sequence is initia ted by writing two unlock write cycles, followed by the program set-up com- mand. The program address and data are written next, which in turn initiate the Embedded Program algo- rithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 14 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 14 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.

26 Am29DS323D 23480A5 October 10, 2006

Figure 3. Program Operation section for information on these status bits. array data, to ensure data integrity. ters, and Figure 19 section for timing diagrams. ings during these operations. quence and any additional addresses and commands. Note: See Table 14 for program command sequence.

28 Am29DS323D 23480A5 October 10, 2006

Table 14. Am29DS323D Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A20–A12 uniquely select any sector. in bypass mode, or is being erased.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A20–A11 are don’t cares.
3. No unlock or command cycles required when bank is in read
4. The Reset command is required to return to reading array data

high (while the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The data is 85h for factory locked and 05h for not factory locked.
2. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

30 Am29DS323D 23480A5 October 10, 2006

Table 15 shows the outputs for RY/BY#. complete, DQ6 stops toggling. Table 15 shows the outputs for Toggle Bit I on DQ6. subsection on DQ2: Toggle Bit II. Figure 6. Toggle Bit Algorithm

32 Am29DS323D 23480A5 October 10, 2006

Table 15. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status in formation. Refer to the appropriate subsection for further
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

34 Am29DS323D 23480A5 October 10, 2006

Notes: 1. The I CC current listed is typically less than 1 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Te st Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 11 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 5 16

1 MHz 1 4

CE# = VIL, OE# = VIH, Word Mode ICC2 VCC Active Write Current (Notes 2, 3) CE# = V IL, OE# = VIH, WE# = VIL 10 15 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 15 25 mA Word 15 25 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 15 25 mA Word 15 25 ICC8 VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE# = VIL, OE# = VIH 10 15 mA IACC ACC Accelerated Program Current, Word or Byte CE# = VIL, OE# = VIH ACC pin 5 10 mA VCC pin 10 15 mA VIL Input Low Voltage –0.5 V CC x 0.2 V VIH Input High Voltage 0.8 x V CC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 1.8–2.2 V 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 1.8–2.2 V 9 11 V VOL Output Low Voltage I OL = 2.0 mA, VCC = VCC min 0.25 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.7 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC–0.1 VLKO Low VCC Lock-Out Voltage (Note 5) 1.2 1.6 V

36 Am29DS323D 23480A5 October 10, 2006

Table 16. Test Specifications Figure 11. Test Setup Figure 12. Input Waveforms and Measurement Levels

1. See Figure 11 and Table 16 for test specifications.
2. For data polling and toggle bit specifications , see “Data Polling and Toggle Bit” on page 44.

0 VRY/BY#

Figure 13. Read Operation Timings

38 Am29DS323D 23480A5 October 10, 2006

Figure 14. Reset Timings

40 Am29DS323D 23480A5 October 10, 2006

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter 110 120JEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 13 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 2 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

42 Am29DS323D 23480A5 October 10, 2006

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. These waveforms are for the word mode.

Figure 19. Chip/Sector Er ase Operation Timings

Figure 20. Back-to-back Read/Write Cycle Timings

44 Am29DS323D 23480A5 October 10, 2006

See Figure 11 and Table 16 for test specifications. Figure 21. Data# Polling Timings (During Embedded Algorithms)

46 Am29DS323D 23480A5 October 10, 2006

Figure 24. Temporary Sector/Sector Block

Figure 25. Sector/Sector Block Protect/Unprotect Timing Diagram

48 Am29DS323D 23480A5 October 10, 2006

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter 110 120JEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 50 ns tDVEH tDS Data Setup Time Min 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 13 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 2 sec

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Wr ite (Erase/Program) Operation Timings

50 Am29DS323D 23480A5 October 10, 2006

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.2 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 2.0 V, one pin at a time. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 2 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 130 sec Byte Program Time 9 270 µs Excludes system level overhead (Note 5) Word Program Time 13 390 µs Accelerated Byte/Word Program Time 7 210 µs Chip Program Time (Note 3) Byte Mode 54 160 sec Word Mode 27 81 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 11 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

October 10, 2006 23480A5 Am29DS323D 51 DATA SHEET PHYSICAL DIMENSIONS FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA) 6 x 12 mm package Dwg rev AF; 1/2000 xFBD 048 6.00 mm x 12.00 mm PACKAGE 1.20 0.20 0.84 0.94

12.00 BSC

6.00 BSC

5.60 BSC

4.00 BSC

0.25 0.30 0.35

0.80 BSC

0.40 BSC

52 Am29DS323D 23480A5 October 10, 2006

TS 048—48-Pin Standard TSOP Dwg rev AA; 10/99

October 10, 2006 23480A5 Am29DS323D 53 DATA SHEET REVISION SUMMARY Revision A (December 1, 1999) Released page 1 only. Publication Number 23480, Revision A (January 25, 2000) Released as full data sheet. The publication number has been changed from 22394 to 23480. Revision A+1 (June 16, 2000) Global The 100 ns speed option has been replaced by a 110 ns option. The data sheet status has changed from “Advance In- formation” to “Preliminary.” In the ordering part number, changed FBGA package code to WM. For 6 x 12 FBGA packages only, the physical marking for regulated voltage range devices is now “Q” and the physical marking for full voltage range devices is now “U.” Optional processing: Deleted the burn-in option. DC Characteristics table CMOS Compatible: Changed maximum specification on V LKO to 1.6 V. AC Characteristics—Read-Only Operations Changed tDF to 16 ns from 30 ns. AC Characteristics—Data Polling and Toggle Bit Added table. Timing specifications for data polling and toggle bit operations differ from those for memory array read operations. AC Characteristics—Erase and Program Operations table; Alternate CE# Controlled Erase and Program Operations table Changed typical and maximum byte and word pro- gramming times to match changes in erase and program performance table. Erase and Program Performance Changed the following specifications: typical and max- imum byte program time, typical and maximum word program time, typical and maximum chip program time for both word and byte modes. Revision A+2 (November 1, 2000) Global Deleted “contact AMD for availability” notes for TSOP package. Added TSOP valid combinations to the Or- dering Information section. In Tables 7 and 14, changed data for SecSi Sector Factory Protect to 85h (factory locked) and 05h (not factory locked). Revision A+3 (November 22, 2000) Removed Preliminary status from document. Table 4, Secured Silicon Sector Addresses for Top Boot Devices. Table 6, Secured Silicon Sector Ad- dresses for Bottom Boot Devices: Added ESN addresses to tables. Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory: Corrected ESN address range. Autoselect Command Sequence: Added table to clar- ify explanation of autoselect codes. Revision A+4 (January 25, 2005) Changed to final datasheet status. Revision A5 (October 10, 2006) Global Added retired product notice on cover page and first page of data sheet. Added cover page and colophon. Connection Diagrams Corrected column labeling on ball grid drawing.

54 Am29DS323D 23480A5 October 10, 2006

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.