S29VS064R

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Technical content

Datasheet sections

• 1.1 Simultaneous Read/ Write Operations
• 8.1 Valid Combinations
• 9.1 ADM Interface Mode (S29VS064R)
• 9.2 AADM Interface Mode (S29XS064R)
• 9.3 Default Access Mode
• 10.1 Versatile IO™ (VIO) Control
• 10.2 Asynchronous Read
• 10.3 Synchronous (Burst) Read Mode
• 10.4 Programmable Wait State
• 10.5 Configuration Register
• 10.6 Handshaking Feature
• 10.7 Simultaneous Read/Write Operations
• 10.8 Writing Commands/Command Sequences
• 10.9 Accelerated Program and Erase Operations
• 12.1 Reading Array Data
• 12.2 Set Configuration Register
• 12.3 Read Configuration Register
• 13.1 Reset Command
• 13.2 Autoselect Command Sequence
• 13.3 Enter/Exit Secured Silicon Sector
• 13.4 Program Command Sequence
• 13.5 Accelerated Program
• 13.6 Write Buffer Programming
• 13.7 Chip Erase Command Sequence
• 13.8 Sector Erase Command Sequence
• 13.9 Erase Suspend/Erase Resume Commands
• 14.1 DQ7: Data# Polling
• 14.2 RDY: Ready
• 14.3 DQ6: Toggle Bit I
• 14.4 DQ2: Toggle Bit II
• 14.5 Reading Toggle Bits DQ6/DQ2
• 14.6 DQ5: Exceeded Timing Limits
• 14.7 DQ3: Sector Erase Start Timeout
• 14.8 DQ1: Write to Buffer Abort
• 19.1 Switching Waveforms
• 20.1 VCC Power-up
• 20.2 Synchronous/Burst Read
• 20.3 Asynchronous Read
• 20.4 Hardware Reset (RESET#)
• 20.5 Erase/Program Operations

Cypress Semiconductor Corporation• 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-00949 Rev. *J Revised January 10, 2018 S29VS064R S29XS064R 64 Mbit (4M x 16-bit), 1.8 V, Multiplexed, Burst MirrorBit® Flash Distinctive Characteristics  Single 1.8 V read, program and erase (1.7 to 1.95 V)  VersatileIO™ Feature – Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VCCQ pin – 1.8 V compatible I/O signals  Address and Data Interface Options – Address and Data Multiplexed for reduced I/O count (ADM) S29VS-R – Address-High, Address-Low, Data Multiplexed for minimum I/O count (AADM) S29XS-R  Simultaneous Read/Write operation – Data can be continuously read from one bank while executing erase/program functions in other bank – Zero latency between read and write operations  Burst length – Continuous linear burst – 8/16 word linear burst with wrap around  Secured Silicon Sector region – 256 words accessible through a command sequence, 128 words for the Factory Secured Silicon Sector and 128 words for the Customer Secured Silicon Sector.  Sector Architecture – Four 8 kword sectors in upper-most address range – One hundred twenty-seven 32 kword sectors – Four banks Security Features  Dynamic Protection Bit (DYB) – A command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector – Sectors can be locked and unlocked in-system at VCC level  Hardware Sector Protection – All sectors locked when VPP = VIL  Handshaking feature – Provides host system with minimum possible latency by monitoring RDY  Supports Common Flash Memory Interface (CFI)  Manufactured on 65 nm MirrorBit® process technology  Cycling endurance: 100,000 cycles per sector typical  Data retention: 10 years typical  Data# Polling and toggle bits – Provides a software method of detecting program and erase operation completion  Erase Suspend/Resume – Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation  Program Suspend/Resume – Suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation  Packages – 44-ball Very Thin FBGA

Document Number: 002-00949 Rev. *J Page 2 of 68 S29VS064R S29XS064R Performance Characteristics Read Access Times Speed Option (MHz) 108 Max. Synch. Latency, ns (tIACC) 80 Max. Synch. Burst Access, ns (tBACC) 7.6 Max. Asynch. Access Time, ns (tACC)8 0 Max OE# Access Time, ns (tOE)1 5 Current Consumption (typical values) Continuous Burst Read @ 108 MHz 32 mA Simultaneous Operation @ 108 MHz 71 mA Program/Erase 30 mA Standby Mode 20 µA Typical Program and Erase Times Single Word Programming 170 µs Effective Write Buffer Programming (V CC) Per Word 14.1 µs Effective Write Buffer Programming (VPP) Per Word 9 µs Sector Erase (8 kword Sector) 350 ms Sector Erase (32 kword Sector) 800 ms

Document Number: 002-00949 Rev. *J Page 4 of 68 S29VS064R S29XS064R 1. General Description The S29V/XS064R are 64 Mb, 1.8 Volt-only, Simultaneous Read/Write, Burst Mode flash memory devices, organized as 4,194,304 VPP, may be used for faster program performance if desired. These devices can also be programmed in standard EPROM programmers. The devices operate within the temperature range of 25°C to +85°C, and are offered in Very Thin FBGA packages. The devices are also available in the temperature range of 40°C to +85°C. Please refer to the Specification Supplement wit h Publication Number S29VS064R_XS064R_SP for specification differences for devices offered in the 45°C to +85°C temperature range.

1.1 Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. The device allows a host system to pr ogram or erase in one bank, th en immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VCCQ pin. The devices use Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the devices additionally require Ready (RDY) and Clock (CLK). This implementation allows easy interface with minimal glue logic to microprocessors/microcontrollers for high performance read operations. The devices offer complete compatibility with the JEDEC 42.4 single-power-supply flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device are similar to reading from other flash or EPROM devices. The host system can detect whethe r a program or erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has b een completed, the device automatically returns to reading arra y data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The devices are fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during p ower transitions. The devices also offers another type of data protection at the sector level. When VPP is at VIL, all sectors are locked. The devices offer two power-sav ing features. When addresses hav e been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Device programming occurs by executing the program command sequ ence. This initiates the Embedded Program algorithm - an internal algorithm that automat ically times the program pulse w idths and verifies proper cell margin. Additionally, Write Buffer Programming is available on this family of devices. This feature provides superior programming performance by grouping locations being programmed. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is no t already fully programmed) befor e executing the erase operatio n. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The Program Suspend/Program Resume feature enables the user to put program on hold to read data from any sector that is not selected for programming. If a read is needed from the Dynamic Protection area, or the CFI area, after an program suspend, the n the user must use the proper c ommand sequence to enter and exit this region. The program suspend/ resume functionality is also available when programming in erase suspend (1 level depth only). The Erase Suspend/Erase Resume feature enables the user to put erase on hold to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Dynamic Protection area, or the CFI area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal s tate machine to reading array data. The RESET# pin may be tied to the syst em reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the flash memory device.

Figure 1. S29VS/XS064R Block Diagram Amax indicates the highest order address bit. Amax equals A21 for S29VS/XS064R.

Figure 2. Block Diagram of Simultaneous Operation Circuit

1. A15–A0 are multiplexed with DQ15–DQ0.
2. Amax indicates the highest order address bit.

Document Number: 002-00949 Rev. *J Page 7 of 68 S29VS064R S29XS064R 3. Connection Diagram Special Package Handling Instructions Special handling is required for flash memory products in FBGA packages.The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. 329 1 0 547 681 1312 1411 NC NC B D E F G H A C RDY VPP A19 VSSA21 VCC CLK WE# NC A17 VCCQ NC A18 A20A16 NC AVD# RESET# VSSQ CE# VSS A/DQ2 A/DQ9A/DQ6A/DQ7 A/DQ12 A/DQ13 A/DQ3 OE# A/DQ8 A/DQ15 A/DQ10 VCCQVSSQA/DQ14 A/DQ4 A/DQ5 A/DQ11 A/DQ0 A/DQ1 NC NC S29VS/XS064R, 44-Ball Very Thin FBGA Top View, Balls Facing Down

Figure 3. VDL044—44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 7.5 x5.0 mm Package

1. DIMENSIONING AND TOLERANCING METHODS PER
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1,
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

n IS THE NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

1. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

Document Number: 002-00949 Rev. *J Page 9 of 68 S29VS064R S29XS064R 5. Input/Output Descriptions 6. Logic Symbol Signal Description A21-A16 Address Inputs. A/DQ15–A/DQ0 Multiplexed A ddress/Data input/output. CE# Chip Enable Input. Asynchrono us relative to CLK for the Burst mode. OE# Output Enable Input. Asynchronous relative to CLK for the Bu rst mode. WE# Write Enable Input. V CC Device Power Supply (1.70 V–1.95 V). VCCQ Input/Output Power Supply (1.70 V–1.95 V). VSS Ground. VSSQ Input/Output Ground. NC Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). RDY Ready output; indicates the status of the Burst read. V OL= data invalid. VOH = data valid. CLK The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. AVD# Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15–A0 are multiplexed, address bits Amax–A16 are address only). VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs. RESET# Hardware reset input. V IL= device resets and returns to reading array data. VPP At 9V, accelerates programming. At VIL, disables program and erase functions. Should be at VIH for all other conditions. 5 to 8 A/DQ15– A/DQ0 Amax–A16 CE# OE# WE# RESET# CLK RDYAVD# VPP Amax indicates the highest order address bit.

The S29VS064R, S29XS064R device consists of 4 banks organized as shown in Table 1 and Table 2. Table 1. S29VS064R, S29XS064R Sector and Memory Address Map (Top Boot)

Table 1. S29VS064R, S29XS064R Sector and Memory Address Map (Top Boot) (Continued)

Table 2. S29VS064R, S29XS064R Sector and Memory Address Map (Bottom Boot)

Table 2. S29VS064R, S29XS064R Sector and Memory Address Map (Bottom Boot) (Continued)

Document Number: 002-00949 Rev. *J Page 18 of 68 S29VS064R S29XS064R 8. Ordering Information The order number (Valid Combination) is formed by the following: S29VS/XS 064 R AB BH W 00 0 PACKING TYPE 0 = Tray [1] 2 = 7-inch Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER (Boot Option) 00 = Top 01 = Bottom TEMPERATURE RANGE W = Wireless (–25°C to +85°C) I = Industrial (–40°C to +85°C) PACKAGE TYPE BH = Very Thin Fine-Pitch BGA, Low Halogen, Lead (Pb)-Free Package SPEED OPTION (BURST FREQUENCY) 0P = 66 MHz 0S = 83 MHz AA = 104 MHz AB = 108 MHz PROCESS TECHNOLOGY R = 65 nm MirrorBit Technology FLASH DENSITY 064 = 64 Mb DEVICE FAMILY S29VS = 1.8 Volt-Only, Simultaneous Read/Write, Burst Mode, Address and Data Multiplexed I/ O Interface S29XS = 1.8 Volt-Only, Simultaneous Read/Write, Burst Mode, Address Low, Address High and Data Multiplexed I/O Interface

Document Number: 002-00949 Rev. *J Page 19 of 68 S29VS064R S29XS064R

8.1 Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consul t your local sales office to c onfirm availability of specific valid combinations and to check on newly released combinations. Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. S29V/XS-R Valid Combinations [1][2] Base Ordering Part Number Speed Option Package Type, Material, and Temperature Packing Type Model Numbers Package Type [2] S29VS064R 0P , 0S, AB BHW 0, 3 [1] 00, 01 7.5 mm x 5.0 mm, 44-ball S29XS064R S29VS064R 0S, AA, AB BHI 0, 2, 3 00, 01 7.5 mm x 5.0 mm, 44-ball S29XS064R

Document Number: 002-00949 Rev. *J Page 20 of 68 S29VS064R S29XS064R 9. Address/Data Configur ation (Interface) Modes There are two options for connection to the address and data buses.  Address and Data Multiplexed (ADM) mode - On the S29VS-R devices upper address is supplied on separate signal inputs and the lower 16-bits of address are multiplexed with 16-bit data on the A/DQ15 to A/DQ0 I/Os.  Address-high, Address-low, and Data Multiplexed (AADM) mode - On the S29XS-R devices upper and lower address are multiplexed with 16-bit data on the A/DQ15 to A/D0 signal I/Os. The two options allow use with the traditional address/data mul tiplexed NOR interface (S29VS fa mily), or an address multiplexe d/ data multiplexed interface with the lowest signal count (S29XS family). ADM or AADM mode can be selected via ordering part number only.

9.1 ADM Interface Mode (S29VS064R)

In ADM mode, the AVD# signal is used to capture the entire addr ess with a single toggle of AVD# in asynchronous mode or in a single clock cycle in synchronous mode.

9.2 AADM Interface Mode (S29XS064R)

Signal input and output (I/O) connections on a high complexity component such as an Application Specific Integrated Circuit (ASIC) are a limited resource. Reduci ng signal count on any interface of the ASIC allows for either m ore features or lower package co st. The memory interface described in this section is intended to reduce the I/O signal count associated with the flash memory interface with an ASIC. The interface is called Address-High, Address-Low, and Data Multiplexed (AADM) because all address and data information is time multiplexed on a single 16-bit wide bus. This interface is electrically compatible with existing ADM 16-bit wide random access static memory interfaces but uses fewer address signals. In that sense AADM is a signal count subset of existing static memory interfaces. This interface can be implemented in existing memory controller designs, as an additional mode, with minimal changes. No new I/O technology is need ed and existing memor y interfaces can con tinue to be supported while the electronics industry adopts thi s new interface. ASIC designers can reuse the existing memory add ress signals above A15 for other functions when an AADM memory is in use. By breaking up the memory addres s in to two time slots the addr ess is naturally extended to be a 32-bit word address. But, usi ng two bus cycles to transfer the a ddress increases initial access latency by increasing the time address is using the bus. Howev er, many memory accesses are to locations in memory nearby the previous access. Very often it is not necessary to provide both cycles of address. This interface stores the high half of address in the memory so that if the high half of address does not change from the previous access, only the low half of address needs to be sent on the bus. If a new upper address is not captured at the beginning of an access the last captured value of the upper address is used. This allows accesses within the same 128-kbyte address range t o provide only the lower address as part of each access. In AADM mode two signal rising edges are needed to capture the upper and lower address portions in asynchronous mode or two signal combinations over two clocks is needed in synchronous mo de. In asynchronous mode the upper address is captured by an AVD# rising edge when OE# is Low; the lower address is captured on the rising edge of AVD# with OE# High. In synchronous mode the upper address is captured at the rising clock edge when AVD # and OE# are Low; the lower address is captured at the rising edge of clock when AVD# is Low and OE# is High. CE# going High at any time during the access or OE# returning H igh after RDY is first asserted High during an access, terminat es the read access and causes the address/data bus direction to sw itch back to input mode. The address/data bus direction switche s from input to output mode only afte r an Address-Low capture whe n AVD# is Low and OE# is High. This prevents the assertion of OE# during Address-High captur e from causing a bus conflict bet ween the host address and memory data signals. Note, in burst mode, this implies at least one cycle of CE# or OE# High before an Address-high for a new access may be placed on the bus so that there is time for the memory to recognize the end of the previous access, stop driving data outputs, and ignore OE# so that assertion of OE# with the new Address-high does not create a bus conflict with a new address being driven on the bus. At high bus frequencies more than one cycle may be need in order to allow t ime for data outputs to stop driving and new address to be driv en (bus turn around time). During a write access, the address/data bus direction is always in the input mode.

order address thus limiting the early boot time address space to the 128 kbytes at the boot end of the device.

9.3 Default Access Mode

Upon power-up or hardware reset, the device defaults to the Asynchronous Access mode. operations in further detail. L = Logic 0, H = Logic 1, X = Don’t Care. Table 3. Device Bus Operations

Document Number: 002-00949 Rev. *J Page 22 of 68 S29VS064R S29XS064R

10.1 Versatile IO™ (V IO) Control

The VersatileIO (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VCCQ pin.

10.2 Asynchronous Read

The device is in the Asynchronous mode when Bit 15 of the Configuration register is set to '1'. To read data from the memory array, the system must first assert a valid address.

10.2.1 S29VS-R ADM Access

With CE# LOW, WE# HIGH, and OE# HIGH, the system presents the a ddress to the device and sets AVD# LOW. AVD# is kept LOW for at least tAVDP ns. The address is latched on the rising edge of AVD#.

10.2.2 S29XS-R AADM Access

With CE# LOW, WE# HIGH, and OE# HIGH, the system presents the u pper address bits to DQ and sets AVD# LOW. The system then sets OE# LOW. The upper address bits are set when AVD# goes HIGH. The system then sets AVD# LOW again, with OE# HIGH to capture the lower address bits. The lower address bits are latched on the next rising edge of AVD#. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable CE# to valid data at the outputs. See AC Characteristics on page 57.

10.3 Synchronous (Burst) Read M ode and Configuration Register

The device is capable of continuous sequential burst operation and linear burst operation of a preset length. In order to use Synchronous (Burst) Read Mode the configuration register bit 15 must be set to 0. Prior to entering burst mode, the system should determine how many wait states are needed for the initial word of each burst access (see Table 4 on page 23), what mode of burst operation is desired, and how the RDY sig nal transitions with valid data. The system would then write the configuration register command sequence. See Configuration Register on page 38 for further details. When the appropriate number of Wait States have occurred, data is output after the rising edge of the CLK. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. RDY indicates the initial latency and any subsequent waits.

10.3.1 S29VS-R ADM Access

To burst read data from the memory array in ADM mode, the syste m must assert CE# to V IL, and provide a valid address while driving AVD# to VIL for one cycle. OE# must remain at VIH during the one cycle that AVD# is low. The data appears on A/D Q15 -A/ DQ0 when CE# remains Low, after OE# is Low and the synchronous access times are satisfied. The next data in the burst sequence is read on each clock cycle that OE# and CE# remain Low. OE# does not terminate a burst access if it rises to V IH during a burst access. The outputs will go to high impedance b ut the burst access will continue until terminated by CE# going to V IH, or AVD# returns to V IL with a new address to initiate a another burst access.

10.3.2 S29XS-R AADM Access

cycle while the upper address is valid. The rising edge of CLK when OE# and AVD# are Low captures the upper 16 bits of address. is read on each clock cycle that OE# and CE# remain Low. be required. The following Tables show the latency for variable wait state operation (note that ws = wait state). Table 4. Wait State vs. Frequency Table 5. Address Latency for 10 -13 Wait States

1 D 1 D 2D 3D 4D 5D 6D 7 1 w s + 2 w s D 8

2 D 2 D 3D 4D 5D 6D 7 1 w s 1 w s + 2 w s D 8

3 D 3 D 4D 5D 6D 7 1 w s 1 w s 1 w s + 2 w s D 8

4 D4 D5 D6 D7 1 ws 1 ws 1 ws 1 ws +2 w s D8

5 D5 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws +2 ws D8

6 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws +2 ws D8

7 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws +2 ws D8

Table 6. Address Latency for 9 Wait States

1 D 1 D 2D 3D 4D 5D 6D 7 1 w s + 1 w s D 8

2 D 2 D 3D 4D 5D 6D 7 1 w s 1 w s + 1 w s D 8

3 D 3 D 4D 5D 6D 7 1 w s 1 w s 1 w s + 1 w s D 8

4 D4 D5 D6 D7 1 ws 1 ws 1 ws 1 ws +1 ws D8

5 D5 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws +1 ws D8

6 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws +1 ws D8

7 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws +1 ws D8

Table 7. Address Latency for 8 Wait States

1 D 1 D 2D 3D 4D 5D 6D 7 1 w s D 8

2 D 2 D 3D 4D 5D 6D 7 1 w s 1 w s D 8

3 D 3 D 4D 5D 6D 7 1 w s 1 w s 1 w s D 8

4 D 4D 5 D 6 D 7 1 w s1 w s1 w s1 w s D 8

5 D 5D 6 D 7 1 w s1 w s1 w s1 w s1 w s D 8

6 D 6D 7 1 w s1 w s1 w s1 w s1 w s1 w s D 8

7 D 7 1 w s1 w s1 w s1 w s1 w s1 w s1 w s D 8

Table 8. Address Latency for 7 Wait States

1 D 1 D 2D 3D 4D 5D 6D 7 D 8 D 9

2 D 2 D 3D 4D 5D 6D 7 1 w s D 8 D 9

3 D 3 D 4D 5D 6D 7 1 w s 1 w s D 8 D 9

4 D4 D5 D6 D7 1 ws 1 ws 1 ws D8 D9

5 D5 D6 D7 1 ws 1 ws 1 ws 1 ws D8 D9

6 D6 D7 1 ws 1 ws 1 ws 1 ws 1 ws D8 D9

7 D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D9

Table 9. Address Latency for 6 Wait States

1 D 1 D 2D 3D 4D 5D 6 D 7 D 8 D 9

2 D 2 D 3D 4D 5D 6D 7 D 8 D 9 D 1 0

3 D 3 D 4D 5D 6D 7 1 w s D 8 D 9 D 1 0

4 D 4 D 5D 6D 7 1 w s 1 w s D 8 D 9 D 1 0

5 D5 D6 D7 1 ws 1 ws 1 ws D8 D9 D10

6 D6 D7 1 ws 1 ws 1 ws 1 ws D8 D9 D10

7 D7 1 ws 1 ws 1 ws 1 ws 1 ws D8 D9 D10

Table 10. Address Latency for 5 Wait States

1 D 1 D 2D 3D 4D 5 D 6 D 7 D 8 D 9

2 D 2 D 3D 4D 5D 6 D 7 D 8 D 9 D 1 0

3 D 3 D 4D 5D 6D 7 D 8 D 9 D 1 0 D 1 1

4 D 4 D 5D 6D 7 1 w s D 8 D 9 D 1 0 D 1 1

6 D6 D7 1 ws 1 ws 1 ws D8 D9 D10 D11

7 D7 1 ws 1 ws 1 ws 1 ws D8 D9 D10 D11

address. See T a b l e3 o np a g e2 1. The reset command does not terminate the burst read operation. As an example: if the starting address in the 8-word mode is 3A h, and the burst sequence would be 3A-3B-3C-3D-3E-3F-38-39h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. (except during the initial access). Table 11. Address Latency for 4 Wait States

1 D 1D 2 D 3 D 4D 5 D 6 D 7 D 8 D 9

2 D 2D 3 D 4 D 5D 6 D 7 D 8 D 9D 1 0

3 D 3D 4 D 5 D 6D 7 D 8 D 9D 1 0 D 1 1

4 D 4D 5 D 6 D 7D 8 D 9D 1 0 D 1 1 D 1 2

5 D5 D6 D7 1 ws D8 D9 D10 D11 D12

6 D6 D7 1 ws 1 ws D8 D9 D10 D11 D12

7 D7 1 ws 1 ws 1 ws D8 D9 D10 D11 D12

Table 12. Address Latency for 3 Wait States

1 D 1D 2 D 3D 4 D 5 D 6 D 7 D 8 D 9

2 D 2D 3 D 4D 5 D 6 D 7 D 8 D 9D 1 0

3 D 3D 4 D 5D 6 D 7 D 8 D 9D 1 0 D 1 1

4 D 4D 5 D 6D 7 D 8 D 9D 1 0 D 1 1 D 1 2

5 D 5D 6 D 7D 8 D 9D 1 0 D 1 1 D 1 2 D 1 3

6 D6 D7 1 ws D8 D9 D10 D11 D12 D13

7 D7 1 ws 1 ws D8 D9 D10 D11 D12 D13

Table 13. Burst Address Groups

Document Number: 002-00949 Rev. *J Page 26 of 68 S29VS064R S29XS064R

10.4 Programmable Wait State

The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD# is driven active before data will be available. Upon power up, the device defaults to the maximum of seven total cycles. The tota l number of wait states is programmable from three to nine cycles . For further details, see Set Configuration Register Command Sequence on page 35.

10.5 Configuration Register

The device uses a configuration register to set the various bur st parameters: number of wait states, burst read mode, burst le ngth, RDY configuration, and synchronous mode active.

10.6 Handshaking Feature

The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be r ead. The host system should use the configuration register to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low.

10.7 Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in one of the other banks of memory. An erase operation may also be suspended to read from or progra m to another location within the same bank (except the sector being erased). Figure 24 on page 66 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to Table 29 on page 55 for read-while-program and read-while-erase current specifications.

10.8 Writing Commands/Command Sequences

The device has inputs/outputs t hat accept both address and data information. To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. An erase operation can erase one sector, multiple sectors, or the entire device. T a b l e1 o np a g e1 0 and Table 2 on page 14 indicate the address space that each sector occupies. The device address space is divided into multiple banks. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. Refer to Table 29 on page 55 for write mode current specifications. The AC Characteristics on page 57 section contains timing specification tables and timing diagrams for write operations.

10.9 Accelerated Progr am and Erase Operations

The device offers accelerated pr ogram and erase operation throu gh the V PP function. V PP is primarily intended to allow faster manufacturing throughput at the factory and not to be used in system operations. If the system asserts VHH on this input, the device uses the higher voltage on the input to reduce the time required for program and erase operations. Removing V HH from the V PP input, upon completion of the embedded program or erase operat ion, returns the device to normal operation. Note that sectors must be unlocked prior to raising VPP to VHH. Note that the VPP pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the VPP pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, VPP locks all sectors. VPP should be at VIH for all other conditions.

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10.10 Write Buffer Programming Operation

Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard “word” programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycl e containing the Write Buffer Load command written at the Sector Address in which programming will occur. At this point, the sy stem writes the number of “ word locations minus 1 ” that will be loaded into the page buffer at the Sector Addres s in which programming wil l occur. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the “Program Buffer to Flash” confirm command. The number of locations to program cannot exceed the s ize of the write buffer or the operation will abort. (Note: The number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the “write-buffer-page” address. All subsequent address/data pairs must fall within the “selected-write-buffer-page”, and be loaded in sequential order. The “write-buffer-page” is selected by using the addresses AMAX-A5 where AMAX is A21 for S29VS/XS064R. The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the wri te buffer. (This means Write Buffer Programming cannot be performed across multiple “w rite-buffer-pages”. This also m eans that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected “write-buffer- page”, the operation will ABORT.) After writing the Starting Addr ess/Data pair, the system then w rites the remaining address/data pairs into the write buffer. W rite buffer locations must be loaded in sequential order. Note that if a Write Buffer address location is loaded multiple times, the “address/data pair” counter will be decremented for every data load operation . Also, the last data loaded at a location before the “Program Buffer to Flash” confirm com mand will be programmed into the device. It is the software’s responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been l oaded, the system must then write the “Program Buffer to Flash” command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The device will then “go busy”. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory becaus e the system can load the last address location, issue the program confirm command at the last loaded address lo cation, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer “embedded” programming operation can be suspen ded using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence can be ABORTED under any of the following conditions:  Load a value that is greater than the page buffer size during the “Number of Locations to Program” step.  Write to an address in a sector different than the one specified during the “Write-Buffer-Load” command.  Write an Address/Data pair to a different write-buffer-page than the one selected by the “Starting Address” during the “write buffer data loading” stage of the operation.  Write data other than the “Confirm Command” after the specified number of “data load” cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for t he “last address location loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. Note: The Secured Silicon s ector, autoselect, and CFI functions are unavailable when a program operation is in progress. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is allowed in any sequence of memory (or address) l ocations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. However, programming the same word address multiple times without intervening erases req uires a modified programming method. Please contact your local Cypress representative for details.

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10.11 Autoselect Mode

The autoselect mode provides ma nufacturer and device identifica tion, and sector protection verification, through identifier co des output from the internal register (which is separate from the m emory array) on DQ15-DQ0. This mode is primarily intended for programming equipment to automatica lly match a device to be pro grammed with its correspondi ng programming algorithm. The autoselect codes can also be accessed in-system. When verifying sector protectio n, the sector address must appea r on the appropriate highest order address bits. The remaining address bits are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The autoselect codes can also be accessed in-system through the command register. The command sequence is illustrated in Table 26 on page 46. Note that if a Bank Address (BA) on address bits A21, A20, and A19 for the VS/XS064R are asserted during the th ird write cycle of the autose lect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autosele ct codes, the host system must issue the autoselect command via the command register, as shown in Table 26 on page 46.

10.12 Sector Protection

The device features sector protection, which can disable both the program and erase operations in certain sectors. Dynamic Protection Bit (DYB) DYB is a security feature used to protect individual sectors from being programmed or erased inadvertently. It is a volatile protection bit and is assigned to each sector. Upon power-up, the contents of all DYBs are cleared (erased to “1”). Each DYB can be individually modified through the DYB Set Command or the DYB Clear Command. The Protection Status for a particular sector is determined by the status of the DYB relative to that sector. By issuing the DYB Set or Clear command sequences, the DYBs will be set (programmed to “0 ”) or cleared (erased to “1”), thus placing each sector in the protected or unprotected state respectively. These states are the so-called Dynamic Locked or Unlocked states due to the fact that they can switch back and forth between the protected and unprotected states. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy remov al of protection when changes are needed. The DYBs maybe set (programmed to “0”) or cleared (erased to “1”) as often as needed. When the parts are first shipped, upon power up or reset, the DYBs are cleared (erased to “1”). Note: Dynamic protection bits revert back to their default values after programming device’s “Lock Register.” The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Set command sequence is all that is necessary. The DYB Set or Clear command for the dynamic sectors signify protected or unprotected state of the sectors respectively. If the user attempts to program or erase a protected sector, th e device ignores the command and returns to read mode. A progra m or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. The programming of the DYB for a given sector can be verified by writing individual status read commands DYB Status.

10.13 Hardware Data Protection Mode

The device offers one type of data protection at the sector level:  When VPP is at VIL, all sectors are locked

10.14 Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control inp uts to prevent unintentional writes when VCC is greater than VLKO.

10.15 Write Pulse “Glitch” Protection

Noise pulses of less than tWEP on WE# do not initiate a write cycle.

10.16 Logical Inhibit

a logical zero while OE# is a logical one. If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the ri sing edge of WE#. The internal state machine is automatically reset to the read mode on power-up.

10.17 Lock Register

The Lock Register consists of one bit. This bit is non-volatile and read-only. DQ15-DQ1 are reserved and are undefined. When the device lock register is programmed (the Secured Silicon lock bit is programmed) all DYBs revert to the power-on defaul t state.

10.18 Standby Mode

consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in Table 29 on page 55 represents the standby current specification.

10.19 Automatic Sleep Mode

and clock remain stable for t ACC + 20 ns. The automatic sleep mode is independent of the CE#, WE #, and OE# control signals. always available to the system. ICC4 in Table 29 on page 55 represents the automatic sleep mode current specification.

10.20 RESET#: Hardware Reset Input

(ICC4). If RESET# is held at VIL but not within VSS, the standby current will be greater. read the boot-up firmware from the flash memory. Refer to the AC Characteristics on page 57 tables for RESET# parameters and to Figure 17 on page 61 for the timing diagram. assertion of RESET# to VIH is permitted. Table 14. Lock Register

10.21 Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.

10.22 Secured Silicon Sector Flash Memory Region

Bit will be permanently set to “1”.  A random, secure ESN only within the Factory Secured Silicon Sector.  Customer code within the Customer Secured Silicon Sector through the Cypress programming services.  Both a random, secure ESN and customer code through the Cypress programming services. using Cypress ’s programming services. first Bank through the last bank is available. The Customer Secured Silicon Sector is located at addresses 000080h–0000FFh. command sequence to return to reading and writing SA0 in the memory array. Table 15. Secured Silicon Sector Addresses

Document Number: 002-00949 Rev. *J Page 31 of 68 S29VS064R S29XS064R The Customer Secured Silicon Sec tor lock must be used with caut ion since, once locked, there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way. 11. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI ) specification outlines device and host system software interr ogation handshake, which allows specific vendor-specified software algorithms to be used for en tire families of devices. Software support can then be device- independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables Table 17–Table 20. To terminate reading CFI data, the system must write the reset command. For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A an d JESD68.01). Please contact your sales office for copies of these documents. Table 16. ID/CFI Data

Description

(SA) + 00h 0001h Cypress Manufacturer ID (SA) + 01h 007Eh (top/bottom) Device ID, Word 1 Extended ID address code. Indicates an extended two byte device ID is located at byte address 1Ch and 1Eh. (SA) + 02h 0001h-Locked, 0000h-Unlocked (SA) + 03h 0000h Reserved (SA) + 04h Reserved Reserved (SA) + 05h Reserved Reserved (SA) + 06h 0010h ID Version (SA) + 07h 00BFh Indicator Bits: DQ15 - DQ8 = Reserved DQ7 - Factory Lock Bit: 1 = Locked; 0 = Not Locked DQ6 - Customer Lock Bit: 1 = Locked; 0 = Not locked DQ5 - DQ0 = Reserved (SA) + 08h Reserved Reserved (SA) + 09h Reserved Reserved (SA) + 0Ah Reserved Reserved (SA) + 0Bh Reserved Reserved (SA) + 0Ch 00F2h Lower Software Bits Bit 0 - Status Register Support 1 = Status Register Supported 0 = Status register not Supported Bit 1 - DQ Polling Support 1 = DQ bits polling supported 0 = DQ bits polling not supported Bit 3-2 - Command Set Support 11 = Reserved 10 = Reserved 01 = Reduced Command Set 00 = Old Command Set Bit 4-F - Reserved (SA) + 0Dh Reserved Upper Software Bits Reserved (SA) + 0Eh 0061h (top/bottom) High Order Device ID, Word 2 (SA) + 0Fh 0001h (top) 0002h (bottom) Low Order Device ID, Word 3

Document Number: 002-00949 Rev. *J Page 32 of 68 S29VS064R S29XS064R Table 17. CFI Query Identification String Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Table 18. System Interface String 1Bh 0017h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0019h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h V PP Min. voltage (00h = no VPP pin present) Refer to 4Dh 1Eh 0000h V PP Max. voltage (00h = no VPP pin present) Refer to 4Eh 1Fh 0008h Typical timeout per single byte/word write 2 N µs 20h 0009h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms 22h 0011h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 0003h Max. timeout for byte/word write 2 N times typical 24h 0003h Max. timeout for buffer write 2N times typical 25h 0003h Max. timeout per individual block erase 2N times typical 26h 0003h Max. timeout for full chip erase 2 N times typical (00h = not supported)

Document Number: 002-00949 Rev. *J Page 33 of 68 S29VS064R S29XS064R Table 19. Device Geometry Definition 27h 0017h Device Size = 2 N byte 28h 0001h Flash Device Interface description (refer to CFI publication 100) 29h 0000h 2Ah 0006h Max. number of bytes in multi-byte write = 2N (00h = not supported) 2Bh 0000h 2Ch 0002h Number of Erase Bl ock Regions within device 2Dh 007Eh (top boot) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 0003h (bottom boot) 2Eh 0000h (top boot) 0000h (bottom boot) 2Fh 0000h (top boot) 0040h (bottom boot) 30h 0001h (top boot) 0000h (bottom boot) 31h 0003h (top boot) Erase Block Region 2 Information 007Eh (bottom boot) 32h 0000h (top boot) 0000h (bottom boot) 33h 0040h (top boot) 0000h (bottom boot) 34h 0000h (top boot) 0001h (bottom boot) 35h 00FFh Erase Block Region 3 Information 36h 00FFh 37h 00FFh 38h 00FFh 39h 00FFh Erase Block Region 4 Information 3Ah 00FFh 3Bh 00FFh 3Ch 00FFh

Document Number: 002-00949 Rev. *J Page 34 of 68 S29VS064R S29XS064R Table 20. Primary Vendor-Specific Extended Query Query-unique ASCII string “PRI”41h 0052h 42h 0049h 43h 0031h Major version number, ASCII 44h 0034h Minor version number, ASCII 45h 0020h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = No t Supported, X = Number of sectors in per group 48h 0000h Sector Temporary Unprote ct 00 = Not Supported, 01 = Supported 49h 0008h Sector Protect/Unprotect scheme 08 = Advanced Sector Protection 4Ah 0020h Simultaneous Operation Number of Sectors in all banks except boot bank 4Bh 0001h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0000h Page Mode 00 = Not Supported, 01 = Supported 4Dh 0085h V PP (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h VPP (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 0003h (top boot) Top/Bo ttom Boot Sector Flag 0001h = Top/Middle Boot Device, 0002h = Bottom Boot Device, 03h = Top Boot Device 0002h (bottom boot) 50h 0001h Program Suspend. 00h = not supported 51h 0000h Unlock Bypass 00 = Not Supported, 01 = Supported 52h 0008h Secured Silicon Secto r (Customer OTP Area) Size 2N bytes 53h 000Eh Hardware Reset Low Time-out during an embedded algorithm to read more mode Maximum 2N ns 54h 000Eh Hardware Reset Low Time-out during an embedded algorithm to read more mode Maximum 2N ns 55h 0005h Erase Suspend Time-out Maximum 2 N ns 56h 0005h Program Suspend Time-out Maximum 2 N ns 57h 0004h Bank Organization: X = Number of banks 58h 0020h (top boot) Bank 0 Region Information. X = Number of sectors in banks 0023h (bottom boot) 59h 0020h Bank 1 Region Information. X = Number of sectors in banks 5Ah 0020h Bank 2 Region Information. X = Number of sectors in banks 5Bh 0023h (top boot) Bank 3 Region Information. X = Number of sectors in banks 0020h (bottom boot)

Document Number: 002-00949 Rev. *J Page 35 of 68 S29VS064R S29XS064R 12. Command Definitions Writing specific address and data commands or sequences into th e command register initiates device operations. Table 26 on page 46 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the rising edge of AVD#. All data is latched on the rising edge of WE#. Refer to AC Characteristics on page 57 for timing diagrams.

12.1 Reading Array Data

The device is automatically set to reading array data after dev ice power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Er ase Suspend command, the correspo nding bank enters the erase-su spend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same e xception. See Erase Suspend/Erase Resume Commands on page 44 for more information. After the device accepts a Prog ram Suspend command, the corresp onding bank enters the program-suspend-read mode, after which the system can read data from any non-program-suspended sector within the same bank. The system must issue the reset command to return a bank to the read (or erase -suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See also Versatile IO™ (VIO) Control on page 22 and Synchronous (Burst) Read Mode and Configuration Register on page 22 in Device Bus Operations on page 21 for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figure 15 on page 59 and Figure 16 on page 60 show the timings.

12.2 Set Configuration Reg ister Command Sequence

The device uses a configuration register to set the various bur st parameters: number of wait states, burst read mode, RDY configuration, and synchronous mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be D0h and address bits should be 555h. During the fourth cycl e, the configuration code should be entered onto the data bus with the address bus set to address 0 00h. Once the data has been programmed into the configuration register, a software reset command is required to set the device into the correct state. The device will power up or after a h ardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronou s mode. The configuration register can not be changed during device operations (program, erase, or sector lock).

12.3 Read Configuration Regi ster Command Sequence

The configuration register can b e read with a four-cycle comman d sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C6h and address bits sho uld be 555h. During the fourth cycle, the configuration code sh ould be read out of the data bus with the address bus set to address 000h. Once the data has been read from the configuration register, a software reset command is required to set the device into the correct set mode.

12.3.1 Read Mode Setting

On power-up or hardware reset, t he device is set to be in async hronous read mode. This setting allows the system to enable or disable burst mode during system operations.

12.3.2 Programmable Wait State Configuration

determine the setting (see Table 21). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency.

1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait St ate Setting is set to a total initial access cycle of 2.

device is set as expected. A hardware reset will set the wait state to the default setting.

12.3.3 Programmable Wait State

speed. Table 22 describes the typical number of clock cycles (wait states) for various conditions.

12.3.4 Handshaking

The autoselect function allows the host system to determine whether the flash device is enabled for handshaking. Table 21. Programmable Wait State Settings

000 R e s e r v e d

Table 22. Wait States for Handshaking

12.3.5 Burst Length Configuration

through the starting location. The sixteen linear wrap around mode operates in a fashion similar to the eight-word mode. Table 23 shows the CR2-CR0 and settings for the four read modes.

1. Upon power-up or hardware reset the default setting is continuous.
2. All other conditions are reserved.

12.3.6 Burst Wrap Around

By default, the device will perform burst wrap around with CR3 set to a ‘1’. Changing the CR3 to a ‘0’ disables burst wrap around.

12.3.7 RDY Configuration

RDY active one clock cycle before valid data.

12.3.8 RDY Polarity

indicate that the device is ready to handle a new transaction when low. Table 23. Burst Length Configuration

Table 24 shows the address bits that determine the configuration register settings for various device functions.

1. Device will be in the default state upon power-up or hardware reset.
2. CR3 will always equal to 1 (Wrap around mode) when CR0,CR1,CR2 = 000 (continuous Burst mode).

Table 24. Configuration Register

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13.1 Reset Command

Writing the reset command resets the banks to the read or erase -suspend-read mode. Address bits are don’t cares for this command. The reset command may be writte n between the sequ ence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mod e. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence bef ore programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequenc e. Once in the autoselect mode, the reset command must be written to return to the read m ode. If a bank entered the autosel ect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing t he reset command returns the banks to the read mode (or erase- suspend-read mode if that bank was in Erase Suspend). Note: If DQ1 goes high during a Write Buffer Pro gramming operat ion, the system must write the “Write to Buffe r Abort Reset” command sequence to RESET the device to reading array data. The standard RESET command will not work. See Table 20 on page 34 for details on this command sequence.

13.2 Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. Autoselect does not support simultaneous operations or burst mode. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then ente rs the autoselect mode. The syst em may read at any address within the same bank any number of times without initiating ano ther autoselect command sequence. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address. The dev ice ID is read in three cycles. During this time, other banks are still available to read the data from the memory. The system must write the reset command to return to the read m ode (or erase-suspend-read mode if the bank was previously in Erase Suspend).

13.3 Enter/Exit Secured Silic on Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the Secur ed Silicon Sector region by issu ing the three-cycle Enter Sec ured Silicon Sector command sequence. The device continues t o access the Secu red Silicon Se ctor region until the system i ssues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Secto r command sequence returns the device to normal operation. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 26 on page 46 shows the address and data requirements for both command sequences.

13.4 Program Command Sequence

When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. on page 48 for information on these status bits. mode, to ensure data integrity.

13.5 Accelerated Program

parameters, and Figure 18 on page 63 for timing diagrams. Figure 4. Program Operation

1. See Table 26 on page 46 for program command sequence.

13.6 Write Buffer Progr amming Command Sequence

Write Buffer Programming Sequence allows for faster programming as compared to the standard Program Command Sequence. See Table 25 for the program command sequence.

1. Write buffer addresses must be loaded in sequential order.

Table 25. Write Buffer Command Sequence

Figure 5. Write Buffer Programming Operation

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13.7 Chip Erase Command Sequence

Chip erase is a six bus cycle op eration. The chip erase command sequence is initiated by writing two unlock cycles, followed b y a set-up command. Two ad ditional unlock writ e cycles are then fol lowed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and ve rifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 26 on page 46 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank return s to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to Write Operation Status on page 48 for information on these status bits. Any commands written during the chip erase operation are ignore d. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command seq uence should be reinitiated once that bank has returned to read ing array data, to ensure data integrity.

13.8 Sector Erase Command Sequence

Sector erase in normal mode is a six bus cycle ope ration. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 26 on page 46 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior t o electrical erase. The system is not required to provide any c ontrols or timings during these operations. The system can monitor DQ3 to determine if the sector erase tim er has timed out (See the section on DQ3: Sector Erase start timeout state indicator.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the sys tem can read data from the non- erasing banks. The system can determine the status of the erase operation by reading DQ7 or D Q6/ DQ2 in the erasing bank. Refer to Write Operation Status on page 48 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Accelerated Sector Erase The device offers accelerated sector erase operation through th e VPP function. This method of erasing sectors is faster than the standard sector erase command sequence. The accelerated sector erase function must not be used more than 100 times per sector. In addition, accelerated sector erase should be performed at room temperature (30C ±10C). The following procedure is used to perform accelerated sector erase: 1. Sectors to be erased must be DYB cleared. All sectors that remain locked will not be erased. 2. Apply 9V to the VPP input. This voltage must be applied at least 1 µs before executing Step 3. 3. Issue the standard chip erase command. 4. Monitor status bits DQ2/DQ6 or DQ7 to determine when erasure is complete, just as in the standard erase operation. See Write Operation Status on page 48 for further details. 5. Lower VPP from 9V to VCC.

Figure 6. Erase Operation See the section on DQ3 for information on the sector erase start timeout state indicator.

13.9 Erase Suspend/Erase Resume Commands

written during the chip erase operation or Embedded Program algorithm. time-out, the device immediately terminates the time-out period and suspends the erase operation. erasing or is erase-suspended. Refer to Write Operation Status on page 48 for information on these status bits. Write Operation Status on page 48 for more information. and Autoselect Command Sequence sections for details. Suspend command can be written after the chip has resumed erasing.

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13.10 Program Suspend/Program Resume Commands

The Program Suspend command allows the syst em to interrupt a em bedded programming operation or a “Write to Buffer” programming operation so that data can read from any non-suspen ded sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL, program suspend latency, and updates the status bits. Addresses are defined when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses n ot in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One Time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the au toselect command sequence when the device is in Program Sus pend mode. The device allows reading autoselect codes in the suspended sectors, since the co des are not stored in the memory array. When the device exits the autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 39 for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 48 for more information. The system must write the Progr am Resume command (address bits are “don’t care”) to exit the Program Suspend mode and continue the programming operatio n. Further writes of the Progr am Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.

13.11 Volatile Sector Protection Command Set

The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB), clear the Dynamic Protection Bit (DYB), and read the logic state of the Dynamic Protection Bit (DYB). The Volatile Sector Protection Command Set Entry command sequence must be issued p rior to any of the commands li sted following to enable proper command execution. Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes for the bank selected with the command. Reads for other banks excluding the selected bank are allowed.  DYB Set Command  DYB Clear Command  DYB Status Read Command The DYB Set/Clear command is us ed to set or clear a DYB for a g iven sector. The high order addr ess bits (Amax-A13 for VS/ XS064R) are issued at the same time as the code 00h or 01h on D Q7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time. The DYBs are set at power-up or hardware reset. The programming state of the DYB for a given sector can be verified by writing a DYB Status Read Command to the device. Note: The bank entered during entry is the active bank. Take for exa mple the active bank is BA0. An y reads in BA0 will result in status reads of the DYB bit. If the user wants to set (programm ed to “0”) in a different bank other than the active bank, say for example BA5, then the active bank switches from BA0 to BA5. Reading in BA5 will result in status read of the bit whereas reading in BA0 will result in true data. The Volatile Sector Protection Command Set Exit command must be issued after th e execution of the commands lis ted previously to reset the device to read mode. Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes for the bank selected.

Table 26. Command Definitions

RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0]. PD(3) = Protection Mode OTP Bit. PD(3) or bit[3]. max - A13 uniquely select any sector. BA = Address of the bank A21-A19. CR = Configuration Register set by data bits D15-D0. RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 0, if unprotected, DQ1 = 1. RD(2) = DQ2 protection indicator bit. If protected, DQ2 = 0, if unprotected, DQ2 = 1. RD(4) = DQ4 protection indicator bit. If protected, DQ4 = 0, if unprotected, DQ4 = 1. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 3 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fo urth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.
5. Unless otherwise noted, address bits A
6. Writing incorrect address and data values or writing them in th e improper sequence may place the device in an unknown state. The system

must write the reset command to return the device to reading array data.

1. No unlock or command cycles required when bank is reading array data.
2. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a

bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read cycle. The system must read device IDs across the 4th, 5th, and 6th cycles,

The system must provide the bank address. See Autoselect Command Sequence on page 39 for more information. Table 26. Command Definitions (Continued)

Document Number: 002-00949 Rev. *J Page 48 of 68 S29VS064R S29XS064R 10. See Table 3 for description of bus operations. 11. See the Autoselect Command Sequence on page 39. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 13. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 14. Command is valid when device is ready to read array data or when device is in autoselect mode. 15. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 16. Command sequence resets device for next command after write-to-buffer operation. 17. Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 18. The Exit command must be issued to reset the device into read mode. Otherwise the device will hang. 19. Requires the Reset command to configure the configuration register. 14. Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 28 on page 53 and the following subsections describe the function of these b its. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress.

14.1 DQ7: Data# Polling

The Data# Polling bit, DQ7, indi cates to the host system whethe r an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word ot her than the last word to be programmed in the write- buffer-page will return false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 i s active for approximately t PSP, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors sele cted for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sector s that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase op eration, DQ7 may change asynchronously with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may ch ange from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6–DQ0 may be still invalid. Valid data on DQ7–DQ0 will appear on successive read cycles. Table 28 on page 53 shows the outputs for Data# Polling on DQ7. Figure 7 on page 49 shows the Data# Polling algorithm. Figure 20 on page 64 in AC Characteristics shows the Data# Polling timing diagram.

Figure 7. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector erase operat ion, a valid address is any sector address within the sector being erased. During chip erase, a valid

address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

14.2 RDY: Ready

The RDY pin is a dedicated status output that indicates valid o utput data on A/DQ15–A/DQ0 durin g burst (synchronous) reads. should wait until RDY is re-asserted before expecting the next word of data. OE# = VIH, and RDY is Hi-Z when CE# = VIH. RDY = VOH when CE# = VIL, and RDY is Hi-Z when CE# = VIH.

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14.3 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising ed ge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. Note that OE# must be low during toggle bit status reads. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP, all sectors protected toggle time, then returns to reading array da ta. If not all selected sectors are protected, the Embedded Era se algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (t hat is, the Embedded Erase algorit hm is in progress), DQ6 toggles . When the device enters the Era se Suspend mode, DQ6 stops toggling. H owever, the system must also use DQ2 to determine which sectors are erasing or erase- suspended. Alternatively, the system can use DQ7 (see <Hypertext>Section 14.1 DQ7: Data# Polling on page 48). If a program address falls withi n a protected se ctor, DQ6 toggles for approximately t PSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: (toggle bit flowc hart), Figure 21 (toggle bit timing diagram), and Table 27 on page 52 (compares DQ2 and DQ6).

14.4 DQ2: Toggle Bit II

WE# pulse in the command sequence. be low during toggle bit status reads. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. on page 53 to compare outputs for DQ2 and DQ6. bit timing diagram), and Table 27 on page 52 (compares DQ2 and DQ6). Figure 8. Toggle Bit Algorithm

14.5 Reading Toggle Bits DQ6/DQ2

program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. and the system must write the reset command to return to reading array data. algorithm when it returns to determine the status of the operation.

14.6 DQ5: Exceeded Timing Limits

produces a “1,” indicating that the program or erase cycle was not successfully completed. mode if a bank was previously in the erase-suspend-program mode). Table 27. DQ6 and DQ2 Indications programming, at any address, toggles, does not toggle. for erasure, toggles, also toggles. selected for erasure, toggles, does not toggle. for erasure, does not toggle, toggles. from any sector not selected for erasure. erase suspend at any address, toggles, is not applicable.

14.7 DQ3: Sector Erase Sta rt Timeout State Indicator

might not have been accepted. Table 28 shows the status of DQ3 relative to the other status bits.

14.8 DQ1: Write to Buffer Abort

Operation on page 27 for more details.

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section

on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status informa tion. Refer to the appropriate subsection for further details.
2. Data are invalid for addresses in a Program Suspended sector.
3. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
4. The data-bar polling algorithm should be us ed for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming

indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location. Table 28. Write Operation Status

1. Maximum I CC specifications are tested with VCC = VCCmax.
2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. I CC active while Embedded Erase or Embedded Program is in progress.
4. Device enters automatic sleep mode when addresses are stable for t ACC + 20 ns. Typical sleep mode current is equal to ICC3.
5. Specifications assume 8 I/Os switching.
6. Not 100% tested. V PP is not a power supply pin.
7. While measuring Output Leakage Current, CE# should be at V IH.

Table 29. CMOS Compatible

66 MHz 31 34

83 MHz 35 38

108 MHz 39 44

66 MHz 24 26

83 MHz 28 30

108 MHz 32 36

5 MHz 20 40 mA

1 MHz 10 20 mA

66 MHz 61 66

108 MHz 71 76

Figure 11. Test Setup

1. Key to Switching Waveforms

19.1 Switching Waveforms

Figure 12. Input Waveforms and Measurement Levels Table 30. Test Specifications

66 MHz 3 ns

20.1 V CC Power-up

1. Reset# must be high after V CC and VIO are higher than VCC minimum.
2. V CC  VIO – 200 mV during power-up.
3. V CC and VIO ramp rate could be non-linear.
4. V CC and VIO are recommended to be ramped up simultaneously.

Figure 13. VCC Power-up Diagram

1. Clock jitter of ±5% permitted.

Figure 14. CLK Characterization

Document Number: 002-00949 Rev. *J Page 58 of 68 S29VS064R S29XS064R

20.2 Synchronous/Burst Read

Note: 1. Not 100% tested. Parameter Description (66 MHz) (83 MHz) (108 MHz) Unit JEDEC Standard tIACC Initial Access Time Max 80 ns tBACC Burst Access Time Valid Clock to Output Delay Max 11.2 9 7.6 ns tAVDS AVD# Setup Time to CLK Min 4 ns tAVDH AVD# Hold Time from CLK Min 3 ns tAVDO AVD# High to OE# Low Min 0 ns tACS Address Setup Time to CLK Min 4 ns tACH Address Hold Time from CLK Min 6 ns tBDH Data Hold Time from Next Clock Cycle Min 3 3 2 ns tOE Output Enable to RDY Low Max 15 ns tCEZ Chip Enable to High-Z [1] Max 10 ns tOEZ Output Enable to High-Z [1] Max 10 ns tCES CE# Setup Time to CLK Min 4 ns tRDYS RDY Setup Time to CLK Min 3.9 3 2 ns tRACC Ready access time from CLK Max 11.2 9 7.6 ns

Figure 15. Burst Mode Read

1. Figure shows total number of clock set to five.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address +3”, additional clock delays are inserted, and are indicated by RDY.

5 cycles for initial access shown.

20.3 Asynchronous Read

Figure 16. Asynchronous Mode Read RA = Read Address, RD = Read Data.

20.4 Hardware Reset (RESET#)

Figure 17. Reset Timings Table 31. Warm-Reset

Document Number: 002-00949 Rev. *J Page 62 of 68 S29VS064R S29XS064R

20.5 Erase/Program Operations

Notes: 1. Not 100% tested. 2. See Erase and Programming Performance on page 67 for more information. 3. Does not include the preprogramming time. Parameter Description Unit JEDEC Standard tAVAV tWC Write Cycle Time [1] Min 60 ns tAVWL tAS Address Setup Time Min 4 ns tWLAX tAH Address Hold Time Min 3.5 ns tAVDP AVD# Low Time Min 6 ns tAAVDS Address Setup to Rising of AVD# Min 4 ns tAAVDH Address Hold from Rising of AVD# Min 3.5 ns tDVWH tDS Data Setup Time Min 20 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 ns tELWL tCS CE# Setup Time to WE# Min 4 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP/tWRL Write Pulse Width Min 25 ns tVLWH AVD# Disable to WE# Disable Min 23.5 ns tWEA WE# Disable to AVD# Enable Min 9.6 ns tCR CE# Low to RDY Valid Max 10 ns tCEZ CE# Disable to Output High-Z Max 10 ns tWEH OE# Disable to WE# Enable Min 4 ns tWHWL tWPH Write Pulse Width High Min 20 ns tSR/W Latency Between Read and Write Operations Min 0 ns tVPP VPP Rise and Fall Time Min 500 ns tVPS VPP Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tESL Erase Suspend Latency Max 30 µs tPSL Program Suspend Latency Max 30 µs tPSP Toggle Time During Programming Within a Protected Sector Typ 20 µs tASP Toggle Time During Sector Protection Typ 20 µs tWEP Noise Pulse Margin on WE# Max 3 ns tERS ER to ES Min 30 µs tPRS PR to PS Min 30 µs

Figure 24. Back-to-Back Read/Write Cycle Timings or erase operation in the “busy” bank. The system should read status twice to ensure valid information.

Document Number: 002-00949 Rev. *J Page 67 of 68 S29VS064R S29XS064R 21. Erase and Programming Performance Notes: 1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V CC, 10,000 cycles typical. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of -25°C, V CC = 1.70 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 32-word write buffer operation. 4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 26 on page 46 for further information on command definitions. 7. Wireless (W) Temperature Range 8. Industrial (I) Temperature Range 22. BGA Ball Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. Parameter Typ [1] Max [2] Unit Comments Sector Erase Time 32 kword V CC 0.8 3.5 s Excludes 00h programming prior to erasure (Note 5) 8 kword V CC 0.35 2 Chip Erase Time VCC 103 453 VPP 103 453 Single Word Programming Time VCC 170 800 [7]/1600 [8] µs Effective Word Programming Time utilizing Program Write Buffer VCC 14.1 94 VPP 96 0 Total 32-Word Buffer Programming Time VCC 450 3000 [7]/6000 [8] VPP 288 1920 Chip Programming Time [4] VCC 59 78.6 s Excludes system level overhead (Note 6) VPP 38 52 Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 4.2 5.0 pF COUT Output Capacitance V OUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 3.9 4.7 pF

Document Number: 002-00949 Rev. *J Page 67 of 68 S29VS064R S29XS064R 23. Document History Document Title: S29VS064R, S29XS064R 64 Mbit (4M x 16-bit), 1.8 V, Multiplexed, Burst MirrorBit® Flash Document Number: 002-00949 Rev. ECN No. Orig. of Change Submission Date Description of Change ** - WIOB 04/23/2010 Spansion Publication Number: S29VS_XS064R_00 Initial release *A - WIOB 08/06/2010 Performance Characteristics Updated table: Typical Program & Erase Times Connection Diagram Updated diagram to show outrigger balls DC Characteristics: CMOS Compatible Updated table: ICCB, ICC2, and ICC5 Erase and Programming Performance Updated table: Changed Typ and Max values for Single Word Programming Time Changed Typ values for buffer and chip programming times Synchronous/Burst Read Updated tOE description Asynchronous Read Updated tOE value *B - WIOB 10/04/2010 DC Characteristics CMOS Compatible table: Changed typical values for ICC3 and ICC6 *C - WIOB 10/27/2010 Configuration Register Corrected CR15 and CR11-13 settings description Removed Note 3 DC Characteristics: CMOS Compatible Removed Note 9 *D - WIOB 12/09/2010 Global Added references to Industrial Specification Supplement Volatile Sector Protection Command Set Command Definitions table: Corrected missing note references for CFI and Set Configuration Register Removed orphan notes *E - WIOB 07/22/2011 Factory Secured Silicon Sector Erase and Programming Performance Reworded to indicate that sector is unprogrammed by default Corrected note 2 for worst case condition temperature *F - WIOB 08/07/2012 Synchronous (Burst) Read Mode and Configuration Register Removed text that implied output drive strength can be controlled through the configuration register *G 5042966 WIOB 12/17/2015 Changed status from Advance to production Updated to Cypress Template *H 5745055 NIBK 06/13/2017 Updated C ypress Logo and Copyright. *I 5965428 BWHA 11/15/2017 Added Memory Map on page 10. *J 6022619 PRIT 01/09/2018 Updated Ordering Information on page 18. Added a row in Valid Combinations on page 19. Added “Ambient temperature for Industrial Device” in Operating Ranges on page 54. Updated table in Erase and Programming Performance on page 67.

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