S29JL032J

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 61

Technical content

Datasheet sections

• 1.1 S29JL032J Features
• 8.1 Word/Byte Configuration
• 8.2 Requirements for Reading Arra y Data
• 8.3 Writing Commands/Command Sequences
• 8.5 Standby Mode
• 8.6 Automatic Sleep Mode
• 8.7 RESET#: Hardware Reset Pin
• 8.8 Output Disable Mode
• 8.9 Autoselect Mode
• 8.10 Boot Sector/Sector Block Pr otection and Unprotection
• 8.11 Write Protect (WP#)
• 8.12 Temporary Sector Unprotect
• 8.13 Secured Silicon Region
• 8.14 Hardware Data Protection
• 10.1 Reading Array Data
• 10.2 Reset Command
• 10.3 Autoselect Command Sequence
• 10.4 Enter Secured Silicon Region/Exit Secured Silicon Region
• 10.5 Byte/Word Program Command Sequence
• 10.6 Chip Erase Command Sequence
• 10.7 Sector Erase Command Sequenc e
• 10.8 Erase Suspend/Erase Resume Commands
• 11.1 DQ7: Data# Polling
• 11.2 RY/BY#: Ready/Busy#
• 11.3 DQ6: Toggle Bit I
• 11.4 DQ2: Toggle Bit II
• 11.5 Reading Toggle Bits DQ6/DQ2
• 11.6 DQ5: Exceeded Timing Limits
• 11.7 DQ3: Sector Erase Timer
• 14.1 CMOS Compatible
• 14.2 Zero-Power Flash
• 17.1 Read-Only Operations
• 17.2 Hardware Reset (RESET#)
• 17.3 Word/Byte Configuration (BYTE#)
• 17.4 Erase and Program Operations
• 17.5 Temporary Sector Unprotect
• 17.6 Alternate CE# Controlled Erase and Program Operations
• 18.1 Erase Endurance
• 18.2 Data Retention
• 21.1 TS 048—48-Pin Standard TSOP
• 21.2 VBK048—48-Pin FBGA

Cypress Semiconductor Corporation •198 Champion Court•San Jose, CA 95134-1709•408-943-2600 Document Number: 002-00857 Rev. *G Revised May 19, 2017 S29JL032J

32 Mbit (4M x 8-Bit/2M x 16-Bit), 3 V

Simultaneous Read/Write Flash Distinctive Characteristics Architectural Advantages  Simultaneous Read/Write operations – Data can be continuously read from one bank while executing erase/program functions in another bank. – Zero latency between read and write operations  Multiple bank architecture – Four bank architectures available (refer to Table 2 on page 12).  Boot sectors – Top or bottom boot sector configurations available – Any combination of sectors can be erased  Manufactured on 0.11 µm Process Technology  Secured Silicon Region: Extra 256 byte sector – Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function – Customer lockable: One-time programmable only. Once locked, data cannot be changed  Zero power operation – Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero.  Compatible with JEDEC standards – Pinout and software compatible with single-power-supply flash standard Package Options  48-ball Fine-pitch BGA  48-pin TSOP Performance Characteristics  High performance – Access time as fast as 60 ns – Program time: 6 µs/word typical using accelerated programming function  Ultra low power consumption (typical values) – 2 mA active read current at 1 MHz – 10 mA active read current at 5 MHz – 200 nA in standby or automatic sleep mode  Cycling endurance: 100K cycles per sector  Data retention: 20 years typical Software Features  Supports Common Flash Memory Interface (CFI)  Erase suspend/Erase resume – Suspends erase operations to read data from, or program data to, a sector that is not being erased, then resumes the erase operation.  Data# polling and toggle bits – Provides a software method of detecting the status of program or erase operations  Unlock bypass program command – Reduces overall programming time when issuing multiple program command sequences Hardware Features  Ready/Busy# output (RY/BY#) – Hardware method for detecting program or erase cycle completion  Hardware reset pin (RESET#) – Hardware method of resetting the internal state machine to the read mode  WP#/ACC input pin – Write protect (WP#) function protects the two outermost boot sectors regardless of sector protect status – Acceleration (ACC) function accelerates program timing  Sector protection – Hardware method to prevent any program or erase operation within a sector – Temporary Sector Unprotect allows changing data in protected sectors in-system General Description The S29JL032J is a 32 Mbit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 60, or 70 ns and is offered in a 48-ball FBGA or a 48-pin TSOP package. Standard control pins—chip enable (CE#), write enable (WE#), and out put enable (OE#)—control norma l read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

Document Number: 002-00857 Rev. *G Page 3 of 61 S29JL032J 1. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into separate banks (see Table 2 on page 12). Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The S29JL032J can be organized with either a top or bottom boot sector configuration.

1.1 S29JL032J Features

The Secured Silicon Region is an extra 256 byte sector capable of being permanently locked by the customer. The Secured Silicon Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been locked and is 0 if lockable. Customers may utilize the Secured Silicon Region as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. The device offers complete compatibility with the JEDEC 42.4 single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Region area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes.

Document Number: 002-00857 Rev. *G Page 4 of 61 S29JL032J 2. Product Selector Guide 3. Block Diagram 3.1 4-Bank Device Part Number S29JL032J Speed Option Standard Voltage Range: VCC = 3.0–3.6 V 60 Standard Voltage Range: VCC = 2.7–3.6 V 70 Max Access Time (ns), tACC 60 70 CE# Access (ns), tCE 60 70 OE# Access (ns), tOE 25 30 VCC VSS Bank 1 Address Bank 2 Address A20–A0 RESET# WE# CE# BYTE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Bank 1 X-Decoder OE# BYTE# DQ15–DQ0 Status Control A20–A0 A20–A0 A20–A0A20–A0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank 2 X-Decoder Y-gate Bank 3 X-Decoder Bank 4 X-Decoder Y-gate Bank 3 Address Bank 4 Address

Document Number: 002-00857 Rev. *G Page 5 of 61 S29JL032J 3.2 2-Bank Device VCC VSS Upper Bank AddressA20–A0 RESET# WE# CE# BYTE# DQ15–DQ0 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ15–DQ0 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address OE# BYTE# Status Control A20–A0 A20–A0 A20–A0A20–A0 DQ15–DQ0 DQ15–DQ0

Document Number: 002-00857 Rev. *G Page 6 of 61 S29JL032J 4. Connection Diagrams 4.1 48-pin TSOP Package 4.2 48-ball FBGA Package A15 A18 A14 A13 A12 A11 A10 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 V SSDQ15/A-1BYTE#A16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19NCRESET# DQ3DQ11DQ10DQ2A20A18WP#/ACC A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 DQ1DQ9DQ8DQ0A5A6A17 B1 C1 D1 E1 F1 G1 H1 VSSOE#CE#A0A1A2A4

Document Number: 002-00857 Rev. *G Page 7 of 61 S29JL032J 5. Pin Description 6. Logic Symbol A20–A0 21 Address Pins DQ14–DQ0 15 Data Inputs/Outputs (x16-only devices) DQ15/A-1 DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# Chip Enable, Active Low OE# Output Enable, Active Low WE# Write Enable, Active Low WP#/ACC Hardware Write Protect/Acceleration Pin. RESET# Hardware Reset Pin, Active Low BYTE# Selects 8-bit or 16-bit mode, Active Low RY/BY# Ready/Busy Output, Active Low V CC 3.0 volt-only single power supply (see Product Selector Guide on page 4 for speed options and voltage supply tolerances) VSS Device Ground NC Not Connected – No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).21 16 or 8 DQ15–DQ0 (A-1) A20–A0 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC

Document Number: 002-00857 Rev. *G Page 8 of 61 S29JL032J 7. Ordering Information The order number (Valid Combination) is formed by the following: Note: 1. Type 0 is standard. Specify others as required. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local Cypress sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29JL032J 60 T F I 01 0 Packing Type 0= T r a y 3 = 13-inch Tape and Reel Model Number 01 = Top Boot Device, 4 Banks: 4/12/12/4 Mb 02 = Bottom Boot Device, 4 Banks: 4/12/12/4 Mb 21 = Top Boot Device, 2 Banks: 4/28 Mb 22 = Bottom Boot Device, 2 Banks: 4/28 Mb 31 = Top Boot Device, 2 Banks: 8/24 Mb 32 = Bottom Boot Device, 2 Banks: 8/24 Mb 41 = Top Boot Device, 2 Banks: 16/16 Mb 42 = Bottom Boot Device, 2 Banks: 16/16 Mb Temperature Range I = Industrial (–40°C to +85°C) Package Material Set F = Pb-free H = Low-halogen, Pb-free Package Type B = Fine-pitch Ball Grid Array Package T = Thin Small Outline Package (TSOP) Standard Pinout Speed Option 60 = 60 ns 70 = 70 ns Device Family S29JL032J

3.0 Volt-only, 32 Mbit (2 M x 16-Bit/4 M x 8-Bit) Simultaneous Read/Write Flash Memory

Manufactured on 110 nm process technology S29JL032J Valid Combinations Device Number/ Description Speed (ns) Package Type Temperat ure Range Additional Ordering Options Packing Type Package

Description

S29JL032J 60, 70 TF I 0, 3 (1) TS048 TSOP BH 31, 32 VBK04

8 FBGA

operations in further detail.

1. Addresses are A20:A0 in word mode (BYTE# = V IH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Boot Sector/Sector Block

Protection and Unprotection on page 18.

1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, protection on the two outermost boot sectors depends on

whether they were last protected or unprotected using the method described in Boot Sector/Sector Block Protection and Unprotection on page 18. If WP#/ACC = VHH, all sectors will be unprotected.

8.1 Word/Byte Configuration

‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#. CE# and OE#. The data I/O pins DQ14–DQ8 are tristated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Table 1. S29JL032J Device Bus Operations

Document Number: 002-00857 Rev. *G Page 10 of 61 S29JL032J

8.2 Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the Read-Only Operations on page 44 for timing specifications and to Figure 17.1 on page 44 for the timing diagram. ICC1 in DC Characteristics on page 40 represents the active current specification for reading array data.

8.3 Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte Configuration on page 9 for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Byte/Word Program Command Sequence on page 28 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 3 on page 13 and Table 4 on page 15 indicate the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. Command Definitions on page 27 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank. ICC2 in the DC Characteristics table represents the active current specification for the write mode. AC Characteristics on page 44 contains timing specification tables and timing diagrams for write operations.

8.3.1 Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. See Write Protect (WP#) on page 20 for related information.

8.3.2 Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 17 and Autoselect Command Sequence on page 28 for more information.

Document Number: 002-00857 Rev. *G Page 11 of 61 S29JL032J

8.4 Simultaneous Read/Write Op erations with Zero Latency

This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 17.8 on page 49 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in DC Characteristics on page 40 represent the current specifications for read-while-program and read-while-erase, respectively.

8.5 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3V. Note that this is a more restricted voltage range than VIH. If CE# and RESET# are held at VIH, but not within VCC ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in DC Characteristics on page 40 represents the standby current specification.

8.6 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in DC Characteristics on page 40 represents the automatic sleep mode current specification.

8.7 RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to Hardware Reset (RESET#) on page 45 for RESET# parameters and to Figure 17.2 on page 45 for the timing diagram.

8.8 Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. S29JL032J Bank Architecture

12 Mbit

Table 3. S29JL032J Sector Addresses - Top Boot Devices (Sheet 1 of 2)

Table 3. S29JL032J Sector Addresses - Top Boot Devices (Sheet 2 of 2)

Table 4. S29JL032J Sector Addresses - Bottom Boot Devices (Sheet 1 of 2)

Table 4. S29JL032J Sector Addresses - Bottom Boot Devices (Sheet 2 of 2)

8.9 Autoselect Mode

through the command register. Table 5. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. autoselect data from that bank and then immediately read array data from another bank, without exiting the autoselect mode. Table 5. S29JL032J Autoselect Codes (High Voltage Method)

8.10 Boot Sector/Sector Block Protection and Unprotection

more adjacent sectors that are protected or unprotected at the same time (see Table 6). implemented via two methods. Table 6. S29JL032J Boot Sector/Sector Block Addresses for Protection/Unprotection (Top Boot Devices)

protected sectors efficiently, the temporary sector unprotect function is available. See Temporary Sector Unprotect on page 20. sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 17 for details. Table 7. S29JL032J Sector/Sector Block Addresses for Protection/Unprotection (Bottom Boot Devices)

8.11 Write Protect (WP#)

two provided by the WP#/ACC pin. addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. protected or unprotected using the method described in Boot Sector/Sector Block Protection and Unprotection on page 18. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.

8.12 Temporary Sector Unprotect

adjacent sectors that are protected or unprotected at the same time (see Table 6 on page 18 and Table 7 on page 19). WP#/ACC pin is at VIL, the two outermost boot sectors will remain protected during the Temporary sector Unprotect mode.

1. All protected sectors un protected (If WP#/ACC = VIL, the outermost two boot sectors will remain protected).
2. All previously protected se ctors are protected once again.

Table 8. WP#/ACC Modes VHH Enables accelerated programming (ACC). See Accelerated Program Operation on page 10.

Document Number: 002-00857 Rev. *G Page 21 of 61 S29JL032J Figure 8.2 In-System Sector Protect/Unprotect Algorithms Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Set up sector address Wait 150 µs Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 ms First Write Cycle = 60h? Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Yes Yes No PLSCNT = 25? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Set up first sector address Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Read from sector address with A6 = 1, A1 = 1, A0 = 0 START PLSCNT = 1 RESET# = VID Wait 1 ms Data = 00h? Last sector verified? Remove VID from RESET# Write reset command Sector Unprotect complete Yes No PLSCNT = 1000? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No All sectors protected? Yes Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Set up next sector address No Yes No Yes No No Yes No Sector Protect Algorithm Sector Unprotect Algorithm First Write Cycle = 60h? Protect another sector? Reset PLSCNT = 1

Document Number: 002-00857 Rev. *G Page 22 of 61 S29JL032J

8.13 Secured Silicon Region

The Secured Silicon Region feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Region is 256 bytes in length, and may shipped unprotected, allowing customers to utilize that sector in any manner they choose, or may shipped locked at the factory (upon customer request). The Secured Silicon Indicator Bit data will be 82h if factory locked, 42h if customer locked, or 02h if neither. Refer to Table 5 on page 17 for more details. The system accesses the Secured Silicon through a command sequence (see Enter Secured Silicon Region/Exit Secured Silicon Region Command Sequence on page 28). After the system has written the Enter Secured Silicon Region command sequence, it may read the Secured Silicon Region by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Region command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of Sector 0. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Region is enabled.

8.13.1 Factory Locked: Secured Silicon Regi on Programmed and Protected At the

In a factory locked device, the Secured Silicon Region is protected when the device is shipped from the factory. The Secured Silicon Region cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number is at addresses 000000h-000007h in word mode (or 000000h-00000Fh in byte mode). The secure ESN is programmed in the next 8 words at addresses 000008h-00000Fh (or 000010h-00001Fh in byte mode). The device is available preprogrammed with one of the following:  A random, secure ESN only  Customer code through Cypress programming services  Both a random, secure ESN and customer code through Cypress programming services Contact an your local sales office for details on using Cypress programming services.

8.13.2 Customer Lockable: Secured Silicon Re gion NOT Programmed or Protected At

If the security feature is not required, the Secured Silicon Region can be treated as an additional Flash memory space. The Secured Silicon Region can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Region.  Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the insystem sector protect algorithm as shown in Figure 8.2 on page 21, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Region without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Region.  To verify the protect/unprotect status of the Secured Silicon Region, follow the algorithm shown in Figure 8.3 on page 23. Once the Secured Silicon Region is locked and verified, the system must write the Exit Secured Silicon Region command sequence to return to reading and writing the remainder of the array. The Secured Silicon Region lock must be used with caution since, once locked, there is no procedure available for unlocking the Secured Silicon Region area and none of the bits in the Secured Silicon Region memory space can be modified in any way.

Document Number: 002-00857 Rev. *G Page 23 of 61 S29JL032J Figure 8.3 Secured Silicon Region Protect Verify

8.14 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 13 on page 33 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.

8.14.1 Low V CC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

8.14.2 Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

8.14.3 Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

8.14.4 Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Write 60h to any address Write 40h to Secure Silicon Region address with A6 = 0, A1 = 1, A0 = 0 START RESET# = VIH or VID Wait 1 ms Read from Secure Silicon Region address with A6 = 0, A1 = 1, A0 = 0 If data = 00h, Secure Silicon Region is unprotected. If data = 01h, Secure Silicon Region is protected. Remove VIH or VID from RESET# Secured Silicon Region exit command Secure Silicon Region Protect Verify complete

1. Common Flash Memory Interface (CFI)

can standardize their existing interfaces for long-term compatibility. when the device is executing an Embedded Program or embedded Erase algorithm. Table 9. The system must write the reset command to return to reading array data. Table 9. CFI Query Identification String Table 10. System Interface String

Table 11. Device Geometry Definition

Table 12. Primary Vendor-Specific Extended Query (Sheet 1 of 2)

the device in an unknown state. A hardware reset may be required to return the device to reading array data. or CE#, whichever happens first. Refer to AC Characteristics on page 44 for timing diagrams.

10.1 Reading Array Data

is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. exception. See Erase Suspend/Erase Resume Commands on page 32 for more information. active program or erase operation, or if the bank is in the autoselect mode. See Reset Command on page 27, for more information. read parameters, and Figure 17.1 on page 44 shows the timing diagram.

10.2 Reset Command

Writing the reset command resets the banks to the read or erase-suspend-read mode. commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. begins, however, the device ignores reset commands until the operation is complete. Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. suspend-read mode if that bank was in Erase Suspend). Please note that the RY/BY# signal remains low until this reset is issued. Table 12. Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Document Number: 002-00857 Rev. *G Page 28 of 61 S29JL032J

10.3 Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in another bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 13 on page 33 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 3 on page 13 and Table 4 on page 15 show the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).

10.4 Enter Secured Silicon Region/E xit Secured Silicon Region Command

The system can access the Secured Silicon Region region by issuing the three-cycle Enter Secured Silicon Region command sequence. The device continues to access the Secured Silicon Region until the system issues the four-cycle Exit Secured Silicon Region command sequence. The Exit Secured Silicon Region command sequence returns the device to normal operation. The Secured Silicon Region is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 13 on page 33 shows the address and data requirements for both command sequences. See also Secured Silicon Region on page 22 for further information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Region is enabled.

10.5 Byte/Word Program Command Sequence

The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 13 on page 33 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to Write Operation Status on page 34 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the Secured Silicon Region, autoselect, and CFI functions are unavailable when a program operation is in progress. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”

Document Number: 002-00857 Rev. *G Page 29 of 61 S29JL032J

10.5.1 Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 13 on page 33 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (Table 13 on page 33). The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for any operation other than accelerated programming, or device damage may result. In addition, the WP#/ ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 10.1 illustrates the algorithm for the program operation. Refer to Erase and Program Operations on page 47 for parameters, and Figure 17.5 on page 48 for timing diagrams. Figure 10.1 Program Operation Note: See Table 13 on page 33 for program command sequence. START Write Program Command Sequence Data Poll from System Verify Data? No Yes Last Address?No Yes Programming Completed Increment Address Embedded Program algorithm in progress

Document Number: 002-00857 Rev. *G Page 30 of 61 S29JL032J

10.6 Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 13 on page 33 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status on page 34 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the Secured Silicon Region, autoselect, and CFI functions are unavailable when an erase operation is in progress. Figure 10.2 on page 31 illustrates the algorithm for the erase operation. Refer to Erase and Program Operations on page 47 for parameters, and Figure 17.7 on page 49 for timing diagrams.

10.7 Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 13 on page 33 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. However, these additional erase commands are only one bus cycle long and should be identical to the sixth cycle of the standard erase command explained above. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input during the time-out period, the normal operation will not be guaranteed. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase Timer on page 38.). The time-out begins from the rising edge of the final WE# or CE# pulse (first rising edge) in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to Write Operation Status on page 34 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the Secured Silicon Region, autoselect, and CFI functions are unavailable when an erase operation is in progress. Figure 10.2 on page 31 illustrates the algorithm for the erase operation. Refer to Erase and Program Operations on page 47 for parameters, and Figure 17.7 on page 49 for timing diagrams.

Document Number: 002-00857 Rev. *G Page 31 of 61 S29JL032J Figure 10.2 Erase Operation Notes: 1. See Table 13 on page 33 for erase command sequence. 2. See DQ3: Sector Erase Timer on page 38 for information on the sector erase timer. START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System Data = FFh?No Yes Erasure Completed Embedded Erase algorithm in progress

Document Number: 002-00857 Rev. *G Page 32 of 61 S29JL032J

10.8 Erase Suspend/Era se Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. The bank address must contain one of the sectors currently selected for erase. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) It is not recommended to program the Secured Silicon Region after an erase suspend, as proper device functionality cannot be guaranteed. Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Write Operation Status on page 34 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to Write Operation Status on page 34 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to Autoselect Mode on page 17 and Autoselect Command Sequence on page 28 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase- suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector. Refer to Table 3 on page 13 and Table 4 on page 15 for information on sector addresses. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. A20–A18 uniquely select a bank.

1. See Table 1 on page 9 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth , fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.
5. Unless otherwise noted, address bits A20–A11 are don’t cares for unlock and command cycles, unless SA or PA is required.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to the read mode (o r to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect

mode, or if DQ5 goes high (while the bank is providing status information). Table 13. S29JL032J Command Definitions

90 XXX 00

55 SA 30

Document Number: 002-00857 Rev. *G Page 34 of 61 S29JL032J 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or Secured Silicon Region factory protect information. Data bits DQ15–DQ8 are don’t care. While reading the autoselect addresses, the bank address must be the same until a reset command is given. See Autoselect Command Sequence on page 28 for more information. 9. For models 01, 02, the device ID must be r ead across the fourth, fifth, and sixth cycles. 10. The data is 82h for factory locked, 42h for customer locked, and 02h for not factory/customer locked. 11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. 17. Additional sector erase commands during the time-out period after an initial sector erase are one cycle long and identical to the sixth cycle of the sector erase command sequence (SA / 30). 11. Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 on page 38 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/ BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed.

11.1 DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 3 ms, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ8 (DQ7–DQ0 for x8-only device) while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on successive read cycles. Table 14 on page 38 shows the outputs for Data# Polling on DQ7. Figure 11.1 on page 35 shows the Data# Polling algorithm. Figure 17.9 on page 50 shows the Data# Polling timing diagram.

Document Number: 002-00857 Rev. *G Page 35 of 61 S29JL032J Figure 11.1 Data# Polling Algorithm Notes: 1. VA = Valid address for programming. During a sector erase operat ion, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

11.2 RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 14 on page 38 shows the outputs for RY/BY#. When DQ5 is set to “1”, RY/BY# will be in the BUSY state, or “0”.

11.3 DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. $1å å$ATA 9ES $1å å.O 9ES 9ES &!), 0!33 2EADå$1n$1 !DDRå å6! 2EADå$1n$1 !DDRå å6! $1å å$ATA 34!24

Document Number: 002-00857 Rev. *G Page 36 of 61 S29JL032J During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 3 ms, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase- suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 34). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Figure 11.2 Toggle Bit Algorithm Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. START No Yes Yes DQ5 = 1?No Yes Toggle Bit = Toggle? No Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Toggle Bit = Toggle? Read Byte Twice (DQ7–DQ0) Address = VA Read Byte (DQ7–DQ0) Address =VA Read Byte (DQ7–DQ0) Address =VA

Document Number: 002-00857 Rev. *G Page 37 of 61 S29JL032J

11.4 DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase- suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 14 on page 38 to compare outputs for DQ2 and DQ6. Figure 11.2 on page 36 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 37 explains the algorithm. See also DQ6: Toggle Bit I on page 35. Figure 17.10 on page 50 shows the toggle bit timing diagram. Figure 17.11 on page 51 shows the differences between DQ2 and DQ6 in graphical form.

11.5 Reading Toggle Bits DQ6/DQ2

Refer to Figure 11.2 on page 36 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 11.2 on page 36).

11.6 DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a sp ecified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” The RDY/BSY# pin will be in the BUSY state under this condition. Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).

11.7 DQ3: Sector Erase Timer

monitor DQ3. See also Sector Erase Command Sequence on page 30. might not have been accepted. Table 14 shows the status of DQ3 relative to the other status bits.

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more
2. DQ7 and DQ2 require a valid address when reading status informati on. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array

data if the system addresses a non-busy bank. Table 14. Write Operation Status

Document Number: 002-00857 Rev. *G Page 40 of 61 S29JL032J 13. Operating Ranges Industrial (I) Devices Ambient Temperature (TA) –40°C to +85°C VCC Supply Voltages VCC for standard voltage range 2.7V to 3.6V Operating ranges define those limits between which the functionality of the device is guaranteed. 14. DC Characteristics

14.1 CMOS Compatible

Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max 1.0 µA ILIT A9 and RESET# Input Load Current VCC = VCC max, OE# = VIH; A9 or RESET# = 12.5V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max, OE# = VIH 1.0 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5V 35 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

CE# = VIL, OE# = VIH, Word Mode ICC2 VCC Active Write Current (Notes 2, 3)C E # = V IL, OE# = VIH, WE# = VIL 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC 0.3V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS 0.3V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC  0.3V; VIL = VSS 0.3V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (Note 2) CE# = VIL, OE# = VIH, 1M H z Byte 21 45 mA Word 21 45 ICC7 VCC Active Read-While-Erase Current (Note 2) CE# = VIL, OE# = VIH, 1M H z Byte 21 45 mA Word 21 45 ICC8 VCC Active Program-While-Erase- Suspended Current (Notes 2, 5) CE# = VIL, OE# = VIH 17 35 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/ Unprotect and Program Acceleration VCC = 3.0V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0V  10% 8.5 12.5 V VOL Output Low Voltage I OL = 2.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 x V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC–0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 1.8 2.0 2.5 V

Document Number: 002-00857 Rev. *G Page 41 of 61 S29JL032J 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested.

14.2 Zero-Power Flash

Figure 14.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Note: Addresses are switching at 1 MHz 0 500 1000 1500 2000 2500 3000 3500 4000 Supply Current in mA Time in ns

Document Number: 002-00857 Rev. *G Page 42 of 61 S29JL032J Figure 14.2 Typical ICC1 vs. Frequency Note: T = 25°C 1 234 5 Frequency in MHz Supply Current in mA 2.7V 3.6V

Document Number: 002-00857 Rev. *G Page 44 of 61 S29JL032J 17. AC Characteristics

17.1 Read-Only Operations

Notes: 1. Not 100% tested. 2. See Figure 15.1 on page 43 and Table 15 on page 43 for test specifications 3. Measurements performed by placing a 50 ohm te rmination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. Figure 17.1 Read Operation Timings Parameter Description Test Setup Speed Options JEDEC Std. 60 70 Unit tAVAV tRC Read Cycle Time (Note 1) Min 60 70 ns tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 60 70 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 60 70 ns tGLQV tOE Output Enable to Output Delay Max 25 30 ns tEHQZ tDF Chip Enable to Output High-Z (Notes 1, 3) Max 16 ns tGHQZ tDF Output Enable to Output High-Z (Notes 1, 3) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 5 10 ns tOH tCE Outputs WE# Addresses CE# OE# HIGH-Z Output Valid HIGH-Z Addresses Stable tRC tACC tOEH tRH tOE tRH

0 VRY/BY#

RESET# tDF

Document Number: 002-00857 Rev. *G Page 45 of 61 S29JL032J

17.2 Hardware Reset (RESET#)

Note: Not 100% tested. Figure 17.2 Reset Timings Parameter Description All Speed Options UnitJEDEC Std tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 35 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 35 µs tRB RY/BY# Recovery Time Min 0 ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB

Document Number: 002-00857 Rev. *G Page 46 of 61 S29JL032J

17.3 Word/Byte Conf iguration (BYTE#)

Figure 17.3 BYTE# Timings for Read Operations Parameter Speed Options JEDEC Std. Description 60 70 Unit tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns tFLQZ BYTE# Switching Low to Output HIGH-Z Max 16 ns tFHQV BYTE# Switching High to Output Active Max 60 70 ns DQ15 Output Data Output (DQ7–DQ0) CE# OE# BYTE# tELFL DQ14–DQ0 Data Output (DQ14–DQ0) DQ15/A-1 Address Input tFLQZ BYTE# Switching from word to byte mode DQ15 Output Data Output (DQ7–DQ0) BYTE# tELFH DQ14–DQ0 Data Output (DQ14–DQ0) DQ15/A-1 Address Input tFHQV BYTE# Switching from byte to word mode

Document Number: 002-00857 Rev. *G Page 47 of 61 S29JL032J Figure 17.4 BYTE# Timings for Write Operations Note: Refer to the table in Erase and Program Operations on page 47 for tAS and tAH specifications.

17.4 Erase and Prog ram Operations

Notes: 1. Not 100% tested. 2. See Data Integrity on page 54 for more information. Parameter tAVAV tWC Write Cycle Time (Note 1) Min 60 70 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 12 ns tWLAX tAH Address Hold Time Min 35 35 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 35 40 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 25 30 ns tWHDL tWPH Write Pulse Width High Min 25 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 6 µs Word Typ 6 tWHWH1 tWHWH1 Accelerated Programming Operation, Byte or Word (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns tESL Erase Suspend Latency Max 35 µs CE# WE# BYTE# The falling edge of the last WE# signal tHOLD (tAH) tSET (tAS)

Document Number: 002-00857 Rev. *G Page 51 of 61 S29JL032J Figure 17.11 DQ2 vs. DQ6 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.

17.5 Temporary Sector Unprotect

Note: Not 100% tested. Figure 17.12 Temporary Sector Unprotect Timing Diagram Parameter Description All Speed OptionsJEDEC Std Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min 4 µs Enter Erase Erase Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Read EraseWE# DQ6 DQ2 Erase Complete Erase Suspend Suspend Program Resume Embedded Erasing RESET# tVIDR VID VSS, VIL, or VIH VID VSS, VIL, or VIH CE# WE# RY/BY# tVIDR tRSP Program or Erase Command Sequence tRRB

Document Number: 002-00857 Rev. *G Page 52 of 61 S29JL032J Figure 17.13 Sector/Sector Block Protect and Unprotect Timing Diagram Note: *For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0

17.6 Alternate CE# Controlled Erase and Program Operations

Notes: 1. Not 100% tested. 2. See Data Integrity on page 54 for more information. Parameter Speed Options JEDEC Std. Description 60 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 60 70 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 35 35 ns tDVEH tDS Data Setup Time Min 30 30 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 25 35 ns tEHEL tCPH CE# Pulse Width High Min 25 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 6 µs Word Typ 6 tWHWH1 tWHWH1 Accelerated Programming Operation, Byte or Word (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec Sector Group Protect: 150 µs Sector Group Unprotect: 15 ms 1 µs RESET# SA, A6, A1, A0 Data CE# WE# OE# 60h 60h 40h Valid* Valid* Valid* Status Sector Group Protect/Unprotect Verify VID VIH

Document Number: 002-00857 Rev. *G Page 53 of 61 S29JL032J Figure 17.14 Alternate CE# Controlled Write (Erase/Program) Operation Timings Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. D OUT is the data written to the device. 4. Waveforms are for the word mode. tGHEL tWS OE# CE# WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# D OUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase tBUSY

18.1 Erase Endurance

1. Each write command to a non-volatile register causes a PE cycle on the entire non-volatile register array.

18.2 Data Retention

Table 16. Erase Endurance Table 17. Data Retention

Document Number: 002-00857 Rev. *G Page 55 of 61 S29JL032J 19. Erase and Programming Performance Notes: 1. Typical program and erase times assume the following conditions: 25°C, V CC = 3.0V, 100,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90°C, V CC = 2.7V, 1,000,000 cycles. 3. In the pre-programming step of the Embedded Erase al gorithm, all bytes are programmed to 00h before erasure. 4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 on page 33 for further information on command definitions. 5. The device has a minimum program and erase cycle endurance of 100,000 cycles per sector. 20. Pin Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 5 sec Excludes 00h programming prior to erasure (Note 3)Chip Erase Time 39 sec Byte Program Time 6 80 µs Excludes system level overhead (Note 4)Word Program Time 6 80 µs Accelerated Byte/Word Program Time 4 70 µs Parameter Symbol Parameter Description Test Setup Max Unit CIN Input Capacitance (applies to A20-A0, DQ15-DQ0) V IN = 0 8.5 pF COUT Output Capacitance (applies to DQ15-DQ0, RY/BY#) V OUT = 0 5.5 pF CIN2 Control Pin Capacitance (applies to CE#, WE#, OE#, WP#/ACC, RESET#, BYTE#) VIN = 0 12 pF

Document Number: 002-00857 Rev. *G Page 56 of 61 S29JL032J 21. Physical Dimensions

21.1 TS 048—48-Pin Standard TSOP

3664 \\ f16-038.10 \\ 11.6.7 PACKAGE TS/TSR 48 JEDEC MO-142 (D) DD SYMBOL MIN NOM MAX A --- --- 1.20 A1 0.05 --- 0.15 A2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 E 11.90 12.00 12.10 e 0.50 BASIC L 0.50 0.60 0.70 Θ 0˚ --- 8 R 0.08 --- 0.20 N4 8 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1982) 2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). 3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK. 4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE. 6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm (0.0028"). 7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE. 9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

Document Number: 002-00857 Rev. *G Page 57 of 61 S29JL032J

21.2 VBK048—48-Pin FBGA

g1001.2 \\ f16-038.25 \\ 07.13.10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. PACKAGE VBK 048 JEDEC N/A 8.15 mm x 6.15 mm NOM PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.00 OVERALL THICKNESS A1 0.18 --- --- BALL HEIGHT D 8.15 BSC. BODY SIZE E 6.15 BSC. BODY SIZE D1 5.60 BSC. BALL FOOTPRINT E1 4.00 BSC. BALL FOOTPRINT MD 8 ROW MATRIX SIZE D DIRECTION ME 6 ROW MATRIX SIZE E DIRECTION N 48 TOTAL BALL COUNT φb 0.33 --- 0.43 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT --- DEPOPULATED SOLDER BALLS

Document Number: 002-00857 Rev. *G Page 58 of 61 S29JL032J 22. Document History Document Title:S29JL032J 32 Mbit (4M x 8-Bit/2M x 16-Bit), 3 V, Simultaneous Read/Write Flash Document Number: 002-00857 Rev. ECN No. Orig. of Change Submission Date Description of Change ** - RYSU 01/27/2010 Spansion Publication Number: S29JL032J_00 Initial release *A - RYSU 06/15/2010 Global Changed all references to typical Sector Erase time from 0.4 sec to 0.5 sec. Changed all references to “Secured Silicon Sector” to “Secured Silicon Region”. Corrected spelling and grammatical errors. Product Selector Guide Corrected Standard Voltage Range of 70 ns Connection Diagrams Added 48-ball FBGA connection diagram. Pin Description Changes “21 Addresses” to “21 Address Pins”. Added clarification that CE#, OE#, WE#, BYTE#, and RY/BY# are Active Low.

Ordering Information

Added FBGA ordering option. Added Low-halogen, Pb-free ordering option. Added valid combinations for FBGA. Word/Byte Configuration Added clarification that BYTE# must be connected to either the system VCC or ground. Secured Silicon Region Added clarification that D7 is the Secured Silicon Factory Indicator Bit. In Figure Secured Silicon Sector Protect Verify, corrected “Write reset command” to “Secured Silicon Region exit command”. Command Definitions Corrected “Writing specific addresses and data commands or sequences” to “Writing specific addresses and data sequences”. Absolute Maximum Ratings Corrected “A9, OE#, and RESET#” to “A9 and RESET#”. DC Characteristics Removed OE# from ILIT parameter description. Removed OE# = 12.5V from ILIT test conditions. Added 1 MHz to ICC6 and ICC7 test conditions. Removed Note 1 from ICC6 and ICC7. Test Conditions Update Figure “Test Setup” to reflect correct test setup. Added Note 1 to clarify that input rise and fall times are 0-100%. Erase and Programming Performance Changed Chip Erase typical time from 28 sec to 39 sec. Removed Note 5. Physical Dimensions Added VBK048 package outline drawing.

Document Number: 002-00857 Rev. *G Page 59 of 61 S29JL032J *B - RYSU 08/25/2010 Global Updated the data sheet designation from Advanced Information to Preliminary. Corrected spelling, capitalization, and grammatical errors. Simultaneous Read/Write Operations with Zero Latency Clarified that JL032J can be configured as either a top or bottom boot sector device, not both. Corrected typo in valid combinations table from “…, 41, 41” to “…, 41, 42”. Clarified that Note 1 applies to the Packing Type column. RESET#: Hardware Reset Pin Changed “Refer to AC Characteristics on page 48” to “Refer to Hardware Reset (RESET#) on page 49”. Secured Silicon Region Clarified the Secured Silicon Indicator Bit data based on factory and customer lock status. Removed forward looking statements regarding factory locking features as they are supported in this device. Common Flash Memory Interface (CFI) Clarified that once in the CFI query mode, the system must write the reset command to return to reading array data. Erase Suspend/Erase Resume Commands Added clarification that “It is not recommended to program the Secured Silicon Region after an erase suspend, as proper device functionality cannot be guaranteed.” Erase and Programming Performance Added Note 5 regarding minimum program and erase cycle endurance. Pin Capacitance Changed section title from "TSOP Pin Capacitance" to "Pin Capacitance". Updated values to reflect maximum capacitances for both TSOP and BGA. Removed typical capacitance values. Added specific pin clarifications to parameter descriptions. Physical Dimensions Updated the VBK048 package outline drawing. Document Title:S29JL032J 32 Mbit (4M x 8-Bit/2M x 16-Bit), 3 V, Simultaneous Read/Write Flash Document Number: 002-00857 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00857 Rev. *G Page 60 of 61 S29JL032J *C - RYSU 04/07/2011 Global Updated the data sheet designation from Preliminary to Full Production (no designation on document). Distinctive Characteristics Corrected "Top and bottom boot sectors in the same device" to "Top and bottom boot sector configurations available". RESET#: Hardware Reset Pin Added warning that keeping CE# at VIL from power up through the first reset could cause erroneuous data on the first read. Reset Command Clarified that during an embedded program or erase, if DQ5 goes high then RY/BY# will remain low until a reset is issued. Hardware Reset (RESET#) Added note to the “Reset Timings” figure clarifying that CE# should only go low after RESET# has gone high. *D - RYSU 08/24/2011 RESET#: Hardware Reset Pin Removed warning that keeping CE# at VIL from power up through the first reset could cause erroneuous data on the first read. Command Definitions Table Added Note 17 to clarify additional sector erase commands during time-out period. Sector Erase Command Sequence Added clarification regarding additional sector erase commands during time-out period. Hardware Reset (RESET#) Removed note to the “Reset Timings” figure clarifying that CE# should only go low after RESET# has gone high. Physical Dimensions Package drawings updated to latest version. *E - RYSU 12/16/2011 Global Corrected all references in the text to the sector erase time-out period from 80 μs to 50 μs. Word/Byte Configuration Removed the statement “Please note that the BYTE# pin must be connected to either the system VCC or ground.” *F 5034593 RYSU 12/08/2015 Updated to Cypress template. *G 5742461 AESATMP7/ SZZX 05/19/2017 Updated Cypress Logo and Copyright. Updated cycling endurance and added Data Integrity section. Corrected typo in the sector address table (SA54 and SA55). Document Title:S29JL032J 32 Mbit (4M x 8-Bit/2M x 16-Bit), 3 V, Simultaneous Read/Write Flash Document Number: 002-00857 Rev. ECN No. Orig. of Change Submission Date Description of Change

Document Number: 002-00857 Rev. *G Revised May 19, 2017 Page 61 of 61 © Cypress Semiconductor Corporation, 2010-2017. This document is the property of Cypress Semiconductor Corporation and its subs idiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusiv e, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IM PLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resusci tation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whol e or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintend ed Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. S29JL032J Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless PSoC® Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support