S25FL032P

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Technical content

Datasheet sections

• 5.1 Valid Combinations
• 7.1 Byte or Page Programming
• 7.2 Quad Page Programming
• 7.3 Dual and Quad I/O Mode
• 7.4 Sector Erase / Bulk Erase
• 7.5 Monitoring Write Operations
• 7.6 Active Power and Standby Power Modes
• 7.7 Status Register
• 7.8 Configuration Register
• 7.9 Data Protection Modes
• 7.10 Hold Mode (HOLD#)
• 7.11 Accelerated Programming Op eration
• 9.1 Read Data Bytes (READ)
• 9.2 Read Data Bytes at Higher Speed
• 9.3 Dual Output Read Mode (DOR)
• 9.4 Quad Output Read Mode (QOR)
• 9.5 DUAL I/O High Performance Read
• 9.6 Quad I/O High Performance Read
• 9.7 Read Identification (RDID)
• 9.8 Read-ID (READ_ID)
• 9.9 Write Enable (WREN)
• 9.10 Write Disable (WRDI)
• 9.11 Read Status Register (RDSR)
• 9.12 Read Configuration Register (RCR)
• 9.13 Write Registers (WRR)
• 9.14 Page Program (PP)
• 9.15 QUAD Page Program (QPP)
• 9.16 Parameter Sector Erase (P4E, P8E)
• 9.17 Sector Erase (SE)
• 9.18 Bulk Erase (BE)
• 9.19 Deep Power-Down (DP)
• 9.20 Release from Deep Power-D own (RES)
• 9.21 Clear Status Register (CLSR)
• 9.22 OTP Program (OTPP)
• 9.23 Read OTP Data Bytes (OTPR)
• 10.1 Programming OTP Address Space
• 10.2 Reading OTP Data
• 10.3 Locking OTP Regions
• 14.1 Absolute Maximum Ratings
• 18.1 Capacitance
• 19.2 SO3 016 — 16-pin Wide Plastic Small
• 19.3 UNE008 — USON 8-contact (5 x 6 mm)
• 19.4 WNF008 — WSON 8-contact (6 x 8 mm)
• 19.5 FAB024 — 24-ball Ball Grid Array
• 19.6 FAC024 — 24-ball Ball Grid Array

32-Mbit 3.0 V Flash Memory Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-00650 Rev. *L Revised May 19, 2017 This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede S25FL032P. These are the factory-recommended migration paths. Refer to the S25FL-L Family datasheets for specifications and ordering information. Distinctive Characteristics Architectural Advantages  Single power supply operation – Full voltage range: 2.7 V to 3.6 V read and write operations  Memory architecture – Uniform 64-KB sectors – Top or bottom parameter block (two 64-KB sectors (top or bottom) broken down into 16 4-KB sub-sectors each) – 256-byte page size – Backward compatible with the S25FL032A device  Program – Page Program (up to 256 bytes) in 1.5 ms (typical) – Program operations are on a page by page basis – Accelerated programming mode via 9-V W#/ACC pin – Quad Page Programming  Erase – Bulk erase function – Sector erase (SE) command (D8h) for 64-KB sectors – Sub-sector erase (P4E) command (20h) for 4-KB sectors – Sub-sector erase (P8E) command (40h) for 8-KB sectors  Cycling endurance – 100,000 cycles per sector typical  Data retention – 20 years typical  Device ID – JEDEC standard two-byte electronic signature – RES command one-byte electronic signature for backward compatibility  One time programmable (OTP) area for permanent, secure identification; can be programmed and locked at the factory or by the customer  Common Flash Interface (CFI) compliant: allows host system to identify and accommodate multiple flash devices  Process technology – Manufactured on 0.09 m MirrorBit® process technology  Package option – Industry Standard Pinouts – 8-pin SO package (208 mils) – 16-pin SO package (300 mils) – 8-contact USON package (5  6 mm) – 8-contact WSON package (6  8 mm) – 24-ball BGA 6  8 mm package, 5  5 pin configuration – 24-ball BGA 6  8 mm package, 6  4 pin configuration Performance Characteristics  Speed – Normal READ (Serial): 40-MHz clock rate – FAST_READ (Serial): 104-MHz clock rate (maximum) – DUAL I/O FAST_READ: 80-MHz clock rate or

20 MB/s effective data rate

– QUAD I/O FAST_READ: 80 MHz clock rate or

40 MB/s effective data rate

 Power saving standby mode – Standby Mode 80 A (typical) – Deep Power-Down Mode 3 A (typical) Memory Protection Features  Memory protection – W#/ACC pin works in conjunction with Status Register Bits to protect specified memory areas – Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 2 of 60 S25FL032P General Description The S25FL032P is a 3.0 V (2.7 V to 3.6 V), single-power-supply Flash memory device. The device consists of 64 uniform 64-KB sectors with the two (top or bottom) 64-KB sectors further split up into thirty-two 4-KB sub sectors. The S25FL032P device is fully backward compatible with the S25FL032A device. The device accepts data written to Serial Input (SI) and outputs data on Serial Output (SO). The devices are designed to be programmed in-system with the standard system 3.0-V VCC supply. The S25FL032P device adds the following high-performance features using five new instructions:  Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz  Quad Output Read using SI, SO, W#/ACC, and HOLD# pins as output pins at a clock rate of up to 80 MHz  Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz  Quad I/O High Performance Read using SI, SO, W#/ACC, and HOLD# pins as input and output pins at a clock rate of up to

80 MHz

 Quad Page Programming using SI, SO, W#/ACC, and HOLD# pins as input pins to program data at a clock rate of up to 80 MHz The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0-V power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device requires a high voltage supply to the W#/ACC pin to enable the Accelerated Programming mode. The S25FL032P device also offers a One-Time Programmable area (OTP) of up to 128 bits (16 bytes) for permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or OTPR instructions. Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 4 of 60 S25FL032P 1. Block Diagram SRAM PS Logic Array - L Array - R RD DATA PATH IO X D E C CS# SCK SI / IO0 SO / IO1 GND HOLD# / IO3 VCC W# / ACC / IO2 Not Recommended for New Design

Figure 1. 16-pin Plastic Small Outline Package (SO) Figure 2. 8-pin Plastic Small Outline Package (SO) Figure 3. 8-contact USON (5 x 6 mm) Package SS) is possible, provided PCB routing ensures 0mV difference between voltage at the USON GND (V SS) lead and the central exposed pad. Figure 4. 8-contact WSON Package (6 x 8 mm) SS) is possible, provided PCB routing ensures 0mV difference between voltage at the WSON GND (V SS) lead and the central exposed pad.

9 W#/ACC/IO2

8 CS#

1. Input/Output Descriptions

Table 1. Input/Output Descriptions input pin in Dual and Quad I/O, and Quad Page Program modes. program data on SI on the rising edge of SCK. Functions as an output pin in Dual and Quad I/O mode. edge of SCK. Triggers output on SO after the falling edge of SCK. at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low. Functions as an output pin in Quad I/O mode. as an output pin in Quad I/O mode.

Document Number: 002-00650 Rev. *L Page 8 of 60 S25FL032P 5. Ordering Information The ordering part number is formed by a valid combination of the following: S25FL 032 P 0X M F I 00 1 Packing Type 0 = Tray 1 = Tube 3 = 13” Tape and Reel Model Number (Additional Ordering Options) 03 = 6 x 4 pin configuration BGA package 02 = 5 x 5 pin configuration BGA package 01 = 8-pin SO package / 8-contact USON package 00 = 16-pin SO package / 8-contact WSON package Temperature Range I = Industrial (–40°C to +85°C) V = Automotive In-cabin (–40°C to +105°C) A = Automotive, AEC-Q100 Grade 3 (–40°C to +85°C) B = Automotive, AEC-Q100 Grade 2 (–40°C to +105°C) Package Materials F = Lead (Pb)-free H = Low-Halogen, Lead (Pb)-free Package Type M = 8-pin / 16-pin SO package N = 8-contact USON / WSON package B = 24-ball BGA 6 x 8 mm package, 1.00 mm pitch Speed 0X = 104 MHz Device Technology P = 0.09 µm MirrorBit ® Process Technology Density 032 = 32 Mbit Device Family S25FL Cypress Memory 3.0 V-only, Serial Peripheral Interface (SPI) Flash Memory Not Recommended for New Design

5.1 Valid Combinations

Table 2 lists the valid combinations configurations planned to be supported in volume for this device. combinations and to check on newly released combinations. Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products. Table 2. S25FL032P Valid Combinations Table 3. S25FL032P Valid Combinations — Automotive Grade / AEC-Q100

Document Number: 002-00650 Rev. *L Page 11 of 60 S25FL032P 7. Device Operations All Cypress SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device that supports an inactive clock while CS# is held low.

7.1 Byte or Page Programming

Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation. Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation.

7.2 Quad Page Programming

The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed using 4 pins as inputs at the same time, thus effectively quadrupling the data transfer rate, compared to the Page Program (PP) instruction. The Write Enable Latch (WEL) bit must be set to a 1 using the Write Enable (WREN) command prior to issuing the QPP command.

7.3 Dual and Quad I/O Mode

The S25FL032P device supports Dual and Quad I/O operation when using the Dual/Quad Output Read Mode and the Dual/Quad I/O High Performance Mode instructions. Using the Dual or Quad I/O instructions allows data to be transferred to or from the device at two to four times the rate of standard SPI devices. When operating in the Dual or Quad I/O High Performance Mode (BBh or EBh instructions), data can be read at fast speed using two or four data bits at a time, and the 3-byte address can be input two or four address bits at a time.

7.4 Sector Erase / Bulk Erase

The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. While bits can be individually programmed from 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level. In addition to the 64-KB Sector Erase (SE), the S25FL032P device also offers 4-KB Parameter Sector Erase (P4E) and 8-KB Parameter Sector Erase (P8E).

7.5 Monitoring Write Operations Using the Status Register

The host system can determine when a Write Register, program, or erase operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. In addition, the S25FL032P device offers two additional bits in the Status Register (P_ERR, E_ERR) to indicate whether a Program or Erase operation was a success or failure.

7.6 Active Power and Standby Power Modes

The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but may still be in the Active Power mode until all program, erase, and Write Registers operations have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB. The Deep Power-Down (DP) command provides additional data protection against inadvertent signals. After writing the DP command, the device ignores any further program or erase commands, and reduces its power consumption to IDP. Not Recommended for New Design

7.7 Status Register

The Status Register contains the status and control bits that can be read or set by specific commands (see Table 10 on page 18).  Write In Progress (WIP): Indicates whether the device is performing a Write Registers, program or erase operation.  Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.  Erase Error (E_ERR): The Erase Error Bit is used as an Erase operation success and failure check.  Program Error (P_ERR): The Program Error Bit is used as an program operation success and failure check.

7.8 Configuration Register

configurations and security features of the device. FREEZE bit is set to ‘0’, then the other bits of the Configuration Register, including FREEZE bit, can be written to. functionality does not work when the device is set in Quad mode. bottom of the array. Note that once this bit is set to a '1', it cannot be changed back to '0'. the BP2-0 bits in the Status Register are non-volatile. Note that once this bit is set to a '1', it cannot be changed back to '0'. protection is defined to start from the bottom of the array. Note that once this bit is set to a '1', it cannot be changed back to '0'. cannot utilize the Parameter sectors if they are protected. The following matrix shows the recommended settings. Table 4. Suggested Cross Settings

11 Parameter Sectors - Top of Array (high address)

(Default) indicates the value of each Configuration Register bit set upon initial factory shipment.

7.9 Data Protection Modes

by Status Register bits BP2:BP0. is a multiple of eight before executing them. Table 5. Configuration Register Table

3 BPNV Configures BP2-0 bits in the Status Register 1 = Volatile

0 FREEZE Locks BP2-0 bits in the Status Register 1 = Enabled

7.10 Hold Mode (HOLD#)

erase operation that is currently in progress. does not occur while SCK is low, the Hold mode begins after the next falling edge of SCK (non-standard use). occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-standard use) See Figure 9. The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the Hold mode. when device communication is resumed, HOLD# must be held high, followed by driving CS# low. Note: The HOLD Mode feature is disabled during Quad I/O Mode. Table 6. TBPROT = 0 (Starts Protection from TOP of Array) Table 7. TBPROT=1 (Starts Protection from BOTTOM of Array)

Figure 9. Hold Mode Operation

7.11 Accelerated Programming Operation

addition, the W#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Note: The ACC function is disabled during Quad I/O Mode.

the memory array of the Flash device. Sector SA0 is split up into sub-sectors SS0 - SS15 (dark gray shading). Sector SA1 is split up into sub-sectors SS16 - SS31(light gray shading). Table 8. S25FL032P Sector Address Table TBPARM=0

Sector SA62 is split up into sub-sectors SS0 - SS15 (dark gray shading). Sector SA63 is split up into sub-sectors SS16 - SS31 (light gray shading). Table 9. S25FL032P Sector Address Table TBPARM=1

nothing, depending on the command. CS# must be driven high after the last bit of the command sequence has been written. sequence on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation. pulses after CS# is driven low is an exact multiple of eight. the operation uninterrupted. The instruction set is listed in Table 10. Table 10. Instruction Set

Table 10. Instruction Set (Continued)

9.1 Read Data Bytes (READ)

are output serially on SO at a frequency fR, on the falling edge of SCK. reverts to 00000h, allowing the read sequence to continue indefinitely. issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 10. Read Data Bytes (READ) Command Sequence

9.2 Read Data Bytes at Higher Speed (FAST_READ)

at that address, are output serially on SO at a frequency fC, on the falling edge of SCK. any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. address counter reverts to 000000h, allowing the read sequence to continue indefinitely. command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 11. Read Data Bytes at Higher Speed (FAST_READ) Command Sequence

9.3 Dual Output Read Mode (DOR)

data transfer rate compared to the FAST_READ instruction. reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. Figure 12. Dual Output Read Instruction Sequence

9.4 Quad Output Read Mode (QOR)

of the FAST_READ instruction. frequency fC on the falling edge of SCK. reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the S25FL device.

24 Bit

Figure 13. Quad Output Read Instruction Sequence

9.5 DUAL I/O High Performa nce Read Mode (DIOR)

memory contents, at the address that is given, are shifted out two bits at a time through IO0 (SI) and IO1 (SO). byte of data is output. The entire memory array can therefore be read with a single DUAL I/O High Performance Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely.

1. During the Dual I/O High Performance Instruction Sequence, if the Mode bits are any value other than Axh, then the next

time CS# is raised high and then asserted low, the device will be released from Dual I/O High Performance Read mode.

1. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 and

It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. during data output to terminate a read operation.

Figure 14. DUAL I/O High Performance Read Instruction Sequence Figure 15. Continuous Dual I/O High Performance Read Instruction Sequence

9.6 Quad I/O High Performa nce Read Mode (QIOR)

HOLD#/IO3), at a maximum frequency of 80 MHz. bits at a time through IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#). byte of data is output. The entire memory array can therefore be read with a single Quad I/O High Performance Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. shown in Figure 17, thus eliminating eight cycles for the instruction sequence.

1. During the Quad I/O High Performance Instruction Sequence, if the Mode bits are any value other than Axh, then the next

time CS# is raised high and then asserted low the device will be released from Quad I/O High Performance Read mode.

1. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0, IO1,

It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. during data output to terminate a read operation. Figure 16. QUAD I/O High Performance Instruction Sequence Figure 17. Continuous QUAD I/O High Performance Instruction Sequence

9.7 Read Identification (RDID)

Cypress devices, it is 01h. The device identification (2 bytes) and CFI bytes are assigned by the device manufacturer. See Table 11 on page 25 for device ID data. held low with a clock input. The RDID command sequence is shown in Figure 18 and Table 10 on page 18. any time during data output (for example, while reading the extended CFI bytes), also terminates the RDID operation. the operation uninterrupted. Figure 18. Read Identification (RDID) Command Sequence and Data-Out Sequence

1. Byte 0 is Manufacturer ID of Cypress.
2. Byte 3 is Extended Device Information String Length, to indicate how many Extended Device Information bytes will follow.
3. Bytes 4, 5 and 6 are Cypress reserved (do not use).
4. For Bytes 07h-0Fh and 3Dh-3Fh, the data will be read as 0xFF.
5. Bytes 10h-50h are factory programmed per JEDEC standard.

Table 11. Manufacturer & Device ID - RDID (JEDEC 9Fh)

Table 12. Product Group CFI Query Identification String Table 13. Product Group CFI System Interface String Table 14. Product Group CFI Device Geometry Definition

Table 15. Product Group CFI Primary Vendor-Specific Extended Query Table 14. Product Group CFI Device Geometry Definition (Continued)

particular part numbers. Refer to Section 18., AC Characteristics on page 49 for typical timeout specifications.

9.8 Read-ID (READ_ID)

Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC Read Identification (RDID) commands. by a low to high transition on CS# chip select input pin. Figure 19. Read-ID (RDID) Command Timing Diagram Table 15. Product Group CFI Primary Vendor-Specific Extended Query (Continued) Table 16. READ_ID Data-Out Sequence

9.9 Write Enable (WREN)

command. The host system must first drive CS# low, write the WREN command, and then drive CS# high. Figure 20. Write Enable (WREN) Command Sequence

9.10 Write Disable (WRDI)

Figure 21. Write Disable (WRDI) Command Sequence

9.11 Read Status Register (RDSR)

Figure 22. Read Status Register (RDSR) Command Sequence The following describes the status and control bits of the Status Register. operation is in progress. This bit is a Read-only bit. Table 17. S25FL032P Status Register

7 SRWD Status Register Write Disable 1 = Protects when W#/ACC is low

6 P_ERR Programming Error Occurred 0 = No Error

5 E_ERR Erase Error Occurred 0 = No Error

4 BP2

2 BP0

1 WEL Write Enable Latch 1 = Device accepts Write Registers, program or erase commands

0 = Ready. Device is in standby mode and can accept commands.

in the Configuration register. The Block Protection (BP2, BP1, BP0) bits are written with the Write Registers (WRR) instruction. instructions. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed. condition of the BP2-0 bits is binary 000 (all 0s). is reset with the Clear Status Register (CLSR) command. set to a “1”, this bit is reset with the Clear Status Register (CLSR) command. Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write Protect (W#/ACC) signal. opcode is no longer accepted for execution. Note: The P_ERR and E_ERR bits will not be set to a 1 if the application writes to a protected memory area.

9.12 Read Configuration Register (RCR)

device is first shipped from the factory to the customer. Refer to Section 7.8 on page 12 for more details. Figure 23. Read Configuration Register (RCR) Instruction Sequence

9.13 Write Registers (WRR)

command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to writing the WRR command. Table 17 shows the status register bits and their functions. The host system must drive CS# low, then write the WRR command and the appropriate data byte on SI Figure 24. The WRR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be used for that purpose. pin must be driven to the logic low state during the entire duration of the sequence. Hardware Protected Mode (HPM). Table 18 shows that W#/ACC must be driven low and the SRWD bit must be 1 for this to occur. written to. As soon as the CS# chip select input pin is driven to the logic high state, the self-timed Write Registers cycle is initiated. Figure 24. Write Registers (WRR) Instruction Sequence – 8 data bits Figure 25. Write Registers (WRR) Instruction Sequence – 16 data bits

As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 6 on page 14. specified by BP2:BP0 (Software Protected Mode, or SPM). Note: HPM is disabled when the Quad I/O Mode is enabled (Quad bit = 1 in the Configuration Register). W# becomes IO2; therefore, HPM cannot be utilized.

9.14 Page Program (PP)

prior to writing the PP command. be driven low for the entire duration of the PP sequence. The command sequence is shown in Figure 26 and Table 10 on page 18. programmed at the requested addresses without having any effect on the other bytes in the same page. resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). (BP2:BP0) (see Table 6 on page 14). Table 18. Protection Modes

Figure 26. Page Program (PP) Command Sequence

9.15 QUAD Page Program (QPP)

functions of Quad Input Page Program are identical to standard Page Program. The QPP instruction sequence is shown below. Figure 27. QUAD Page Program Instruction Sequence

9.16 Parameter Sec tor Erase (P4E, P8E)

command is required prior to writing the Parameter Sector Erase commands. low for the entire duration of the P4E/P8E sequence. The command sequence is shown in Figure 28 and Table 10 on page 18. exact timing is not specified). erased properly if n or n+1 is a valid 4 KB parameter Sector; that is, if n is not a valid 4K parameter Sector, then it will not be erased. If n+1 is not a valid 4 KB parameter Sector, then it will not be erased. Figure 28. Parameter Sector Erase (P4E, P8E) Instruction Sequence

9.17 Sector Erase (SE)

prior to writing the SE command. (see Table 6 on page 14) is a valid address for the SE command. CS# must be driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 29 and Table 10 on page 18. device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). Figure 29. Sector Erase (SE) Command Sequence

9.18 Bulk Erase (BE)

BE sequence. The command sequence is shown in Figure 30 and Table 10 on page 18. device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). Figure 30. Bulk Erase (BE) Command Sequence

9.19 Deep Power-Down (DP)

lowest power consumption when the quickest return to device activity is required. DP sequence. The command sequence is shown in Figure 31 and Table 10 on page 18. Section 9.20 and Section 9.21). Figure 31. Deep Power-Down (DP) Command Sequence

9.20 Release from Deep Power-Down (RES)

in the Deep Power-Down mode, all commands except RES are ignored. sequence. The command sequence is shown in Figure 32 and Table 10 on page 18. standby mode after a delay of tRES (see Figure 25). In the standby mode, the device can execute any read or write command. Note: The RES command does not reset the Write Enable Latch (WEL) bit. Figure 32. Release from Deep Power-Down (RES) Command Sequence

9.20.1 Release from Deep Power-Down and Read Electronic Signature (RES)

offered it; however, the Electronic Signature should not be used for new designs, which should read the RDID data instead. with CS# low cause the device to output the Electronic Signature repeatedly. When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as previously described. operation continues uninterrupted. Figure 33. Release from Deep Power-Down and RES Command Sequence

3 Dummy Bytes

9.21 Clear Status Register (CLSR)

Figure 34. Clear Status Register (CLSR) Instruction Sequence

9.22 OTP Program (OTPP)

will be ignored. To program the OTP in bit granularity, the rest of the bits within the data byte can be set to “1”. in “Locking OTP Regions”). Subsequent OTP programming can be performed only on the unprogrammed bits (that is, “1” data). Note: The Write Enable (WREN) command must precede the OTPP command before programming of the OTP can occur. Figure 35. OTP Program Instruction Sequence

9.23 Read OTP Data Bytes (OTPR)

the starting address after the OTP address is at its maximum; instead, the data will be indeterminate. Figure 36. Read OTP Instruction Sequence

regions that can be individually locked. special ordered, Cypress can program (and lock) in a unique customer ID.  The thirty 16-byte and one 10-byte OTP regions are open for the customer usage. data cannot changed. The locking process is permanent and cannot be undone. commands to the normal address space.  The OTP Region is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.  The ACC function is not available when accessing the OTP Regions.

10.1 Programming OTP Address Space

operations outside the valid OTP address range will be ignored.

10.2 Reading OTP Data

valid OTP address range will yield indeterminate data. Table 19. ESN1 and ESN2

10.3 Locking OTP Regions

of OTP memory, as highlighted in Figure 37 and Figure 38. Figure 37. OTP Memory Map - Part 1

1. Bit 0 at address 0x100h locks ESN1 region.
2. Bit 1 at address 0x100h locks ESN2 region.
3. Bits 2-7 (“X”) are NOT programmable and will be ignored.

Figure 38. OTP Memory Map - Part 2

1. Bit 7 (“X”) at address 0x215h is NOT programmable and will be ignored.

Register and Configuration Register contains 00h (all bits are set to 0).

1. Program Acceleration via W#/ACC Pin

normal operation after a period of tWC. Figure 41. ACC Program Acceleration Timing Requirements Only Read Status Register (RDSR) and Page Program (PP) operation are allow when ACC is at (V HH). The W#/ACC pin is disabled during Quad I/O mode. Table 20. Power-Up / Power-Down Voltage and Timing Table 21. ACC Program Acceleration Specifications

1. Electrical Specifications

14.1 Absolute Maximum Ratings

1. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one seco nd.
2. Stresses above those listed under “Absolute Maximum Ratings” ma y cause permanent damage to the device. This is a stress rating only; functional operation of the

rating conditions for extended periods may affect device reliability. Figure 42. Maximum Negative Overshoot Waveform Figure 43. Maximum Positive Overshoot Waveform

Operating ranges define those limits between which functionality of the device is guaranteed. Table 22. Operating Ranges Table 23. DC Characteristics (CMOS Compatible)

Figure 44. AC Measurements I/O Waveform

0.8 VCC

0.2 VCC

0.7 VCC

0.3 VCC

0.5 VCC

Table 24. Test Specifications

Table 25. AC Characteristics Symbol (Notes) Parameter (Notes) Min.

1. Typical program and erase times assume the following condit ions: 25°C, VCC = 3.0 V; 10,000 cycles; checkerboard data pattern.
2. Under worst-case conditions of 85°C; V CC = 2.7 V; 100,000 cycles.
3. Acceleration mode (9 V ACC) only in Program mode, not Erase.
4. Only applicable as a constraint for WRR instruction when SRWD is set to a ‘1’.
5. t WH + tWL must be less than or equal to 1/fC.

18.1 Capacitance

1. Sampled, not 100% tested.
2. Test conditions T A = 25°C, f = 1.0 MHz.
3. For more information on pin capacit ance, please consult the IBIS models.

Figure 45. SPI Mode 0 (0,0) Input Timing Table 25. AC Characteristics (Continued) Symbol (Notes) Parameter (Notes) Min.

Document Number: 002-00650 Rev. *L Page 52 of 60 S25FL032P 19. Physical Dimensions

19.1 SOC008 wide — 8-pin Pl astic Small Outline Package (208-mils Body Width)

5.28 BSCD

0.51 2 0 1 0 N L e E 15° 0.76

5.28 BSC

8.00 BSC

1.36 REF

0.25 BSC

1.27 BSC

1.70 1.75 0.05 0.33 0.36 0.15 0.19 c b A 1.90 2.16 0.25 0.48 0.46 0.20 0.24 0-8° REF 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. 1. ALL DIMENSIONS ARE IN MILLIMETERS. NOTES: D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS 5. DATUMS A AND B TO BE DETERMINED AT DATUM H. 6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED 7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE 8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR LOWER RADIUS OF THE LEAD FOOT. IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY 0.25 mm FROM THE LEAD TIP. PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT THE PLASTIC BODY. PACKAGE LENGTH. SEATING PLANE. DIMENSIONS SYMBOL MIN. NOM. MAX. 002-15548 ** Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 53 of 60 S25FL032P

19.2 SO3 016 — 16-pin Wide Plastic Small Outline Packag e (300-mils Body Width)

0.33 C

0.25 M DCA - B

0.20 C A-B

0.10 C 0.10 C

0.10 C D

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. 1. ALL DIMENSIONS ARE IN MILLIMETERS. NOTES: D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS 5. DATUMS A AND B TO BE DETERMINED AT DATUM H. 6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED 7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE 8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR LOWER RADIUS OF THE LEAD FOOT. IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE h D N e b c E A 0.75

10.30 BSC

0.30 0.33 0.25 0.20

7.50 BSC

0.10 0.31 0.51 2.652.35 A2 2.05 2.55 b1 0.27 0.48 0.300.20c1 0.40L 1.27

1.40 REF

0 5° 15° 0 0° 2 - DIMENSIONS SYMBOL MIN. NOM. MAX. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY 0.25 mm FROM THE LEAD TIP. PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT THE PLASTIC BODY. PACKAGE LENGTH. SEATING PLANE. 002-15547 *A Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 54 of 60 S25FL032P

19.3 UNE008 — USON 8-contact (5 × 6 mm) No-Lead Package

BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE. MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED N IS THE TOTAL NUMBER OF TERMINALS. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. NOTES: MAX. PACKAGE WARPAGE IS 0.05mm. THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA. ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE. 1.27 BSC. 0.40

6.00 BSC

5.00 BSC

4.00 3.40 0.20 MIN. 0.50 0.02 0.60 K A D E b L ND N e 0.00 3.30 0.45 3.90 0.35 0.55 3.50 0.05 0.55 4.10 0.45 0.65 A3 0.20 REF DIMENSIONS SYMBOL MIN. NOM. MAX. BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS SLUG AS WELL AS THE TERMINALS. 002-18903 ** Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 55 of 60 S25FL032P

19.4 WNF008 — WSON 8-contact (6 × 8 mm) No-Lead Package

A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE. MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED N IS THE TOTAL NUMBER OF TERMINALS. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. NOTES: MAX. PACKAGE WARPAGE IS 0.05mm. THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA. ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE. 1.27 BSC. 0.40 4.80 5.80 0.75 0.02 0.50 A D E b L ND N e 0.00 5.70 0.70 4.70 0.35 0.45 5.90 0.05 0.80 4.90 0.45 0.55 DIMENSIONS SYMBOL MIN. NOM. MAX. BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS SLUG AS WELL AS THE TERMINALS. 0.20 MIN.K -0.00 0.15 002-18902 ** Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 56 of 60 S25FL032P

19.5 FAB024 — 24-ball Ball Gr id Array (6 x 8 mm) Package

METALLIZED MARK INDENTATION OR OTHER MEANS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. e REPRESENTS THE SOLDER BALL GRID PITCH. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.8. ALL DIMENSIONS ARE IN MILLIMETERS. PARALLEL TO DATUM C. NOTES: SD b eD eE ME N 0.35

0.00 BSC

1.00 BSC

0.40 0.45 MD E D A A1 0.20

4.00 BSC

• 1.20 SE 0.00 BSC DIMENSIONS SYMBOL MIN. NOM. MAX. "SE" = eE/2. 002-15534 ** Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 57 of 60 S25FL032P

19.6 FAC024 — 24-ball Ball Gr id Array (6 x 8 mm) Package

METALLIZED MARK INDENTATION OR OTHER MEANS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. e REPRESENTS THE SOLDER BALL GRID PITCH. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.8. ALL DIMENSIONS ARE IN MILLIMETERS. PARALLEL TO DATUM C. NOTES: SD b eD eE ME N 0.35

0.50 BSC

0.40 0.45 MD E D A A1 0.25

3.00 BSC

• 1.20 SE 0.50 BSC DIMENSIONS SYMBOL MIN. NOM. MAX. "SE" = eE/2. 002-15535 ** Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 58 of 60 S25FL032P 20. Revision History Document History Page Document Title: S25FL032P, 32-Mbit 3.0 V Flash Memory Document Number: 002-00650 Rev. ECN No. Orig. of Change Submission Date Description of Change **  BWHA 06/09/2008 Initial release *A  BWHA 02/12/2009 Connection Diagrams: Added USON package Valid Combinations Table: Added Tray packing type Configuration Register: Added OTP description for BPNV bit Configuration Register Table: Corrected TBPARM description. Added “Default” setting information upon initial factory shipment. Instruction Set: Separated Mode bit and Dummy bytes Product Group CFI Primary Vendor-Specific Extended Query: Corrected data of 45h bytes Read-ID (READ_ID): Removed statement of 8-cycle buffer for Manufacturer ID and the Device ID Read Status Register: Corrected description for SRWD bit in the Status Register Table. Modified E_ERR and P_ERR descriptions Read Configuration Register: Updated figure Parameter Sector Erase (P4E, P8E): Updated figure Release from Deep Power-Down and Read Electronic Signature (RES): Updated figure OTP Regions: Modified description for the ACC function Power-up and Power-down: Changed specification for t PU Absolute Maximum Ratings: Corrected the Table DC Characteristics: Changed maximum specifications for I CC1 and ICC3. Modified Test Conditions for ISB1 and IPD AC Characteristics: Changed maximum specifications for tW. Added note for max values assume 100k cycles. Changed Clock High/Low time. *B  BWHA 05/26/2009 Connection Diagrams: Corrected package name Dual Output Read Mode (DOR): Added statement for Dual Output Read command Quad Output Read Mode (QOR): Added statement for Quad Output Read command Power Up & Power Down: Updated V CC(low) Min in Table: Power-Up / Power-Down Voltage and Timing AC Characteristics: Updated t WH, tCH and tWL, tCL Revision History: Corrected “Revision 02 (February 12, 2009)” for AC Characteristics *C  BWHA 07/22/2009 Distinctive Characteristics: Added BGA package information Connection Diagrams: Added BGA package Ordering Information: Added Automotive In-cabin information. Added BGA package information. Valid Combinations: Corrected Valid Combinations Table Configuration Register: Added Suggested Cross Settings Table Accelerated Programming Operation: Added note for ACC function Read Identification (RDID): Updated Read Identification description. Updated figure for RDID. Updated CFI table for 29h. Write Registers (WRR): Added note for HPM Parameter Sector Erase (P4E, P8E): Updated description for P4E/P8E command. Sector Erase (SE): Updated description for SE command Release from Deep Power-Down (RES): Added note for RES command Not Recommended for New Design

Document Number: 002-00650 Rev. *L Page 59 of 60 S25FL032P *C (Cont.)  BWHA 07/22/2009 Operating Ranges: Updated descriptions. Added ESN1 and ESN2 Table. AC Characteristics: Added Automotive In-cabin spec for fC. Updated tWH, tCH and tWL, tCL. Physical Dimensions: Added BGA 6 x 8 mm package *D  BWHA 10/05/2009 Global: Changed all references to RDID clock rate from 40 to 50 MHz Connection Diagrams: Added “5 x 5 pin configuration” to Figure 2.5 title. Added 6 x 4 pin configuration BGA connection diagram. Added note regarding exposed central pad on bottom of package to the WSON and USON connection diagram. Ordering Information: Added Automotive In-Cabin temperature valid combinations for BGA packages. Added 02 and 03 model numbers for BGA packages. Removed BGA from 00 model number description. Added Low-Halogen material option. Valid Combinations: Changed valid BGA model number combinations to 02 and 03. Changed valid BGA material option to Low-Halogen. Removed Note 1. Physical Dimensions: Added FAC024 BGA package AC Characteristics: Removed 76 MHz Automotive in-cabin spec from f C and Note 9. *E  BWHA 12/07/2011 Instruction Set Table: Updated QIOR command Power-Up / Power-Down Voltage and Timing Table: Updated tPU (max) Initial Delivery State: Modified section Capacitance: Added notes to table Physical Dimensions: Updated the package outline drawing for SOIC, WSON, USON, and BGA 5x5 packages. *F  BWHA 09/21/2012 AC Characteristics: Changed Output Hold Time (t HO) to 2 ns (min). *G  BWHA 10/30/2012 Command Definitions: Instruction Set table: Corrected the value of CLSR command Write Registers (WRR): Protection Modes table: Added Parameter Sector Erase to Memory Content columns for clarification Parameter Sector Erase (P4E, P8E): Updated the table reference.  BWHA 01/29/2013 Capacitance: Added “Typical” values column. Corrected “Max” values for CIN / COUT (Input / Output Capacitance). *I 4904072 BWHA 09/18/2015 Updated to Cypress template. *J 5615358 ECAO 03/24/2017 Corrected tCFT and tCRT positions in Figure 45 on page 50. Updated Cypress logo and Sales page. *K 5711277 ECAO 04/25/2017 Added Valid Automotive Ordering Combinations in Section 5.1, Valid Combinations on page 9 Updated all package outline drawings in Section 19., Physical Dimensions on page 52 *L 5742306 ECAO 05/19/2017 Added Valid Automotive Ordering Combinations in Section 5.1, Valid Combinations on page 9. Added “Not Recommended for New Design (NRND)” status. Document History Page (Continued) Document Title: S25FL032P, 32-Mbit 3.0 V Flash Memory Document Number: 002-00650 Rev. ECN No. Orig. of Change Submission Date Description of Change Not Recommended for New Design

Document Number: 002-00650 Rev. *L Revised May 19, 2017 Page 60 of 60 © Cypress Semiconductor Corporation, 2008-2017. This document is the property of Cypress Semiconductor Corporation and its subs idiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. 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You shall indemnify and hold Cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. S25FL032P Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless PSoC® Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support Not Recommended for New Design