RTQ5115-QA RICHTEK | Alldatasheet
Document overview
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Technical content
Features
Input Voltage Operating Range is 3.15V to 5.5V Step-Down Regulator : VIN Range is 3.15V to 5.5V Max Current 2.4A/2A/1.6A/2A Programmable Frequency from 500kHz to 2MHz I2C Programmable Output Level I2C Programmable Operation Mode (Force PWM or Auto PSM/PWM) I2C Programmable Output Discharge Mode (Discharge or Floating) Linear Regulators : VIN Range is 2.5V to 5.5V I2C Programmable Output Level Embedded 32Bytes MTP for Factory Tuning External MTP Pin for Write Protection Sequence can be Controlled by I2C or each EN pins Defined by MASK_GPIO Pin OT/UVP/VIN LV/POWRON Press Time Interrupt (IRQ) I2C Control Interface : Support Fast Mode Up to 400kb/s AEC-Q100 Grade 2 Qualified RoHS Compliant and Halogen Free
Applications
Industrial/Automotive Integrated PMIC with 4-Channel Synchronous Buck Converters, 8 LDOs, and MTP Non-Volatile Memory for Industrial and Automotive Applications Marking Information RTQ5115GQW-QA : Product Number YMDNN : Date Code RTQ5115-QA VINL456 VINL123 AGND VINL78 VOUTLx VDDP VIN VINBx LXBx VOUTBxS SCL SDA IRQ PWRHOLD PWRON REBOOT MTP MASK_GPIO SADDR PG ENBx ENLx RTQ5115 GQW-QA YMDNN
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 1 VOUTL1 Output voltage regulation node for LDO1. 2 VINL123 Input power for LDO1, LDO2 and LDO3. 3 VOUTL2 Output voltage regulation node for LDO2. 4 VOUTL3 Output voltage regulation node for LDO3. 5 VOUTL6 Output voltage regulation node for LDO6. 6 VOUTL5 Output voltage regulation node for LDO5. 7 VINL456 Input power for LDO4, LDO5 and LDO6. 8 VOUTL4 Output voltage regulation node for LDO4. 9 VOUTL7 Output voltage regulation node for LDO7. 10 VINL78 Input power for LDO7 and LDO8. 11 VOUTL8 Output voltage regulation node for LDO8. 12 ENL4 Enable control input for LDO4. 13 ENL5 Enable control input for LDO5. 14 ENL6 Enable control input for LDO6. 15 SCL Clock input for I 2C. Open-drain output. Pin Configuration (TOP VIEW) WQFN-56L 7x7
Ordering Information
Note : Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Package Type QW : WQFN-56L 7x7 (W-Type) RTQ5115 Lead Plating System G : Green (Halogen Free and Pb Free) -QA Grade QA : AEC-Q100 Qualified and Screened by High Temperature Code Version VOUTL1 VOUTL3 VOUTL2 ENL4 VOUTL8 VINL78 VOUTL7 VOUTL4 VINL456 VOUTL6 VOUTL5 VINL123 SCL SDA ENL7 ENL8 IRQ PWRHOLD AGND PWRON REBOOT MTP MASK_GPIO LXB2 VOUTB2S ENB2 VINB4 VOUTB3S AGND LXB3 LXB3 VINB3 VINB3 LXB2 ENL3 ENL2 ENL1 VIN VDDP VINB1 VOUTB1S ENB1 LXB1 LXB1 262524232221201918171615 454647484950515253545556 LXB431 ENB330 VOUTB4S29 SADDR ENB4 ENL5 13 ENL6 14 VINB2 VINB2 AGND VINB1 AGND PG
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin No. Pin Name Pin Function 16 SDA Data input for I 2C. Open-drain output. 17 ENL7 Enable control input for LDO7. 18 ENL8 Enable control input for LDO8. 19 IRQ Open-drain IRQ output node. 20 PG Power good indicator. 21, 34, 56, 57 (Exposed Pad) AGND Analog ground. The exposed pad must be soldered to a large PCB and connected to AGND for maximum power dissipation. 22 PWRON Manual power on. 23 REBOOT System power reboot. 24 MTP MTP write protection pin. Logic low is inhibited and logic high is permit to write.
25 MASK_GPIO
Select I2C or EN pin for Bucks and LDOs. Connect a 100k pull-low resistor. As MASK_GPIO is high, ignore all EN pins. As MASK_GPIO is low, EN pins and I 2C both can control. EN pins priority is higher than I2C. 26 PWRHOLD Power hold input. 27 SADDR I 2C slave address. 28 ENB4 Enable control input for Buck4. 29 VOUTB4S Output voltage regulation node for Buck4. 30 ENB3 Enable control input for Buck3. 31 LXB4 Internal switch node to output inductor connection for Buck4. 32 VINB4 Input power for Buck4. 33 VOUTB3S Output voltage regulation node for Buck3. 35, 36 LXB3 Internal switch node to output inductor connection for Buck3. 37, 38 VINB3 Input power for Buck3. 39 VOUTB2S Output voltage regulation node for Buck2. 40 ENB2 Enable control input for Buck2. 41, 42 LXB2 Internal switch node to output inductor connection for Buck2. 43, 44 VINB2 Input power for Buck2. 45, 46 VINB1 Input power for Buck1. 47, 48 LXB1 Internal switch node to output inductor connection for Buck1. 49 ENB1 Enable control input for Buck1.
50 VOUTB1S Output voltage regulation node for Buck1
51 VDDP Internal bias regulator voltage. External load on this pin is not allowed. 52 VIN Input power for analog base. 53 ENL1 Enable control input for LDO1. 54 ENL2 Enable control input for LDO2. 55 ENL3 Enable control input for LDO3.
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Central Controller I2C Programmable State Machine LDO1 300mA LDO2 300mA LDO3 300mA LDO4 300mA LDO5 300mA LDO6 300mA LDO7 300mA LDO8 300mA Buck2 Buck1 2.4A VINL123 VINL456 VOUTL2 VOUTL3 VOUTL4 VOUTL5 VOUTL6 VOUTL7 VOUTL8 SDA SCL IRQ PWRHOLD REBOOT VINB1 LXB1 VOUTB2S LXB2 VINB2 VOUTB1S MASK_GPIO SADDR PWRON ENB1 to ENB4 ENL1 to ENL8 MTP VOUTL1 VINL78 PG Buck3 1.6A VINB3 LXB3 VOUTB3S Buck4 VINB4 LXB4 VOUTB4S Analog Base VIN VDDP AGND GND GND GND GND
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Absolute Maximum Ratings (Note 1) Power Dissipation, PD @ TA = 25°C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)
Electrical Characteristics
(TJ = −40°C to 105°C, VIN = 3.15V to 5.5V (Note 5, 6)) Parameter Symbol Test Conditions Min Typ Max Unit AMR for VIN -- -- 6 V Operation Voltage of VIN As fSW > 1MHz, 3.15V VIN 5.5V. If fSW 1MHz, VIN 4V. 3.15 -- 5.5 V PMIC Quiescent Current I IN VIN = 5V, LDOs, Bucks are ON with no load. Bucks operate in auto mode (Reg 0x06 = FFh) 350 700 950 VIN = 5V, SCL = SDA = 0V, LDO and Bucks are OFF, Disable PMIC (Reg0x15[7] = 1) 5 30 60 Warning for Die Temperature OTW Temperature 1 -- 100 -- Temperature 2 -- 125 -- Over-Temperature Protection OTP -- 165 -- C OTP and Warning Hysteresis -- 10 -- C Input Pull-Low 100k Resistor RLow V IN = 5V, temperature = 40C to 105C 70 115 160 k
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Buck1 to Buck4 Input Voltage V INB 3.15 -- 5.5 V Consumption Current I VINB AUTO mode I OUT = 0mA, each Buck 10 30 50 A Output Voltage Accuracy V OUTAcc 3.1V < V IN < 5.5V, 1mA < I OUT < I MAX, Switching Frequency f SW I 2C programmable 0.5 -- 2.00 MHz Switching Frequency Accuracy 1MHz fSW 10 -- 10 fSW 1MHz 20 -- 20 Peak Current Limit OCP Buck1 3.1 4.4 5.8 A Buck2 2.8 4 5.2 Buck3 2.6 3.7 4.8 Buck4 2.8 4 5.2 Under-Voltage Protection UVP VOUTB1S to VOUTB4S < 0.66 x (V OUT target) 56 66 76 % Maximum Output Current I MAX Buck1 2.4 -- -- A Buck2 2 -- -- Buck3 1.6 -- -- Buck4 2 -- -- High-Side On-Resistance R pon V IN = 3.7V 50 150 250 m Low-Side On-Resistance R non V IN = 3.7V 40 110 160 m LDO1 to LDO8 Input Voltage for VINL123/456/78 VINL 2.5 -- 5.5 V Output Voltage LDO123/78 V OUTL 3.1V VIN 5.5V, 50A IOUT IMAX Output Voltage LDO456 V OUTL 3.1V VIN 5.5V, 50A IOUT IMAX Output Current I OUT 300 -- -- mA Output Short Current Isht 330 450 600 mA Voltage Difference V IN VOUT VIN > 3.1V VIN = VSET, IOUT = IOUTMAX 0.05 0.10 0.30 V VIN > 2.5V 0.05 0.11 0.50 Supply Current I SS I OUT = 0mA 10 50 75 A Shutdown Current I OFF 0 1 2 A Control Input Pin Electrical Characteristics Voltage Output Low V OL -- -- 0.4 V Input Voltage High-Level V IH 1.5 -- -- V Low-Level V IL -- -- 0.7
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit PG Pin Electrical Characteristics Output Low Voltage PG Isink = 1mA,V IN = 3.15V to 5.5V -- -- 0.2 V Output High Leakage PG TA = 25C, VIN = 3.15V to 5.5V 1 0 1 TA = 105C,VIN = 3.15V to 5.5V -- 0.1 -- Note 1. Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Limits apply to the recommended operating temperature range of −40°C to 105 °C, unless otherwise noted. Minimum and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T A = 25 °C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply : VIN = 3.15V to 5.5V. Note 6. In applications where high power dissipation or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T A-MAX) is dependent on the maximum operating junction temperature (T J-MAX = 125 °C), the maximum power dissipation of the device in the application (P D-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (R θJA), as given by the following equation : TA-MAX = TJ-MAX - (RθJA x PD-MAX).
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Application Circuit Suggested Components for Typical Application Circuit Description Part Number Manufacturer Inductor for Buck-2.2H MDWK4040T2R2MMV TAIYO NRS5030T2R2NMGJV TAIYO CIN for Buck-10F C1206X7R1E516DT Murata EMK316AB7106KL-T TAIYO COUT for Buck-22F C1206X7R22E416DT Murata JMK316AB7226KL-TR TAIYO CIN/COUT for LDO/VIN/VDDP-1F C0603X7R1E216DT Murata EMK107B7105KA-T TAIYO RTQ5115-QA ENL1 to ENL8 ENB1 to ENB4 VINL456 VINL1232 AGND 57 (Exposed Pad) VINL7810 VOUTL3 VOUTL4 VOUTL5 VOUTL6 VOUTL8 VOUTL7 VOUTL2 VOUTL1 1 VDDP51 VIN52 VINB2 LXB2 VOUTB2S 43, 44 41, 42 VINB1 LXB1 VOUTB1S 22µF 2.2µH 10µF 45, 46 47, 48 VINB4 LXB4 VOUTB4S VINB3 LXB3 VOUTB3S 37, 38 35, 36 PWRON 22 IRQ SCL SDA REBOOT PWRHOLD PG SADDR MTP MASK_GPIO AP As MTP connect to AGND Inhibit to write MTP. As MTP connect to VIN Permit to write MTP. As MASK_GPIO connect to AGND EN pins can control. As MASK_GPIO connect to VIN Ignore all EN pins. As SADDR connect to AGND Slave address = 0111111 As SADDR connect to VIN Slave address = 0110111 1µF 1µF 1µF 1µF 1µF 1µF 1µF 1µF 1µF 1µF 1µF 1µF 1µF 10µF 10µF 10µF 22µF 2.2µH 22µF 2.2µH 22µF 2.2µH 21, 34, 56, External REBOOT KEY External PWRON KEY
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics CH1 Buck Efficiency vs. Output Current 100 10 100 1000 10000 Output Current (mA) Efficiency (%) VOUT = 1.35V, L = 2.2μH, COUT = 10μF VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 5V VIN = 5.5V CH2 Buck Efficiency vs. Output Current 100 10 100 1000 10000 Output Current (mA) Efficiency (%) VOUT = 1.5V, L = 2.2μH, COUT = 10μF VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 5V VIN = 5.5V CH3 Buck Efficiency vs. Output Current 100 10 100 1000 10000 Output Current (mA) Efficiency (%) VOUT = 1.2V, L = 2.2μH, COUT = 10μF VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 5V VIN = 5.5V CH4 Buck Efficiency vs. Output Current 100 10 100 1000 10000 Output Current (mA) Efficiency (%) VOUT = 3.3V, L = 2.2μH, COUT = 10μF VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 4.5V VIN = 5V VIN = 5.5V CH2 Buck Output Voltage vs. Output Current 1.47 1.48 1.49 1.50 1.51 1.52 1.53 0 500 1000 1500 2000 Output Current (A) Output Voltage (V) L = 2.2μH, COUT = 10μF VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 5V VIN = 5.5V CH1 Buck Output Voltage vs. Output Current 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 0 300 600 900 1200 1500 1800 2100 2400 Output Current (mA) Output Voltage (V) L = 2.2μH, COUT = 10μF VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 5V VIN = 5.5V
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. CH4 Buck Output Voltage vs. Input Voltage 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 Input Voltage (V) Output Voltage (V) L = 2.2μH, COUT = 10μF IOUT = 0mA IOUT = 500mA IOUT = 1000mA IOUT = 1500mA IOUT = 2000mA CH3 Buck Output Voltage vs. Input Voltage 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 Input Voltage (V) Output Voltage (V) L = 2.2μH, COUT = 10μF IOUT = 0mA IOUT = 500mA IOUT = 1000mA IOUT = 1600mA CH1 Buck Output Voltage vs. Input Voltage 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 Input Voltage (V) Output Voltage (V) L = 2.2μH, COUT = 10μF IOUT = 0mA IOUT = 500mA IOUT = 1000mA IOUT = 1500mA IOUT = 2000mA IOUT = 2400mA CH2 Buck Output Voltage vs. Input Voltage 1.45 1.47 1.49 1.51 1.53 1.55 Input Voltage (V) Output Voltage (V) L = 2.2μH, COUT = 10μF IOUT = 0mA IOUT = 500mA IOUT = 1000mA IOUT = 1500mA IOUT = 2000mA CH4 Buck Output Voltage vs. Output Current 3.08 3.13 3.18 3.23 3.28 3.33 3.38 0 500 1000 1500 2000 Output Current (mA) Output Voltage (V) L = 2.2μH, COUT = 10μF VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 4.5V VIN = 5V VIN = 5.5V CH3 Buck Output Voltage vs. Output Current 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 0 200 400 600 800 1000 1200 1400 1600 Output Current (mA) Output Voltage (V) L = 2.2μH, COUT = 10μF VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 5V VIN = 5.5V
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. LDO7 Output Voltage vs. Input Voltage 2.40 2.42 2.44 2.46 2.48 2.50 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Voltage (V) IOUT = 0mA IOUT = 100mA IOUT = 200mA IOUT = 300mA COUT = 1μF LDO5 Output Voltage vs. Input Voltage 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 Input Voltage (V) Output Voltage (V) IOUT = 0mA IOUT = 100mA IOUT = 200mA IOUT = 300mA COUT = 1μF LDO7 Output Voltage vs. Output Current 2.40 2.42 2.44 2.46 2.48 2.50 2.52 0 50 100 150 200 250 300 Output Current (mA) Output Voltage (V) COUT = 1μF VIN = 2.5V VIN = 3V VIN = 3.6V VIN = 4.2V VIN = 5V VIN = 5.5V LDO2 Output Voltage vs. Input Voltage 1.75 1.76 1.76 1.77 1.77 1.78 1.78 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Voltage (V) IOUT = 0mA IOUT = 100mA IOUT = 200mA IOUT = 300mA COUT = 1μF LDO2 Output Voltage vs. Output Current 1.750 1.755 1.760 1.765 1.770 1.775 1.780 1.785 1.790 0 50 100 150 200 250 300 Output Current (mA) Output Voltage (V) COUT = 1μF VIN = 2.5V VIN = 3V VIN = 3.6V VIN = 4.2V VIN = 5V VIN = 5.5V LDO5 Output Voltage vs. Output Current 3.20 3.22 3.24 3.26 3.28 3.30 3.32 0 50 100 150 200 250 300 Output Current (mA) Output Voltage (V) COUT = 1μF VIN = 3.3V VIN = 3.6V VIN = 3.9V VIN = 4.2V VIN = 5V VIN = 5.5V
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Application Information
The RTQ5115 is a highly-integrated solution for automotive system including PMIC and memory system. The RTQ5115 application mechanism and I 2C compatible interface are introduced in later sections. The system's slave address is 0110111 (As SADDR = high) or 0111111 (As SADDR = low). PMIC - Power management system provides 8 low dropout linear regulator and 4 high efficiency synchronous step- down DC-DC converters. Power-On and Power-Off sequences are control by PWRON and REBOOT input pins. Detail time sequence control is described in Power ON/OFF diagram. The I 2C interface can program individual regulator output voltage as well as on/off control and voltage setting. I2C Interface Timing Diagram The RTQ5115 acts as an I2C -bus slave. The I2C-bus master configures the settings for all function blocks by sending command bytes to the RTQ5115 via the 2-wire I 2C-bus. The I2C timing diagrams are list in the following. Parameter Symbol Test Conditions Min Typ Max Unit I2C Interface Electrical Characteristics SDA, SCLK Input High Level Threshold 1.5 -- -- V SDA, SCLK Input Low Level Threshold -- -- 0.4 V SCLK Clock Rate f SCL -- -- 400 kHz Hold Time (Repeated) START Condition. After this period, the first clock pulse is generated tHD;STA 0.6 -- -- s LOW Period of the SCL Clock tLOW 1.3 -- -- s HIGH Period of the SCL Clock t HIGH 0.6 -- -- s Set-Up Time for a Repeated START Condition tSU;STA 0.6 -- -- s Data Hold Time t HD;DAT 0 -- 0.9 s Data Set-Up Time t SU;DAT 100 -- -- ns Set-Up Time for STOP Condition tSU;STO 0.6 -- -- s Bus Free Time Between a STOP and START Condition tBUF 1.3 -- -- s Rise Time of Both SDA and SCL Signals tR 20 -- 300 ns Fall Time of Both SDA and SCL Signals tF 20 -- 300 ns SDA and SCL Output Low Sink Current IOL SDA or SCL voltage = 0.4V 2 -- -- mA
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Read and Write Function I2C Waveform Information S 0 1 A P LSBMSB A Assume Address = m Data for Address = m Data for Address = m + N - 1 A Data for Address = m + 1 S 0 P Assume Address = m Data for Address = m Data for Address = m + N - 1 Data for Address = m + 1 Sr Slave Address Register Address Slave Address Data 1 R/W R/W Data N LSBMSB AA A A A A A A Read N bytes of data from Registers LSBMSB Data 2 Data N LSB MSB LSBSlave Address Register Address Data 1 Data 2 MSB MSB LSB Write N bytes of data to Registers Driven by Master, Driven by Slave, Start, Repeat StartStop, S SrP S 0 1 A P LSBMSB Assume Address = m Data for Address = m Sr Slave Address Register Address Slave Address Data R/W AA A Read single byte of data from Register S 0 P Assume Address = m Data for Address = mR/W A A A Slave Address Register Address Data MSB LSB Write single byte of data to Register SDA SCL tF tLOW tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tHD;STA tSP tBUF tSU;STO PS tR SrS tF tR
©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. will follow the power on sequence to turn on channels. shown in Figure 1 and Table 1. or VIN (VIN < 1.7V) to resume operation. Figure 1. Power ON/OFF Flow Chart
©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 1. Protection List
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. PMIC - POWER ON/OFF Setting The circuit setting for communication between the RTQ5115 and AP is showed as below. PG Rising Slew Rate PG Falling Slew Rate PG Pin The PG comparator features an open drain output. The PG pin pull high to input voltage with 10k Ω which slew rate define as follow. 10k CL= 20pF Rph Rpl PG trise = 3 x Rph x CL = 600ns VIN 10k CL= 20pF Rph Rpl MOSFET equivalent resistane = 40 PG tfall = 3 x Rpl x CL = 2.4ns VIN State Machine ENL1 to ENL8 ENB1 to ENB4 PWRON IRQ SCL SDA REBOOT PWRHOLD SADDR MTP MASK_GPIO APRESET As MTP connect to AGND Inhibit to write MTP. As MTP connect to VIN Permit to write MTP. As MASK_GPIO connect to AGND EN pins can control. As MASK_GPIO connect to VIN Ignore all EN pins. As SADDR connect to AGND Slave address = 0111111 As SADDR connect to VIN Slave address = 0110111 External REBOOT KEY External PWRON KEY
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Power Hold Function When the “PWRHOLD” signal does not come during THOLD time, the RTQ5115 will do shutdown sequence. If users want to disable power hold function, set “DisTHOLD” bit in I2C register 0x10 bit[0] to disable this function. In the timing diagram below, the “THOLD” and “PG_DLY” can be set by MTP program. GPIO Pin Pull-Up/Down Defined Pin No. Pin Name GPIO Pin Pull-Up/Down Defined Resistor
12 ENL4 Internal 100k pull low resistor Internal
13 ENL5 Internal 100k pull low resistor Internal
14 ENL6 Internal 100k pull low resistor Internal
15 SCL Open drain, need to connect pull up resistor with
range from 2.2k to 10k External
16 SDA Open drain, need to connect pull up resistor with
range from 2.2k to 10k External
17 ENL7 Internal 100k pull low resistor Internal
18 ENL8 Internal 100k pull low resistor Internal
22 PWRON Internal 100k pull up resistor Internal
23 REBOOT Internal 100k pull low resistor Internal
24 MTP Internal 100k pull low resistor Internal
26 PWRHOLD Internal 100k pull low resistor Internal
27 SADDR Internal 100k pull low resistor Internal
28 ENB4 Internal 100k pull low resistor Internal
30 ENB3 Internal 100k pull low resistor Internal
40 ENB2 Internal 100k pull low resistor Internal
49 ENB1 Internal 100k pull low resistor Internal
53 ENL1 Internal 100k pull low resistor Internal
54 ENL2 Internal 100k pull low resistor Internal
55 ENL3 Internal 100k pull low resistor Internal
START_TIME Turn off sequence : First-on-last-Off PG PG_DLY
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. When AP sends the “PWRHOLD” signal during THOLD time, the RTQ5115 will keep power-on. Timing Based ON/OFF Sequence (PWRON_NORMOFF_EN, Reg0x15[0] = 1) BUCK1 LDO1 LDO8 BUCK4 PWRHOLD PWRON THOLD Low to High signal from AP. START_TIME PG PG_DLY BUCK1 BUCK2 LDO1 LDO8 PWRON BUCK4 START_TIME Normal power on ... Normal power off SHDN_PRESS tSS tSS tSS tSS PG PG_DLY
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Level Based ON/OFF Sequence (PWRON_NORMOFF_EN, Reg0x15[0] = 1) Abnormal OFF (OTP, Buck 1/2/3/4 UVP) PWRON BUCK1 BUCK2 BUCK3 LDO1 LDO8 START_TIME Normal power on SHDN_PRESS Normal power off > 80% > 80% > 80% > 80% > 80% 8ms 8ms 8ms 8ms PG_DLY PG LDO2 tdly_Buck tdly_Buck tdly_LDO …... …... Note. Sequence : BUCK1 BUCK2 BUCK3 BUCK4 LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 tdly_Buck : 192 x (1/fsw) + 40µs ±35% tdly_LDO : 110µs ±20% (If previous one channel is Buck, additional delay time 32 x (1/fsw) need to be added to tdly_LDO.) BUCK1 BUCK2 LDO1 LDO8 IRQ PWRON BUCK4 START_TIME SHDN_DLYTIME tSS tSS Normal power on Abnormal power offIRQ Even Occur PG_DLY PG
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Based ON/OFF Sequence by VIN (VINLV_ENSHDN, Reg0x16[1] = 0) (VINLV_ENSHDN, Reg0x16[1] = 1; VINLV_SEQ_EN, Reg0x16[0] = 1) PG BUCK1 BUCK2 LDO1 LDO8 VIN BUCK4 > 80% > 80% > 80% > 80% VDDP 600µs PG_DLY IC POR (VIN < 1.7V) PG BUCK1 BUCK2 LDO1 LDO8 VIN BUCK4 > 80% > 80% > 80% > 80% VDDP 600µs PG_DLY 8ms 8ms 8ms < 8ms VOFF setting Reg0x12[7:5] IC POR (VIN < 1.7V)
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. DC-DC 1/2/3/4 Output Voltage1 DC-DC 1/2/3/4 Output Voltage2 DC-DC 1/2/3/4 Output Voltage3 DC-DC 1/2/3/4 Output Voltage4 PMU On/Off Sequence Setting In the RTQ5115, users can set the power on/off sequence and output voltage by I2C register 0x01 to 0x04 for Buck output voltage, 0x07 to 0x0E for LDO output voltage and 0x2C to 0X32 for startup sequence setting. Synchronous Step-Down DC-DC Converter Four current mode synchronous step-down DC-DC converters operate with internal power MOSFETs and compensation network. These channels supply the power core chip of portable system. They can be operated at 100% maximum duty cycle to extend battery operating voltage range. When the input voltage is close to the output voltage, the converter enters low dropout mode with low output ripple. The operating frequency range of step-down converter is 0.5MHz to 2MHz. Four step-down converters have RAMP control function as the following diagram. Input and Output Capacitors Selection The RTQ5115 is designed to work with low ESR ceramic capacitors. The effective value of these capacitors is defined as the actual capacitance under voltage bias and temperature. All ceramic capacitors have a large voltage coefficient, in addition to normal tolerances and temperature coefficients. Under D.C. bias, the capacitance value drops considerably. Larger case sizes or higher voltage capacitors are better in this regard. To help mitigate these effects, multiple small capacitors can be used in parallel to bring the minimum effective capacitance up to the desired value. The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. A low ESR input capacitor with larger ripple current rating should be used for the maximum RMS current. RMS current is given by : OUT INRMS OUT(MAX) IN OUT V VI = I 1 VV This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT / 2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life, which makes it advisable to either further derate the capacitor or choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. The selection of C OUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple, load step transients, and the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be examined by viewing the load transient response as described in a later section. The output ripple, ΔV OUT, is determined by : OUT L SW OUT 1V I E S R + 8f C The output ripple is highest at maximum input voltage since DIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing.
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Page 8 shows the nominal values of input/output capacitance recommenced for the RTQ5115. Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔI L increases with higher VIN and decreases with higher inductance : OUT OUTL OSC IN VVI = 1 fL V Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔI L = 0.4 (IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : OUT OUT OSC L(MAX) IN(MAX) VVL = 1 fI V Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or permalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. However, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depend on the price vs. size requirements and any radiated field/EMI requirements.
©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
- OTW125/OTW100 means the 125°C/100°C pre-warming over-temperature.
IRQ_status registers are implemented as reset after read. delay2 power off delay time. Table 2. REBOOT Input Control Setting
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. EEPROM (MTP) Control Flow The RTQ5115 embeds 32 bytes MTP memory, and it allows users to save some I2C register bank data to MTP. When the I 2C register 0x3A Bit[0]/Bit[1] is wrote to “1”, the MTP Page1/Page2 will execute erase process firstly. Because the erase process will be done in every writing time, the MTP data will be missed. So it would be best for users to read data from MTP to I 2C first before executing writing process. Set I2C Register 0x3A Bit[4] =1 PMU will read MTP data to relative I2C register bank. Set I2C Register 0x3A Bit[0] PMU will erase the MTP page1 data PMU will move relative I2C register bank data to MTP Reading MTP process Writing MTP process Page 1 writing follow : Set I2C Register 0x3A Bit[5] =1 PMU will read MTP data to relative I2C register bank. Set I2C Register 0x3A Bit[1] PMU will erase the MTP page2 data PMU will move relative I2C register bank data to MTP Reading MTP process Writing MTP process Page 2 writing follow : Thermal Considerations The junction temperature should never exceed the absolute maximum junction temperature T J(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula : P D(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125 °C. The junction-to-ambient thermal resistance, θ JA, is highly package dependent. For a WQFN-56L 7x7 package, the thermal resistance, θJA, is 27°C/W on a standard JEDEC 51-7 high effective-thermal- conductivity four-layer test board. The maximum power dissipation at T A = 25°C can be calculated as below : PD(MAX) = (125°C − 25°C) / (27°C/W) = 3.7W for a WQFN- 56L 7x7 package. The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, θJA. The derating curves in Figur e 2 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 2. Derating Curve of Maximum Power Dissipation PCB layout guidelines must be strictly followed. the top layer for good filtering. should be minimized for lower EMI. parasitic resistance and inductance from the PCB trace.
©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 3. PCB Layout Guide
32 VINB4
trace, keep sensitive compontents away from this trace.
©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 3. I2C Register Table
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 04 BUCKcontrol4 Bit Name Description R/W Reset Value [7:2] Buck4Output[5:0] Buck4 output voltage regulation 000000 : 0.7V, 50mV per step 000001 : 0.75V 111010 : 3.6V 111111 : 3.6V R/W Option [1:0] Buck4VRC VRC setting 00 : 50mV/10s, 01 : 100mV/10s, 10 : 200mV/10s, 11 : 400mV/10s R/W Option Address 05 VRC Control Bit Name Description R/W Reset Value
7 Buck1VRC_EN
0 : Disable - voltage ramps up to target voltage with one time 1 : Enable - voltage ramps up to target voltage with slope control R/W Option
6 Buck2VRC_EN
0 : Disable - voltage ramps up to target voltage with one time 1 : Enable - voltage ramps up to target voltage with slope control R/W Option
5 Buck3VRC_EN
0 : Disable - voltage ramps up to target voltage with one time 1 : Enable - voltage ramps up to target voltage with slope control R/W Option
4 Buck4VRC_EN
0 : Disable - voltage ramps up to target voltage with one time 1 : Enable - voltage ramps up to target voltage with slope control R/W Option [3:0] Reserved R/W 0000 Address 06 BUCK Mode Bit Name Description R/W Reset Value
7 Buck1mode
0 : Force PWM 1 : Auto Mode (PSM/PWM) R/W Option
6 Buck2mode
0 : Force PWM 1 : Auto Mode (PSM/PWM) R/W Option
5 Buck3mode
0 : Force PWM 1 : Auto Mode (PSM/PWM) R/W Option
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
4 Buck4mode
0 : Force PWM 1 : Auto Mode (PSM/PWM) R/W Option
3 Buck1oms
Buck1 output off mode state 0 : Floating 1 : Ground-discharged R/W Option
2 Buck2oms
Buck2 output off mode state 0 : Floating 1 : Ground-discharged R/W Option
1 Buck3oms
Buck3 output off mode state 0 : Floating 1 : Ground-discharged R/W Option
0 Buck4oms
Buck4 output off mode state 0 : Floating 1 : Ground-discharged R/W Option Address 07 LDOcontrol1 Bit Name Description R/W Reset Value
7 Reserved R/W 0
[6:0] LDO1OUT[6:0] LDO1 output voltage regulation 0000000 : 1.6V, 25mV per step 0000001 : 1.625V ... 1010000 : 3.6V (MAX) 1111111 : 3.6V (MAX) R/W Option Address 08 LDOcontrol2 Bit Name Description R/W Reset Value [6:0] LDO2OUT[6:0] LDO2 output voltage regulation 0000000 : 1.6V, 25mV per step 0000001 : 1.625V ... 1010000 : 3.6V (MAX) 1111111 : 3.6V (MAX) R/W Option Address 09 LDOcontrol3 Bit Name Description R/W Reset Value [6:0] LDO3OUT[6:0] LDO3 output voltage regulation 0000000 : 1.6V, 25mV per step 0000001 : 1.625V ... 1010000 : 3.6V (MAX) 1111111 : 3.6V (MAX) R/W Option
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 0A LDOcontrol4 Bit Name Description R/W Reset Value [6:0] LDO4OUT[6:0] LDO4 output voltage regulation 0000000 : 3 V, 25mV per step 0000001 : 3.025V ... 0011000 : 3.6V (MAX) 1111111 : 3.6V (MAX) R/W Option Address 0B LDOcontrol5 Bit Name Description R/W Reset Value [6:0] LDO5OUT[6:0] LDO5 output voltage regulation 0000000 : 3V, 25mV per step 0000001 : 3.025V ... 0011000 : 3.6V (MAX) 1111111 : 3.6V (MAX) R/W Option Address 0C LDOcontrol6 Bit Name Description R/W Reset Value [6:0] LDO6OUT[6:0] LDO6 output voltage regulation 0000000 : 3.0V, 25mV per step 0000001 : 3.025V ... 0011000 : 3.6V (MAX) 1111111 : 3.6V (MAX) R/W Option Address 0D LDOcontrol7 Bit Name Description R/W Reset Value [6:0] LDO7OUT[6:0] LDO7output voltage regulation 0000000 : 1.6V, 25mV per step 0000001 : 1.625V ... 1010000 : 3.6V (MAX) 1111111 : 3.6V (MAX) R/W Option
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 0E LDOcontrol8 Bit Name Description R/W Reset Value [6:0] LDO8OUT[6:0] LDO8utput voltage regulation 0000000 : 1.6V, 25mV per step 0000001 : 1.625V ... 1010000 : 3.6V (MAX) 1111111 : 3.6V (MAX) R/W Option Address 0F LDOs off mode state Bit Name Description R/W Reset Value
7 LDO8oms
LDO8 output off mode state 0 : Floating 1 : Ground-discharged R/W 1
6 LDO7oms
LDO7 output off mode state 0 : Floating 1 : Ground-discharged R/W 1
5 LDO6oms
LDO6 output off mode state 0 : Floating 1 : Ground-discharged R/W 1
4 LDO5oms
LDO5 output off mode state 0 : Floating 1 : Ground-discharged R/W 1
3 LDO4oms
LDO4 output off mode state 0 : Floating 1 : Ground-discharged R/W 1
2 LDO3oms
LDO3 output off mode state 0 : Floating 1 : Ground-discharged R/W 1
1 LDO2oms
LDO2 output off mode state 0 : Floating 1 : Ground-discharged R/W 1
0 LDO1ms
0 : Floating 1 : Ground-discharged R/W 1 Address 10 REBOOT/PWRHOLD delay time control Bit Name Description R/W Reset Value [7:6] Delayed2[1:0] Delayed2 setting (00 : 100ms/01 : 500ms/10 : 1s/11 : 2s) R/W Option [5:4] Delayed1[1:0] Delayed1 setting (00 : 100ms/01 : 500ms/10 : 1s/11 : 2s) R/W Option [3:2] THOLD[1:0] THOLD setting (00 : 100ms/01 : 500ms/10 : 1s/11 : 2s) R/W Option
1 Reserved R/W 0
0 DisTHOLD
Ignore THOLD Time. 0 : Keep PWRHOLD function. 1 : Ignore PWRHOLD function. R/W Option
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 11 ON Event Setting Bit Name Description R/W Reset Value [7:5] On_Event Powered on because of 000 : PWRON key-pressed 001 : VIN plugged in 010 : From REBOOT pin event 111 : No event happen R 111 [4:0] Reserved R/W 0 Address 12 VIN UVLO/Buck On/Off Bit Name Description R/W Reset Value [7:5] VOFF setting VIN UVLO 2.8V to 3.5V per 0.1V to power off PMIC (Hysteresis = VOFF setting + 0.35V) 000 : 2.8V 001 : 2.9V 010 : 3V 011 : 3.1V 100 : 3.2V 101 : 3.3V 110 : 3.4V 111 : 3.5V R/W Option
4 Reserved R/W 0
3 Buck4 Buck4 control
(0 : Disable Buck4/1 : Enable Buck4) R/W Option
2 Buck3 Buck3 control
(0 : Disable Buck3/1 : Enable Buck3) R/W Option
1 Buck2 Buck2 control
(0 : Disable Buck2/1 : Enable Buck2) R/W Option
0 Buck1 Buck1 control
(0 : Disable Buck1/1 : Enable Buck1) R/W Option
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 13 LDOs On/Off Bit Name Description R/W Reset Value
7 LDO8 LDO8 control
(0 : Disable LDO8 / 1 : Enable LDO8) R/W Option
6 LDO7 LDO7 control
(0 : Disable LDO7 / 1 : Enable LDO7) R/W Option
5 LDO6 LDO6 control
(0 : Disable LDO6 / 1 : Enable LDO6) R/W Option
4 LDO5 LDO5 control
(0 : Disable LDO5 / 1 : Enable LDO5) R/W Option
3 LDO4 LDO4 control (0 : Disable LDO4 / 1 : Enable
LDO4) R/W Option
2 LDO3 LDO3 control
(0 : Disable LDO3 / 1 : Enable LDO3) R/W Option
1 LDO2 LDO2 control
(0 : Disable LDO2 / 1 : Enable LDO2) R/W Option
0 LDO1 LDO1 control
(0 : Disable LDO1 / 1 : Enable LDO1) R/W Option
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 14 PWRON(Power On Key) time Parameters Setting / PG delay Bit Name Description R/W Reset Value [7:6] START_TIME Startup time setting 00 : 100s (pressing time - low level) 01 : 100ms 10 : 1s 11 : 2s R/W Option [5:4] L_PRESS_TIME Long-press time setting (after Power-On, 00 : 1s (falling edge to rising edge) 01 : 1.5s 10 : 2s 11 : 2.5s Sending short/long-press IRQ to CPU ex : 1.5s low time < 1.5s (short IRQ) low time > 1.5s but < 6s (shutdown time) (long IRQ) low time > 6s (shutdown time) (shutdown) R/W Option [3:2] SHDN_PRESS Key-press forced shutdown time setting 00 : 4s/0ms (pressing time : low level) 01 : 6s/1ms 10 : 8s/1ms 11 : 10s/2ms (allow option 0/1/1/2ms by SHDN_PRESS_SHORT) R/W Option [1:0] PG_DLY PG signal delay after the last power startup is done 00 : 10ms 01 : 50ms 10 : 100ms 11 : 200ms/5ms (allow option 5ms by PG_DLY_5ms_EN) R/W Option
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 15 SHDN Control Bit Name Description Read/Write Reset Value
7 SHDN_CTRL
Power off setting by CPU, after set, 100ms delayed power off 0 : Normal operation 1 : Disable the PMIC output R/W 0
6 SHDN_TIMING
Disable Buck/LDO only for normal power off (SHDN_CTRL = 1) 0 : Disable at the same time 1 : Contrary to the startup timing (first_on-last_off) R/W Option [5:4] SHDN_DLYTIME Delayed shutdown time after send the (PWRON)key-press-forced-shutdown IRQ (when IRQ is disable, there is no delay) 00 : 100ms 01 : 500ms 10 : 1s 11 : 2s R/W Option
3 Reserved R/W 0
2 PG_DLY_5ms_EN 0 : 0x14[1:0] = 11, delay is 200ms
1 : 0x14[1:0] = 11, delay is 5ms R/W Option
1 SHDN_PRESS_SHORT
0 : 0x14[3:2], SHDN_PRESS time is 4s/6s/8s/10s 1 : 0x14[3:2], SHDN_PRESS time is 0ms/1ms/1ms/2ms R/W Option
0 PWRON_NORMOFF_EN PWRON off sequence
0 : Disable this event. 1 : Enable this event R/W Option Address 16 Powered off conditions enable setting Bit Name Description Read/Write Reset Value
7 BCK1LV_ENSHDN Buck1 output voltage low SHDN
0 : Disable this event. 1 : Enable this event R/W 0
6 BCK2LV_ENSHDN Buck2 output voltage low SHDN
0 : Disable this event. 1 : Enable this event R/W 0
5 BCK3LV_ENSHDN Buck3 output voltage low SHDN
0 : Disable this event. 1 : Enable this event R/W 0
4 BCK4LV_ENSHDN Buck4 output voltage low SHDN
0 : Disable this event. 1 : Enable this event R/W 0
3 PWRON_ENSHDN PWRON key-pressed forced SHDN
0 : Disable this event. 1 : Enable this event R/W 1
2 OT_ENSHDN Over temperature SHDN
0 : Disable this event. 1 : enable this event R/W 1
1 VINLV_ENSHDN VIN voltage low (VOFF) SHDN
0 : Disable this event. 1 : Enable this event R/W Option
0 VINLV_SEQ_EN Off sequence after VIN voltage low (VOFF)
0 : Disable this event. 1 : Enable this event R/W Option
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 17 OFF Event (Only reset by POR) Bit Name Description Read/Write Reset Value [7:4] OFF_Event Powered off because of (Only shows last power-off event) 0000 : VIN voltage low (VOFF) (Set by reg) 0001 : Buck1 output voltage low 0010 : Buck2 output voltage low 0011 : Buck3 output voltage low 0100 : PWRON key-pressed forced shutdown 0101 : Power Off register setting 0110 : Over-temperature event 0111 : Reboot restart. 1000 : Buck4 output voltage low 1001 : PWR_HOLD fail. 1010 : No event happen. 1111 : No event happen R 1111 [3:0] Reserved R 0000 Address 28 IRQ Enable1 Bit Name Description Read/Write Reset Value
7 OT_IRQ Internal over-temperature was triggered, IRQ
6 Bck1LV_IRQ Buck1 output voltage equal 66% x VTarget,
5 Bck2LV_IRQ Buck2 output voltage equal 66% x VTarget,
4 Bck3LV_IRQ Buck3 output voltage equal 66% x VTarget,
3 Bck4LV_IRQ Buck4 output voltage equal 66% x VTarget,
2 PWRONSP_IRQ PWRON short press, IRQ enable
(32s deglitch time) R/W 0
1 PWRONLP_IRQ PWRON long press, IRQ enable
(32s deglitch time) R/W 0
0 SYSLV_IRQ VIN voltage is lower than VOFF, IRQ enable R/W 0
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 29 IRQ Status1 Bit Name Description Read/Write Reset Value
7 OT Internal over-temperature R 0
6 Bck1LV Buck1 output voltage equal 66% x V Target R 0
5 Bck2LV Buck2 output voltage equal 66% x V Target R 0
4 Bck3LV Buck3 output voltage equal 66% x V Target R 0
3 Bck4LV Buck4 output voltage equal 66% x V Target R 0
2 PWRONSP PWRON short press (32 s deglitch time) R 0
1 PWRONLP PWRON long press (32 s deglitch time) R 0
0 VINLV VIN voltage is lower than VOFF R 0
Bit Name Description Read/Write Reset Value
7 KPSHDN_IRQ Key-press forced shutdown, IRQ enable R/W 1
6 PWRONR_IRQ PWRON press rising edge, IRQ enable R/W 0
5 PWRONF_IRQ PWRON press falling edge, IRQ enable R/W 0
[4:0] Reserved R 0000 Address 2B IRQ Status2 Bit Name Description Read/Write Reset Value
7 KPSHDN Key-press forced shutdown R 0
6 PWRONR PWRON press rising edge R 0
5 PWRONF PWRON press falling edge R 0
[4:2] Reserved R 000 1 OTW125 Internal 125 C pre-warning over-temperature. R 0 0 OTW100 Internal 100 C pre-warning over-temperature. R 0 Address 2C PMU On/Off Sequence1 Bit Name Description (Setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (The sequence is planed by first on last off) Read/Write Reset Value [7:4] Buck2_Seq[3:0] Setting Buck2 on/off sequence priority R/W Option [3:0] Buck1_Seq[3:0] Setting Buck1 on/off sequence priority R/W Option Address 2D PMU On/Off Sequence2 Bit Name Description (Setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (The sequence is planed by first on last off) Read/Write Reset Value [7:4] Buck4_Seq[3:0] Setting Buck4 on/off sequence priority R/W Option [3:0] Buck3_Seq[3:0] Setting Buck3 on/off sequence priority R/W Option
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 2E PMU On/Off Sequence3 Bit Name Description (Setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (The sequence is planed by first on last off) Read/Write Reset Value [7:4] LDO2_Seq[3:0] Setting LDO2 on/off sequence priority R/W Option [3:0] LDO1_Seq[3:0] Setting LDO1 on/off sequence priority R/W Option Address 2F PMU On/Off Sequence4 Bit Name Description (Setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (The sequence is planed by first on last off) Read/Write Reset Value [7:4] LDO4_Seq[3:0] Setting LDO4 on/off sequence priority R/W Option [3:0] LDO3_Seq[3:0] Setting LDO3 on/off sequence priority R/W Option Address 30 PMU On/Off Sequence5 Bit Name Description (Setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (The sequence is planed by first on last off) Read/Write Reset Value [7:4] LDO6_Seq[3:0] Setting LDO6 on/off sequence priority R/W Option [3:0] LDO5_Seq[3:0] Setting LDO5 on/off sequence priority R/W Option Address 31 PMU On/Off Sequence5 Bit Name Description (Setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (The sequence is planed by first on last off) Read/Write Reset Value [7:4] LDO8_Seq[3:0] Setting LDO8 on/off sequence priority R/W Option [3:0] LDO7_Seq[3:0] Setting LDO7 on/off sequence priority R/W Option Address 32 Soft-Start Control Bit Name Description Read/Write Reset Value [7:6] Reserved R Option [5:2] Soft-Start End Control @ MASK_GPIO = 0 (External Enable pin define) 0000 : First turn on channel decide the PG_DLY time. 0001 : Buck1 decide the PG_DLY time. 0100 : Buck1 decide the PG_DLY time. 0101 : LDO1 decide the PG_DLY time. 1100 : LDO8 decide the PG_DLY time. 1111 : LDO8 decide the PG_DLY time. R/W Option [1:0] Soft-Start Voltage level / time soft-start control. Voltage Level 00 : When output voltage arrives to 80% VTarget, next channel will turn on. Soft-start time interval (TSS) : 01 : 1ms 10 : 4ms 11 : 8ms R/W Option
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Address 33 Buck Syn-Clock Control Bit Name Description Read/Write Reset Value [7:6] VCO_VRC VCO input voltage slop. 00 : 25mV/10s, 01: 25mV/20s 10 : 25mV/40s, 11: 25mV/80s Note : The VCO’s voltage input range is 0.375V to 1.8V and the output frequency is 500kHz to 2.18MHz. R/W Option [5:0] VCO_DVS VCO input voltage DVS control 000000 : 0.375V (500kHz) ……… 111001 : 1.8V (2MHz) ……… 111111 : 1.8V (2MHz) R/W Option Address 34 Buck Syn-Clock Spread Spectrum Control Bit Name Description Read/Write Reset Value [7:1] Reserved R/W 0000000
0 SSOSC
Buck Clock Spread Spectrum Control 0 : Disable spread spectrum function. 1 : Turn on spread spectrum function. R/W Option Address 3A EEPROM (MTP) Control Bit Name Description Read/Write Reset Value [7:6] Reserved R/W 00
5 MTP Page 2 Read Read MTP Page 2 R 0
4 MTP Page 1 Read Read MTP Page 1 R 0
[3:2] Reserved R/W 00
1 MTP Page 2 write Write MTP Page 2, and MTP also needs to be
logic high. W 0
0 MTP Page 1 write Write MTP Page 1, and MTP also needs to be
logic high. W 0
©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 3. I2C to MTP Mapping Table
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. I2C Register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0X09 Function LDOcontrol3 Meaning Reserved LDO3OUT[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x0A Function LDOcontrol4 Meaning Reserved LDO4OUT[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x0B Function LDOcontrol5 Meaning Reserved LDO5OUT[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x0C Function LDOcontrol6 Meaning Reserved LDO6OUT[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x0D Function LDOcontrol7 Meaning Reserved LDO7OUT[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x0E Function LDOcontrol8 Meaning Reserved LDO8OUT[6:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x10 Function REBOOT/PWRHOLD delay time control Meaning Delayed2[1:0] Delayed1[1:0] THOLD Reserved DisTHOLD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x12 Function VIN UVLO (update default value after power on) Meaning VOFF setting Reserved Reserved Reserved Reserved Reserved Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A B B B B
DSQ5115-QA-06 June 2021www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. MTP Page-2 I2C Register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x14 Function PWRON time Parameters Setting / PG delay Meaning START_TIME L_PRESS_TIME SHDN_PRESS PG_DLY Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x15 Function SHDN Control Meaning Reserved SHDN_ TIMING SHDN_DLYTIME Reserved PG_DLY_ 5ms_EN SHDN_ PRESS_ SHORT PWRON_ NORMOFF _EN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition B A A A A A A A 0x16 Function Powered Off conditions enable setting Meaning Reserved Reserved Reserved Reserved Reserved Reserved VINLV_ ENSHDN VINLV_ SEQ_EN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x2C Function PMU On/Off Sequence1 Meaning Buck2_Seq[3:0] Buck1_Seq[3:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x2D Function PMU On/Off Sequence2 Meaning Buck4_Seq[3:0] Buck3_Seq[3:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x2E Function PMU On/Off Sequence3 Meaning LDO2_Seq[3:0] LDO1_Seq[3:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x2F Function PMU On/Off Sequence4 Meaning LDO4_Seq[3:0] LDO3_Seq[3:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Reset Condition A Reset by MTP (Register 0x12 VOFF Setting). B Reset when VIN < 1.7V. I2C Register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x30 Function PMU On/Off Sequence5 Meaning LDO6_Seq[3:0] LDO5_Seq[3:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x31 Function PMU On/Off Sequence6 Meaning LDO8_Seq[3:0] LDO7_Seq[3:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x32 Function Soft-Start Control Meaning Reversed Reversed Soft-Start End Select @ MASK_GPIO = 1 Soft-Start Control Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x33 Function Buck Syn-Clock Control Meaning VCO_VRC VCO_DVS Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A 0x34 Function Buck Syn-Clock Spread Spectrum Control Meaning Reversed Reversed Reversed Reversed Reversed Reversed Reversed SSOSC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Condition A A A A A A A A
©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 4. MTP Code Table
DSQ5115-QA-06 June 2021 www.richtek.com ©Copyright 2021 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 6.900 7.100 0.272 0.280 D2 5.150 5.250 0.203 0.207 E 6.900 7.100 0.272 0.280 E2 5.150 5.250 0.203 0.207 e 0.400 0.016 L 0.350 0.450 0.014 0.018 W-Type 56L QFN 7x7 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2
DSQ5115-QA-06 June 2021www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Footprint Information P A xA yB xB y C D S xS y Tolerance Footprint Dimension (mm) Package Number of Pin