RTQ2071-QA RICHTEK | Alldatasheet
Document overview
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Technical content
Features
⚫ AEC-Q100 Grade 1 ⚫ FMEA Compliant Pin Placement and Protection Mechanisms ⚫ Three Step-Down Converters (HVBuck1, LVBuck2 and LVBuck3) Peak Current Mode PWM Operation Fixed Switching Frequency at 2.1MHz EMI Reduction with Spread Spectrum and Phase Shift HVBuck1 Input Voltage from 4V to 18.5V, Adjustable Output Voltage and Up to 2A Output Current LVBuck2 Input Voltage from 2.7V to 5V, Fixed Output Voltage and 1.5A Output Current LVBuck3 Input Voltage from 2.7V to 5V, Fixed Output Voltage and 750mA Output Current Pins Related to LVBuck2/LVBuck3 Allowable Floating if Channel Unused ⚫ Low Dropout Regulator (LDO) Input Voltage from 2.7V to 5V and 300mA Output Current 10 Adjustable Output Voltage Settings via RSET Pin High PSRR : 60dB at 100kHz, 40dB at 1MHz ⚫ Output Function Sequence Control for External Power IC via SEQOUT (RTQ2071A-QA) Power Status Indication via PG (RTQ2071B-QA) ⚫ 10 Flexible Power Sequence Settings via SEQ Pin ⚫ Small Form Factor WETD-VQFN-16L 3x3 Wettable Flanks Package
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023
Applications
⚫ Automotive Camera Modules Surround View Camera Front View Camera Rear View Camera Dash Cam DVR Driver Monitoring System Cabin Monitor eMirror Marking Information SB= : Product Code YMDNN : Date Code RTQ2071AGQVT-QA-11 SB=YM DNN SA= : Product Code YMDNN : Date Code RTQ2071BGQVT-QA-11 SA=YM DNN Pin Configuration (TOP VIEW) BOOT SW1 AGND VIN RSET SEQOUT VOUT3 SEQ VOUT2 PVD23 SW2 SW3 FB1 PVCC LDOOUT LDOIN 13141516 8765 PGND WETD-VQFN-16L 3x3 (RTQ2071A-QA) BOOT SW1 AGND VIN RSET PG VOUT3 SEQ VOUT2 PVD23 SW2 SW3 FB1 PVCC LDOOUT LDOIN 13141516 8765 PGND WETD-VQFN-16L 3x3 (RTQ2071B-QA)
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Simplified Application Circuit FB1 SW1 VINVIN PVD23 VOUT2 SW2 VOUT3 SW3 LDOIN LDOOUT * SEQOUT/ PG VOUT_HV1 BOOT PGND VOUT_HV1 * VSEQOUT/ VPG RTQ2071A-QA RTQ2071B-QA CIS IOVDD AVDD DVDD * SEQOUT pinout is for RTQ2071A-QA; PG pinout is for RTQ2071B-QA. Functional Pin Description Pin No. Pin Name Pin Function 1 AGND Analog ground. 2 VIN Supply voltage input of HVBuck1. Connect a 4.7F or larger decouple ceramic capacitor between this pin and ground. 3 SW1 HVBuck1 switch node. 4 BOOT Bootstrap capacitor connection pin for HVBuck1. Connect a 0.1F ceramic capacitor between this pin and SW1. 5 VOUT2 Output voltage feedback input of LVBuck2. Directly connect the output capacitor node to this pin for better regulation. 6 SW2 LVBuck2 switch node. 7 PVD23 Supply voltage input of LVBuck2 and LVBuck3. Connect a 4.7F or larger decouple ceramic capacitor between this pin and ground. 8 SW3 LVBuck3 switch node.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Pin No. Pin Name Pin Function 9 VOUT3 Output voltage feedback input of LVBuck3. Directly connect the output capacitor node to this pin for better regulation. 10 SEQ Power sequence selection. SEQOUT Sequence control output with open drain structure for external power IC. (RTQ2071A-QA) PG Power status indication pin with open drain structure for HVBuck1, LVBuck2, LVBuck3 and LDO. PG at high state indicates all outputs work well. (RTQ2071B-QA) 12 RSET LDO output voltage selection. 13 LDOOUT LDO output. Connect a 2.2F ceramic decouple capacitor between this pin and ground. 14 LDOIN Supply voltage input of LDO. Connect a 2.2F or larger decouple ceramic capacitor between this pin and ground.
15 PVCC
Internal analog power output. Connect a 1μF ceramic decouple capacitor between this pin and ground. Note additional external loading on this pin is forbidden. 16 FB1 Output voltage feedback input of HVBuck1. (Exposed Pad) PGND IC thermal pad and power ground. It must connect to main ground plane for proper operation.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Functional Block Diagram RTQ2071A-QA PVD23 VOUT2 LDOOUT LDOIN VIN PVCC SW1 FB1 SEQOUT RSET SEQ SW3SW2 VOUT3 AGND VREF, IBIAS, OSC, OTP BOOT PGND Pre-Regulator LVBuck2 Driver Control LDO Driver Control HVBuck1 Driver Control LVBuck3 Driver Control SEQOUT Control Control Logic PVD23 POR/ UVLO VIN Sequence/ LDO Output Voltage Control CH Protection UVP, OVP, OCP, Input OVP RTQ2071B-QA LDOOUT LDOIN VIN PVCC SW1 FB1 PG RSET SEQ SW3SW2 VOUT3 VREF, IBIAS, OSC, OTP BOOT Pre-Regulator LVBuck2 Driver Control LDO Driver Control HVBuck1 Driver Control LVBuck3 Driver Control PG Control Control Logic PVD23 POR/ UVLO VIN Sequence/ LDO Output Voltage Control PVD23 VOUT2 CH Protection UVP, OVP, OCP, Input OVP AGND PGND
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Operation The RTQ2071A -QA/RTQ2071B-QA is a highly integrated power-management integrated circuit (PMIC) for automotive camera system, which includes three step-down converters (CH1 HVBuck1, CH2 LV Buck2, CH3 LVBuck3) and one generic LDO (CH4 LDO). System Under-Voltage Protection and Over-Voltage Protection The RTQ2071A -QA/RTQ2071B-QA stops operating if VIN voltage falls below the Under -Voltage Lock Out level (UVLO_L). There is a typical 500mV hyster esis implemented to avoid unstable on/ off behaviors. The shift values of UVLO_H and UVLO_L both toward to the same direction. (To positive or negative at the same time.) The device is initialized in its default state after VIN voltage recoverin g from UVLO_ H. When V IN voltage reaches the Over -Voltage Protection level, the step-down converters, LDO and SEQOUT (RTQ2071A-QA) are disabled immediately. Then the IC enters into latch off state and only can re -start with VIN ON/OFF. Meanwhile, the PG status will be also set to 0V to indicate IC fault condition. Thermal Protection The RTQ2071A -QA/RTQ2071B-QA features an over - temperature protection (OTP). When the junction temperature is higher than 160°C typical value, OTP is triggered to disable all outputs and the device enters into a latch off state. When the RTQ2071A -QA/ RTQ2071B-QA recovers from OTP, the device only can re-start with VIN ON/OFF. Pre-Regulator The device integrates a 4.45V linear regulator (PVCC) supplied by VIN to provide power to the internal circuitry. The PVCC can be used as the RSET and SEQ pull -up supply but it is “NOT” allowed to power other device or circuitry. A 1 F decoupling capacitor must be connected between PVCC and AGND to filter the noise and it needs to be placed as close as po ssible to the PVCC pin. Peak Current Mode Control The three step-down converters utilize the peak current mode control. An internal oscillator initiates turn -on of the high-side MOSFET switch. At the beginning of each clock cycle, the internal high -side MOSFET switch turns on, allowing current to ramp up in the inductor. With comparisons of the inductor peak current signal during high -side MOSFET switch on interval and the internal compensation signal derived from the sensed feedback voltage with referenc e voltage, the high -side MOSFET switch is turned off and inductor current continues to flow through the low-side MOSFET switch. This cycle repeats at the next clock cycle. In this way, the regulated inductor current controls duty -cycle and output voltage of the converter. Spread-Spectrum Operation Due to the periodicity of the switching signal, the energy concentrates in one particular frequency and its harmonics. The energy is radiated and possible to result in a potent ial EMI issue. The RTQ2071A -QA/ RTQ2071B-QA equips a spread -spectrum function to meet CISPR and automotive EMI compliances. The spread-spectrum function is implemented by a pseudo random sequence and uses +6% spread of the switching frequency. For example, when the switching frequency typical value is 2.1MHz, the frequency range varies from 2.1MHz to 2.226MHz. Therefore, the RTQ2071A-QA/RTQ2071B-QA can guarantee that the 2.1MHz switching frequency does not drop into the 1.8MHz AM band limit. Phase-Shifted Operation The RTQ2071A -QA/RTQ2071B-QA supports phase shift operations among the step -down converters for further easing the simultaneous switching energy radiation quantity. The internal clock is automatically shifted to different respective sub -clocks for step-down converters. For example, when two step -down converters application, the beginning turn -on time between two high -side MOSFETs will have a 180 - degree phase difference. Likewise, a 120 -degree phase difference when three step-down converters.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. do not affect the device operation. good output (PG) to monitor the output voltage status. pull-up resistor from SEQ pin to an external voltage. Table 1. Unused Channel Pin Connection
5 VOUT2 Floating
6 SW2 Floating
7 PVD23 Connect to a fixed
8 SW3 Floating
9 VOUT3 Floating
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Absolute Maximum Ratings (Note 1) ⚫ VOUT2, PVD23, VOUT3, SEQ, SEQOUT (RTQ2071A-QA), ⚫ Power Dissipation, PD @ TA = 25C ⚫ Package Thermal Resistance (Note 2) ⚫ ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)
Electrical Characteristics
(TA = TJ = −40C to 125C, VIN = 6V, VOUT_HV1 = 3.6V, VOUT_LV2 = 1.1V, VOUT_LV3 = 1.8V, VOUT_LDO = 3.3V, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit System Under-Voltage Lockout Threshold UVLO_H VIN rising 3.6 3.8 4 V UVLO_L VIN falling 3.15 3.3 3.45 V Input Over-Voltage Protection VIN_OV 18.6 20 21.5 V CH1 HVBuck1 Input Voltage Range VIN 4 -- 18.5 V Output Voltage Range VOUT_HV1 Buck mode operation. Switching frequency, minimum on time and minimum off time need to be considered. 2.7 -- 5 V
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Output Feedback Voltage Accuracy VFB1 0.788 0.8 0.812 V Switching Frequency fSW_HV1 1.89 2.1 2.31 MHz Spread-Spectrum Range SS_HV1 -- 6 -- % Switching Minimum On Time tON_MIN_HV1 -- -- 55 ns Switching Minimum Off Time tOFF_MIN_HV1 -- -- 50 ns High-Side MOSFET On Resistance RON_HS_HV1 From VIN pin to SW1 pin 115 210 340 m Low-Side MOSFET On Resistance RON_LS_HV1 From SW1 pin to PGND pin 40 110 200 m Inductor Peak Current Limit ICL_PK_HV1 2.4 3 3.6 A Inductor Valley Current Limit ICL_VL_HV1 -- 2.7 -- A Negative Inductor Peak Current Limit ICL_NPK_HV1 1 2.5 4 A Output Discharge Resistor RDIS_HV1 220 270 360 Output Under-Voltage Falling Threshold UVP_F_HV1 40 50 60 % Output Feedback Over-Voltage Rising Threshold OVP_R_HV1 -- 110 -- % CH2 LVBuck2 (VIN_PVD23 = 3.6V) Input Voltage Range VIN_PVD23 2.7 -- 5 V Output Voltage VOUT_LV2 -- 1.1 -- V Output Voltage Accuracy VOUT_ACC_LV2 −1.5 -- 1.5 % Switching Frequency fSW_LV2 1.89 2.1 2.31 MHz Spread-Spectrum Range SS_LV2 -- 6 -- % Switching Minimum On Time tON_MIN_LV2 -- -- 44 ns High-Side MOSFET On Resistance RON_HS_LV2 From PVD23 pin to SW2 pin 110 150 215 m Low-Side MOSFET On Resistance RON_LS_LV2 From SW2 pin to PGND pin 60 90 145 m Inductor Peak Current Limit ICL_PK_LV2 1.8 2.2 2.6 A
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Parameter Symbol Test Conditions Min Typ Max Unit Inductor Valley Current Limit ICL_VL_LV2 -- 1.8 -- A Negative Inductor Peak Current Limit ICL_NPK_LV2 0.7 1.7 2.9 A Output Discharge Resistor RDIS_LV2 6 9 14 Output Under-Voltage Falling Threshold UVP_F_LV2 40 50 60 % Output Over-Voltage Rising Threshold OVP_R_LV2 -- 120 -- % Output Over-Voltage Falling Threshold OVP_F_LV2 -- 110 -- % Input Over-Voltage Rising Threshold OVP_IN_R_LV2 5.35 5.8 6.25 V Input Over-Voltage Hysteresis OVP_IN_HYS_LV2 VIN_PVD23 falling -- 580 -- mV CH3 LVBuck3 (VIN_PVD23 = 3.6V) Input Voltage Range VIN_PVD23 2.7 -- 5 V Output Voltage VOUT_LV3 -- 1.8 -- V Output Voltage Accuracy VOUT_ACC_LV3 −1.5 -- 1.5 % Switching Frequency fSW_LV3 1.89 2.1 2.31 MHz Spread-Spectrum Range SS_LV3 -- 6 -- % Switching Minimum On Time tON_MIN_LV3 -- -- 44 ns High-Side MOSFET On Resistance RON_HS_LV3 From PVD23 pin to SW3 pin 240 310 440 m Low-Side MOSFET On Resistance RON_LS_LV3 From SW3 pin to PGND pin 170 230 360 m Inductor Peak Current Limit ICL_PK_LV3 0.96 1.2 1.44 A Inductor Valley Current Limit ICL_VL_LV3 -- 1.08 -- A Negative Inductor Peak Current Limit ICL_NPK_LV3 0.7 1.7 2.9 A Output Discharge Resistor RDIS_LV3 7 10 15 Output Under-Voltage Falling Threshold UVP_F_LV3 40 50 60 %
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Output Over-Voltage Rising Threshold OVP_R_LV3 -- 120 -- % Output Over-Voltage Falling Threshold OVP_F_LV3 -- 110 -- % Input Over-Voltage Rising Threshold OVP_IN_R_LV3 5.35 5.8 6.25 V Input Over-Voltage Hysteresis OVP_IN_HYS_LV3 VIN_PVD23 falling -- 580 -- mV CH4 LDO (VIN_LDO = 3.6V) Input Voltage Range VIN_LDO 2.7 -- 5 V Output Voltage Range VOUT_LDO VOUT_LDO setting via RSET 1.8 -- 3.5 V Output Voltage Accuracy VOUT_ACC_LDO VIN_LDO - VOUT_LDO > 0.3V, IOUT_LDO = 0mA to 300mA −1.5 -- 1.5 % Maximum Output Current IOUT_MAX_LDO 300 -- -- mA Dropout Voltage VDROP_300_LDO IOUT_LDO = 300mA (Note 5) -- -- 300 mV VDROP_150_LDO IOUT_LDO = 150mA (Note 5) -- -- 150 Output Current Limit ICL_LDO 345 450 555 mA Output Discharge Resistor RDIS_LDO 48 76 104 Output Under-Voltage Falling Threshold UVP_F_LDO 30 40 50 % Output Over-Voltage Rising Threshold OVP_R_LDO -- 125 -- % Output Over-Voltage Falling Threshold OVP_F_LDO -- 110 -- % Input Over-Voltage Rising Threshold OVP_IN_R_LDO 5.35 5.8 6.25 V Input Over-Voltage Hysteresis OVP_IN_HYS_LDO VIN_LDO falling -- 500 -- mV PVCC (Note 6) Internal Regulator Output Voltage VOUT_PVCC 4.33 4.58 4.83 V Over-Current Limit ICL_PVCC 150 -- 300 mA SEQOUT (RTQ2071A-QA) Output Low Voltage Current into SEQOUT pin equal to 2mA -- -- 200 mV
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Parameter Symbol Test Conditions Min Typ Max Unit Input Leakage Current ILEAK_SEQOUT 1.8V applied on SEQOUT pin -- -- 1 A Power Good (RTQ2071B-QA) Pull Down Voltage VOUT_L_PG Current into PG pin equal to 5mA -- -- 200 mV Input Leakage Current ILEAK_PG 1.8V applied on PG pin -- -- 1 A Timing Soft-Start Time tSS_HV1 Time from VOUT_HV1 0% rise to 90% of target value, no load 500 1000 1500 tSS_LV2 Time from VOUT_LV2 0% rise to 90% of target value, no load 500 1000 1500 tSS_LV3 Time from VOUT_LV3 0% rise to 90% of target value, no load 500 1000 1500 tSS_LDO Time from the previous turn on channel's output voltage reaching 90% of target value to VOUT_LDO rise to 90% of target value. 200 700 1100 PG Delay Time tDLY_PG (RTQ2071B-QA) 9 10 11 ms System Characteristics The following specifications are guaranteed by design and are not performed in production testing. (TA = TJ = −40C to 125C, Parameter Symbol Test Conditions Min Typ Max Unit System Over-Temperature Protection OTP -- 160 -- C Over-Temperature Protection Hysteresis OTP_H -- 20 -- C CH1 HVBuck1 Maximum Output Current IOUT_MAX_HV1 2 -- -- A Load Regulation VLOAD_REG_HV1 IOUT_HV1 = 0A to 2A -- -- 0.1 %/A Line Regulation VLINE_REG_HV1 VIN = 5V to 18.5V, IOUT_HV1 = 2A -- -- 1 % Load Transient VLOAD_TRAIN_HV1 IOUT_HV1 = 10mA to 500mA to 10mA, 1s −150 -- 150 mV Line Transient VLINE_TRAIN_HV1 VIN = 5V to 18.5V to 5V, 100s, IOUT_HV1 = 10mA/500mA −50 -- 50 mV Output Ripple VRIPPLE_HV1 Peak to peak in one switching cycle -- -- 20 mVpp
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit CH2 LVBuck2 (VIN_PVD23 = 3.6V) Maximum Output Current IOUT_MAX_LV2 1.5 -- -- A Load Regulation VLOAD_REG_LV2 IOUT_LV2 = 0A to 1.5A -- -- 0.1 %/A Line Regulation VLINE_REG_LV2 VIN_PVD23 = 2.7V to 5V, IOUT_LV2 = 1.5A -- -- 1 % Load Transient VLOAD_TRAIN_LV2 IOUT_LV2 = 10mA to 500mA to 10mA, 1s −50 -- 50 mV Line Transient VLINE_TRAIN_LV2 VIN_PVD23 = 3V to 5V to 3V, 50s, IOUT_LV2 = 10mA/1A −50 -- 50 mV Output Ripple VRIPPLE_LV2 Peak to peak in one switching cycle -- -- 10 mVpp CH3 LVBuck3 (VIN_PVD23 = 3.6V) Maximum Output Current IOUT_MAX_LV3 750 -- -- mA Load Regulation VLOAD_REG_LV3 IOUT_LV3 = 0A to 750mA -- -- 0.1 %/A Line Regulation VLINE_REG_LV3 VIN_PVD23 = 2.7V to 5V, IOUT_LV3 = 750mA -- -- 1 % Load Transient VLOAD_TRAIN_LV3 IOUT_LV3 = 10mA to 300mA to 10mA, 1s −50 -- 50 mV Line Transient VLINE_TRAIN_LV3 VIN_PVD23 = 3V to 5V to 3V, 50s, IOUT_LV3 = 10mA/300mA −50 -- 50 mV Output Ripple VRIPPLE_LV3 Peak to peak in one switching cycle -- -- 10 mVpp CH4 LDO (VIN_LDO = 3.6V) Power Supply Rejection Ratio PSRR_LDO IOUT_LDO = 100mA, f = 100kHz -- 60 -- dB IOUT_LDO = 100mA, f = 1MHz -- 40 -- Output Noise Voltage eN_LDO IOUT_LDO = 100mA, f = 100Hz to 100kHz -- 60 -- V Load Transient VLOAD_TRAIN_LDO IOUT_LDO = 10mA to 200mA to 10mA, 1s −25 -- 25 mV Line Transient VLINE_TRAIN_LDO All VOUT_LDO, VIN_LDO step 600mV, LDO not in dropout condition, 10s, IOUT_LDO = 1mA/300mA −25 -- 25 mV Component Requirement (Note 4) Effective Input Capacitance CIN_HV1 1.5 4.7 10 F CIN_PVD23 1.5 4.7 10 CIN_LDO 0.7 2.2 4 Effective Output Capacitance COUT_HV1 3.3 10 14 COUT_LV2 4.5 10 14 COUT_LV3 4.5 10 14 COUT_LDO 0.7 2.2 4
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Parameter Symbol Test Conditions Min Typ Max Unit Output Inductance LHV1 1 1.5 2 H LLV2 0.68 1 1.2 LLV3 0.68 1 1.2 Effective Boot Capacitance CBOOT 0.07 0.1 0.13 F Effective PVCC Capacitance CPVCC 0.3 1 1.4 F Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured under natural convection (still air) at T A = 25°C with the component mounted on a high effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. JC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precautions are recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. Note 6. PVCC is the pre-regulator output voltage only for internal circuitry. External loading on PVCC pin is forbidden.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Typical Application Circuit RTQ2071A-QA FB1 SW1 VIN PVCC VIN PVD23 VOUT2 SW2 VOUT3 SW3 LDOIN LDOOUT SEQOUT SEQ VOUT_LV2 1.1V VOUT_HV1 3.6V AGND 1.5μH 1μH 10μF 4.7μF 2.2μF 10μF 2.2μF RSET BOOT 0.1μF PGND 1μF VOUT_HV1 VOUT_HV1 4.7μF VOUT_LV3 1.8V 1μH 10μF VOUT_LDO 3.3V
11 VSEQOUT
VOUT_LV3 RTQ2071A-QA 13.7k 3.92k 10k R4* 330k R3* RTQ2071B-QA FB1 SW1 VIN PVCC VIN PVD23 VOUT2 SW2 VOUT3 SW3 LDOIN LDOOUT PG SEQ VOUT_LV2 1.1V VOUT_HV1 3.6V AGND 1.5μH 1μH 10μF 4.7μF 2.2μF 10μF 2.2μF RSET BOOT 0.1μF PGND 1μF VOUT_HV1 VOUT_HV1 4.7μF VOUT_LV3 1.8V 1μH 10μF VOUT_LDO 3.3V
11 VPG
VOUT_LV3 RTQ2071B-QA 13.7k 3.92k 10k R4* 330k R3*
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 2. Component List of Evaluation Board R3* : Resistor is adjustable with different LDO output voltages. R4* : Resistor is adjustable with different power on sequences.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Typical Operating Characteristics HVBuck1 Efficiency 100 0.01 0.1 1 10 Output Current (A) Efficiency (%) VOUT_HV1 = 3.6V VIN = 6V VIN = 9V VIN = 12V VIN = 18.5V HVBuck1 Load Regulation 3.58 3.60 3.62 3.64 3.66 3.68 Output Current (A) Output Voltage (V) VOUT_HV1 = 3.6V VIN = 6V VIN = 9V VIN = 12V VIN = 18.5V LVBuck2 Efficiency 100 0.01 0.1 1 10 Output Current (A) Efficiency (%) VOUT_LV2 = 1.1V VIN_PVD23 = 2.7V VIN_PVD23 = 3.1V VIN_PVD23 = 3.3V VIN_PVD23 = 3.6V VIN_PVD23 = 4.3V VIN_PVD23 = 5V LVBuck2 Load Regulation 1.094 1.096 1.098 1.100 1.102 1.104 Output Current (A) Output Voltage (V) VOUT_LV2 = 1.1V VIN_PVD23 = 2.7V VIN_PVD23 = 3.1V VIN_PVD23 = 3.3V VIN_PVD23 = 3.6V VIN_PVD23 = 4.3V VIN_PVD23 = 5V LVBuck3 Efficiency 100 0.01 0.1 1 Output Current (A) Efficiency (%) VOUT_LV3 = 1.8V VIN_PVD23 = 2.7V VIN_PVD23 = 3.1V VIN_PVD23 = 3.3V VIN_PVD23 = 3.6V VIN_PVD23 = 4.3V VIN_PVD23 = 5V LVBuck3 Load Regulation 1.794 1.796 1.798 1.800 1.802 1.804 Output Current (A) Output Voltage (V) VOUT_LV3 = 1.8V VIN_PVD23 = 2.7V VIN_PVD23 = 3.1V VIN_PVD23 = 3.3V VIN_PVD23 = 3.6V VIN_PVD23 = 4.3V VIN_PVD23 = 5V
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 LDO Load Regulation 3.305 3.310 3.315 3.320 3.325 3.330 Output Current (A) Output Voltage (V) VOUT_LDO = 3.3V VIN_LDO = 3.6V VIN_LDO = 3.9V VIN_LDO = 4.1V VIN_LDO = 4.5V VIN_LDO = 4.7V VIN_LDO = 5V LDO Dropout Voltage vs. Output Current 100 120 140 160 180 200 0 50 100 150 200 250 300 Output Current (mA) LDO Dropout Voltage (mV) VOUT_LDO = 3.3V 85°C 25°C −40°C LDO PSRR -100 -80 -60 -40 -20 100 1000 10000 100000 1000000 10000000 Frequency (Hz) PSRR (dB) VIN_LDO = 3.6V, VOUT_LDO = 3.3V, IOUT_LDO = 100mA 85°C 25°C −40°C LDO Output Noise 0.01 0.1 100 10 100 1000 10000 100000 Frequency (Hz) Noise (μV/sqrt (Hz)) VOUT_LDO = 3.3V, IOUT_LDO = 100mA 85°C 25°C −40°C HVBUCK1 (2V/Div) LVBUCK2 (0.5V/Div) SEQ9 Power On Time (1ms/Div) VIN = 6V, VOUT_HV1 = 3.6V, VOUT_LV2 = 1.1V, VOUT_LV3 = 1.8V, VOUT_LDO = 3.3V LVBUCK3 (0.5V/Div) LDO (1V/Div) LVBUCK3 (0.5V/Div) LDO (1V/Div) SEQ9 Power Off Time (4ms/Div) VIN = 6V, VOUT_HV1 = 3.6V, VOUT_LV2 = 1.1V, VOUT_LV3 = 1.8V, VOUT_LDO = 3.3V HVBUCK1 (2V/Div) LVBUCK2 (0.5V/Div)
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com
Application Information
Richtek’s component specification does not include the following information in the Application Information section. Thereby no warranty is given regarding its validity and accuracy. Customers should take responsibility to verify their own designs and reserve suitable design margin to ensure the functional suitability of their components and systems. Power Sequence Control The RTQ2071A-QA/RTQ2071B-QA supports 10 power-on sequences for the step-down converters and LDO via the dedicated resistor on SEQ pin. SEQ pin is not allowable at floating state and resistance selected out of range is not guaranteed to correct power-on sequence. In addition, there is only simultaneous power-off for all outputs. To fix the resistor selec tion on SEQ pin be fore enabling the device. Any change during the power on procedure is not guarantee to the correct power -on sequence. Below table shows the power -on sequence with its corresponding resistance. Table 3. Power-On Sequence Control channel continues to proceed power on sequence. (2) For RTQ2071B-QA, 1ms time interval will substitute the SEQOUT output. Below is the SEQ1 example.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 4. LDO Output Voltage decrease to the reset level. and the device only can re-start with VIN ON/ OFF. protection level, the devic e disables all channels.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 5. Protection
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Channel Type Threshold (Typ.) Deglitch Time (Typ.) Protection Reset and Threshold (Typ.) CH4 LDO UVP VOUT_LDO≤VOUT_L DO setting x 40% 5s Disable all channels then latch-off protection VIN ≤ 3.3V, then VIN ≥ 3.8V OVP VOUT_LDO ≥ VOUT_LDO x 125% 5ms Disable all channels VOUT_LDO ≤ VOUT_LDO x 110% with deglitch 5ms OCP IOUT_LDO ≥ 450mA 10ms Disable all channels then latch-off protection VIN ≤ 3.3V, then VIN ≥ 3.8V Input OVP VIN_LDO ≥ 5.8V 5s Disable all channels VIN_LDO ≤ 5.3V with deglitch 5s Input and Output Capacitor Selection ⚫ HVBuck1, LVBuck2 and LVBuck3 It is recommended at least a 4.7 F input capacitor with a 10 F output capacitor for step -down converters. The ripple voltage is an important index for choosing output capacitor. This portion consists of two parts. One is the product of ripple current with the ESR of the output capacitor, while the other part is formed by the charging and discharging process of the output capacitor. The output ripple can be calculated as below. ∆VOUTRipple = ∆VESR + ∆VOUT = ∆VESR + ∆IL 8 × COUT × fSW where ∆VESR = ICrms × RCESR ⚫ LDO Like any low dropout regulator, the external capacitor of the RTQ2071A-QA/RTQ2071B-QA must be carefully selected for regulator stability and performance. Using a 2.2 F capacitor for the LDO’s input and output is suitable. Additional capacitor paralleled on the output may get better noise suppression but also lead to higher input inrush current when LDO outputs. It should be taken into consideration carefully. Thermal Considerations The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula : PD(MAX) = (TJ(MAX) – TA) / JA where T J(MAX) is the maximum junction temperature; TA is the ambient temperature; and JA is the junction-to-ambient thermal resistance. For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditio ns is 150°C. The junction -to- ambient thermal resistance, JA, is highly package dependent. For a WETD -VQFN-16L 3x3 package, the thermal resistance, JA, is 30°C/W on a standard JEDEC 51 -7 high effective -thermal-conductivity four - layer test board. The maximum power dissipation at T A = 25°C can be calculated as below : PD(MAX) = (150°C – 25°C) / (30°C/W) = 4.16W for a WETD-VQFN-16L 3x3 package. The maximum power dissipation depends on the operating ambient temperature for the fixed T J(MAX) and the thermal resistance, JA. The derating curves in Figure 3 allows the designer to see the effect of rising ambient t emperature on the maximum power dissipation.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 3. Derating Curve of Maximum Power layout guidelines must be strictly followed. inductance from the PCB trace.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 4. PCB Layout Guide
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.650 1.750 0.065 0.069 E 2.950 3.050 0.116 0.120 E2 1.650 1.750 0.065 0.069 e 0.500 0.020 L 0.350 0.450 0.014 0.018 L1 0.075 0.175 0.003 0.007 WETD V-Type 16L QFN 3x3 Package
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Footprint Information Package Number of Pin Footprint Dimension (mm) Tolerance P Ax Ay Bx By C D Sx Sy
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Packing Information Tape and Reel Data Package Type Tape Size (W1) (mm) Pocket Pitch (P) (mm) Reel Size (A) Units per Reel Trailer (mm) Leader (mm) Reel Width (W2) Min./Max. (mm) (mm) (in) QFN/DFN 3x3 12 8 180 7 1,500 160 600 12.4/14.4 Tape Size W1 P B F ØJ H C, D and K are determined by component size. The clearance between the components and the cavity is as follows: - For 12mm carrier tape: 0.5mm max.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Tape and Reel Packing Step Photo/Description Step Photo/Description Reel 7” 3 reels per inner box Box A HIC & Desiccant (1 Unit) inside 12 inner boxes per outer box Caution label is on backside of Al bag Outer box Carton A Container Package Reel Box Carton Size Units Item Size(cm) Reels Units Item Size(cm) Boxes Unit QFN & DFN 3x3 7” 1,500 Box E 18.6*18.6*3.5 1 1,500 For Combined or Partial Reel.
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2071-QA-03 July 2023 Packing Material Anti-ESD Property Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications witho ut notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should ver ify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent righ ts of Richtek or its subsidiaries. Surface Resistance Aluminum Bag Reel Cover tape Carrier tape Tube Protection Band /cm2 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011
Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2071-QA-03 July 2023 www.richtek.com Datasheet Revision History Version Date Description Item 03 2023/7/31 Modify Ordering Information on P1 Electrical Characteristics on P9 Application Information on P19 Packing Information on P28, 29, 30