RTL8208B

RTL8208B-LF REALTEK | Alldatasheet

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SINGLE-CHIP OCTAL 10/100BASE-TX/FX PHY TRANSCEIVER DATASHEET Rev. 1.3

22 September 2006

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw RTL8208B-LF RTL8208BF-LF

Single-Chip Octal 10/100-TX/FX PHY Transceiver ii Track ID: JATR-1076-21 Rev. 1.3 COPYRIGHT ©2006 Realtek Semiconductor Corp. A ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular pu rpose. Realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the engineer’s reference and provides detailed programming information. Though every effort has been made to ensure th at this document is cu rrent and accurate, more information may have become available subsequent to the production of th is guide. In th at event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2003/12/16 Draft release. 1.1 2004/08/30 First approved release. 1.2 2004/08/31 Change bias resistor value to 2K ohm in Figure 22 on page 49. 1.3 2006/09/22 1. Add Fiber Application information for RTL8208BF-LF. 2. Modify Figure 1, page 3, and Figure 2, page 4. 3. Modify Table 1. Pin Assignments, on page 5. 4. Modify Table 5. RMII/SMII/SS-SMII Pins, page 7. 5. Corrected SMI Clock frequency from 25MHz to 2.5MHz (Table 6, page 9, section 7.1.1, page 26, and Table 40, page 52). 6. Recommend LEDMODE Pin be pulled high or pulled low (see Table 8, page 10). 7. Add LED rise and fall timing (Figure 16, page 42). 8. Change 2SB1188 to 2SB1182 (Figure 20 and Table 35, page 47). 9. Modify Table 36. Absolute Maximum Ratings, and Table 37. Operating Range, on page 50. 10. Add power startup internal sequence (section 9.6 Power Start Up & Internal Reset Sequence, page 56). 11. Modify section 10 Mechanical Dimensions, page 58. 12. Modify section 11 Ordering Information, page 59.

Single-Chip Octal 10/100-TX/FX PHY Transceiver iii Track ID: JATR-1076-21 Rev. 1.3 Table of Contents

Single-Chip Octal 10/100-TX/FX PHY Transceiver iv Track ID: JATR-1076-21 Rev. 1.3

Single-Chip Octal 10/100-TX/FX PHY Transceiver 1 Track ID: JATR-1076-21 Rev. 1.3 1. General Description The RTL8208B-LF and RTL8208BF-LF (jointly refe rred to as the RTL8208B(F)-LF) are single-chip highly integrated 8-port, 10Base-T/100Base-TX (FX) Ethernet transceivers implemented in 0.18µm CMOS technology. They are currently the world’s sma llest Octal-PHY chip package. Realtek patented removal of traditional SD pins in 100Base-FX (RTL8208BF-LF only) allow us to obt ain a lower pin- count. Flexible hardware settings are provided to configure the various operating modes of the chip. The RTL8208B(F)-LF provides 8 separa te and independent channels. Each channel consists of an RMII/SMII/SS-SMII interface-to-MAC controller, and hardware pins are used to configure the interface for RMII, SMII, or SS-SMII mode. In RMII mode, another hardware pin is used to set Port-Pair Loopback mode (PP-LPBK MODE, RTL8208BF-LF onl y), which can extend p hysical transmission length and perform physical media transport operations without a switch controller. A PECL (Pseudo Emitter Coupled Logic) receiver accep ts input from a fiber transceiver and directly passed to a clock recovery circuit for data/clock recovery. The chip utilizes an advanced CMOS process to meet low voltage and low power requirements . With on-chip DSP (Dig ital Signal Processing) technology, the chip provides excellent performance under all operating conditions. A built-in UTP cable tester diagnoses an open/short fault in an attached cable. The RTL8208B(F)-LF also features very low power consumption (maximum of 1.6W). Additionally, pin-outs are designed to provide optimized direct routing, which simplifies the layout work and reduces EMI noise issues.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 2 Track ID: JATR-1076-21 Rev. 1.3 2. Features „ Supports 8-port integrated physical layer and transceiver for 10Base-T and 100Base-TX „ Up to 8 ports support 100Base-FX (RTL8208BF-LF only) „ Reduced 100Base-FX (RTL8208BF-LF only) interface (patented) „ Robust baseline wander correction for improved 100Base-TX performance „ Complies with IEEE 802.3/802.3u „ IEEE 802.3u compliant auto negotiation for 10/100Mbps control „ Hardware controlled Flow control advertisement ability „ Supports RMII/SMII/SS-SMII interfaces „ Very low power consumption „ Supports Port-Pair Loopback mode (PP- LPBK mode, RTL8208BF-LF only) „ Supports two power reduction methods: ‹ Power saving mode (cable detection) ‹ Power down mode „ Power-on auto reset function eliminates the need for external reset circuits „ Crossover detection and auto correction „ Polarity detection and Auto Correction „ Flexible serial/scan LED display modes „ Cable tester for diagnosing open/short faults in attached cables „ 128-pin QFP package „ 1.8V/3.3V power supply „ 0.18µm, CMOS technology 3. Applications RTL8208B-LF „ Octal PHY for Fast Ethernet switch with twisted pair interface RTL8208BF-LF „ Octal PHY for Fast Ethernet switch with twisted pair interface and fiber capability

Figure 1. Pin Assignments (RTL8208B-LF) Note: Signal type codes are listed in section 5 Pin Descriptions, page 6. Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 1.

Figure 2. Pin Assignments (RTL8208BF-LF) Note: Signal type codes are listed in section 5 Pin Descriptions, page 6. Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 2.

Table 1. Pin Assignments

RTL8208BF-LF refer to Figure 2, page 4, for a graphical representation. Table 2. Media Connection Pins Table 3. Power and Ground Pins VDDAH 127 AP 3.3V Power to regulator. VDD 60, 90 DP 1.8V Power to digital core. VDDO 46, 68, 103 DP 3.3V Power to digital I/O.

Table 4. Miscellaneous Pins must be asserted low for at least 10ms. XI 119 I 25MHz Crystal input or 25MHz Oscillator clock input. The clock tolerance is ±50ppm. XO 120 O 25MHz Crystal output. If XI is 25MHz active, REFCLK is a 50MHz output. SMII/SS-SMII mode = 125MHz ±50ppm clock input. IBREF 125 AO Reference Bias Resistor. ground through an external 2KΩ resistor. VCTRL 126 AO V oltage control. Table 5. RMII/SMII/SS-SMII Pins I Transmit Data Input (bit 0). synchronously to REFCLK from the MAC. I Transmit Data Input (bit 1). SMII/SS-SMII: The I/O pin of TX_EN should not be used.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 8 Track ID: JATR-1076-21 Rev. 1.3 Pin Name Pin Type Description TX_EN[7:0] TX_CLK/TX_EN[4] 59, 67, 75, 81, 88, 96, 102, 110 I Transmit Enable. RMII: TX_EN indicates the di-bits on TXD is valid and is synchronous to REFCLK. SMII: The I/O pin of TX_EN should not be used. SS-SMII: TX_EN[4] of RMII is used as TX_CLK, which is a 125MHz clock input from MAC. The I/O pin of TX_EN should not be used. RXD0[7:0] 106 O (Pd) (Pd) (Pu) (Pd) (Pu) (Pd) (Pd) (Pd) Receive Data Input (bit 0). RMII: RXD0 and RXD1 output di-bits synchronously to REFCLK. SMII: RXD0 outputs data or in-band management information synchronously to REFCLK. In 100Mbps, RXD0 outputs a new 10- bit segment starting with SYNC. In 10Mbps, RXD0 must repeat each 10-bit segment 10 times. SS-SMII: RXD0 behaves as SMII except synchronous to RX_CLK instead of REFCLK and inputs a new 10-bit segment starting with RX_SYNC instead of SYNC. All pins driver capacity = 8mA RXD1[7:0] 105 O (Pd) (Pd) (Pd) (Pd) (Pd) (Pd) (Pu) (Pd) Receive Data Input (bit 1). RMII: RXD1 and RXD0 output di-bits synchronously to REFCLK. SMII/SS-SMII: The I/O pin of RXD1 should not be used. All pins driver capacity = 8mA CRS_DV[7:0] RX_SYNC/CRS_DV[3] RX_CLK/CRS_DV[4] 78 (16mA) O (Pu) (Pu) (Pu) (ND) (Pu) (Pu) (Pd) (Pd) Carrier Sense and Data Valid. RMII: CRS_DV is asynchronous to REFCLK and asserts when the medium is non-idle. SMII: CRS_DV[7:0] are not used and driven low. SS-SMII: CRS_DV[3] of RMII is used as RX_SYNC which is a sync signal used to delimit the 10-bit segment of RXD0 for all ports. CRS_DV[4] of RMII is used as RX_CLK, which is a 125MHz clock output. CRS_DV[7:5] and CRS_DV[2:0] are not used. All pins driver capacity = 8mA, except pin 78 (16mA). SYNC/ TX_SYNC 82 I (Pd) Sync/Transmit Synchronous. SMII: SYNC is a sync signal used to delimit a 10-bit segment of RXD0 and TXD0 for all ports. SS-SMII: TX_SYNC is a sync signal used to delimit the 10-bit segment of TXD0 for all ports.

Table 6. SMI (Serial Management Interface) up resistor is required (as specified in IEEE802.3u). operation of the RTL8208B(F)-LF. operation of the RTL8208B(F)-LF. Table 7. LED Pins In scan LED mode, SCAN_LED[7:0] is the Scan LED port enable. See section 7.9 LED Configuration, page 38. All pins driver capacity = 8mA. Link/Act, Spd) for each port. which outputs the reference clock for the serial LED signals. All pins driver capacity = 8mA.

Table 8. Mode Control Pins Select 10/100BaseTX or 100BaseFX (default = 2’b00). 2’b00: All 8 ports (port0~port7) are 10Base-T/100Base-TX. 2’b01: Port 7 is 100FX, other ports are 10Base-T/100Base-TX. 2’b11: All 8 ports are 100Base-FX. 2’b00: All 8 ports (port0~port7) are 10Base-T/100Base-TX. 2’b01: Port 7 and 5 are 100FX, others are 10Base-T/100Base-TX. 2’b11: All 8 ports are 100Base-FX.

105 I/O,

Port-Pair Loopback mode (default =0). Upon power-on reset, this pin is input to assert PP-LPBK MODE. regeneration/transformation repeater. PHY Address (default = 2’b01). We recommend using a resistor to pull up or pull down. 64, 56 I/O, (Pu,Pu) Select RMII/SMII/SS-SMII mode (default = 2’b11). We recommend using a resistor to pull up or pull down. 72 I/O, (Pu) Twisted Pair Pause capability (default =1). 85 I/O, (Pu) 100Base-FX Flow control capability (default =1). 70 I/O, (Pd) Twisted Pair Asymmetric Pause capability (default =0). 0: Without asymmetric flow control ability.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 11 Track ID: JATR-1076-21 Rev. 1.3 Pin Name Pin Type Description FX_ASY_PAUSE/ RXD1[4] 76 I/O, (Pd) 100Base-FX Asymmetric Flow control capability (default =0). Forces the asymmetric flow control capability of Reg.4.11 and Reg.5.11 upon power-on reset. 1: Asymmetric flow control ability in 100Base-FX 0: No asymmetric flow control ability in 100Base-FX Note: RTL8208BF-LF only. FX_DUPLEX/ CRS_DV[2] 93 I/O, (Pu) FX_DUPLEX: Force 100Base-FX Full Duplex Mode (default =1). This pin sets 100Base-FX duplex and affects those ports in 100Base-FX mode. 1: Full duplex 0: Half duplex Upon reset, this pin sets the default values of Reg.0.8 of those ports in 100Base-FX. Note: RTL8208BF-LF only. EN_AUTOXOVER/ RXD1[1] 97 I/O, (Pu) Enable Auto Crossover Detection (default =1). 1: Enable auto crossover detection 0: Disable auto crossover detection DISBLINK/ RXD1[2]

91 I/O, (Pd) Disable power-on/reset LED blinking: (default = 0)

1: Disable power-on LED blinking 0: Blink LED_BLNK_TIME/ RXD0[5] 71 I/O, (Pu) LED Blink Time (default =1). Controls the blinking speed of activity and collision LEDs. 1: 43ms (recommended to use external 10K pull up resistor) 0: 120ms LEDSEL/RXD1[3] 83 I/O, (Pd) LED Selection (default=1’b0). LEDSEL 1’b1: Scan LED 1’b0: Serial LED LEDMODE[1:0]/ RXD0[2:1] 92, 98 I/O, (Pd, Pd) LEDMODE[1:0] (default = 00). When using the RTL8208B(F)-LF LED solution , we recommend using an external resister to pull high or pull low. In Serial LED, LEDMODE[1:0] controls the forms of serial LED status. LEDMODE Mode Output 2’b00 3-bit serial stream Col/Fulldup, Link/Act, Spd 2’b01 2-bit serial stream Spd, Link/Act 2’b10 3-bit for Bi-color LED Col/Fulldup, Link/Act, Spd 2’b11 1-bit serial stream Link/Act/Spd In Scan LED, LEDMODE[1:0] controls the output of SCAN_STATUS[2:0]. LEDMODE Mode Output 2’b00 Mode 0 Col/Fulldup, Link/Act, Spd 2’b01 Mode 1 RX, TX, Link 2’b10 Mode 2 NC, Bi-color Link/Act/Spd, NC 2’b11 Reserved FRC_PARA_FULL/ RXD0[6]

63 I/O

(Pd) Force full duplex when link is established by parallel detection (default=0). 1: Force full duplex when link is established by parallel detection 0: Normal operation

In SMII, SEL_RXC control the clock to output delay of RXD. Recommended to set SEL_RXC=1. In SS-SMII, SEL_RXC, must be set to 1. In SMII, SEL_TXC control the clock to output delay of TXD. Recommended to set SEL_TXC=1. In SS-SMII, SEL_TXC, must be set to 1. Table 9. Test Pins

106 I/O,

Enable analog parameter write (default =0). DTEST1 122 I/O Reserved for internal use.

Table 10. Register Descriptions 2 PHY Identifier 1 Register. 3 PHY Identifier 2 Register. 4 Auto-Negotiation Advertisement Register. 5 Auto-Negotiation Link Partner Ability Register. 6 Auto-Negotiation Expansion Register.

Table 11. Register0: Control

0.14 Loopback This will loopback TXD to RXD and ignore all activity on

0.13 Spd_Sel When NWay is enabled, this bit reflects the auto negotiation

When NWay is disabled, this bit can be set by SMI*. When 100FX is enabled, this bit =1 (Read Only).

0.12 Auto Negotiation

This bit can be set through SMI (Read/Write). When 100FX is enabled, this bit =0 (Read only). 0.10 Isolate 1: Electrically isolat e the PHY from RMII/SMII/SS-SMII.

0.9 Restart Auto

0.8 Duplex Mode When NWay is enabled, this bit reflects the result of auto

*SMI: Serial Management Interface composed of MDC, MDIO, that allows the MAC to manage the PHY. Control register bits will have no effect until the reset proce ss has completed (approximately 1 µs). operation, it will return a ‘0’ when read.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 15 Track ID: JATR-1076-21 Rev. 1.3 Loopback – The RTL8208B(F)-LF may be placed into l oopback mode by writing a ‘1’ to bit 14. Loopback mode may be cleared either by writing a ‘0’ to bit 14 or by resetting the chip. When this bit is read, it will return a ‘1’ when the chip is in software-controlled loopback mode, otherwise it will return a ‘0’. Speed Selection – If auto negotiation is enabled, this bit has no effect on the speed selection. However, if auto negotiation is disabled usi ng software control, the operating speed of the RTL8208B(F)-LF can be forced by writing the appropr iate value to bit 13. Writing a ‘1’ to this bit forces 100Base-X operation, while writing a ‘0’ forces 10Base-T operation. When this bit is read, it returns the value of the software-controlled forced-speed selection only. Auto Negotiation Enable – Default is auto negotiation enabled fo r all TP ports, and disabled for FX ports. Auto negotiation can be disabled via software control by setting 0.12=0. Power Down – The RTL8208B(F)-LF supports a low power mode. Writing a ‘1’ will enable power down mode, and writing a ‘0’ will return the RTL8208B(F)-LF to normal operation. When read, this register will return a ‘1’ when in power down mode, and a ‘0’ during normal operation. Isolate – Each PHY may be isolated from its MII by wri ting a ‘1’ to bit 10. All MII outputs will be tri- stated and all MII inputs will be ignored. Since the MI I management interface is still active, the isolate mode may be cleared either by writing a ‘0’ to bit 10 or by resetting the chip. When this bit is read, it will return a ‘1’ when the chip is in isolate mode, and return a ‘0’ during normal operation. Restart Auto Negotiation – Bit 9 is a self-clearing bit that allows the auto negotiation process to be restarted, regardless of the status of the auto negotiation state machine. In order for this bit to have an effect, auto negotiation must be enabled. Writing a ‘1’ to this bit restarts auto negotiation. Writing a ‘0’ to this bit has no effect. When this bit is read, it will always return a ‘0’. Duplex Mode – By default, the RTL8208B(F)-LF powers up in half duplex mode . The chip can be forced into full duplex mode by writing a ‘1’ to bit 8 while auto negotiation is disabled. Half duplex mode can be resumed either by writing a ‘0 ’ to bit 8 or by resetting the chip . When NWay is enabled, this bit reflects the results of auto negotiation, and is in read -only mode. When NWay is disabled, this bit can be set through the SMI, and is in Read/Write mode. When 100FX is enabled, this bit can be set through the SMI or FX_DUPLEX pin and is in Read/Write mode. Reserved Bits – All reserved MII register bits must be written as ‘0’ at all times. Ignore the RTL8208B(F)-LF output when these bits are read.

Table 12. Register1: Status

1.6 MF Preamble

1.5 Auto-negotiate

1.4 Remote Fault 1: Remote fault indication from link partner has been

register 1 via the management interface.

1.3 Auto-Negotiation

1.2 Link Status 1: Link has not failed since previous read

If the link fails, this bit will be set to 0 until read. 1.1 Jabber Detect 1: Jabber detected. is supported only in 10Base-T mode.

1.0 Extended Capability 1: Extended register capable (permanently =1)

100Base_TX_FD – The RTL8208B(F)-LF is capable of operating in 100Base-TX full duplex mode. 100Base_TX_HD – The RTL8208B(F)-LF is capable of operating in 100Base-TX half duplex mode. 10Base_T_FD – The RTL8208B(F)-LF is capable of operating in 10Base-T full duplex mode. 10Base_T_HD – The RTL8208B(F)-LF is capable of operating in 10Base-T half duplex mode.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 17 Track ID: JATR-1076-21 Rev. 1.3 Reserved – Ignore the output of the RTL8208B(F)-LF when these bits are read. MF Preamble Suppression – Management Frame Preamble Suppr ession is permanently set in the RTL8208B(F)-LF, allowing subsequent MII management frames to be accepted, with or without the standard preamble pattern. Only two preamble bits are required between successive management commands, instead of the normal 32. However, a minimu m of 32 preamble bits ar e required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions (as defined in the IEEE 802.3u spec). Reads of this bit will always return a ‘1’. Auto-Negotiation Complete – Bit 5 will return a ‘1’ if the auto negotiation process has been completed and the contents of registers 4 and 5 are valid. Remote Fault – When the link partner detects a far-end fault, it sends a far-end indication stream pattern. When the RTL8208B(F)-LF receives this pattern, it sets Reg1.4=1. Auto-Negotiation Ability – The RTL8208B(F)-LF is capable of performing IEEE auto negotiation, and will return a ‘1’ when bit 4 is read, regardless of whether or not the auto negotiation function has been disabled. Link Status – The RTL8208B(F)-LF will return a ‘1’ on bit 2 when the link state machine is in Link Pass, indicating that a valid link has been established. Othe rwise, it will return ‘0’. When a link failure occurs after the link pass state has been entered, the Link Stat us bit will be latched at ‘0’ and will remain so until the bit is read. After the bit is read, it becomes ‘1’ if the Link Pass state has been entered again. Jabber Detect – The RTL8208B(F)-LF will return a ‘1’ on bit 1 if a jabber condition has been detected. After the bit is read, or if the chip is reset, it reve rts to ‘0’. This is for 10Base-T only. Jabber occurs when a predefined excessively long packet is detected in 10Base-T mode. When the duration of TX_EN exceeds the jabber timer (21ms), transmit and loopback functions are disabled and the COL LED starts blinking. After TX_EN goes low for more than 500ms, the transmitter is re-enabled and the COL LED stops blinking. Extended Capability – The RTL8208B(F)-LF supports extended capability registers and will return a ‘1’ when bit 0 is read. Several extended registers have been implemented in the RTL8208B(F)-LF.

32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. Table 13. Register2: PHY Identifier 1 Register Table 14. Register3: PHY Identifier 2 Register

Table 15. Register4: Auto-Negotiation Advertisement

4.15 Next Page 1: Next Page enabled

4.13 Remote Fault 1: Transmit remote fault

4.11 Asymmetric Pause 1: Advertises that the RTL8208B(F)-LF has asymmetric

4.10 Pause 1: Advertises that the RTL8208B(F)-LF has flow control

In 100FX mode, this bit is set by FX_PAUSE upon reset. Reserved – Reserved bits are R/W to allow for forward compatibility with future IEEE standards.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 20 Track ID: JATR-1076-21 Rev. 1.3 Asymmetric Pause – Setting this bit indicates the availability of Asymmetric Flow Control capabilities when full duplex operation is in use. This bit is used by one MAC to communicate Asymmetric Pause Capability to its Link Partner and has no effect on PHY operation. Pause –Setting this bit indicates the av ailability of Flow Control capab ilities when full duplex operation is in use. This bit is used by one MAC to communi cate Pause Capability to its Link Partner and has no effect on PHY operation. 100Base-T4 – Because the RTL8208B(F)-LF does not support the T4 function, any reads to this bit will return a ‘0’. 100Base-TX-FD – This bit advertises that the RTL8208B(F )-LF can operate in 10 0Base-TX full duplex mode. Writing a ‘0’ to this bit will suppress advertisi ng of this ability. Resetting the chip restores the default value. The default value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return the last written value, or the default value if no write has been completed since the last reset. 100Base-TX – This bit advertises that the RTL8208B(F )-LF can operate in 100Base-TX half duplex mode. Writing a ‘0’ to this bit will suppress advertising of this ability. Resetting the chip will restore the default value. The default value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return the last written value, or the default value if no write has been completed since the last reset. 10Base-T-FD – This bit advertises that the RTL8208B(F )-LF can operate in 10Base-T full duplex mode. Writing a ‘0’ to this bit will suppress advertising of this ability. Resetting the chip will restore the default value. The default value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return the last written value, or the default value if no write has been completed since the last reset. 10Base-T – This bit advertises that the RTL8208B(F)-LF can operate in 10Base-T half duplex mode. Writing a ‘0’ to this bit will suppress advertising of this ability. Resetting the chip will restore the default value. The default value is ‘1’ and writing a ‘1’ will set this bit to ‘1’. Reading this bit will return the last written value, or the default value if no write has been completed since the last reset. Selector Field – Bits 4:0 contain a fixed value of 00001, indicating that the ch ip belongs to the IEEE 802.3 class of PHY transceivers.

content changes after successful auto negotiation. Table 16. Register5: Auto-Negotiation Link Partner Ability

5.15 Next Page 1: Link partner desires Next Page transfer

5.14 Acknowledge 1: Link Partner acknowledges reception of FLP words

5.13 Remote Fault 1: Remote Fault indicated by Link Partner

5.11 Asymmetric Pause 1: Asymmetric Flow control supported by Link Partner

Partner ability (read only). In 100FX mode, this bit is set by FX_ASY_PAUSE or SMI.

5.10 Pause 1: Flow control supported by Link Partner

Partner ability (read only). In 100FX mode, this bit is set by FX_PAUSE or SMI.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 22 Track ID: JATR-1076-21 Rev. 1.3 Next Page – Bit 15 returns a value of ‘1’ when the Link Partner implements the Next Page function and has Next Page information that it wants to tr ansmit. However, since the RTL8208B(F)-LF does not implement the Next Page function, it ignores the Next Page bit, except to copy it to this register. Acknowledge – Bit 14 is used by auto negotiation to indica te that a device has successfully received its Link Partner’s Link Code Word. Remote Fault – Bit 13 returns a value of ‘1’ when the Link Partner signals that a fault has occurred. Reserved – Not defined by the IEEE 802.3 standard. Asymmetric Pause – Indicates that the Link Partner asymmetric pause bit is set. Pause – Indicates that the Link Partner pause bit is set. 100Base-T4 – Though the RTL8208B(F)-LF does not support th e T4 function, this bit reflects the T4 ability of the Link Partner. 100Base-TX-FD – This bit indicates that the Link Part ner can support 100Base- TX full duplex mode. This bit is cleared any time auto negotiation is restarted or the RTL8208B(F)-LF is reset. 100Base-TX – This bit indicates that the Link Partner can support 100Base-TX half duplex mode. This bit is cleared any time auto negotiation is restarted or the RTL8208B(F)-LF is reset. 10Base-T-FD – This bit indicates that th e Link Partner can support 10Base- T full duplex mode. This bit is cleared any time auto negotiation is restarted or the RTL8208B(F)-LF is reset. 10Base-T – This bit indicates that the Link Partner can support 10Base-T half duplex mode. This bit is cleared any time auto negotiation is restarted or the RTL8208B(F)-LF is reset. Selector Field – Bits 4:0 reflect the value of the Link Partne r’s selector field. These bits are cleared each time auto negotiation is restarted or the chip is reset, and generally reflects the value 0001, indicating that the Link Partner is an IEEE 802.3 device.

Table 17. Register6: Auto-Negotiation Expansion

6.4 Parallel Detection

6.3 Link Partner Next

6.2 Local Next Page

6.1 Page Received 1: A New Page has been received

6.0 Link Partner Auto-

In 100FX or auto-negotiation disabled, this bit is always 1. Reserved – Ignore the output of the RTL8208B(F)-LF when these bits are read. is reset to ‘0’ after the register is read, or when the chip is reset. has the same value as bit 15 of the Link Partner Ability Register. return a ‘0’ when bit 2 is read. checked, and acknowledged. This bit is cleared when the link is lost or the chip is reset. not comply with IEEE auto negotiation, the bit returns a value of ‘0’.

Table 18. Port 1 Register24: Cable Tester Control Register0

11 ENRTCT 1: Run cable test

ENRTCT – Set to ‘1’ to run the UTP cable test, and set to ‘0’ after completion of the cable test process. Table 19. Port1 Register29: Cable Tester Control Register1

14 SELTX 1: Cable test on TX pair

Table 20. Port1 Register30: Cable Status Register

15 RTCT_RDY 1: Cable test status is ready

14 Reserved RO 0

13:12 Status Cable tester status. Status and Distance are valid. Status – Cable test status is valid after completion of cable test process. These bits are valid after completion of the cable test process.

signals, MDIO and MDC, which allow the MAC controlle r to control and monitor the state of the PHY. MDC is a clock input for PHY to latch MDIO on its rising edge. The clock can run from DC to 2.5MHz. Table 21. SMI Read/Write Cycles Note1: *Z: high-impedance. During idle time, MDIO state is determined by an external 1.5KΩ pull-up resistor. regeneration /transformation repeater, so a switch controller is not necessary. In Table 22, ‘U’ means UTP port, ‘F’ means Fiber port. Table 22. Port Pair-Loop Back Mode (PP-LPBK) (RTL8208BF-LF Only)

Single-Chip Octal 10/100-TX/FX PHY Transceiver 27 Track ID: JATR-1076-21 Rev. 1.3 Since this configuration is a loopback connection, it us es full duplex only. Half duplex is not supported. The loopback-pair ports should be c onfigured to the same speed. A lthough this mode does not effect normal NWay mode, in order to keep each pair’s two ports at the same speed, there is an auto-detection scheme. This scheme specifies that if one port of th e pair is already linked, when the other port is linked later, the earlier link-on port will re-sta rt auto negotiation. When PP-LPBK mode is set, there are three requirements: it must be based upon RMII mode; no switch controller can be connected; and TX_EN[7:0] must be pulled down. 7.1.3. PHY Address Each transceiver in the RTL8208B(F)-LF has a unique PHY address for MII management. The address is set through the PHY address pins. The pins are latched at th e trailing end of a reset. Transceiver 1 will have the address AA000, where AA=PHYAD [4:3]. Each internal PHY address is AA000, AA001, AA010, AA011, AA100, AA101, AA110, AA111. Every time an SMI write or read operation is executed, the transceiver compares the PHY address with its own PHY address defin ition, and the operation is executed only when the addresses match. 7.1.4. Auto-Negotiation For 10/100Mbps TP ports, the RTL8208B(F)-LF default setup is Auto-Negotiation enabled. Setting Register 0.12=0 via an SMI write will disable Auto -Negotiation. For a 100FX port, Auto-Negotiation is always disabled. For an Auto-Negotiation enabled port, the RTL8208B (F)-LF will negotiate with its link partner to determine the speed and duplex status. The RTL8208B(F)-L F’s ability is advertised in Register 4. After Auto-Negotiation is finished, the link partner’s ability is stored in Register 5. If the link partner is Auto-Negotia tion disabled, the RTL8208B(F)-LF ente rs a parallel-detection state to identify the speed of the link partner. The RTL8208B(F)-LF will link at the same speed as the link partner, in half duplex mode if FRC_PARA_FULL=0 upon reset, or in full duplex mode if FRC_PARA_FULL=1 upon reset. Auto-Negotiation is also used to determine full-duplex fl ow control. Flow control ability is advertised in Register 4.10. The link partner’s flow control ability is stored in Re gister 5.10. See the following section for more information. 7.1.5. Full-Duplex Flow Control If hardware pins TP_PAUSE or FX_PAUSE are enable d at power-on reset, Register 5.10=1 and Register 4.10=1. Therefore, after reset is completed: When Auto-Negotiation is enabled -- Register 4.10 may be overwritten by the MAC, and Register 5.10 may be updated after NWay has completed. Register 5.10 is set as read-only for the MAC. When Auto-Negotiation is disabled -- Register 5.10 is set to R/W for the MAC through the SMI interface. If the SMI does not write to Register 5.10, the Register remains 5.10=1, which means hardware forced flow control is enabled.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 28 Track ID: JATR-1076-21 Rev. 1.3 7.2. Initialization and Setup 7.2.1. Reset The RTL8208B(F)-LF is initialized wh ile in the reset state. During reset, each transceiver is reset simultaneously. There are three ways to reset the RTL8208B(F)-LF: Power-on auto reset; hardware pin reset; and software reset. The internal power-on auto-r eset circuit can reset the chip while the reset pin is floating. The hardware reset signal must be asserted low for at least 10ms on the RESET# pin. A software reset is implemented by writing Register 0.15=1, which is self-clearing. 7.2.2. Setup and Configuration The operational modes of the RTL8208B(F)-LF can be c onfigured either by hardware pin (pulled high or low) upon reset, or by software programming vi a accessing the RTL8208B(F)-LF registers through the SMI (see section 5 Pin Descriptions, page 6 for details). 7.3. 10Base-T 7.3.1. Transmit Function When TX_EN is active, TXD from RMII/SMII/SS-SMII is serialized, Manche ster-encoded, and driven onto the network medium as a packet stream. An on-chip filtering and wave shaping circuit eliminates the need for external filtering. The transmit function is disabled when the link has failed or when the auto- negotiation process is in progress. 7.3.2. Receive Function The Manchester decoder converts the incoming serial st ream when the circuit de tects the signal, and the digital serial stream is then converted to 2-bit (RMII) or 1-bit (SMII/SS-SMII) data format. The preamble of the incoming stream is stripped off and regenerated. SFD is ge nerated into RXD once the incoming SFD is detected and data bits entering the elastic buffer are over threshold. 7.3.3. Link Monitor The 10Base-T link pulse detection circ uit continually monitors the RXIP /RXIN pins for the presence of valid link pulses. Auto-polarity is implemented to correct the detected reve rse polarity of RXIP/RXIN signal pairs. The 10Base-T link pulse detection circ uit constantly monitors the RXIP/RXIN pins for the presence of valid link pulses. Auto-polarity is implemented fo r correcting the detected reverse polarity of the RXIP/RXIN signal pairs.

Single-Chip Octal 10/100-TX/FX PHY Transceiver 29 Track ID: JATR-1076-21 Rev. 1.3 7.3.4. Jabber Jabber occurs when TX_EN is asserted for longer than 21ms. Both transmit and loopback functions are disabled once jabber has occurred. The MII Register 1.1 (Jabber detect) bit is set high until jabber disappears and the bit is read again. The Jabber f unction is supported in 10- Base-T only, and is not implemented in 100Base-TX. The collision LED of the corresponding port will blink while Jabber occurs. Jabber is dismissed after TX_EN remains low for at least 500ms. 7.3.5. Loopback Loopback mode can be achieved by writing to Register 0.14=1. Loopback mode routes transmitted data at the output of NRZ to the NRZI conversion module, back to the receiving path. This mode is used to check the device’s connections at the 5-bit symbol bus, and verify the operation of the Phase-Locked Loop (PLL). 7.4. 100Base-TX An internal 125MHz clock is generated by an on-chip PLL circuit to synchronize the transmit data or generate the clock signal for the incoming data stream. 7.4.1. Transmit Function Upon detection of TX_EN high, the RTL8208B(F)-L F converts RMII/SMII/SS-SMII TXD to a 5-bit code-group and substitutes J/K code-groups for the fi rst two code-groups (Start of Stream Delimiters (SSD)). As long as TX_EN is asserted high, 4B5B c oding continues for all data . At the end of TX_EN, T/R code-groups are appended to the last data field. These are stripped off at the remote receiving end. During the inter-packet gap, where TX_EN deasserte d, IDLE code-groups are transmitted for clocking purposes of the remote receiver. The 5-bit serial da ta stream is 4B5B coded and then scrambled, as defined by the TP-PMD Stream Cipher function, to flatten the power spectrum energy such that EMI effects are significantly reduced. The scrambled seed is unique for each port based on PHY addresses. After scrambling, the bit stream is driven onto the network media in the form of M LT-3 signaling. This multi- level signaling technology moves the power spectrum energy from high frequenc y to low frequency, which also benefits EMI emission. Scrambling is not implemented in 100Base-FX.

and ends toggling once the data in the elastic buffer has been dumped to RXD. Table 23. 4B/5B Coding *Treated as an invalid code (mapped to 0111) when received in data field.

enter the ‘Link Pass’ state and the transmit and receive functions will be enabled. 100Ω termination and a 1:1 transformer. resulting in potentially serious BLW. If BLW is not compensated for, packet loss will occur. SEL_TXFX[1:0], port 7 or port 6/7, or all eight ports can be configured for 100Base-FX operation. operate correctly, both sides of the connection should be set to the same duplex and flow control ability. Table 24. 100Base-FX UTP: 10Base-T/100Base-TX. FX: 100Base-FX. significantly reduces the pin count in this octal PHY. level MLT3. The data stream is not scrambled for fiber-optic transmission.

transceiver only operates in a 3.3V environment. Refer to Figure 22, page 49 for more information. Table 25. PECL DC Characteristics recovery circuit for data/clock recovery. Scrambling/de-scrambling is bypassed in 100Base-FX. In 100Base-FX mode, if the RTL8208BF-LF receive path detects a valid link word, it enters the link state. RTL8208BF-LF uses a reduced 100Base-FX interface. problems on the receive path. The FEFI mechanism is used only in 100Base-FX applications.

MODE[1:0] upon power-on reset, the RTL8208B(F)-LF operates in RMII mode (default). Table 26. RMII/SMII/SS-SMII Modes Table 27. RMII/SMII/SS-SMII Signals

Figure 3. RMII Signal Diagram

wakes up from power saving mode and operates in normal mode according to the result of the connection. Power saving mode is not supported when in 100FX operation. transmit/receive functions on that port. Table 30. Serial LED Mode

single LED package with two LEDs connected in parallel and with opposite polarities. Table 32. Bi-Color LED Figure 14. 3-Bit Bi-Color LED below, are controlled by LEDMODE[1:0] pins, which are latched upon reset. Table 33. Scan LED

00 Mode 0 Col/Fulldup, Link/Act, Spd

01 Mode 1 Rx, Tx, Link

10 Mode 2 for Bi-color LED NC, Bi-color Link/Act/Spd, NC

11 Reserved

Table 34. Scan LED Status Link/Act Link/Activity Indicator. Blinks when the corresponding port is transmitting or receiving. High for 100Mbps and low for 10Mbps. Col/Fulldup Collision/Full duplex Indicator. High for full duplex, low for half duplex. Blinks when collisions occur on the corresponding port. Bi-Color LED Link, Activity, and Speed Indicator. Its polarity depends on the Speed status. Blinks when the corresponding port is transmitting or receiving. RX High for receive activity. TX High for transmit activity.

Figure 17. External Circuit for Scan LED Mode 0

Figure 18. External Circuit for Scan LED Mode 1

Figure 19. External Circuit for Scan LED Mode 2

Single-Chip Octal 10/100-TX/FX PHY Transceiver 46 Track ID: JATR-1076-21 Rev. 1.3 7.10. Crossover Detection and Auto Correction During the link setup phase, the RTL8208B(F)-LF checks whether it receives active signals on each port in order to determine if a connection can be es tablished. In cases where the RTL8208B(F)-LF receiver data pin pair is connected to th e receiver data pin pair of the peer device, or vice versa, the RTL8208B(F)-LF will automatically cha nge its configuration to swap rece iver data pins with transmitter data pins. If a port is connected to a PC or NI C with MDI-X inte rface with a crossover cable, the RTL8208B(F)-LF will reconfigure the port to ensure proper connection. This effectively replaces the DIP switch commonly used for reconfiguring a port on a hub or switch. By pulling-up EN_AUTOXOVER, the RTL8208B(F)-LF iden tifies the type of connected cable and sets the port to MDI or MDIX. When switching to MDI mode, the RTL8208B(F)-LF uses TXOP/N as transmit pairs; when switching to MDIX mode, the RTL8208B(F)-LF uses RXIP/N as transmit pairs. The same is true for the receive pairs. This functi on is port-based. Pulling-down EN_AUTOXOVER disables this function and the R TL8208B(F)-LF operates in MD I mode, in which TXOP/N represents transmit pairs, and RXIP/N represents receive pairs. Note: IEEE 802.3 compliant forced mode 100M ports with Autoxover have link problems with NWAY (Auto-Negotiation) ports. It is recommended to NOT use Autoxover for forced 100M. 7.11. Polarity Detection and Auto Correction For better noise immunity and lower interference to ambient devices, the Ethern et electrical signal on a twisted pair cable is transmitted in differential form. That is, the signal is transmitted on two wires in each direction with inverse polarities (+/-). If wiring on the connector is fa ulty, or a faulty transformer is used, the two inputs to a transceiver may carry signals w ith opposite but incorrect polarities. As a direct consequence, the transceiver will not work properly. When the RTL8208B(F)-LF operates in 10Base-T mode, it automatically re verses the polarity of its two receiver input pins if it detects that the polarities of the incoming signals on the pins is incorrect. However, this feature is unnecessary when the RTL8208B(F)-LF is operating in 100Base-TX mode.

the stability of the 1.8V power significantly. Figure 20. Using a PNP Transistor to Transform 3.3V Into 1.8V Table 35. An Example Using Power Transistor 2SB1182 Note: Absolute maximum ratings (Ta=25°C). The cable tester (UTP cable only) determines the quality of the cable s, connectors, and terminations. magnitude of the reflection and the time it takes for th e reflection to come back are shown in registers.

Figure 21. 10Base-T/100Base-TX Application

Figure 22. 100Base-FX Application (RTL8208BF-LF only)

Table 36. Absolute Maximum Ratings Table 37. Operating Range Table 38. DC Characteristics

Single-Chip Octal 10/100-TX/FX PHY Transceiver 51 Track ID: JATR-1076-21 Rev. 1.3 Parameter Symbol Conditions Min Typical Max Units TTL Input High V oltage Vih 2 - - V TTL Input Low V oltage Vil - - 0.8 V TTL Input Current Iin -10 - 10 uA TTL Input Capacitance Cin - 3 - pF Output High V oltage Voh 2.6 - - V Output Low V oltage Vol - - 0.4 V Output Tristate Leakage Current |IOZ| - - 10 uA Transmitter, 100Base-TX (1:1 Transformer Ratio) TX+/- Output Current High IOH - - 40 mA TX+/- Output Current Low IOL 0 - - uA Transmitter, 10Base-T(1:1 Transformer Ratio) TX+/- Output Current High IOH - - 100 mA TX+/- Output Current Low IOL 0 - - uA Receiver, 100Base-TX RX+/- Common-mode Input V oltage - - 1.8 - V RX+/- Differential Input Resistance - - 2.5 - kΩ Receiver, 10Base-T Differential Input Resistance - - 2.5 - kΩ Input Squelch Threshold - - 340 - mV

Table 39. AC Characteristics Table 40. Digital Timing Characteristics

Table 41. RMII Receive Timing Figure 23. RMII Receive Timing

management becomes more critical. A method to estimate the possible Ta is outlined below. ambient air. This is an index of heat dissipation capability. A lower θja means better thermal performance. package top case. θjc is important when an external heat sink is attached on the package top. Figure 30. Cross-section of 128-Pin QFP Table 47. Thermal Operating Range Table 48. Thermal Resistances

Single-Chip Octal 10/100-TX/FX PHY Transceiver 58 Track ID: JATR-1076-21 Rev. 1.3 10. Mechanical Dimensions See the Mechanical Dimensions notes on the next page.

Min Typical Max Min Typical Max 1. Dimensions D 1 & E1 do not include mold protrusion. A - - 0.134 - - 3.40 2. Controlling dimension: Millimeter (mm).

23.2 BSC

20.00 BSC

17.20 BSC

14.00 BSC

L1 0.063 BSC 1.60 BSC CHECK DWG NO. θ 0° - 12° 0° - 12° REALTEK SEMICONDUCTOR CORP. Table 49. Ordering Information