RTL8211C-GR_08 REALTEK | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 59
Technical content
INTEGRATED 10/100/1000 GIGABIT ETHERNET TRANSCEIVER DATASHEET Rev. 1.1
11 January 2008
Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver ii Track ID: JATR-1076-21 Rev. 1.1 COPYRIGHT ©2008 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engi neer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary 1.0 2007/09/05 First release. 1.1 2008/01/11 Revised RTL8211CL pin 38 (Table 3, page 5). Revised RTL8211CL pin 34 (Table 6, page 6). Added section 6.8 LED Configuration, page 20. Removed MII timing diagram. Changed A VDD12/DVDD12 1.2V supply voltage to 1.0V . Revised Table 20, page 25. Revised Table 21, page 26. Added 100Base-T4 support (Table 25, page 29). Added Table 39, page 36.
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver iii Track ID: JATR-1076-21 Rev. 1.1 Table of Contents
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver iv Track ID: JATR-1076-21 Rev. 1.1
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 1 Track ID: JATR-1076-21 Rev. 1.1 1. General Description The Realtek RTL8211C(L) is a highly integrated Ethe rnet transceiver that complies with 10Base-T, 100Base-TX, and 1000Base-T IEEE 802.3 standards. It provides all the necessary physical layer functions to transmit and receive Ethernet packets over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. The RTL8211C(L) uses state-of-the-art DSP tec hnology and an Analog Front End (AFE) to enable high-speed data transmission and reception over UTP cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented in the RTL8211C(L) to provide robust transmission and reception capabilities at 10Mbps, 100Mbps, or 1000Mbps. Data transfer between MAC and PHY is via the Reduced Gigabit Media Independent Interface (RGMII) for 1000Base-T, and Media Independent Interface (MII) for 10Base-T/100Base-TX.
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 2 Track ID: JATR-1076-21 Rev. 1.1 2. Features 1000Base-T IEEE 802.3ab Compliant 100Base-TX IEEE 802.3u Compliant 10Base-T IEEE 802.3 Compliant IEEE 802.3 Compliant RGMII/MII Supports Auto-Negotiation Supports Parallel Detection Crossover Detection & Auto-Correction Automatic polarity correction Transmit wave-shaping DSP processing Internal hybrids for 1000Base-T Baseline Wander Correction Supports half/full duplex operation Transmission rate up to 1Gbps over industry standard CAT.5 UTP cable with BER less than -10 in 1000Base-T The design transceiver capability target is up to 120m for CAT.5 cable in 1000Base-T Supports 3.3V or 2.5V signaling for RGMII Supports 25MHz external crystal or OSC Provides 125MHz clock source for MAC Provides 6 network status LEDs (RTL8211C) Provides 3 network status LEDs (RTL8211CL) Supports Link Down power saving Built-in Switching regulator 64-pin QFN (RTL8211C-GR) 48-pin LQFP (RTL8211CL-GR)) 0.11µm process with very low power consumption 3. System Applications Network Interface Adapter, MAU (Media Access Unit), CNR (Communication and Network Riser), ACR (Advanced Communication Riser), Ethernet hub, and Ethernet switch. In addition, it can be used in any embedded system with an Ethernet MAC that needs a UTP physical connection.
Figure 1. RTL8211C Pin Assignments (64-Pin QFN) Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.
Figure 2. RTL8211CL Pin Assignments (48-Pin LQFP) ‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
and on page 3 (RTL8211CL) for a graphical representation. Table 1. Transceiver Interface and is the transmit pair in 10Base-T and 100Base-TX. receive pair in 10Base-T and 100Base-TX. pair, and is the receive pair in 10Base-T and 100Base-TX. transmit pair in 10Base-T and 100Base-TX. In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair. Table 2. Clock Input/output of 25MHz clock reference. 41 32 CLK125 O 125MHz reference clock generated from internal PLL.
Table 3. RGMII/MII Data is transmitted from MAC to PHY via TXD[3:0]. 29 27 TXCTL I Receive control signal from the MAC. Data is transmitted from PHY to MAC via RXD[3:0]. 16 13 RXCTL O Transmit Control Signal to the MAC. 19 16 TXDLY I RGMII Transmit Clock Timing Control. 43 38 RXDLY I RGMII Receive r Clock Timing Control. Table 4. Management Interface 30 30 MDC I Management Data Clock. 31 31 MDIO IO Input/Output of Management Data. Table 5. Reset 38 29 PHYRSTB I Hardware Reset. Active low.
Table 6. Mode Selection Note: See section 6.3 Hardware Configuration, page 10 for details. Table 7. LED Indication Note: See section 6.8 LED Configuration, page 20 for details. Table 8. Regulator and Reference External Resistor Reference. 63 44,45 VDDREG Power 3.3V power supply for switching regulator. 1 48 REG_OUT O Switching regulator 1.0V output. Connect to a 4.7µH inductor. 5 3 FB12 I Feedback pin for switching regulator. 58 39 ENSWREG I 3.3V: Enable switching regulator. 0V: Disable switching regulator.
Table 9. Power and Ground 18, 23, 49 15, 21, 37 DVDD33 Power RGMII Interface I/O voltage =3.3V . 36, 45 28, 36 DVDD12 Power Digital Power. 1.0V . 8, 60 6, 41 A VDD33 Power Analog Power. 3.3V . E-Pad 7, 20, 33, 47 GND Ground Ground. Mechanical Dimensions, page 49. Table 10. Not Connected NULL NC NC 0: Not Connected.
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 8 Track ID: JATR-1076-21 Rev. 1.1 6. Function Description 6.1. Transmitter Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the RTL8211C(L) is capable of operating at 10/100/1000Mbps link speed over standard CAT.5 UTP cable and CAT.3 UTP cable (10Mbps). 6.1.1. RGMII (1000Mbps) Mode The RTL8211C(L)’s PCS layer receives data bytes from the MAC through the RGMII interface and performs the generation of continuous code-groups through 4D-PAM5 coding technology. Then those code groups are passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a D/A converter. 6.1.2. MII (100Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125MHz NRZ and NRZI signals. After that, the NRZI signal are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media. 6.1.3. MII (10Mbps) Mode The transmit 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. Then the 10Mbps serial data is converted into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter.
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 9 Track ID: JATR-1076-21 Rev. 1.1 6.2. Receiver 6.2.1. RGMII (1000Mbps) Mode Input signals from the media first pass through the on-chip sophisticated hybrid circuit to subtract the transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received signal is processed with state-of-the-art technology, such as adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5 decoding. Then, the 8-bit-wide data is recovered and is sent to the RGMII interf ace at a clock speed of 125MHz. The Rx MAC retrieves the packet data from the receive MII/RGMII interface and sends it to the Rx Buffer Manager. 6.2.2. MII (100Mbps) Mode The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz. 6.2.3. MII (10Mbps) Mode The received differential signal is converted into a Ma nchester-encoded stream first. Next, the stream is processed with a Manchester decoder, and is de-seria lized into 4-bit-wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz.
external pull-high or pull-low via resister is required. Table 11. CONFIG Pins vs. Configuration Register Table 12. Configuration Register Definition PHYAD sets the PHY address for the device. AN[1:0] Auto-Negotiation (NWay) Configuration. AN[1:0] controls the setting of Auto-Negotiation enable/disable, speed, and duplex setting.
In order to reduce the pin count on the RTL8211C(L), the LED pins are duplex with the PHY address pins. 4.7KΩ). If no LED indications are needed, the components of the LED path (LED+510Ω) can be removed. Figure 3. LED and PHY Address Configuration
up to 100Mbps operation, and the RGMII interface supports up to 1000Mbps operation. the PHY. TXD[3:0] and RXD[3:0] signals are used for date transitions. are used for date transitions on rising edge and on falling edge of clock. MDIO high during idle and turnaround. be at least one idle bit between operations. Table 13. Typical MDIO Frame Format
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 14 Track ID: JATR-1076-21 Rev. 1.1 6.6. Auto-Negotiation Auto-Negotiation is a mechanism to determine the fastest connection between two link partners. For copper media applications, it was introduced in IEEE 802.3u fo r Ethernet and Fast Ethernet, and then in IEEE 802.3ab to address extended functions for Gigabit Ethernet. It performs the following:
- Auto-Negotiation Priority Resolution
- Auto-Negotiation Master/Slave Resolution
- Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution
- Crossover Detection & Auto-Correction Resolution Upon de-assertion of a hardware reset, the RTL8211C (L) can be configured to have auto-negotiation enabled, or be forced to operate in 10Base-T, 100Base-TX, or 1000Base-T mode via the CONFIG pins (see section 6.3 Hardware Configuration, page 10). If th e RTL8211C(L) is configured to operate only in 1000Base-T mode, then auto-negotiation is still enabled with only 1000Base-T mode advertised. The auto-negotiation process is initiated automatically upon any of the following:
- Power-up
- Hardware reset
- Software reset (register 0.15)
- Restart auto-negotiation (register 0.9)
- Transition from power down to power up (register 0.11)
- Entering the link fail state
Table 14. 1000Base-T Base and Next Pages Bit Assignments D[12:5] A[7:0] Tec hnology Ability Field. D[4:0] S[4:0] Selector Field. Indicates to its link partner that it is an IEEE Std 802.3 device. synchronization with its link partner during Next Page exchange. M[10:0] - 1000Base-T Message Code.
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 16 Track ID: JATR-1076-21 Rev. 1.1 Bit Name Bit Description Register Location U12 Ack2 Acknowledge 2. 1: Indicates to its link partner that a device has the ability to comply with the message. U11 T Toggle. Used by the NWay arbitration function to ensure synchronization with its link partner during Next Page exchange. U[10:5] - Reserved. Transmit as 0 - U4 - 1000Base-T Half Duplex. 1: Half duplex 0: No half duplex RGMII register 9.8 (GBCR) Table 30, page 32. U3 - 1000Base-T Full Duplex. 1: Full duplex 0: No full duplex RGMII register 9.8 (GBCR) Table 30, page 32. U2 - 1000Base-T Port Type Bit. 1: Multi-port device 0: Single-port device RGMII register 9.8 (GBCR) Table 30, page 32. U1 - 1000Base-T Master-Slave Manual Configuration Value. 1: Master 0: Salve This bit is ignored if bit 9.12=0 RGMII register 9.8 (GBCR) Table 30, page 32. U0 - 1000Base-T Master-Slave Manual Configuration Enable. 1: Manual Configuration Enable This bit is intended to be used for manual selection in Master-Slave mode, and is to be used in conjunction with bit 9.11 RGMII register 9.8 (GBCR) Table 30, page 32. PAGE 2 (Unformatted Next Page) U15 NP Next Page. 1: Indicates that Next Pages follow 0: Indicates that no Next Pages follow U14 Ack Acknowledge. 1: Indicates that a device has successfully received its link partner’s Link Code Word (LCW) U13 MP Message Page. 1: Indicates to its link partner that this is a message page, not an unformatted page. U12 Ack2 Acknowledge 2. 1: Indicates to its link partner that a device has the ability to comply with the message. U11 T Toggle. Used by the NWay arbitration function to ensure synchronization with its link partner during Next Page exchange. U[10:0] - 1000Base-T Master-Slave Seed Bit[10:0] Master-Slave Seed Value SB[10:0]
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 17 Track ID: JATR-1076-21 Rev. 1.1 6.6.1. Auto-Negotiation Priority Resolution Upon the start of auto-negotiation, to advertise its capabilities each station transmits a 16-bit packet called a Link Code Word (LCW), within a burst of 17 to 33 Fast Link Pulses (FLP). A device capable of auto-negotiation transmits and receives the FLPs. The receiver must identify three identical LCWs before the information is authenticated and used in the arbitration process. The devices decode the base LCW and select capabilities with the highest common denominator supported by both devices. To advertise 1000Base-T capability, both link partners, sharing the same link medium, should engage in Next Page (1000Base-T Message Page, Unformatted Page 1, and Unformatted Page 2) exchange. Auto-negotiation ensures that the highest priority prot ocol will be selected as the link speed based on the following priorities advertised through the Link Code Word (LCW) exchange. Refer to IEEE 802.3 Clause 28 for detailed information. 1. 1000Base-T Full Duplex (highest priority) 2. 1000Base-T Half Duplex 3. 100base-Tx Full Duplex 4. 100base-Tx Half Duplex 5. 10base-T Full Duplex 6. 10base-T Half Duplex (lowest priority)
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 18 Track ID: JATR-1076-21 Rev. 1.1 6.6.2. Auto-Negotiation Master/Slave Resolution To establish a valid 1000Base-T link, the Master/Slave mode of both link partners should be resolved through the auto-negotiation process: Master Priority: Multi-port > Single port Manual > Non-manual Determination of Master/Slave configuration from LCW: Manual_MASTER=U0*U1 Manual_SLAVE=U0*!U1 Single-port device=!U0*!U2 Multi-port device=!U0*U2 Where: U0 is bit 0 of the Unformatted Page 1 U1 is bit 1 of the Unformatted Page 1 U2 is bit 2 of the Unformatted Page 1 Where there are two stations with the same configuration, the one with higher Master-Slave seed SB[10:0] in the unformatted page 2 shall become Master. Master-Slave configuration process resolution: Successful: Bit 10.15 Master-Slave Configuration Fault is set to logical 0, and bit 10.14 is set to logical 1 for Master resolution, or set to logical 0 for Slave resolution. Unsuccessful: Auto-Negotiation restarts. Fault detect: Bit 10.15 is set to logical 1 to indicate that a configuration fault has been detected. Auto-Negotiation restarts automatically. This happens when both stations are set to manual Master mode or manual Slave mode, or after seven attempts to configure the Master-Slave relationship through the seed method has failed. 6.6.3. Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution Auto-negotiation is also used to determine the flow control capability between link partners. Flow control is a mechanism that can force a busy transmitting link partner to stop transmitting in a full duplex environment by sending special MAC control frames. In IEEE 802.3u, a PAUSE control frame had already been defined. However, in IEEE 802.3ab, a new ASY-PAUSE control frame was defined; if the MAC can only generate PAUSE frames but is not able to re spond to PAUSE frames generated by the link partner, then it is called Asymmetric PAUSE. PAUSE/ASYMMETRIC PAUSE capability can be configured by setting the ANAR bits 10 and 11 (Table 25, page 29). Link partner PAUSE capabilities can be determined from ANLPAR bits 10 and 11 (Table 26, page 30). A PHY layer device such as the RTL8211C(L) is not directly involved in PAUSE resolution, but simply advertises and reports PAUSE capabilities dur ing the Auto-Negotiation process. The MAC is responsible for final PAUSE/ASYMMETRIC PAUSE resolution after a link is established, and is responsible for correct flow control actions thereafter.
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 19 Track ID: JATR-1076-21 Rev. 1.1 6.7. Crossover Detection and Auto-Correction Ethernet needs a crossover mechanism between both link partners to cross the transmit signal to the Auto-Correction Configuration eliminates the need for crossover cables between devices, such as two PC’s connected to each other with a CAT.3 or CAT.5 Ethern et cable. The basic concept is to assume the initial default setting is MDI mode, and then check the link status. If no link is established after a certain time, change to MDI Crossover mode and repeat the process until a link is established. An 11-bit pseudo-random timer is applied to decide the mode change time interval. Crossover Detection & Auto-Correction is not a part of the Auto-Negotiation process, but it utilizes the process to exchange the MDI/MDI Crossover confi guration. If the RTL8211C(L) is configured to only operate in 100Base-TX or only in 10Base-T mode, then Auto-Negotiation is disabled only if the Crossover Detection & Auto-Correction function is also disabl ed. If Crossover Detection & Auto-Correction are enabled, then Auto-Negotiation is enabled and th e RTL8211C(L) advertises only 100Base-TX mode or 10Base-T mode. If the speed of operation is confi gured manually and Auto-Negotiation is still enabled because the Crossover Detection & Auto-Correction func tion is enabled, then the duplex advertised is as follows: 1. If CONFIG is set to half duplex, then only half duplex is advertised. 2. If CONFIG is set to full duplex, then both full and half duplex are advertised. If the user wishes to advertise only full duplex at a particular speed with the Crossover Detection & Auto-Correction function enabled, then Auto-Nego tiation should be enabled (register 0.12) with the appropriate advertising capabilities set in registers 4 or 9. The Crossover Detection & Auto-Correction function may be enabled/disabled by setting (register 16.6) manually. After initial configuration following a hardware reset, Auto-Negotiation can be enabled and disabled via least one of the following events occurs:
- Software reset (register 0.15)
- Restart of Auto-Negotiation (register 0.9)
- Transition from power-down to power-up (register 0.11) Registers 4 and 9 are internally latched once each time Auto-Negotiation enters the ABILITY DETECT state in the arbitration state machine (IEEE 802.3). Hence a write into register 4 or 9 has no effect once the RTL8211C(L) begins to transmit Fast Link Pulses. Register 7 is treated in a similar manner as 4 and 9 during additional Next Page exchanges. Once the RTL8211C(L) completes Auto-Negotiation, it updates the various statuses in registers 1, 5, 6, and 10. The speed, duplex, page received, and Auto-Negotiation comple ted statuses are also available in registers 17 and 19.
Table 15. LED Configuration (RTL8211C)
- To change the register page, see note 2 (bel ow) and Table 18, page 22. The functionality of the
RTL8211CL LEDs is shown in Table 16. and LED DUPLEX are for RTL8211C use. Table 16. LED Default Definitions (RTL8211CL) Table 17. LED Indication
The functionality of the RTL8211CL LED pins can be customized from Page2 register26 (see Table 18). There are sixteen configuration types (see Table 19). Table 18. LED Register Table (RTL8211CL) Table 19. LED Configuration Table (RTL8211CL)
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 23 Track ID: JATR-1076-21 Rev. 1.1 6.8.1. LED Special Link Modes (RTL8211CL Only) The RTL8211CL supports four special LED link modes. Mode A Setting Description All LED bits=0 All LED pins floating and power saving Mode B Setting Description LED0=1 LED1 or LED2=1 LED0=Full Duplex Mode C Setting Description LED0=0 LED1=0 LED2=Any LED0=TX LED1=RX Mode D Setting Description LED0=0 LED1=1 LED2=Any LED0=10 Activity LED1=100 Activity
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 24 Track ID: JATR-1076-21 Rev. 1.1 6.9. Polarity Correction The RTL8211C(L) automatically corrects polarity errors on the receive pairs in 1000Base-T and 10Base-T modes. In 100Base-TX mode polarity is irrelevant . In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle symbols. Once the descrambler is locked, the polarity is also locked on all pairs. The polarity becomes unlocked only when the receiver loses lock. In 10Base-T mode, polarity errors are corrected based on the det ection of validly spaced link pulses. The detection begins during the MDI crossover detection phase a nd locks when the 10Base-T link is up. The polarity becomes unlocked when the link is down. 6.10. Power The RTL8211C(L) implements a voltage regulator to generate operating power. The system vendor needs to supply a 3.3V, 1A steady power source. The RTL 8211C(L) converts the 3.3V steady power source to 1.0V via a switching regulator. Another possible implementation is to use an external regulator to generate 1.0V. Be sure that the regulator meets the required current rate. The RTL8211C(L) implements an option for the RGM II power pins. The standard I/O voltage of the RGMII interface is 3.3V, with support for 2.5V to lower EMI. The 2.5V power source for RGMII is from an external regulator.
Table 20. Register Mapping and Definitions 0 RW BMCR Basic Mode Control Register. 1 RO BMSR Basic Mode Status Register. 2 RO PHYID1 PHY Identifier Register 1. 3 RO PHYID2 PHY Identifier Register 2. 4 RW ANAR Auto-Negotiati on Advertising Register. 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register. 6 RW ANER Auto-Negotiation Expansion Register. 7 RW ANNPTR Auto-Negotiation Ne xt Page Transmit Register. 8 RW ANNPRR Auto-Negotiation Ne xt Page Receive Register. 9 RW GBCR 1000Base-T Control Register. 10 RO GBSR 1000Base-T Status Register. 15 RO GBESR 1000Base-T Extended Status Register. 16 RW PHYCR PHY Specific Control Register. 17 RO PHYSR PHY Specific Status Register. 18 RW INER Interrupt Enable Register. 19 RO INSR Interrupt Status Register. 21 RO RXERC Receive Error Counter. 24 RW LEDCR LED Control Register. 31 RW PAGSEL Page Select Register. 26/Page2 RW LEDCR LED Control Register.
Table 21. BMCR (Basic Mode Control Register, Address 0x00) 0.14 Loopback RW 0 Loopback Mode for 10M &100M. 0.13 Speed[0] RW 0 Speed Select bit 0. determine device speed selection. 0.12 ANE RW 1 Auto-Negotiation Enable. RXC, RXCLT, RXD[3:0], COL and CRS outputs. 0.9 Restart_AN RW, SC 0 Restart Auto-Negotiation. 0.8 Duplex RW 1 Duplex Mode. This bit is valid only in force mode, i.e., NWay is disabled.
0.7 Collision test RW 0 Collision Test. de-asserted within 4-bit times in response to the de-assertion of TXEN. 0.6 Speed[1] RW 1 Speed Select bit 1. 0.5:0 RSVD RO 000000 Reserved. Restart_AN (0.9) is asserted, or PWD (0.11) transitions from power down to normal operation. auto-negotiation are performed even if bits Reset (0.15) and Restart_AN (0.9) are not set by the user. Table 22. BMSR (Basic Mode Status Register, Address 0x01) 1.15 100Base-T4 RO 0 100Base-T4 Capability. 1.14 100Base-TX (full) RO 1 100Bas e-TX Full Duplex Capability. 1.13 100Base-TX (half) RO 1 100Base-TX Half Duplex Capability. 1.12 10Base-T (full) RO 1 10Base-T Full Duplex Capability. 1: Device is able to perform 10Base-T in full duplex mode. 0: Device is not able to perform 10Base-T in full duplex mode. 1.11 10Base-T (half) RO 1 10Base-T Half Duplex Capability. 1.10 100Base-T2 (full) RO 0 100Bas e-T2 Full Duplex Capability. 1.9 100Base-T2 (half) RO 0 100Base-T2 Half Duplex Capability.
RO 1 1000Base-T Extended Status Register. This register is read-only and is always set to 1. 1.6 Preamble Suppression RO 1 Preamble S uppression Capability (Permanently On).
1.5 Auto-Negotiation
RO 0 Auto-Negotiation Complete. 1.4 Remote Fault RO 0 Remote Fault. 1: Remote fault condition detected (cleared on read or by reset).
1.3 Auto-Negotiation
1.2 Link Status RO 0 Link Status. This register indicates whether the link was lost since the last read. register bit 17.10 Link Real Time. 1.1 Jabber Detect RO 0 Jabber Detect.
1.0 Extended Capability RO 1 1: Extended register capabilities, always 1
Table 23. PHYID1 (PHY Identifier Register 1, Address 0x02) 2.15:0 OUI_MSB RO 0000000000011100 Organizationally Unique Identifier Bit 3:18. Note: Realtek OUI is 0x000732.
Table 24. PHYID2 (PHY Identifier Register 2, Address 0x03) 3.15:10 OUI_LSB RO 110010 Organizationally Unique Identifier Bit 19:24. Table 25. ANAR (Auto-Negotiation Advertising Register, Address 0x04)
4.15 NextPage RW 0 1: Additiona l next pages exchange desired
4.13 Remote fault RW 0 1: Set Remote Fault bit
4.11 Asymmetric
4.10 PAUSE RW 0 1: Advertise support of pause frames
Note 1: The setting of Register 4 has no effect unless NWay is restarted or the link goes down. to 0 if no additional next pages are needed.
Table 26. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05) 5.15 Next Page RO 0 Next Page Indication. 5.13 Remote Fault RO 0 Remote Fault indicated by Link Partner. 5.12:5 Technology Ability Field RO 00000000 Received C ode Word Bit 12:5. 5.4:0 Selector Field RO 00000 R eceived Code Word Bit 4:0. Note: Register 5 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed. Table 27. ANER (Auto-Negotiation Expansion Register, Address 0x06) 6.15:5 RSVD RO 0x000 Reserved.
6.4 Parallel Detection Fault RO 0 1: A fault has been detected via the Parallel Detection function
6.3 Link Partner Next
6.2 Local Next Pageable RO 1 1: Local Device is able to send Next Page
6.1 Page Received RO 0 1: A New Pa ge (new LCW) has been received
6.0 Link Partner
Note: Register 6 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
Table 28. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07) 7.15 Next Page RW 0 Next Page Indication. 7.14 RSVD RO 0 Transmit Code Word Bit 14. 7.13 Message Page RW 1 Message Page. 7.12 Acknowledge 2 RW 0 Acknowledge2. 7.11 Toggle RO 0 Toggle bit. RW 0x001 Content of Message/Unformatted Page. Transmit Code Word Bit 10:0. Table 29. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08) 8.15 Next Page RO 0 Receive d Link Code Word Bit 15. 8.14 Acknowledge RO 0 Receive d Link Code Word Bit 14. 8.13 Message Page RO 0 Recei ved Link Code Word Bit 13. 8.12 Acknowledge 2 RO 0 Receive d Link Code Word Bit 12. 8.11 Toggle RO 0 Received Link Code Word Bit 11. 8.10:0 Message/ Unformatted Field RO 0x00 Received Link Code Word Bit 10:0. Note: Register 8 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
Table 30. GBCR (1000Base-T Control Register, Address 0x09) 9.15:13 Test Mode RW 0 Test Mode Select.
9.12 MASTER/SLA VE Manual
RW AN[3:0] Enable Manual Master/Slave Configuration.
9.11 MASTER/SLA VE
RW AN[3:0] Advertise Master/Slave Configuration Value. 9.10 Port Type RW AN[3:0] Advertise Device Type Preference. 9.9 1000Base-T Full Duplex RW AN[3:0] Adve rtise 1000Base-T Full-Duplex Capability. 9.8 1000Base-T Half Duplex RW AN[3:0] A dvertise 1000Base-T Half-Duplex Capability. Note 1: Values set in register 9.12:8 have no effect unless Auto-Negotiation is restarted (Reg0.9) or the link goes down. Note 2: Bits 9.11 and 9.10 are ignored when bit 9.12=0.
Table 31. GBSR (1000Base-T Status Register, Address 0x0A)
10.15 MASTER/SLA VE
RO, SC 0 Master/Slave Manual Configuration Fault Detected.
10.14 MASTER/SLA VE
RO 0 Master/Slave Configuration Result. 10.13 Local Receiver Status RO 0 Local Receiver Status. 10.12 Remote Receiver Status RO 0 Remote Receiver Status.
10.11 Link Partner 1000Base-T
RO 0 Link Partner 1000Base-T Full Duplex Capability.
10.10 Link Partner 1000Base-T
RO 0 Link Partner 1000Base-T Half Duplex Capability. 10.7:0 Idle Error Count RO, SC 0x00 MSB of Idle Error Counter. The counter stops automatically when it reaches 0xff. Note 1: Values set in register 10.11:10 are not valid until register 6.1 is set to 1. Note 2: SC: Self-cleared after read. Note 3: Register 10 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed. Table 32. GBESR (1000Base-T Extended Status Register, Address 0x0F) 15.11:0 RSVD RO 0x000 Reserved.
Table 33. PHYCR (PHY Specific Control Register, Address 0x10) 16.15:12 RSVD RW 0000 Reserved.
16.11 Assert CRS on Transmit RW 0 1: Assert CRS on transmit
16.10 Force Link Good RW 0 1: Force link good 0: Normal operation
16.9:7 RSVD RW 011 Reserved. Note: Before setting the register, address 0xE bit10 need set to 1. After setting the register, a PHY reset is required.
16.4 Disable CLK125 RW 1 1: CLK125 remains at logic High
16.3:1 RSVD RW 111 Reserved.
16.0 Disable Jabber RW 0 1: Disable ja bber function 0: Enable jabber function
Table 34. PHYSR (PHY Specific Status Register, Address 0x11) 17.15:14 Speed RO 01 Link Speed. 17.13 Duplex RO 0 Full/Half Duplex Mode. 17.12 Page received RO 0 New Page Received.
17.11 Speed and duplex
RO 0 Speed and Duplex Mode Resolved. 17.10 Link (real time) RO 0 Real Time Link Status. 17.9:7 RSVD RO 000 Reserved. 17.6 MDI crossover status RO 0 MDI/MDI Crossover Status.
17.5 LED Control RW 0 0: Low active 1: High active
17.4 LED Definition RW 1 0: N/A
17.3 ALDPS RW 0 0: Disable Advance link down power saving
17.0 Jabber (real time) RO 0 Real Time Jabber Indication.
Table 35. INER (Interrupt Enable Register, Address 0x12)
18.15 Auto-Negotiation Error Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
18.14 Speed Change Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
18.13 Duplex Mode Change Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
18.12 Page Received Interrupt RW 0 1: Interrupt enab le 0: Interrupt disable
18.11 Auto-Negotiation Completed
18.10 Link Status Change Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
18.9 Symbol Error Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
18.8 False Carrier Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
18.6 MDI Crossover Change Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
18.1 Polarity Change Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
18.0 Jabber Interrupt RW 0 1: Interrupt enable 0: Interrupt disable
Table 36. INSR (Interrupt Status Register, Address 0x13)
19.15 Auto-Negotiation Error RO 0 1: Auto-Negotiation Error 0: No Auto-Negotiation Error
19.14 Speed Change RO 0 1: Link speed changed 0: Link speed not changed
19.13 Duplex Mode Change RO 0 1: Duplex mode changed 0: Duplex mode not changed
19.12 Page Received RO 0 1: Page (a new LCW) received
19.11 Auto-Negotiation Completed RO 0 1: Auto-Negotiation completed
19.10 Link Status Change RO 0 1: Link status changed 0: Link status not changed
19.9 Symbol Error RO 0 1: Symbol error detected 0: No symbol error detected
19.8 False Carrier RO 0 1: False carri er 0: No false carrier detected
19.6 MDI Crossover Change RO 0 1: Crossover status changed
19.5:2 RSVD RO 0000 Reserved.
19.1 Polarity Change RO 0 1: Polarity Changed 0: Polarity not changed
Note: This bit is valid only when 1000Base-T is enabled.
19.0 Jabber RO 0 1: Jabber detected 0: No jabber detected
Table 37. RXERC (Receive Error Counter, Address 0x15) 21.15:0 Receive Erro r Count RO 0x0000 Recei ve Error Count. Note: The RXERC register is self-cleared after a read. Table 38. LEDCR (LED Control Register, Address 0x18)
24.15 Disable LED RW 0 0: Enable
Table 39. PAGSEL (Page Select Register, Address 0x1F) 31.2:0 Pagesel RW 000 Page Select Signal.
- The input 3.3V power trace connected to VDDREG should be wider than 40mils.
- The bulk de-coupling capacitors (C82 and C83) should be placed within 200mils (0.5cm) of VDDREG to prevent input voltage overshoot.
- The output power trace out of REG_OUT should be wider than 60mils.
- Keep L20 within 200mils (0.5cm) of REG_OUT.
- Keep C18 and C19 within 200mils (0.5cm) of L20 to ensure stable output power and better power efficiency.
- Both C18 and C82 are strongly recommended to be ceramic capacitors. Note: Violation of the above rules will damage the IC.
Figure 6. Switching Regulator Application
Table 40. Inductor and Capacitor Parts List Note: Capacitors (C18 and C82) are suggested to be ceramic due to their low ESR value.
choosing a proper output capacitor is to choose the lowest ESR to reduce the output voltage ripple. Choosing a ceramic 22µF 0805 (Y5V) in this case w ill cause malfunction of the switching regulator. Placing several Electrolytic capacitors in parallel will help lower the output voltage ripple. Figure 11. Electrolytic 100µF (Ripple Too High)
Figure 16. Application Diagram
Table 42. Absolute Maximum Ratings Note:Refer to the most updated schematic circuit for correct configuration. Table 43. Recommended Operating Conditions Table 44. Crystal Requirements fundamental mode, AT-cut type. fundamental mode, AT-cut type. Ta=25°C. fundamental mode, AT-cut type. Ta=-20°C~+70°C.
Table 45. DC Characteristics Figure 17. MII Management Timing Parameters Table 46. MII Management Timing Parameters
Figure 18. RGMII Timing Modes
Table 47. RGMII Timing Parameters
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 49 Track ID: JATR-1076-21 Rev. 1.1 11. Mechanical Dimensions 11.1. RTL8211C 64-Pin QFN Mechanical Dimensions Note: For RTL8211C-GR specific information, refer to line 3. Note: Exposed Pad is Analog and Digital Ground.
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 50 Track ID: JATR-1076-21 Rev. 1.1 11.2. RTL8211CL 48-Pin LQFP Mechanical Dimensions
RTL8211C & RTL8211CL Datasheet Integrated 10/100/1000 Gigabit Ethernet Transceiver 51 Track ID: JATR-1076-21 Rev. 1.1 11.3. RTL8211CL 48-Pin LQFP Mechanical Dimensions Notes Notes: 1. To be determined at seating plane -c- 2. Dimensions D1 and E1 do not include mold protrusion. Symbol Dimension in Inchs Dimension in Millimeters D1 and E1 are maximum plastic body size dimensions including mold mismatch. Min Nom Max Min Nom Max 3. Dimension b does not include dambar protrusion. A - - 0.067 - - 1.70 Dambar cannot be located on the lower radius of the foot. D 0.354 BSC 9.00 BSC 7. Contro lling dimension: millimeter. D1 0.276 BSC 7.00 BSC 8. Reference document: JEDEC MS-026, BBC E 0.354 BSC 9.00 BSC TITLE: 48LD LQFP ( 7x7x1.4mm) E1 0.276 BSC 7.00 BSC PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm e 0.020 BSC 0.50 BSC LEADFRAME MATERIAL: L1 0.039 REF 1.00 REF VERSION 1 APPROVE PAGE OF θ1 0 ° - - 0° - - DWG NO. SS048 - P1 θ2 12 ° TYP 12 ° TYP CHECK DATE θ3 12 ° TYP 12 ° TYP REALTEK SEMICONDUCTOR CORP.
Table 48. Ordering Information Note: See page 2 (RTL8211C-GR) and page 3 (RTL8211CL-GR) for package identification.