RTL8110SB-VD-LF

RTL8110SB-VD REALTEK | Alldatasheet

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INTEGRATED GIGABIT ETHERNET CONTROLLER (LOM) DATASHEET Rev. 1.6

26 October 2005

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) i i Track ID: JATR-1076-21 Rev. 1.6 COPYRIGHT ©2005 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. USING THIS DOCUMENT This document is intended for use by the softwa re engineer when pr ogramming for Realtek RTL8110SB(L) controller chips. Information pertaini ng to the hardware design of products using these chips is contained in a separate document. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2003/11/17 First release. 1.1 2004/01/28 EEDI/AUX and EEDO description changed in Table 3, page 7. Pin 11 changed from NC to VSS (see Table 8, page 9). Pin 12 changed from NC to A VDDH (see Table 8, page 9). 1.2 2004/04/16 Add MiniPCI function related content. 1.3 2004/07/26 Revised VDD25 parameters (see Table 12, page 26, and Table 15, page 27). Corrected ‘VDD25’ pin name to ‘A VDDL’. 1.4 2004/08/10 Revised Pin 126 (VDD12A) description (see Table 8, page 9, Table 11, page 26, Table 12, page 26, and Table 15, page 27). 1.5 2004/10/05 Package changes. See section 8, Mechanical Dimensions, page 39, and section 1.51 2004/10/06 Package drawing correction (all data remains unchanged). See section 8.3, 128-Pin EDHS-LQFP Mechanical Dimensions, page 41. 1.6 2005/10/26 Revise section 9 Ordering Information, page 43.

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) iii Track ID: JATR-1076-21 Rev. 1.6 Table of Contents

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) i v Track ID: JATR-1076-21 Rev. 1.6

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 1 Track ID: JATR-1076-21 Rev. 1.6 1. General Description The Realtek RTL8110SB(L) LOM Gigabit Ethernet controllers combine a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a tr iple-speed Ethernet transceiver, 32-bit PCI bus controller, and embedded memory. With state- of-the-art DSP technology and mixed-mode signal technology, they offer high-speed transmission ove r CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polar ity correction, adaptive equalization, cross-talk cancellation, echo cancella tion, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. The devices support the PCI v2.3 and MiniPCI v1.0 bus interfaces for host communications with power management, and are compliant with the IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. They also support an auxili ary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. They support the Advanced Configuration Power ma nagement Interface (ACPI)--power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)--to achieve the most efficient power management possible. PCI Message Signaled Interrupt (MSI) is also supported. In addition to the ACPI feature, the RTL8110SB( L) supports remote wake-up (including AMD Magic Packet, Re-LinkOk, and Microsoft ® Wake-up frame) in both ACPI and APM (Advanced Power Management) environments. The LWAKE pin provides four different output si gnals including active high, active low, positive pulse, and negative pulse . The versatility of the LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality. To support WOL from a deep power down state (e.g. D3cold, i.e. main power is off and only auxiliary exists), the auxiliary power source must be able to provide the required power for the RTL8110SB(L). The RTL8110SB(L) is fully compliant with Microsoft ® NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and supports IEEE 802 IP Layer 2 priority encoding and 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operati on on a network server. Also, the devices boost their PCI performance by supporting PCI Memory Read Li ne & Memory Read Multiple when transmitting, and Memory Write and Invalidate when receiving. To better qualify for server use, the RTL8110SB(L) support the PCI Dual Address Cycle (DAC) command when the assigned buffers reside at a physical memory address higher than 4 Gigabytes. See section 9, Ordering Information, page 43 for package type details.

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 2 Track ID: JATR-1076-21 Rev. 1.6 2. Features „ Integrated 10/100/1000 transceiver „ Auto-Negotiation with Next Page capability „ Supports PCI rev.2.3, 32-bit, 33/66MHz „ Supports CLKRUNB and miniPCI v1.0 „ Supports pair swap/polarity/skew correction „ Crossover Detection & Auto-Correction „ Wake-on-LAN and remote wake-up support „ Microsoft® NDIS5 Checksum Offload (IP, TCP, UDP) and largesend offload support „ Supports Full Duplex flow control (IEEE 802.3x) „ Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab „ Supports IEEE 802.1P Layer 2 Priority Encoding „ Supports IEEE 802.1Q VLAN tagging „ Serial EEPROM „ 3.3V signaling, 5V PCI I/O tolerant „ Transmit/Receive FIFO (8K/64K) support „ Supports power down/link down power saving „ Supports PCI Message Signaled Interrupt (MSI) „ Various 128-pin package types available 3. System Applications „ Gigabit Ethernet on Motherboard „ Gigabit Ethernet MiniPCI Card

Figure 1. 128-Pin (L)QFP Pin Assignments is shown in the location marked ‘V’.

T/S: Tri-State bi-directional input/output pin. Table 1. Power Management/Isolation O/D 31 Power Management Event: Open drain, active low. that a power management event has occurred. I 23 Isolate Pin: Active low. (including PCIRSTB and PCICLK) as long as the Isolate pin is asserted. CONFIG bits: LWACT (Config1.4) and LWPTN (Config4.2).

0 Active high Active low LWPTN

1 Positive pulse Negative pulse

when PMEB asserts and ISOLATEB is low.

Table 2. PCI Interface those clocks where both IRDYB and TRDYB are asserted. input to the PCI device. Supports up to a 66MHz PCI clock. the negated (deasserted) state. recognizes its target address after FRAMEB is asserted. FRAMEB is de-asserted, the transaction is in the final data phase. check if the current transaction is addressed to it. central arbiter has granted the ownership of the bus to the RTL8110SB(L). This input is used when the device is acting as a bus master.

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 6 Track ID: JATR-1076-21 Rev. 1.6 Symbol Type Pin No Description REQB T/S 30 Request: The RTL8110SB(L) will assert this signal low to request the ownership of the bus from the central arbiter. IDSEL I 46 Initialization Device Select: This pin allows the device to identify when configuration read/write transactions are intended for it. INTAB O/D 25 Interrupt A: Used to request an interrupt. It is asserted low when an interrupt condition occurs, as defined by the Interrupt Status, Interrupt Mask. IRDYB S/T/S 63 Initiator Ready: This indicates the initiating agent’s ability to complete the current data phase of the transaction. As a bus master, this signal will be asserted low when the device is ready to complete the current data phase transaction. This signal is used in conjunction with the TRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low. As a target, this signal indicates that the master has put data on the bus. TRDYB S/T/S 67 Target Ready: This indicates the target agent’s ability to complete the current phase of the transaction. As a bus master, this signal indicates that the target is ready for the data during write operations, or is ready to provide the data during read operations. As a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYB signal. Data transaction takes place at the rising edge of CLK, when both IRDYB and TRDYB are asserted low. PAR T/S 76 Parity: This signal indicates even parity across PCIADPIN31-0 and CBEB3-0 including the PAR pin. PAR is stable and valid one clock after each address phase. For data phase, PAR is stable and valid one clock after either IRDYB is asserted on a write transaction or TRDYB is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. As a bus master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. M66EN I 88 66MHZ_ENABLE: This pin indicates to the device whether the bus segment is operating at 66 or 33MHz. When this pin (active high) is asserted, the current PCI bus segment that the device resides on operates in 66MHz mode. If this pin is de-asserted, the current PCI bus segment operates in 33MHz mode. PERRB S/T/S 70 Parity Error: This pin is used to report data parity errors during all PCI transactions except a Special Cycle. PERRB is driven active (low) two clocks after a data parity error is detected by the device receiving data, and the minimum duration of PERRB is one clock for each data phase with parity error detected. SERRB O/D 75 System Error: If an address parity error is detected and Configuration Space Status register bit 15 (detect parity error) is enabled, the device asserts the SERRB pin low and bit 14 of the Status register in Configuration Space. STOPB S/T/S 69 Stop: Indicates that the current target is requesting the master to stop the current transaction. PCIRSTB I 27 Reset: When PCIRSTB is asserted low, the device performs an internal system hardware reset. PCIRSTB must be held for a minimum period of 120ns.

Table 3. EEPROM EESK O 111 Serial data clock. EEDI/AUX O/I 109 EEDI: Output to serial data input pin of EEPROM. AUX: Input pin to detect if Aux. Power exists or not on initial power-on. assumes that no Aux. Power exists. EEDO I 108 Input from serial data output pin of EEPROM. EECS O 106 EECS: EEPROM chip select. Table 4. Transceiver Interface the transmit pair in 10Base-T and 100Base-TX. pair in 10Base-T and 100Base-TX. is the transmit pair in 10Base-T and 100Base-TX. pair in 10Base-T and 100Base-TX. In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair. Table 5. Clock Xtal1 I 121 Input of 25MHz clock reference. Xtal2 O 122 Output of 25MHz clock reference.

Table 6. Regulator & Reference CTRL25 O 8 Regulator Control. V oltage control to external 2.5V regulator. CTRL12 O 125 Regulator Control. V oltage control to external 1.2V regulator. RSET I 127 Reference. External Resistor Reference. Table 7. LEDs Note 1: During power down mode, the LED signals are logic high. Note 2: LEDS1-0’ s initial value comes from 93C46/93C56/93C66.

Table 8. Power & Ground VDD12A Power 126 Analog 1.2V power supply. A VDDL Power 3, 7, 16, 20 Analog 2.5V power supply. A VDDH Power 10, 12, 120 Analog 3.3V power supply. Table 9. NC (Not Connected) Pins

Local Bus Specifications Rev. 2.3, March 29, 2002. little-endian or big-endian orderi ng through the use of the ENDIAN b it of the C+ Command Register. the RTL8110SB(L) is set to big-endian or little-endian mode. Figure 2. Little-Endian Byte Ordering

Figure 3. Big-Endian Byte Ordering Interrupts are performed by asynchronously asserting the INTAB pin. This pin is an open drain output. Mask Register. This allows the system to defer interrupt processing as needed. as its GNTB is deasserted. Software is able to read or write to LTR, and the default value is 00H. through software. The RTL8110SB(L) only supports 32-bit addressing as a target.

system must tri-state the address bus, and convert the C/BE bus to byt e enables after th e address cycle. TRDYB. STOPB will remain asserted until FRAMEB is detected as deasserted. Figure 4. Target Read Operation

with TRDYB. STOPB will remain asserted until FRAMEB is detected as deasserted. Figure 5. Target Write Operation

will be generated on the clock following GNTB. RTL8110SB(L) will never force a wait state during a read operation. Figure 6. Master Read Operation

will be generated on the clock following GNTB. RTL8110SB(L) will never force a wait state during a write operation. Figure 7. Master Write Operation

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 1 6 Track ID: JATR-1076-21 Rev. 1.6 6.2.5. Configuration Access Configuration register accesses are similar to target reads and writes in that they are single data word transfers and are initiated by the system. For the system to initiate a Configuration access, it must also generate IDSEL as well as the correct Comma nd (1010b or 1011b) during the Address phase. The RTL8110SB(L) will respond as it does during Target ope rations. Configuration reads must be 32-bits wide, but writes may access individual bytes. 6.3. LED Functions The RTL8110SB(L) supports 4 LED signals in 4 diffe rent configurable operation modes. The following sections describe the different LED actions. 6.3.1. Link Monitor The Link Monitor senses the link integrity or if a station is down, such as LINK10, LINK100, LINK1000, LINK10/100/1000, LINK10/ACT, LINK 100/ACT, or LINK1000/ACT. Wh enever link status is established, the specific link LED pin is driven lo w. Once a cable is disconn ected, the link LED pin is driven high, indicating that no network connection exists.

In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring. Figure 8. Rx LED

In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. Figure 9. Tx LED

Figure 10. Tx/Rx LED

Figure 11. LINK/ACT LED

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 2 1 Track ID: JATR-1076-21 Rev. 1.6 6.4. PHY Transceiver 6.4.1. PHY Transmitter In 10Mbps mode, the Tx MAC retrieves packet data from the Tx Buffer Manager and sends it out through the transmitting physical layer in terface. The transmit 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. Th en, the 10Mbps serial data is converted into a Manchester-encoded data stream and is transmitted onto the media by the DAC converter. In 100Mbps mode, the transmitted 4-bit nibbles (TXD[ 3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code via 4B/5B coding technology, sc rambling, and serializing before being converted to 125MHz NRZ and NRZI signals. Af ter that, the NRZI signal is passed to the MLT-3 encoder, then to the DAC converter for transmission onto the media. In 1000Mbps mode, the RTL8110SB(L)’s PCS layer re ceives data bytes from the MAC through the GMII interface and performs the generation of continuous code-groups through 4D-PAM5 coding technology. Then those code groups are passed thr ough a waveform shaping filter to minimize EMI effects, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a DAC. 6.4.2. PHY Receiver In MII (10Mbps) mode, the received differential si gnal is converted into a Manchester-encoded data stream. The stream is processed with a Manchester de coder, and is de-serialized into 4-bit wide nibbles. The 4-bit nibbles are presented to the MII interf ace at a clock speed of 2.5MHz. In 100Mbps mode, the MLT-3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT-3 and NRZI decoder, descrambler, 4B/5B decoder, and then is presented to the MII interface in 4-bit wide nibbles at a clock speed of 25MHz. In GMII mode, the input signal from the media fi rst passes through the on-ch ip sophisticated hybrid circuit to subtract the transmitted signal from the i nput signal for effective reduction of near-end echo. Afterwards, the received signal is processed with adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellati on, echo cancellation, timing recover y, error correction, and 4D-PAM5 decoding. Then the 8-bit wide data is recovered and is sent to the GM II interface at a clock speed of 125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the Rx Buffer Manager.

Reg8 as defined in IEEE 802.3ab. ability for the RTL8110SB(L) to read from and write data to an external serial EEPROM device. consists of EESK, EECS, EEDO, and EEDI. Table 10. EEPROM Interface EECS 93C46 (93C56/93C66) chip select. EESK EEPROM serial data clock. EEDI/Aux Input data bus/Input pin to detect if Aux. Power exists or not on initial power-on.

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 2 3 Track ID: JATR-1076-21 Rev. 1.6 6.7. Power Management The RTL8110SB(L) is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class Power Management Referen ce Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8110SB(L) can monitor the network for a Wa keup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via PME# when such a packet or event occurs. Then, the whole system can be restored to a normal state to process incoming jobs. When the RTL8110SB(L) is in power down mode (D1 ~ D3):

• The Rx state machine is stopped, and the RTL8110SB(L) monitors the network for wakeup events such as a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8110SB(L) will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx FIFO buffer.
• The FIFO status and packets that have already been received into the Rx FIFO before entering power down mode are held by the RTL8110SB(L).
• Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.
• After restoration to a D0 state, the RTL8110SB(L) transfers data that was not moved into the Tx FIFO buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. The D3cold_support_PME bit (bit15, PMC register) a nd the Aux_I_b2:0 bits (bit8 :6, PMC register) in PCI configuration space depend on the existence of Aux power (bit15, PMC) = 1. If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s. Example: If EEPROM D3c_support_PME = 1:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 F7, then PCI PMC = C2 F7)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 F7, then PCI PMC = 02 76) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C2 F7 (Realtek EEPROM default value).

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 2 4 Track ID: JATR-1076-21 Rev. 1.6 If EEPROM D3c_support_PME = 0:

• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 77, then PCI PMC = C2 77)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 77, then PCI PMC = 02 76) In the above case, if wakeup support is not desired wh en main power is off, it is suggested that the EEPROM PMC be set to 02 76. Link Wakeup occurs only when the following conditions are met:
• The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be asserted in the current power state. Magic Packet Wakeup occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8110SB(L), e.g. a broadcast, multicast, or unicast packet addressed to the current RTL8110SB(L) adapter.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be asserted in the current power state.
• The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid (Fast) Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame is acceptable to the RTL8110SB(L), e.g. a broadcast, multicast, or unicast address to the current RTL8110SB(L) adapter.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 16-bit CRC* of the received Wakeup Frame matches the 16-bit CRC* of the sample Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8110SB(L) is configured to allow direct packet wakeup, e.g. a broadcast, multicast, or unicast network packet. *16-bit CRC: The RTL8110SB(L) supports two normal wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet).

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 2 5 Track ID: JATR-1076-21 Rev. 1.6 The PME# signal is asserted only when the following conditions are met:

• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8110SB(L) may assert PME# in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wakeup Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8110SB(L) to stop asserting a PME# (if enabled). When the device is in power down mode, e.g. D1-D3, the IO and MEM spaces are all disabled. After a RST# assertion, the device’s power stat e is restored to D0 automatically if the original power state was cold. There is no hardware delay at th e device’s power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The sett ing may be changed from the EEPROM, if required. The RTL8110SB(L) also supports the legacy L AN WAKE-UP function. The LW AKE pin is used to notify legacy motherboards to execute the wake-up process whenever the device receives a wakeup event, such as a Magic Packet. The LWAKE signal is asserted according to the following settings: 1. LWPME bit (bit4, CONFIG4):
• LW AKE can only be asserted when PMEB is asserted and ISOLATEB is low.
• LW AKE is asserted whenever a wakeup event occurs. 2. Bit1 of DELAY byte (offset 1Fh, EEPROM):
• LW AKE signal is enabled.
• LW AKE signal is disabled.

Table 11. Absolute Maximum Ratings Table 12. Recommended Operating Conditions Table 13. Crystal Requirements fundamental mode, AT-cut type.

25 MHz

fundamental mode, AT-cut type. Ta=25°C. fundamental mode, AT-cut type.

Table 14. Thermal Characteristics Table 15. DC Characteristics

Figure 12. Serial EEPROM Interface Timing Table 16. EEPROM Access Timing Parameters

Table 17. PCI Bus Timing Parameters

Figure 13. Output Timing Measurement Conditions Figure 14. Input Timing Measurement Conditions Table 18. Measurement Condition Parameters

1 V/ns

Figure 27. Parity Operation – One Example

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 3 9 Track ID: JATR-1076-21 Rev. 1.6 8. Mechanical Dimensions 8.1. 128-Pin DHS-QFP Mechanical Dimensions See the Mechanical Dimensions notes on the next page.

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 4 0 Track ID: JATR-1076-21 Rev. 1.6 8.2. Notes for 128-Pin DHS-QFP Dimensions Symbol Dimensions in inches Dimensions in mm Notes: Min Typical Max Min Typical Max 1. Dimensions D & E do not include interlead flash. A - - 0.134 - - 3.40 2. Dimension b does not include dambar protrusion/intrusion. v i s u a l i n s p e c t i o n . OUTLINE e 0.020 BSC 0.50 BSC LEADFRAME MATERIAL y - - 0.004 - - 0.10 DATE θ 0° - 12° 0° - 12° REALTEK SEMICONDUCTOR CORP.

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 4 1 Track ID: JATR-1076-21 Rev. 1.6 8.3. 128-Pin EDHS-LQFP Mechanical Dimensions GAGE PLANE DETAIL A-A L S .25 B R2 B WITH PLATING BASE METAL SECTION B-B 53b cc 1

7.44 REF

7.55 REF

0.08 C --C-- SEATING PLANE be A A1 6 See the Mechanical Dimensions notes on the next page.

RTL8110SB(L) Datasheet I n t e g r a t e d G i g a b i t E t h e r n e t C o n t r o l l e r ( L O M ) 4 2 Track ID: JATR-1076-21 Rev. 1.6 8.4. Notes for 128-Pin EDHS-LQFP Dimensions Symbol Dimension in inch Dimension in mm Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.09 - 0.20 c 1 0.004 - 0.006 0.09 - 0.16 e 0.020 BSC 0.50 BSC L1 0.039 REF 1.00 REF R2 0.003 - 0.008 0.08 - 0.20 θ1 4° TYP 4 ° TYP θ2 12° TYP 12 ° TYP θ3 12° TYP 12 ° TYP Notes: 1.To be determined at seating plane -c- 2.Dimensions D1 and E1 do not include mold protrusion. D 1 and E1 are maximum plastic body size dimensions including mold mismatch. 3.Dimension b does not include dambar protrusion. Dambar cannot be located on the lower radius of the foot. 4.Exact shape of each corner is optional. 5.These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A 1 is defined as the distance from the seating plane to the lowest point of the package body. 7.Controlling dimension: millimeter. 8. Reference document: JEDEC MS-026, BHB TITLE: 128LD EDHS-LQFP (14x20x1.4mm) PACKAGE OUTLINE CU L/F, FOOTPRINT 2.0 mm LEADFRAME MATERIAL: C7025 1/1H APPROVE DOC. NO. VERSION PAGE 1 OF 1 CHECK DWG NO. DC128-SW1 DATE 26 NOV . 2002 REALTEK SEMICONDUCTOR CORP.

Table 20. Ordering Information Note: See page 3 for package identification.