RTL8201FN-VB-CG

RTL8201F-VB-CG REALTEK | Alldatasheet

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SINGLE-CHIP/PORT 10/100M ETHERNET PHYCEIVER WITH AUTO MDIX DATASHEET (CONFIDENTIAL: Development Partners Only) Rev. 1.4

30 November 2011

Track ID: JATR-2265-11 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX ii Track ID: JATR-2265-11 Rev. 1.4 COPYRIGHT ©2011 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. LICENSE This product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and US6,327,625. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX iii Track ID: JATR-2265-11 Rev. 1.4

REVISION HISTORY

Revision Release Date Summary 1.0 2010/12/17 First release. 1.1 2011/02/18 Revised to VB model. Revised Table 22 Register 30 Interrupt Indicators and SNR Display Register, page 21. Added interrupt function. Added MMD Register Mapping and Definition section. Revised section 8.2 Interrupt, page 31. Revised Table 46 Absolute Maximum Ratings, page 44. Revised 9.1.3 Power On and PHY Reset Sequence, page 45. Revised Table 49 RMII Input Mode Power Dissipation (Whole System), page 46. 1.2 2011/04/21 Revised Figure 2 Block Diagram, page 4. Revised Table 3 RMII Interface, page 10. Revised Table 7 Device Configuration Interface, page 11. Revised Table 9 Reset and Other Pins, page 14. Revised Table 11 Register 0 Basic Mode Control Register, page 15. Revised Table 15 Register 4 Auto-Negotiation Advertisement Register (ANAR), page 17. Revised Table 20 Register 24, page 20. Revised Table 24 Page4 Register 16 EEE Capability Enable Register, page 22. Revised Table 25 Page4 Register 21 EEE Capability Register, page 22. Revised Table 30 Page7 Register 19 , page 24. Added section 7.21 Page 7 Register 24 Spread Spectrum Clock Register, page 25. Revised section 8.1.2 Serial Management Interface, page 29. Revised section 8.7 Reset and Transmit Bias, page 38. Added section 8.13 Spread Spectrum Clock (SSC), page 43. Added Figure 21 MII Interface Setup/Hold Time Definitions, page 47. Added Figure 26 RMII Interface Setup, Hold Time, and Output Delay Time Definitions, page 49. Added Figure 28 MDC/MDIO Interface Setup, Hold Time, and Valid from MDC Rising Edge Time Definitions, page 51. 1.3 2011/07/14 Added Figure 1 Application Diagram, page 3. Revised Table 30 Page7 Register 19 Interrupt, WOL Enable, and LEDs Function Registers, page 24. Added Table 34 EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00), page 25. Added Table 35 EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01), page 26. Added section 8.4.1 LED and PHY Address, page 32. Added section 8.4.8 EEE LED, page 36. Revised section 8.7 Reset and Transmit Bias, page 38. 1.4 2011/11/30 Revised Figure 2 Block Diagram, page 4. Revised Table 4 Clock Interface, page 10 (CKXTAL2 pin revised from I to IO).

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX iv Track ID: JATR-2265-11 Rev. 1.4 Table of Contents

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX v Track ID: JATR-2265-11 Rev. 1.4

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX vi Track ID: JATR-2265-11 Rev. 1.4

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 1 Track ID: JATR-2265-11 Rev. 1.4 1. General Description The RTL8201F-VB-CG, RTL8201FL-VB-CG, and R TL8201FN-VB-CG are single-chip/single-port 10/100Mbps Ethernet PHYceivers that support:

• MII (Media Independent Interface)
• RMII (Reduced Media Independent Interface) The RTL8201F/FL/FN implement all 10/100M Ethernet Physical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10Base-TX Encoder/Decoder, and Twisted-Pair Media Access Unit (TPMAU). The RTL8201F/FL/FN support auto MDIX. A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX fiber optical transceiver. The chip utilizes an advanced CMOS pro cess to meet low voltage and low power requirements. With on-chip DSP (Digital Signal Processing ) technology, the chip provides excellent performance under all operating conditions. Note: Version differences are listed in section 11 Ordering Information, page 58.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 2 Track ID: JATR-2265-11 Rev. 1.4 2. Features „ Supports IEEE 802.3az-2010 (EEE) „ 100Base-TX IEEE 802.3u Compliant „ 10Base-T IEEE 802.3 Compliant „ Supports MII mode „ Supports RMII mode „ Full/half duplex operation „ Twisted pair or fiber mode output „ Supports Auto-Negotiation „ Supports power down mode „ Supports Link Down Power Saving „ Supports Base Line Wander (BLW) compensation „ Supports auto MDIX „ Supports Interrupt function „ Supports Wake-On-LAN (WOL) „ Adaptive Equalization „ Automatic Polarity Correction „ LEDs ‹ RTL8201F and RTL8201FL provide two network status LEDs ‹ RTL8201FN provides three network status LEDs „ Supports 25MHz external crystal or OSC „ Supports 50MHz external OSC Clock input „ Provides 50MHz clock source for MAC „ Low power supply 1.1V and 3.3V; 1.1V is generated by an internal regulator „ 0.11µm CMOS process „ Packages: ‹ 32-pin MII/RMII QFN ‘Green’ package (RTL8201F) ‹ 48-pin MII/RMII LQFP ‘Green’ package (RTL8201FL) ‹ 48-pin MII/RMII QFN ‘Green’ package (RTL8201FN)

Figure 1. Application Diagram

3 Level

3 LevelMLT -3

Figure 2. Block Diagram

Figure 3. RTL8201F QFN-32 Pin Assignments

Figure 4. RTL8201FL LQFP-48 Pin Assignments

Figure 5. RTL8201FN QFN-48 Pin Assignments

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 8 Track ID: JATR-2265-11 Rev. 1.4 6. Pin Descriptions I: Input LI: Latched Input during Power up or Reset O: Output IO: Bi-directional input and output P: Power HZ: High impedance during power on reset PU: Internal Pull up during power on reset PD: Internal Pull down during power on reset OD: Open Drain output 6.1. MII Interface Table 1. MII Interface

Description

TXC O/PD 15 22 22 Transmit Clock. This pin provides a continuous clock as a timing reference for TXD [3:0] and TXEN signals. TXC is 25MHz in 100Mbps mode and 2.5MHz in 10Mbps mode. TXEN I/PD 20 27 27 Transmit Enable. The input signal indicates the presence of valid nibble data on TXD [3:0]. An internal weakly pulled low resistor prevents the bus floating. TXER I/PD - 12 12 Transmit Error. TXD[0] TXD[1] TXD[2] TXD[3] I/PD I/PD I/PD I/PD Transmit Data. The MAC will source TXD [0:3] synchronous with TXC when TXEN is asserted. An internal weakly pulled low resistor prevents the bus floating. RXC O/PD 13 19 19 Receive Clock. This pin provides a continuous clock reference for RXDV and RXD [0:3] signals. RXC is 25MHz in 100Mbps mode and 2.5MHz in 10Mbps mode. COL O/PD 27 38 38 Collision Detect. COL is asserted high when a collision is detected on the media. CRS/ CRS_DV O/PD 26 36 36 Carrier Sense. This pin’s signal is asserted high if the media is not in Idle state.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 9 Track ID: JATR-2265-11 Rev. 1.4 Name Type Pin No. (8201F) Pin No. (8201FL) Pin No. (8201FN) RXDV LI/O/PD 8 13 13 Receive Data Valid. This pin’s signal is asserted high when received data is present on the RXD[3:0] lines. The signal is de-asserted at the end of the packet. The signal is valid on the rising edge of the RXC. This pin should be pulled low when operating in MII mode. 0: MII mode 1: RMII mode An internal weakly pulled low resistor sets this to the default of MII mode. It is possible to use an external 4.7KΩ pulled high resistor to enable RMII mode. After power on, the pin operates as the Receive Data Valid pin. RXD[0] RXD[1] RXD[2] RXD[2]/ INTB O/PD LI/O/PD O/PD O/PD Receive Data. These are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the RXC for reception by the external physical unit (PHY). Note 1: An internal weakly pulled low resistor sets RXD[1] to the LED function (default). Use an external 4.7KΩ pulled high resistor to enable the WOL function for the RTL8201F . Note 2: The RTL8201F Pin11 is named RXD[2]/INTB. When in RMII mode, this pin is used for the interrupt function. See Table 9, page 14 for INTB descriptions. RXD[3]/ CLK_CTL LI/O/PD 12 18 18 Receive Data. This is the parallel receive data line aligned on the nibble boundaries driven synchronously to the RXC for reception by the external physical unit (PHY). RXD[3]/CLK_CTL pin is the Hardware strap in RMII Mode. 1: REF_CLK input mode 0: REF_CLK output mode Note: An internal weakly pulled low resistor sets RXD[3]/CLK_CTL to REF_CLK output mode (default). RXER/ FXEN LI/O/PD 28 39 39 Receive Error. If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid symbol, this pin will go high. Fiber/UTP Enable. This pin’s status is latched at power on reset to determine the media mode to operate in. 1: Fiber mode 0: UTP mode An internal weakly pulled low resistor sets this to the default of UTP mode. It is possible to use an external 4.7KΩ pulled high resistor to enable fiber mode. After power on, the pin operates as the Receive Error pin.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 10 Track ID: JATR-2265-11 Rev. 1.4 6.2. Serial Management Interface Table 2. Serial Management Interface MDC I/PU 22 30 30 Management Data Clock. This pin provides a clock synchronous to MDIO, which may be asynchronous to the transmit TXC and receive RXC clocks. The clock rate can be up to 2.5MHz. Use an internal weakly pulled high resistor to prevent the bus floating. MDIO IO/PU 23 31 31 Management Data Input/Output. This pin provides the bi-directional signal used to transfer management information. 6.3. RMII Interface Table 3. RMII Interface TXC IO/PD 15 22 22 Synchronous 50MHz Clock Reference for Receive, Transmit, and Control Interface. The direction is decided by Page 7, Register 16. The default direction is reference clock output mode if RXD[3]/CLK_CTL pin floating. CRS/ CRS_DV O/PD 26 36 36 Carrier Sense/Receive Data Valid. CRS_DV shall be asserted by the PHY when the receive medium is non-idle. TXEN I/PD 20 27 27 Transmit Enable. TXD[0:1] I/PD 16, 17 23, 24 23, 24 Transmit Data. RXD[0:1] O/PD 9, 10 14 , 16 14, 16 Receive Data. RXER/ FXEN LI/O/PD 28 39 39 Receive Error. RX_ER is a required output of the PHY , but is an optional input for the MAC. 6.4. Clock Interface Table 4. Clock Interface CKXTAL2 IO 32 43 43 25MHz Crystal Output. This pin provides the 25MHz crystal output. If an external 25MHz/50MHz oscillator or clock is used, connect CKXTAL2 to the oscillator or clock output (see section 9.4 Oscillator Requirements, page 53). CKXTAL1 I 31 42 42 25MHz Crystal Input. This pin provides the 25MHz crystal input. Must be shorted to GND when an external 25MHz/50MHz oscillator or clock drives CKXTAL2.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 11 Track ID: JATR-2265-11 Rev. 1.4 6.5. 10Mbps/100Mbps Network Interface Table 5. 10Mbps/100Mbps Network Interface MDI+[0] MDI-[0] IO 3 Transmit Output. Differential transmit output pair shared by 100Base-TX, 100Base-FX, and 10Base-T modes. When configured as 100Base-TX, output is an MLT-3 encoded waveform. When configured as 100Base-FX, the output is pseudo- ECL level. MDI+[1] MDI-[1] IO 5 Receive Input. Differential receive input pair shared by 100Base-TX, 100Base-FX, and 10Base-T modes. 6.6. Transmit Bias Reference Table 6. Transmit Bias Reference RSET I 1 46 46 Transmit Bias Resistor Connection. This pin should be pulled to GND by a 2.49KΩ (1%) resistor to define driving current for the transmit DAC. 6.7. Device Configuration Interface Table 7. Device Configuration Interface RXDV LI/O/PD 8 13 13 Receive Data Valid. This pin’s signal is asserted high when received data is present on the RXD [3:0] lines. The signal is de-asserted at the end of the packet. The signal is valid on the rising edge of the RXC. This pin should be pulled low when operating in MII mode. 0: MII mode 1: RMII mode An internal weakly pulled low resistor sets this to the default of MII mode. It is possible to use an external 4.7KΩ pulled high resistor to enable RMII mode. After power on, the pin operates as the Receive Data Valid pin. RXD[1] LI/O/PD 10 16 16 An internal weakly pulled low resistor sets RXD[1] to the LED function (default). Use an external 4.7KΩ pulled high resistor to enable the WOL function for the RTL8201F.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 12 Track ID: JATR-2265-11 Rev. 1.4 Name Type Pin No. (8201F) Pin No. (8201FL) Pin No. (8201FN) PHYAD[0] LED0/ PHYAD[0]/ PMEB LED1/ PHYAD[1] LED2/ PHYAD[2] LI/O/PU LI/O/PU LI/O/PD LI/O/PD PHY Address and Customized LED Settings. The default available PHY addresses are: RTL8201F: 00000~00011. RTL8201FL: 00100~00111 (when PMEB pin is pulled high) 00000~00011 (when PMEB pin is pulled low) RTL8201FN: 00000~00111. Traditional LED Function Selection LED _Sel 00 01 10 11 LED0 ACT ALL LinkALL/ ACTALL Link10/ ACTALL LINK10 /ACT10 LED1 LINK 100 LINK 100 LINK 100 LINK100/ ACT100 LED2 Reserved Reserved Reserved Reserved Note 1: For Customized LED Settings, see section 7.17, page 23. Note 2: LED_Sel default is 11. Refer to section 7.19, page 24. An internal weakly pulled low resistor sets RXD[1] to the LED function for RTL8201F (default). Use an external 4.7KΩ pulled high resistor to enable the WOL function for RTL8201F. Traditional LED Function Selection for the RTL8201F with WOL Enabled With the RTL8201F WOL function enabled, the PHY address must be 00001 or 00011. LED _Sel 00 01 10 11 LED1 LINK 100 LINK 100 LINK 100 LINK100/ ACT100 RXD[3]/ CLK_CTL LI/O/PD 12 18 18 Receive Data. This is the parallel receive data line aligned on the nibble boundaries driven synchronously to the RXC for reception by the external physical unit (PHY). RXD [3]/CLK_CTL pin is the Hardware strap in RMII Mode. 1: REF_CLK input mode 0: REF_CLK output mode Note: An internal weakly pulled low resistor sets RXD[3]/CLK_CTL to REF_CLK output mode (default).

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 13 Track ID: JATR-2265-11 Rev. 1.4 Name Type Pin No. (8201F) Pin No. (8201FL) Pin No. (8201FN) LI/O/PD 28 39 39 Fiber/UTP Interface. This pin’s status is latched at power on reset to determine the media mode to operate in. 1: Fiber mode 0: UTP mode An internal weakly pulled low resistor sets this to the default of UTP mode. It is possible to use an external 4.7KΩ pulled high resistor to enable fiber mode. EN_LDO_ OUT LI/O/PU - - 11 LDO Mode Strap. 1: LDO enable 2: LDO disable 6.8. Power and Ground Pins Table 8. Power and Ground Pins A VDD33 P 7, 30 6, 41 6, 41 3.3V Analog Power Input. 3.3V power supply for analog circuit; should be well decoupled. DVDD33 P 14 15, 21, 37 15, 21, 37 3.3V Digital Power Input. 3.3V power supply for digital circuit. DVDD10 P - 28 28 1.1V Digital Power. A VDD10OUT O 2 48 48 Power Output. Be sure to connect a 0.1µF ceramic capacitor for decoupling purposes. The connection method is outlined in section 8.8 3.3V Power Supply and V oltage Conversion Circuit, page 38. DVDD10OUT O 29 40 40 Power Output. Be sure to connect a 0.1µF ceramic capacitor for decoupling purposes. The connection method is outlined in section 8.8 3.3V Power Supply and V oltage Conversion Circuit, page 38. GND P E-PAD 7, 20, 33, E-PAD Ground. Should be conn ected to a larger GND plane. Exposed Pad (E-Pad) is Analog and Digital Ground.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 14 Track ID: JATR-2265-11 Rev. 1.4 6.9. Reset and Other Pins Table 9. Reset and Other Pins PHYRSTB I/HZ 21 29 29 RESETB. Set low to reset the chip. For a complete reset, this pin must be asserted low for at least 10ms. Note: When the WOL function is enabled, keep the pin high (RTL8201FN only). INTB O/OD - 32 20 Interrupt. Set low if link status changed, duplex changed, or auto negotiation failed. Active Low. This pin is an open-drain design, and for default value should be pulled high by an external 4.7KΩ. If not used, keep floating. RXD[2]/INTB O/PD 11 - - Interrupt. Set low if link status changed, duplex changed, or auto negotiation failed. Active Low. This pin is an open-drain design, and for default value should be pulled high by an external 4.7KΩ. If not used, keep floating. Note: This pin is used for the interrupt function only when in the RMII mode. PMEB O/OD 24 10 33 Power Management Enable. Set low if received a magic packet or wake up frame; active low. 6.10. NC (Not Connected) Pins Table 10. NC (Not Connected) Pins 44, 45 3, 7, 8, 9, 10, 44, 45, 47 Not Connected.

following abbreviations are used. Note: RW/EFUS and RW/LI types will return to default values after a software reset (set Reg.0 Bit15 to 1). Table 11. Register 0 Basic Mode Control Register default state. This bit is self-clearing. software reset (set Bit15 to 1). physical link associated with the PHY . 0:13 Speed Selection This bit sets the network speed. When 100Base-FX mode is enabled, this bit=1 and is read only. This bit enables/disables the NWay auto-negotiation function. When 100Base-FX mode is enabled, this bit=0 and is read only. internal crystal oscillator circuit. The MDC, MDIO is still alive for accessing the MAC. 0:10 Isolate 1: Electrically isolate the PHY from MII/GMII/RGMII/RSGMII. PHY is still able to respond to MDC/MDIO.

This bit allows the NWay auto-negotiation function to be reset. 0:7 Collision Test Collision Test. 0:6 Speed Selection[1] Speed Select Bit 1. Table 12. Register 1 Basic Mode Status Register management interface read/write transaction after reset. transactions as per IEEE 802.3u specifications.

read. For the current link status, read this register twice. Table 13. Register 2 PHY Identifier Register 1 Table 14. Register 3 PHY Identifier Register 2 Table 15. Register 4 Auto-Negotiation Advertisement Register (ANAR) 4:15 Next Page Next Page Bit.

4:4~0 Selector Field Binary Encoded Selector Supported by This Node. content changes after a successful auto-negotiation if Next-pages are supported. Table 16. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) 5:15 Next Page Next Page Bit. Partner ability (read only).

established by parallel detection. 5:4~0 Selector Field Link Partner’s Binary Encoded Node Selector. Currently only CSMA/CD 00001 is specified. This register contains additional status for NWay auto-negotiation. Table 17. Register 6 Auto-Negotiation Expansion Register (ANER)

Table 18. Page 0 Register 13 MACR (MMD Access Control Register; Address 0x0D) 13.4:0 DEV AD WO 0 Device Address. Note 1: Used in conjunction with the MAADR (Register 14) to provide access to the MMD address space. associated with the value in the DEVAD field. direct the MAADR data accesses to the appropriate registers within the MMD. Table 19. Page 0 Register 14 MAADR (MMD Access Address Data Register; Address 0x0E) Note: Used in conjunction with the MACR (Register 13) to provide access to the MMD address space. Table 20. Register 24 Power Saving Mode Register (PSMR) 24:15 Enpwrsave Enable Power Saving Mode. The bit will return to default value by software reset.

Table 21. Register 28 Fiber Mode and Loopback Register 28:1 Force_MDI Force MDI/MDIX Mode. Table 22. Register 30 Interrupt Indicators and SNR Display Register 30:15 Anerr Auto-Negotiation Error Interrupt. 30:14 Spdchg Speed Mode Change Interrupt. 30:13 Duplexchg Duplex Mode Change Interrupt. 30:11 Linkstatuschg Link Status Change Interrupt. Table 23. Register 31 Page Select Register

Table 24. Page4 Register 16 EEE Capability Enable Register 16:9 Tx_quiet_en Enable Ability to Turn Off Power 100TX when TX in Quiet State. This bit is recommended to be set to 1 when EEE is enabled. 16:8 Rx_quiet_en Enable Ability to Turn Off Power 100RX when RX in Quiet state. This bit is recommended to be set to 1 when EEE is enabled. Table 25. Page4 Register 21 EEE Capability Register Table 26. Page7 Register 16 RMII Mode Setting Register (RMSR) 16:12 Rg_rmii_clkdir This Bit Sets the Type of TXC in RMII Mode. Note: Set Page7, Register 16 to ‘7FFB’ when an external clock (25MHz and 50MHz) inputs to the CKXTAL2 pin.

This register is for setting customized LEDs. Table 27 shows the customized LED matrix table. Table 27. Customized LED Matrix Table Note: The RTL8201F/FL only supports LED0 and LED1. The RTL8201FN supports LED0, LED1, and LED2. Table 28. Page7 Register 17 Customized LEDs Setting Register 17:11~8 LED_sel2 Customized LED2 Setting. enable customized LED function. 17:7~4 LED_sel1 Customized LED1 Setting. enable customized LED function. 17:3~0 LED_sel0 Customized LED0 Setting. enable customized LED function. Table 29. Page7 Register 18 EEE LEDs Enable Register

Table 30. Page7 Register 19 Interrupt, WOL Enable, and LEDs Function Registers 19:13 Int_linkchg Link Change Interrupt Mask. behavior (see Table 22, page 21). 19:12 Int_dupchg Duplex Change Interrupt Mask. interrupt behavior (see Table 22, page 21). 19:11 Int_anerr NWay Error Interrupt Mask. behavior (see Table 22, page 21). 19:10 Rg_led0_wol_sel LED and Wake-On-LAN Function Selection (RTL8201F Only). enable the WOL function for the RTL8201F. 19:5~4 LED_sel[1:0] Traditional LED Function Selection. 19:3 Customized_LED Customized LED Enable. See the section 8.4.7 Customized LED, page 35 for detail.

Table 31. Page7 Register 20 MII TX Isolate Register Table 32. Page7 Register 24 Spread Spectrum Clock Register Note: MMD registers are placed at Page 0 Register 13 and Register 14. Table 33. MMD Register Mapping and Definition Table 34. EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) 3.0.15:11 RSVD RW 0 Reserved.

3.0.10 Clock Stop Enable RW 0 1: PHY stops RXC in LPI

Table 35. EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01) 3.1.15:12 RSVD RO 0 Reserved.

3.1.11 TX LPI Received RO, LH 0 1: TX PCS has received LPI

3.1.10 RX LPI Received RO, LH 0 1: RX PCS has received LPI

3.1.9 TX LPI Indication RO 0 1: TX PCS is currently receiving LPI

3.1.8 RX LPI Indi cation RO 0 1: RX PCS is currently receiving LPI

3.1.6 Clock Stop Capable RO 1 1: MAC stops TXC in LPI

Table 36. EEECR (EEE Capability Register, MMD Device 3; Address 0x14) 3.20.15:2 RSVD RO 0 Reserved. Table 37. EEEWER (EEE Wake Error Register, MMD Device 3; Address 0x16) sequence within the time required for the specific PHY type.

Table 38. EEEAR (EEE Advertisement Register, MMD Device 7; Address 0x3c) 7.60.15:3 RSVD RW 0 Reserved. 7.60.1 100Base-TX EEE RW 1 Advertise 100Base-TX EEE Capability. Table 39. EEELPAR (EEE Link Partner Ability Register, MMD Device 7; Address 0x3d) 7.61.15:3 RSVD RO 0 Reserved.

7.61.1 LP 100Base-TX EEE RO 0 1: Link Partner is capable of 100Base-TX EEE

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 28 Track ID: JATR-2265-11 Rev. 1.4 8. Functional Description The RTL8201F/FL/FN PHYceiver is a physical layer device that integrates 10Base-T and 100Base-TX/100Base-FX functions, and some extra pow er management features . This device supports the following functions:

• MII interface with MDC/MDIO management interface to communicate with the MAC
• IEEE 802.3u clause 28 Auto-Negotiation ability
• Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
• Power Down mode support
• 4B/5B transform
• Scrambling/De-scrambling
• NRZ to NRZI, NRZI to MLT-3
• Manchester Encode and Decode for 10Base-T operation
• Clock and Data recovery
• Adaptive Equalization
• Automatic Polarity Correction
• Far End Fault Indication (FEFI) in fiber mode
• Network status LEDs
• Wake-On-LAN (WOL)
• Energy Efficient Ethernet (EEE)
• Spread Spectrum Clock (SSC) for RMII REF_CLK output mode

a standard interface between the PHY and MAC layer. for both transmit and receive functions. supplied by the PHY – during the interval TXEN is asserted. and COL signals are used for collision detection and handling. has been confirmed and will be de-asserted when the IDLE pattern has been confirmed. or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal. reconciliation sublayer that an error was detected somewhere in the frame. Interface should have the frame structure shown in Table 40. Table 40. Management Frame Format frame structure for the management interface is illustrated in Figure 6 and Figure 7, page 30.

page0 register30 through the MDC/MDIO interface in response. through the MDC/MDIO management interface. (Page7 Register 19 Bit[13:11]). 100Mbps and half-duplex mode. Table 42. Setting the Medium Type and Interface Mode to MAC

signals, in four configurable operation modes. The following sections describe the various LED actions. Figure 8. LED and PHY Address Configuration The Link Monitor senses li nk integrity, such as LINK 10, LINK 100, LINK 10/ACT, or LINK 100/ACT. the link LED pin is driven high, indicating that no network connection exists.

enabled/disabled via page7, reg19[3] register (Figure 13). Refer to section 7.17, page 23 for customized LED register setting. Figure 13. Customized LED with/without LPI LED Mode

EEE Idle mode: LED continuous slow blinking. EEE Active mode: LED fast and slow blinking (on packet transmission and reception). Refer to Table 29, page 23 for EEE LED enable setting. Figure 14. EEE LED Behavior Table 43. Power Saving Mode Pin Settings PHY , it must create the MDC/MDIO timing by itself (this is done by software). off the transmit function. If the link is off, FLP or 100Mbps IDLE/10Mbps NLP will not be transmitted. 60%~80% when the link is down.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 37 Track ID: JATR-2265-11 Rev. 1.4 8.6. 10M/100M Transmit and Receive 8.6.1. 100Base-TX Transmit and Receive Operation 100Base-TX Transmit Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code (4B/5B encoding). Scrambling, seri alizing, and conversion to 125MHz, and NRZ to NRZI then takes place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver. The transmitter will first assert TXEN. Before transm itting the data pattern, it will send a /J/K/ symbol (Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a hub/switch environment, each RTL8201F/FL/FN will have different scrambler seeds and so spread the output of the MLT-3 signals. 100Base-TX Receive The received signal is compensated by the adaptive eq ualizer to make up for signal loss due to cable attenuation and Inter Symbol Interference (ISI). Ba seline Wander Correction mo nitors the process and dynamically applies corrections to the process of signal equalization. The Phase Locked Loop (PLL) then recovers the timing information from the signals and from the receive clock. With this, the received signal is sampled to form NRZI (Non-Return-to-Zero Inverted) data. The next steps are the NRZI to NRZ (Non- Return-to-Zero) process, unscrambling of the data, serial to parallel and 5B to 4B conversion, and passing of the 4B nibble to the MII interface. 8.6.2. 100Base-FX Fiber Transmit and Receive Operation The RTL8201F/FL/FN can be configured to 100B ase-FX mode via hardware configuration. The hardware 100Base-FX setting take s priority over NWay settings. A scrambler is not required in 100Base-FX. 100Base-FX Transmit Di-bits of TXD are processed as 100Base-TX except wi thout a scrambler before the NRZI stage. Instead of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL signals, which enter the fiber transceiver in differential-pair form. 100Base-FX Receive The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX. 8.6.3. 10Base-T Transmit and Receive Operation 10Base-T Transmit Transmit data in 4-bit nibbles (TXD[ 3:0]) clocked at 2.5MHz (TXC) is fi rst fed to a parallel-to-serial converter, then the 10Mbps NRZ si gnal is sent to a Manchester en coder. The Manchester encoder converts the 10Mbps NRZ data into a Manchester Enc oded data stream for the TP transmitter and adds a Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Fi nally, the encoded data stream is shaped by a band-limited filter embedded in the RTL8201F/FL/FN and then transmitted.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 38 Track ID: JATR-2265-11 Rev. 1.4 10Base-T Receive In 10Base-T receive mode, the Manchester decode r in the RTL8201F/FL/FN converts the Manchester encoded data stream into NRZ data by decoding the da ta and stripping off the SO I pulse. The serial NRZ data stream is then converted to a parallel 4-bit nibble signal (RXD[0:3]). 8.7. Reset and Transmit Bias There are two RTL8201F/FL/FN reset types: 1. Hardware Reset: Pull the PHYRSTB pin high fo r at least 150ms to access the RTL8201F/FL/FN registers. Pull the PHYRSTB pin low for at least 10m s and then pull high. All re gisters will return to default values after a hardware reset. The medi a interface will disconnect and restart the auto- negotiation/parallel detection process. 2. Software Reset: Set register 0 bit 15 to 1 for at least 20ms to access the R TL8201F/FL/FN registers. A Software reset will only partially reset the registers, and will reset the chip status to ‘initializing’. The RSET pin must be pulled low by a 2.49K Ω resistor with 1% accuracy to establish an accurate transmit bias. This will affect the signal quality of the transmit wavefo rm. Keep its circuitry away from other clock traces and transmit/receive paths to avoid signal interference. 8.8. 3.3V Power Supply and Voltage Conversion Circuit The RTL8201F/FL/FN is fabricated in a 0.11µm proce ss. The core circuit needs to be powered by 1.1V, however, the digital IO and DAC ci rcuits need a 3.3V power supply. Regulators are embedded in the RTL8201F/FL/FN to convert 3.3V to 1.1V. Note: The internal linear regulator output voltage is 1.1V . A 1.05V is supplied when using external core power. The external 1.05V power supply is not suggested for the RTL8201F/FL as the internal regulators cannot be disabled (the RTL8201F/FL does not have an EN_LDO_OUT pin to disa ble the internal 1.1V power supply), and the internal and external power sources may conflict. As with many commercial voltage conversion devices, th e 1.1V output pin of this circuit requires the use of an output capacitor (0.1µF X5R low-ESR ceramic capacitor) as part of the device frequency compensation. The analog and digital ground planes should be as large and intact as possible. If the ground plane is large enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the total ground plane is not sufficiently large, partition of the ground plan e is not a good idea. In this case, all the ground pins can be connected together to a larger single and intact ground plane. Note: The embedded 1.1V LDO is designed for PHYceiver device internal use only. Do not provide this power to other devices.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 39 Track ID: JATR-2265-11 Rev. 1.4 8.9. Automatic Polarity Correction The RTL8201F/FL/FN automatically corrects polarity errors on the receive pairs in 10Base-T mode (polarity is irrelevant in 100Base-TX mode). In 10Base-T mode, polarity errors are corrected based on the detection of validly spaced link pulses. Detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The polarity becomes unlocked when the link goes down. 8.10. Far End Fault Indication The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled, and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method that is composed of 84 consecutive ‘1’s followed by one ‘0 ’. When the RTL8201F/FL/FN detects this pattern three times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201F/FL/FN will start sending this pattern, which in turn causes the remote si de to detect a Far End Fault. This means that the receive path has a problem from the point of view of the RTL8201F/FL/FN. The FEFI mechanism is used only in 100Base-FX mode. 8.11. Wake-On-LAN (WOL) 8.11.1. Magic Packet and Wake-Up Frame Format The RTL8201F/FL/FN can monitor the network for a Wake-Up Frame or a Magic Packet, and notify the system via the PMEB (Power Management Event; ‘B’ means low active) pin when such a packet or event occurs. The system can then be restored to a normal state to process incoming jobs. The PMEB pin must be connected with a 4.7k-ohm resistor and pulle d up to 3.3V. When the Wake-Up Frame or a Magic Packet is sent to the PHY, the PMEB pin will be se t low to notify the system to wake up. Refer to the WOL application note for details. Magic Packet Wake-Up occurs only when the following conditions are met:

• The destination address of the received Magic Packet is acceptable to the RTL8201F/FL/FN, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8201F/FL/FN.
• The received Magic Packet does not contain a CRC error.
• The Magic Packet pattern matches; i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid Ethernet packet. A Wake-Up Frame event occurs only when the following conditions are met:
• The destination address of the received Wake-Up Frame is acceptable to the RTL8201F/FL/FN, e.g., a broadcast, multicast, or unicast address to the current RTL8201F/FL/FN.
• The received Wake-Up Frame does not contain a CRC error.

Table 44. Wake-On-LAN Pin Types (MII Mode) Note 1: If TX Isolate=1, the TXC is halted and the pin type is ‘L’. Set page0, register0, and bit10=1 to change the TXC pin type to ‘PD’. Note 2: If RX Isolate=1, all the MII RX interfaces are halted and the pin types are ‘PD’. Table 45. Wake-On-LAN Pin Types (RMII Mode) Note 1: If TXC (REF_CLK) is in input mode (MAC to PHY), the REF_CLK cannot halt at WOL Enable. the TXC pin type to ‘PD’, set page0, register0, bit10=1. Note 3: If RX Isolate=1, all RMII RX interfaces are halted and the pin types are ‘PD’.

without dropping/corrupting frames. EEE also specifies a negotiation method to enable link partners to determine whether EEE is supported. Refer to http://www.ieee802.org/3/az/index.html for more details. power saving mode register settings. lowering unwanted EMI noise. 7 Register 24 Spread Spectrum Clock Register, page 25). Figure 19. Spectrum Spread Clock

Table 46. Absolute Maximum Ratings Note: The internal linear regulator output voltage is 1.1V . Table 47. Recommended Operating Conditions Note: The internal linear regulator output voltage is 1.1V .

Figure 20. Power On and PHY Reset Sequence Table 48. Power On and PHY Reset Sequence Note: Rt2 requires 100µs Rise Time only when using an external 1.05V power supply.

The whole system power dissipation (including regulator loss) is shown in Table 49. Table 49. RMII Input Mode Power Dissipation (Whole System) Note: Setting page 4 register 21 bit12 to ‘1’ will reduce power consumption when the system is idle. Table 50. Input Voltage: Vcc

Table 52. MII Reception Cycle Timing Figure 26. RMII Interface Setup, Hold Time, and Output Delay Time Definitions

Figure 27. RMII Transmission and Reception Cycle Timing Table 53. RMII Transmission and Reception Cycle Timing Note 1: RMII TX timing can be adjusted by setting page7, register16[11:8]; the minimum adjustable resolution is 2ns. Any changes for these bits are not recommended as the default value is the optimum setting. changes for these bits are not recommended as the default value is the optimum setting.

Table 55. Crystal Characteristics Fundamental Mode, A T-Cut Type. Fundamental Mode, A T-Cut Type. Ta=0°C~70°C. Fundamental Mode, A T-Cut Type. Ta=25°C. Note 1: 25KHz to 25MHz RMS < 3ps. Note 2: Broadband RMS < 9ps. Table 56. Oscillator Requirements Note 1: 25KHz to 25MHz RMS < 3ps. Note 2: Broadband RMS < 9ps.

Table 57. Clock Requirements Note 1: 25KHz to 25MHz RMS < 3ps. Note 2: Broadband RMS < 9ps. Table 58. Transformer Characteristics

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 55 Track ID: JATR-2265-11 Rev. 1.4 10. Mechanical Dimensions 10.1. RTL8201F (QFN-32) Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A3 0.20REF 0.008REF D/E 5.00BSC 0.197BSC e 0.50BSC 0.020BSC Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). Note 2: REFERENCE DOCUMENT: JEDEC MO-220.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 56 Track ID: JATR-2265-11 Rev. 1.4 10.2. RTL8201FL (LQFP-48) Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A1 0.05 - 0.15 0.002 - 0.006 D/E 9.00BSC 0.354BSC D1/E1 7.00BSC 0.276BSC e 0.50BSC 0.020BSC L1 1.00REF 0.039REF Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). Note 2: REFERENCE DOCUMENT: JEDEC MS-026.

RTL8201F/RTL8201FL/RTL8201FN Datasheet Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 57 Track ID: JATR-2265-11 Rev. 1.4 10.3. RTL8201FN (QFN-48) Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A3 0.20REF 0.008REF D/E 6.00BSC 0.236BSC e 0.40BSC 0.016BSC Notes 1: CONTROLLING DIMENSION: MILLIMETER (mm). Note 2: REFERENCE DOCUMENT: JEDEC MO-220.

Table 59. Ordering Information Note: See page 5, 6, and 7 for package identification. Table 60. RTL8201F Series Selection Guide Note: The RTL8201F INTB pin is used for the interrupt function only when in the RMII mode.