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10/100 FAST ETHERNET PHYCEIVER WITH AUTO MDIX DATASHEET Rev. 1.3
17 September 2007
Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX ii Track ID: JATR-1076-21 Rev. 1.3 COPYRIGHT ©2007 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX iii Track ID: JATR-1076-21 Rev. 1.3
REVISION HISTORY
Revision Release Date Summary 1.0 2006/06/29 First release. 1.1 2006/08/22 Revised pin names: PWFBOUT18 => PWOUT18 PWFBOUT15 => PWOUT15. Revised RTL8201N-GR (64-Pin QFN) Pin Assignments: DVDD33 (pin 18, 34, 49) => NC DVDD15 (pin 32, 45, 59) => NC (see Table 9 and Table 10). Revised Table 32, Power Dissipation, page 27. 1.2 2007/02/12 Revised COL/C ONFIG[6] description, Table 2, MII Interface, page 6. Added section 6.3 RMII Interface, page 7. Revised Table 32, Power Dissipation, page 27. Added section 9.2.3 RMII Transmission Cycle Timing, page 31. 1.3 2007/09/17 Added RTL8201R data. Revised Figure 1, page 3 (Added RMII Interface). Revised Table 3 RMII Interface, page 7 (REFCLK description). Revised Table 5 Clock Interface, page 8 (exchanged the pin numbers of CKXTAL1 and CKXTAL2. Revised Table 28 Auto-Negotiation Mode Pin Settings, page 22 (modified MII/SNI description). Modified section 9.2.3 and section 9.2.4 RMII Transmission/Reception Cycle Timing, page 31.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX iv Track ID: JATR-1076-21 Rev. 1.3 Table of Contents
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX v Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 1 Track ID: JATR-1076-21 Rev. 1.3 1. General Description The RTL8201N (64-Pin QFN) is a single-chip/single-port PHYceiver that supports:
- MII (Media Independent Interface)
- RMII (Reduced Media Independent Interface)
- SNI (Serial Network Interface) The RTL8201R (32-Pin QFN) is a single-chip/single-port PHYceiver that supports RMII mode only. The chips implement all 10/100M Ethernet Physical -layer functions includ ing the Physical Coding Sublayer (PCS), Physical Medium Attachment (P MA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), with an auto MDIX function, 10Base-Tx Encoder/Decoder, and Twisted-Pair Media Access Unit (TPMAU). A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX fiber optical transceiver. The chip utilizes an advanced CMOS pro cess to meet low voltage and low power requirements. With on-chip DSP (Digital Signal Processing ) technology, the chip provides excellent performance under all operating conditions.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 2 Track ID: JATR-1076-21 Rev. 1.3 2. Features The Realtek RTL8201N & RTL8201R are Fast Ethernet PHYceivers with selectab le MII, RMII, or SNI interfaces to the MAC chip. They provide the following features: RTL8201N-GR supports MII, RMII, and 7-wire SNI RTL8201R-GR supports RMII mode only Supports 50MHz output for RMII mode (RTL8201R only) 10/100Mbps operation Full/half duplex operation Twisted pair or fiber mode output Auto-Negotiation Supports power down mode Supports operation under Link Down Power Saving mode Supports Base Line Wander (BLW) compensation Supports auto MDIX Supports repeater mode Adaptive Equalization Network status LEDs Flow control support 25MHz crystal/oscillator as clock source IEEE 802.3/802.3u compliant Supports IEEE 802.3u clause 28; 1.5V operation with 3.3V IO signal tolerance Low power supply, 1.5V, 1.8V, and 3.3V; 1.5V/1.8V is generated by an internal regulator 0.15µm CMOS process 64-pin (RTL8201N) or 32-pin (RTL8201R) QFN packages 3. Applications Network Interface Adapter MAU (Media Access Unit) CNR (Communication and Network Riser) ACR (Advanced Communication Riser) Ethernet hub Ethernet switch In addition, it can be used in any embedded system with an Ethernet MAC that needs a UTP physical connection or Fiber PECL interface to an external 100Base-FX optical transceiver module.
3 Level
Figure 1. Block Diagram
Figure 2. RTL8201N-GR (64-Pin QFN) Pin Assignments Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
Note: The RTL8201R-GR (32-Pin QFN) supports RMII mode only. Figure 3. RTL8201R-GR (32-Pin QFN) Pin Assignments Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 6 Track ID: JATR-1076-21 Rev. 1.3 6. Pin Descriptions LI: Latched Input during Power up or Reset O: Output I: Input IO: Bi-directional input and output P: Power 6.1. Management Interface Table 1. Management Interface
Description
MDC I 30 17 Management Data Clock. This pin provides a clock synchronous to MDIO, which may be asynchronous to the transmit TXC and receive RXC clocks. The clock rate can be up to 2.5MHz. Use an internal weak pull high resistor to prevent the bus floating. MDIO IO 31 18 Management Data Input/Output. This pin provides the bi-directional signal used to transfer management information. 6.2. MII Interface (RTL8201N Only) Table 2. MII Interface (RTL8201N Only) TXC O 24 Transmit Clock. This pin provides a continuous clock as a timing reference for TXD[3:0] and TXEN. TXEN I 29 Transmit Enable. The input signal indicates the presence of valid nibble data on TXD[3:0]. An internal weak pull low resistor to prevent the bus floating. TXD[3:0] I 28, 27, 26, 25 Transmit Data. The MAC will source TXD[0..3] synchronous with TXC when TXEN is asserted. An internal weak pull high resistor prevents the bus floating. RXC O 22 Receive Clock. This pin provides a continuous clock reference for RXDV and RXD[0..3] signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode. COL/ CONFIG[6] LI/O 46 Collision Detect. COL is asserted high when a collision is detected on the media. During power on reset, this pin status is latched to determine at which interface mode to operate: 0: MII mode 1: SNI mode This pin can be directly connected to GND or VCC.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 7 Track ID: JATR-1076-21 Rev. 1.3 Name Type Pin No. (64-pin) CONFIG[5] LI/O 47 Carrier Sense. This pin’s signal is asserted high if the media is not in Idle state. During power on reset, this pin set high to put the RTL8201N into repeater mode. This pin can be directly connected to GND or VCC. RXDV/ RMII LI/O 16 Receive Data Valid. This pin’s signal is asserted high when received data is present on the RXD[3:0] lines. The signal is de-asserted at the end of the packet. The signal is valid on the rising edge of the RXC. During power on reset, this pin status is latched to determine at which interface mode to operate: 0: MII mode (RTL8201N Only) 1: RMII mode This pin can be directly connected to GND or VCC. RXD[3:0] O 21, 20, 19 , 17 Receive Data. These are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the RXC for reception by the external physical unit (PHY). RXER/ CONFIG[8] LI/O 35 Receive Error. If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid symbol, this pin will go high. Fiber/UTP Enable. During power on reset, this pin status is latched to determine the media mode to operate in. 1: Fiber mode 0: UTP mode An internal weak pull low resistor sets this to the default of UTP mode. It is possible to use an external 5.1KΩ pull high resistor to enable fiber mode. After power on, the pin operates as the Receive Error pin. 6.3. RMII Interface Table 3. RMII Interface RXDV O 16 9 Receive Data Valid RXD[1:0] O 19, 17 11, 10 Receive Data TXEN I 29 15 Transmit Enable TXD[1:0] I 26, 25 14, 13 Transmit Data RXER O 35 19 Receive Error REFCLK I 24 12 Synchronous clock reference for receive, transmit, and control interface REFCLK O NULL 12 50MHz reference clock generated from internal PLL. CLK_CTL LI NULL 16 REFCLK Control This pin is latched to input during a power on or reset condition. It determines the REFCLK pin type. 1: REFCLK pin is input type 0: REFCLK pin is output type This pin can be directly connected to GND or VCC.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 8 Track ID: JATR-1076-21 Rev. 1.3 6.4. SNI (Serial Network Interface) 10Mbps Only. (RTL8201N Only) Table 4. SNI (Serial Network Interface) 10Mbps Only. (RTL8201N Only) COL O 46 Collision Detect. RXD0 O 17 Received Serial Data. CRS O 47 Carrier Sense. RXC O 22 Receive Clock. Resolved from received data. TXD0 I 25 Transmit Serial Data. TXC O 24 Transmit Clock. Generated by PHY . TXEN I 29 Transmit Enable. For MAC to indicate transmit operation. 6.5. Clock Interface Table 5. Clock Interface CKXTAL2 O 61 30 25MHz Crystal Output. This pin provides the 25MHz crystal output. It must be left open when an external 25MHz oscillator drives X1. CKXTAL1 I 62 31 25MHz Crystal Input. This pin provides the 25MHz crystal input. If a 25MHz oscillator is used, connect CKXTAL1 to the oscillator’s output (see 9.3 Crystal Characteristics, page 35, for clock source specifications). 6.6. 10Mbps/100Mbps Network Interface Table 6. 10Mbps/100Mbps Network Interface MDI+[0] MDI-[0] O O Transmit Output. Differential transmit output pair shared by 100Base-TX, 100Base-FX, and 10Base-T modes. When configured as 100Base-TX, output is an MLT-3 encoded waveform. When configured as 100Base-FX, the output is pseudo-ECL level. RSET I 1 1 Transmit Bias Resistor Connection. This pin should be pulled to GND by a 2KΩ (1%) resistor to define driving current for the transmit DAC. The resistance value may be changed, depending on experimental results of the RTL8201N/RTL8201R.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 9 Track ID: JATR-1076-21 Rev. 1.3 Name Type Pin No. (64-pin) Pin No. (32-pin) MDI+[1] MDI-[1] I I Receive Input. Differential receive input pair shared by 100Base-TX, 100Base-FX, and 10Base-T modes. 6.7. Device Configuration Interface (RTL8201N Only) Table 7. Device Configuration Interface (RTL8201N Only) CONFIG[4:0] I 53, 54, 56, 57, 58 PHY Address. Set the PHY address for the device. CONFIG[5] LI/O 47 Repeater mode. Set high to put the RTL8201N into repeater mode. This pin can be directly connected to GND or VCC. CONFIG[6] LI/O 46 MII/SNI interface. This pin is latched to input during a power on or reset condition. Pull high to set the RTL8201N into SNI mode operation. Set low for MII mode. This pin can be directly connected to GND or VCC. CONFIG[7] LI 37 Auto-negotiation mode. This pin is latched to input during a power on or reset condition. Set high to enable Auto-negotiation mode, set low to force mode. This pin can be directly connected to GND or VCC. CONFIG[8] LI/O 35 Fiber/UTP Enable. During power on reset, this pin status is latched to determine the media mode to operate in. 1: Fiber mode 0: UTP mode An internal weak pull low resistor sets this to the default of UTP mode. It is possible to use an external 5.1KΩ pull high resistor to enable fiber mode. CONFIG[9] LI 33 Speed Mode. This pin is latched to input during a power on or reset condition. Set high to put the RTL8201N into 100Mbps operation. This pin can be directly connected to GND or VCC. ISOLATE I 52 Set high to isolate the RTL8201N from the MAC. This will also isolate the MDC/MDIO management interface. In this mode, the power consumption is minimal. This pin can be directly connected to GND or VCC. DUPLEX LI 51 This pin is latched to input during a power on or reset condition. Set high to enable full duplex. This pin can be directly connected to GND or VCC. LDPS I 44 Set high to put the RTL8201N into LDPS mode. This pin can be directly connected to GND or VCC (see 8.7 Power Down, Link Down, Power Saving, and Isolation Modes, page 23, for more information).
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 10 Track ID: JATR-1076-21 Rev. 1.3 6.8. LED Interface Table 8. LED Interface/PHY Address Configuration LED_LINK10 O 50 25 10Mbps link indicator. LED_LINK100 O 48 24 100Mbps link indicator. LED_DUPLEX O 43 NULL Duplex LED. LED_RX O 40 23 Receive LED. LED_TX O 39 22 Transmit LED. CONFIG[4:0]/ CONFIG[1:0] I 53, 54, 56, 57, 58 27, 28 PHY Address. Set the PHY address for the device. 6.9. Power Pins Table 9. Power Pins A VDD33 P 60 29 3.3V Analog Power Input. 3.3V power supply for analog circuit; should be well decoupled. DVDD33 P 23, 42, 55 26 3.3V Digital Power Input. 3.3V power supply for digital circuit. A VDD18 P 5, 10 5, 8 Analog Power. 1.8V . DVDD15 P 36 20 Digital Power. 1.5V . 6.10. Reset and Other Pins Table 10. Reset and Other Pins PHYRSTB I 38 21 RESETB. Set low to reset the chip. For a complete reset, this pin must be asserted low for at least 10ms. PWOUT18 PWOUT15 O O Power Output. Be sure to connect a 22µF tantalum capacitor for frequency compensation. The connection method is outlined in 8.11 3.3V Power Supply and V oltage Conversion Circuit, page 26. 32, 34, 41, 45, 49, 59, 63 NULL Not Connected.
This section describes the functions and usage of the registers available in the RTL8201N/RTL8201R. Table 11. Register 0 Basic Mode Control Register state. This bit is self-clearing. 0:13 Spd_Set This bit sets the network speed. After completing auto negotiation, this bit will reflect the Speed status. When 100Base-FX mode is enabled, this bit=1 and is read only. This bit enables/disables the NWay auto-negotiation function. 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored. speed and the data transfer mode, respectively. When 100Base-FX mode is enabled, this bit=0 and is read only. This bits allows the NWay auto-negotiation function to be reset. After completing auto-negotiation, this bit will reflect the duplex status. 0:0 RMII Mode This bit sets the RMII mode.
Table 12. Register 1 Basic Mode Status Register
Table 13. Register 2 PHY Identifier Register 1 Table 14. Register 3 PHY Identifier Register 2 Table 15. Register 4 Auto-Negotiation Advertisement Register (ANAR) CSMA/CD 00001 is specified. No other protocols are supported.
content changes after a successful auto-negotiation if Next-pages are supported. Table 16. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)
This register contains additional status for NWay auto-negotiation. Table 17. Register 6 Auto-Negotiation Expansion Register (ANER) 6:4 MLF Indicates whether a multiple link fault has occurred. 6:3 LP_NP_ABLE Indicates whether the link partner supports Next Page negotiation. Next Pages. Internal use only. 6:1 PAGE_RX This bit is set when a new Link Code Word Page has been received. ability register (register 5) is read by management. Table 18. Register 16 NWay Setup Register (NSR) Table 19. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)
722ms time-out’ to be reported. Table 20. Register 18 RX_ER Counter (REC) received. The value is valid while the link is established. Table 21. Register 19 SNR Display Register Table 22. Register 25 Test Register
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 17 Track ID: JATR-1076-21 Rev. 1.3 8. Functional Description The RTL8201N/RTL8201R PHYceiver is a physical layer device that in tegrates 10Base-T and 100Base-TX/100Base-FX functions, and some extra pow er management features into a 64-pin/32-pin single chip that is used in 10/100 Fast Ethernet applications. This device supports the following functions:
- MII interface with MDC/MDIO SMI management interface to communicate with MAC (RTL8201N only)
- RMII interface with MDC/MDIO SMI management interface to communicate with MAC
- IEEE 802.3u clause 28 Auto-Negotiation ability
- Flow control ability support to cooperate with MAC
- Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
- Flexible LED configuration
- 7-wire SNI (Serial Network Interface) support (only in 10Mbps mode & only RTL8201N)
- Power Down mode support
- 4B/5B transform
- Scrambling/De-scrambling
- NRZ to NRZI, NRZI to MLT-3
- Manchester Encode and Decode for 10Base-T operation
- Clock and Data recovery
- Adaptive Equalization
- Far End Fault Indication (FEFI) in fiber mode 8.1. MII/RMII Modes 8.1.1. MII Data Transition (RTL8201N Only) To set the RTL8201N for MII mode operation, pull th e MII/SNI pin low and se t the ANE, SPEED, and DUPLEX pins. The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying a standard interface between the PHY and MAC layer. This interface operates at two frequencies – 25MHz and 2.5MHz to support 100Mbps/10Mbps bandwidth for both transmit and receive functions. Transmission The MAC asserts the TXEN signal. It then changes byt e data into 4-bit nibbles and passes them to the signal supplied by the PHY – during the interval TXEN is asserted. Reception The PHY asserts the RXEN signal. It passes the r eceived nibble data RXD[ 0..3] clocked by RXC. CRS and COL signals are used for collision detection and handling.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 18 Track ID: JATR-1076-21 Rev. 1.3 In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is recognized as IDLE it will be de-asserted. In 10Bas e-T mode, CRS will assert when the 10M preamble has been confirmed and will be de-asserted when the IDLE pattern has been confirmed. The RXDV signal will be asserted when decoded 5B are /J/K/ and will be de-asserted if the 5B are /T/R/ or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal. The RXER (Receive Error) signa l will be asserted if a ny 5B decode errors occur, e.g., an invalid J/K, invalid T/R, or invalid symbol. This pin will go high for one or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame. Note: The RTL8201N does not use a TXER signal. This does not affect the transmit function. 8.1.2. RMII Data Transition The RTL8201N/RTL8201R comply with the RMII requirements outlined in the RMII Consortium specification. The main advantage introduced by RMII is pin count reduction; e .g., it operates with only one 50MHz reference clock for both the TX and RX side s, without separate clocks needed for both paths, as with the MII interface. However, some hardware modification is needed for this change, the most important of which is the presence of an elastic buffer for absorp tion of the frequency difference between the 50MHz reference clock and the clocking information of the incoming data stream. Another change implemented is that MII RXDV and Carrier_Sense are merged into one signal, CRS_DV, which is asserted high when detecting incoming pack et data. When internal Carrier_Sense de-asserted, CRS_DV is de-asserted when the first di-bit of a nibble is presented onto RXD[1..0] synchronously to REFCLK. If there is still data in the FIFO that has not yet been pr esented onto RXD[1..0], then, on the second di-bit of a nibble, CRS_DV r easserts. This pattern of assertion and de-assertion continues until all received data in the FIFO has been presented onto RXD[1..0]
illustrated in Figure 4 and Figure 5. pattern, it will change to 100Mbps and half duplex mode. Table 24. Setting the Medium Type and Interface Mode to MAC (RTL8201N Only) L L UTP mode and MII interface. L H UTP mode and SNI interface. H X Fiber mode and MII interface.
Table 25. UTP Mode and MII Interface (RTL8201N Only) /100Base-TX, half/full duplex mode operation. Table 26. UTP Mode and SNI Interface (RTL8201N Only) X X L The duplex pin is pulled low to support the 10Base-T half duplex function. 10Base-T half duplex is the specified default mode in the SNI interface. pulled high to support 10Base-T full duplex function. and SPEED configuration is ignored when Fiber mode is enabled. Table 27. Fiber Mode and MII Interface (RTL8201N Only) X X H The duplex pin is pulled high to support 100Base-FX full duplex function. X X L The duplex pin is pulled low to support 100Base-FX half duplex function.
This section describes methods to configure th e RTL8201N and set the auto-negotiation mode. Table 28 shows the various pins and their settings. Table 28. Auto-Negotiation Mode Pin Settings Saving, and Isolation Modes, page 23). Down, Link Down, Power Saving, and Isolation Modes, page 23). the RTL8201N. This pin pulled high will se t the RTL8201N into SNI mode operation. Serial Network Interface, page 23). Parallel Detection, page 20). and Parallel Detection, page 20).
default operation to 10Mbps and half-duplex mode. Note: The RTL8201N also supports full-duplex mode operation if the DUPLEX pin has been pulled high. receive serial data, transmit enable, collision detect, and carry sense signals. mode. The first three modes are configured through software, and the fourth through hardware. Table 29. Power Saving Mode Pin Settings IDLE/10Mbps NLP will not be transmitted. However, some signals similar to NLP will be transmitted. IDLE/10Mbps NLP again. This can cut power used by 60%~80% when the link is down. the PHY , it must create the MDC/MDIO timing by itself (this is done by software). Note: Isolation is supported by the RTL8201N only.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 24 Track ID: JATR-1076-21 Rev. 1.3 8.8. Media Interface 8.8.1. 100Base-TX Transmit & Receive Operation 100Base-TX Transmit (RTL8201N) Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code (4B/5B encoding). Scrambling, seri alizing, and conversion to 125MHz, and NRZ to NRZI then takes place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver. The transmitter will first assert TXEN. Before transm itting the data pattern, it will send a /J/K/ symbol (Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a hub/switch environment, each RTL8201N will have different scrambler seeds and so spread the output of the MLT-3 signals. 100Base-TX Transmit (RTL8201R) Transmit data in 2-bit nibbles (TXD[1:0]) clocked at 50MHz (REFCLK) is transformed into 5B symbol code (4B/5B encoding). Scrambling, serializing, a nd conversion to 125MHz, and NRZ to NRZI then takes place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver. The transmitter will first as sert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol (Start-of-frame delimiter), the data symbol , and finally a /T/R/ symbol known as the End-Of- Frame delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a hub/switch environment, each RTL8201R will have different scrambler seeds and so spread the output of the MLT-3 signals. 100Base-TX Receive The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable attenuation and Inter Symbol Interference (ISI). Ba seline Wander Correction mo nitors the process and dynamically applies corrections to th e process of signal equa lization. The PLL then recovers the timing information from the signals and from the receive clock. With this, the received signal is sampled to form NRZI data. The next steps are the NR ZI to NRZ process, unscrambling of the data, serial to parallel and 5B to 4B conversion, and passing of the 4B nibble to the MII/RMII interface.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 25 Track ID: JATR-1076-21 Rev. 1.3 8.8.2. 100Base-FX Fiber Transmit & Receive Operation (RTL8201N Only) The RTL8201N can be configured as 100Base-FX vi a hardware configuration. The hardware 100Base FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX. 100Base-FX Transmit Di-bits of TXD are processed as 100Base-TX except wi thout a scrambler before the NRZI stage. Instead of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL signals, which enter the fiber transceiver in differential-pairs form. 100Base-FX Receive The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX. 8.8.3. 10Base-T Transmit & Receive Operation 10Base-T Transmit (RTL8201N) Transmit data in 4-bit nibbles (TXD[ 3:0]) clocked at 2.5MHz (TXC) is fi rst fed to a parallel-to-serial converter, then the 10Mbps NRZ si gnal is sent to a Manchester en coder. The Manchester encoder converts the 10Mbps NRZ data into a Manchester Enc oded data stream for the TP transmitter and adds a Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Fi nally, the encoded data stream is shaped by a band-limited filter embedded in the RTL8201N and then transmitted. 10Base-T Transmit (RTL8201R) Transmit data in 2-bit nibbles (TXD[1: 0]) clocked at 50MHz (REFCLK) is first fed to a pa rallel-to-serial converter, then the 10Mbps NRZ si gnal is sent to a Manchester en coder. The Manchester encoder converts the 10Mbps NRZ data into a Manchester Enc oded data stream for the TP transmitter and adds a Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Fi nally, the encoded data stream is shaped by a band-limited filter embedded in the RTL8201R and then transmitted. 10Base-T Receive (RTL8201N) In 10Base-T receive mode, the Manchester decoder in the RTL8201N converts the Manchester encoded data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data stream is converted to a parallel 4-bit nibble signal (RXD[3:0]). 10Base-T Receive (RTL8201R) In 10Base-T receive mode, the Manchester decoder in the RTL8201R converts the Manchester encoded data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data stream is converted to a parallel 2-bit nibble signal (RXD[1:0]).
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 26 Track ID: JATR-1076-21 Rev. 1.3 8.9. Repeater Mode Operation Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, se ts the RTL8201N/RTL8201R into repeater mode. In repeater mode, the RTL8201N/RTL 8201R will assert CRS hi gh only when receiving a packet. In NIC mode, the RTL8201N/RTL8201R w ill assert CRS high both when transmitting and receiving packets. If using the RTL8201N/RTL8201R in a NIC or switch application, set to the default mode. NIC/Switch mode is the default setting and has the RPTR pin pulled low, or bit 15 of register 17 is set to 0. 8.10. Reset and Transmit Bias The RTL8201N/RTL8201R can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It can also be reset by setting bit 15 of regist er 0 to 1, and then setting it back to 0. Reset will clear the registers and re-initialize them. The me dia interface will disconnect and restart the auto- negotiation/parallel detection process. The RTSET pin must be pulled low by a 2K Ω resister with 1% accuracy to establish an accurate transmit bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from other clock traces and transmit/receive paths to avoid signal interference. 8.11. 3.3V Power Supply and Voltage Conversion Circuit The RTL8201N/RTL8201R is fabricated in a 0.15 µm process. The core circuit needs to be powered by 1.5V, however, the digital IO and DAC circuits need a 3.3V power supply. Two regulators are embedded in the RTL8201N/RTL8201R to convert 3.3V to 1.5V and 1.8V. As with many commercial voltage conversion devices, the 1.5V/1.8V output pin (PWFBOUT) of this circu it requires the use of an output capacitor (22µF tantalum capacitor) as part of the device frequency compensation. The analog and digital ground planes should be as large and intact as possible. If the ground plane is large enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the total ground plane is not sufficiently large, partition of the ground plan e is not a good idea. In this case, all the ground pins can be connected together to a larger single and intact ground plane. 8.12. Far End Fault Indication (RTL8201N Only) The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled, and indicates when a FEFI has been detected. FEFI is an alternativ e in-band signaling method which is composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201N detects this pattern three times, Reg.1.4 is set, which means the transmit path (t he Remote side’s receive path) has a problem. On the other hand, if an incoming signal fails to caus e a ‘Link OK’, the RTL8201N will start sending this pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path has a problem from the point of view of the RTL8201N. The FEFI mechanism is used only in 100Base-FX mode.
Table 30. Absolute Maximum Ratings Table 31. Operating Conditions Table 32. Power Dissipation
Table 33. Input Voltage: Vcc
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 36 Track ID: JATR-1076-21 Rev. 1.3 10. Mechanical Dimensions 10.1. RTL8201N 64-Pin QFN Mechanical Dimensions Note: For RTL8201N specific information, refer to line 4. Note: Exposed Pad is Analog and Digital Ground.
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 37 Track ID: JATR-1076-21 Rev. 1.3 10.2. RTL8201R 32-Pin QFN Mechanical Dimensions
RTL8201N &RTL8201R Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 38 Track ID: JATR-1076-21 Rev. 1.3
Table 43. Ordering Information Note: See page 4 and 5 for package identification.