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10/100 FAST ETHERNET PHYCEIVER WITH AUTO MDIX DATASHEET Rev. 1.1

26 September 2007

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX ii Track ID: JATR-1076-21 Rev. 1.1 COPYRIGHT ©2007 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2007/08/31 First release. 1.1 2007/09/26 Modify Table 2 RMII Interface, page 6 (CLK_CTL data). Modify Table 33 MII Transmission Cycle Timing, page 26 (t5 100Mbps data). Modify Table 40 Crystal Characteristics, page 33 (Frequency Tolerance at -20~70°C data).

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX iii Track ID: JATR-1076-21 Rev. 1.1 Table of Contents

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX iv Track ID: JATR-1076-21 Rev. 1.1

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 1 Track ID: JATR-1076-21 Rev. 1.1 1. General Description The RTL8201DL is a single-chip/single-port PHYceiver that supports:

  • MII (Media Independent Interface)
  • RMII (Reduced Media Independent Interface)
  • SNI (Serial Network Interface). It implements all 10/100M Ethernet Physical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium Attachme nt (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP- PMD), with an auto MDIX function, 10Base-Tx Enc oder/Decoder, and Twisted-Pair Media Access Unit (TPMAU). A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX fiber optical transceiver. The chip utilizes an advanced CMOS pro cess to meet low voltage and low power requirements. With on-chip DSP (Digital Signal Processing ) technology, the chip provides excellent performance under all operating conditions.

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 2 Track ID: JATR-1076-21 Rev. 1.1 2. Features The Realtek RTL8201DL is a Fast Ethernet PHYceiver with selectable MII, RMII, or SNI interface to the MAC chip. It provides the following features: „ Supports MII and 7-wire SNI (Serial Network Interface) „ Supports RMII mode (new RTL8201DL function) „ 10/100Mbps operation „ Full/half duplex operation „ Twisted pair or fiber mode output „ Auto-Negotiation „ Supports power down mode „ Supports operation under Link Down Power Saving mode „ Supports Base Line Wander (BLW) compensation „ Supports auto MDIX „ Supports repeater mode „ Adaptive Equalization „ Network status LEDs „ Flow control support „ 25MHz crystal/oscillator as clock source „ IEEE 802.3/802.3u compliant „ Supports IEEE 802.3u clause 28; 1.5V operation with 3.3V IO signal tolerance „ Low power supply, 1.5V, 1.8V and 3.3V; 1.5V/1.8V is generated by an internal regulator „ 0.15µm CMOS process „ 48-pin LQFP package 3. Applications „ Network Interface Adapter „ MAU (Media Access Unit) „ CNR (Communication and Network Riser) „ ACR (Advanced Communication Riser) „ Ethernet hub „ Ethernet switch In addition, it can be used in any embedded system with an Ethernet MAC that needs a UTP physical connection or Fiber PECL interface to an external 100Base-FX optical transceiver module.

3 Level

Figure 1. Block Diagram

Figure 2. Pin Assignments Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.

Table 1. MII Interface This pin provides a continuous clock as a timing reference for TXD[3:0] and TXEN. weak pull low resistor to prevent the bus floating. internal weak pull high resistor prevents the bus floating. This pin provides a continuous clock reference for RXDV and RXD[0..3] signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode. COL/SNI LI/O 36 Collision Detect. COL is asserted high when a collision is detected on the media. This pin can be directly connected to GND or VCC. This pin’s signal is asserted high if the media is not in Idle state. During power on reset, this pin set high to put the RTL8201DL into repeater mode. This pin can be directly connected to GND or VCC. to use an external 5.1KΩ pull high resistor to enable RMII mode. After power on, the pin operates as the Receive Data Valid pin. synchronously to the RXC for reception by the external physical unit (PHY).

to use an external 5.1KΩ pull high resistor to enable fiber mode. After power on, the pin operates as the Receive Error pin. MDC I 25 Management Data Clock. internal weak pull high resistor to prevent the bus floating. MDIO IO 26 Management Data Input/Output. This pin provides the bi-directional signal used to transfer management information. Table 2. RMII Interface 1: REFCLK pin is input type. 0: REFCLK pin is output type. MAC is supplied from REFCLK as 50MHz Clock. This pin is also hardware strapping for auto MDIX. function will be disabled if the REFCLK pin is output type. TXC/REFCLK IO 18 Synchronous 50MHz Clock Refere nce for Receive, Transmit and Control Interface.

Table 3. SNI (Serial Network Interface) 10Mbps Only COL/SNI O 36 Collision Detect. RXD0 O 13 Received Serial Data. CRS/RPTR O 37 Carrier Sense. RXC O 17 Receive Clock. Reso lved from received data. TXD0 I 19 Transmit Serial Data. TXC/REFCLK O 18 Transmit Clock. Generated by PHY . TXEN I 23 Transmit Enable. For MAC to indicate transmit operation. Table 4. Clock Interface CKXTAL2 O 46 25MHz Crystal Output. CKXTAL1 I 47 25MHz Crystal Input. clock source specifications). Table 5. 10Mbps/100Mbps Network Interface waveform. When configured as 100Base-FX, the output is pseudo-ECL level. RSET I 1 Transmit Bias Resistor Connection. experimental results of the RTL8201DL.

Table 6. Device Configuration Interface PHYAD[2:0] I 42, 43, 44 PHY Address. Set the PHY address for the device. CRS/RPTR LI/O 37 Repeater Mode. COL/SNI LI/O 36 M II/SNI Interface. be directly connected to GND or VCC. ANE LI 30 Auto-Negotiation Mode. Saving Modes, page 21, for more information). Table 7. LED Interface/PHY Address Configuration LED_10 O 39 10Mbps Link Indicator. LED_100 O 38 100Mbps Link Indicator.

Table 8. Power and Ground Pins A VDD33 P 45 3.3V Analog Power Input. 3.3V power supply for analog circuit; should be well decoupled. DVDD33 P 34, 40 3.3V Digital Power Input. 3.3V power supply for digital circuit. A VDD18 P 5, 10 1.8V Analog Power. DVDD15 P 29 1.5V Digital Power. GND P 8, 9, 11, 41 Ground. Should be connected to a larger GND plane. Table 9. Reset and Other Pins Be sure to connect a 22µF tantalum capacitor for frequency compensation. Conversion Circuit, page 24.

This section describes the functions and usage of the registers available in the RTL8201DL. Table 10. Register 0 Basic Mode Control Register state. This bit is self-clearing. 0:13 Spd_Set This bit sets the network speed. After completing auto negotiation, this bit will reflect the Speed status. When 100Base-FX mode is enabled, this bit=1 and is read only. This bit enables/disables the NWay auto-negotiation function. 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored. speed and the data transfer mode, respectively. When 100Base-FX mode is enabled, this bit=0 and is read only. The MDC, MDIO is still alive for accessing the MAC. This bit allows the NWay auto-negotiation function to be reset. 0:8 Duplex Mode This bit sets the duplex mode if auto-negotiation is disabled (bit 0:12=0). After completing auto-negotiation, this bit will reflect the duplex status. 0:0 RMII Mode This bit sets the RMII mode.

Table 11. Register 1 Basic Mode Status Register

Table 12. Register 2 PHY Identifier Register 1 Table 13. Register 3 PHY Identifier Register 2 Table 14. Register 4 Auto-Negotiation Advertisement Register (ANAR) CSMA/CD 00001 is specified. No other protocols are supported.

content changes after a successful auto-negotiation if Next-pages are supported. Table 15. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) 5:4~0 Selector Link Partner’s binary encoded node selector.

This register contains additional status for NWay auto-negotiation. Table 16. Register 6 Auto-Negotiation Expansion Register (ANER) 6:4 MLF Indicates whether a multiple link fault has occurred. 6:3 LP_NP_ABLE Indicates whether the link partner supports Next Page negotiation. Next Pages. Internal use only. ability register (register 5) is read by management. Table 17. Register 16 NWay Setup Register (NSR) Table 18. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)

Table 19. Register 18 RX_ER Counter (REC) received. The value is valid while the link is established. Table 20. Register 19 SNR Display Register 19:15~4 Reserved Realtek Test Mode Internal Use. Do not change this field without Realtek’s approval. Table 21. Register 25 Test Register

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 16 Track ID: JATR-1076-21 Rev. 1.1 8. Functional Description The RTL8201DL PHYceiver is a physical laye r device that inte grates 10Base-T and 100Base-TX/100Base-FX functions, and some extra power management features into a 48-pin single chip that is used in 10/100 Fast Ethernet applications. This device supports the following functions:

  • MII interface with MDC/MDIO SMI management interface to communicate with MAC
  • IEEE 802.3u clause 28 Auto-Negotiation ability
  • Flow control ability support to cooperate with MAC
  • Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
  • Flexible LED configuration
  • 7-wire SNI (Serial Network Interface) support (only in 10Mbps mode)
  • Power Down mode support
  • 4B/5B transform
  • Scrambling/De-scrambling
  • NRZ to NRZI, NRZI to MLT-3
  • Manchester Encode and Decode for 10Base-T operation
  • Clock and Data recovery
  • Adaptive Equalization
  • Far End Fault Indication (FEFI) in fiber mode

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 17 Track ID: JATR-1076-21 Rev. 1.1 8.1. MII and Management Interface 8.1.1. Data Transition To set the RTL8201DL for MII mode operation, pull the CO L/SNI pin low and set the ANE and SPEED pins. The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying a standard interface between the PHY and MAC layer. This interface operates at two frequencies – 25MHz and 2.5MHz to support 100Mbps/10Mbps bandwidth for both transmit and receive functions. Transmission The MAC asserts the TXEN signal. It then changes byt e data into 4-bit nibbles and passes them to the signal supplied by PHY – during the interval TXEN is asserted. Reception The PHY asserts the RXEN signal. It passes the r eceived nibble data RXD[ 0..3] clocked by RXC. CRS and COL signals are used for collision detection and handling. In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is recognized as IDLE it will be de-asserted. In 10Bas e-T mode, CRS will assert when the 10M preamble has been confirmed and will be de-asserted when the IDLE pattern has been confirmed. The RXDV signal will be asserted when decoded 5B are /J/K/ and will be de-asserted if the 5B are /T/R/ or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal. The RXER (Receive Error) signa l will be asserted if a ny 5B decode errors occur, e.g., an invalid J/K, invalid T/R, or invalid symbol. This pin will go high for one or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame. Note: The RTL8201DL does not use a TXER signal. This does not affect the transmit function.

receives a 100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode. media configuration of the RTL8201DL. Table 23. Setting the Medium Type and Interface Mode to MAC L L UTP Mode and MII Interface. L H UTP Mode and SNI Interface. H X Fiber Mode and MII Interface. Table 24. UTP Mode and MII Interface H L Auto-Negotiation Enabled. The ability field does not support 100Mbps operation. Default Setup, Auto-Negotiation Enabled. L L Auto-Negotiation Disabled. Forces the RTL8201DL into 10Base-T and full duplex mode. L H Auto-Negotiation Disabled. Forces the RTL8201DL into 100Base-TX and full duplex mode.

Table 25. UTP Mode and SNI Interface X X The RTL8201DL also Supports Full Duplex in SNI Mode. Enable) and SPEED configuration is ignored when Fiber mode is enabled. Table 26. Fiber Mode and MII Interface X X The RTL8201DL also Supports Full Duplex in Fiber Mode. recognize the Link partner’s NWay ability by examining bit 10 of ANLPAR (register 5). shows the various pins and their settings. Table 27. Auto-Negotiation Mode Pin Settings RPTR Pull high to set the RTL8201DL into Repeater Mode. This pin is pulled low by default (see 8.8 Repeater Mode Operation, page 23). LDPS Pull high to set the RTL8201DL into LDPS Mode. This pin is pulled low by default (see 8.6 Power Down, Link Down, and Power Saving Modes, page 21). MII/SNI Pull low to set RTL8201DL into MII Mode operation, which is the Default Mode for the RTL8201DL. RTL8201DL will operate at 10Mbps (see 8.5 Serial Network Interface, page 21). ANE Auto-Negotiation Enable. parallel detection mechanism (see 8.2 Auto-Negotiation and Parallel Detection, page 19). SPEED When ANE is pulled high, the ability to adjust speed is setup. operation (see 8.2 Auto-Negotiation and Parallel Detection, page 19).

detect, and carry sense signals. mode. The first three modes are configured through software, and the fourth through hardware. Table 28. Power Saving Mode Pin Settings 100Mbps IDLE/10Mbps NLP again. This can cut power used by 60%~80% when the link is down. MDC/MDIO timing by itself (this is done by software).

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 22 Track ID: JATR-1076-21 Rev. 1.1 8.7. Media Interface 8.7.1. 100Base-TX Transmit and Receive Operation 100Base-TX Transmit Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code (4B/5B encoding). Scrambling, seri alizing, and conversion to 125MHz, and NRZ to NRZI then takes place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver. The transmitter will first assert TXEN. Before transm itting the data pattern, it will send a /J/K/ symbol (Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a hub/switch environment, each RTL8201DL will have diffe rent scrambler seeds and so spread the output of the MLT-3 signals. 100Base-TX Receive The received signal is compensated by the adaptive eq ualizer to make up for signal loss due to cable attenuation and Inter Symbol Interference (ISI). Ba seline Wander Correction mo nitors the process and dynamically applies corrections to th e process of signal equa lization. The PLL then recovers the timing information from the signals and from the receive clock. With this, the received signal is sampled to form NRZI data. The next steps are the NR ZI to NRZ process, unscrambling of the data, serial to parallel and 5B to 4B conversion, and passing of the 4B nibble to the MII interface. 8.7.2. 100Base-FX Fiber Transmit and Receive Operation The RTL8201DL can be configured as 100Base-FX via hardware configuration. The hardware 100Base-FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX. 100Base-FX Transmit Di-bits of TXD are processed as 100Base-TX except wi thout a scrambler before the NRZI stage. Instead of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL signals, which enter the fiber transceiver in differential-pairs form. 100Base-FX Receive The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 23 Track ID: JATR-1076-21 Rev. 1.1 8.7.3. 10Base-T Transmit and Receive Operation 10Base-T Transmit Transmit data in 4-bit nibbles (TXD[ 3:0]) clocked at 2.5MHz (TXC) is fi rst fed to a parallel-to-serial converter, then the 10Mbps NRZ si gnal is sent to a Manchester en coder. The Manchester encoder converts the 10Mbps NRZ data into a Manchester Enc oded data stream for the TP transmitter and adds a Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Fi nally, the encoded data stream is shaped by a band-limited filter embedded in the RTL8201DL and then transmitted. 10Base-T Receive In 10Base-T receive mode, the Manchester decoder in the RTL8201DL converts the Manchester encoded data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data stream is converted to a parallel 4-bit nibble signal (RXD[0:3]). 8.8. Repeater Mode Operation Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, sets the RTL8201DL into repeater mode. In repeater mode, the RTL8201DL w ill assert CRS high only when receiving a packet. In NIC mode, the RTL8201DL will assert CRS high both when tran smitting and receiving packets. If using the RTL8201DL in a NIC or switch application, set to th e default mode. NIC/Switch mode is the default setting and has the RPTR pin pulled low, or bit 15 of register 17 is set to 0. 8.9. Reset and Transmit Bias The RTL8201DL can be reset by pulling the RESETB pi n low for about 10ms, then pulling the pin high. It can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear the registers and re-initialize them. The media in terface will disconnect and restart the auto- negotiation/parallel detection process. The RTSET pin must be pulled low by a 2K Ω resister with 1% accuracy to establish an accurate transmit bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from other clock traces and transmit/receive paths to avoid signal interference.

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 24 Track ID: JATR-1076-21 Rev. 1.1 8.10. 3.3V Power Supply and Voltage Conversion Circuit The RTL8201DL is fabricated in a 0.15 µm process. The core circuit needs to be powered by 1.5V, however, the digital IO and DAC circuits need a 3.3V power supply. Two regulators are embedded in the RTL8201DL to convert 3.3V to 1.5V and 1.8V. As with many commercial voltage conversion devices, the 1.5V/1.8V output pin (PWFBOUT) of this circuit requires the use of an output capacitor (22uF tantalum capacitor) as part of the device frequency compensation. The analog and digital ground planes should be as large and intact as possible. If the ground plane is large enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the total ground plane is not sufficiently large, partition of the ground plan e is not a good idea. In this case, all the ground pins can be connected together to a larger single and intact ground plane. 8.11. Far End Fault Indication The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled, and indicates when a FEFI has been detected. FEFI is an alternativ e in-band signaling method which is composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201DL detects this pattern three times, Reg.1.4 is set, which means the transmit path (t he Remote side’s receive path) has a problem. On the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201DL will start sending this pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path has a problem from the point of view of the RTL8201DL. The FEFI mechanism is used only in 100Base-FX mode.

Table 29. Absolute Maximum Ratings Table 30. Operating Conditions Table 31. Power Dissipation

Table 32. Input Voltage: Vcc Table 33. MII Transmission Cycle Timing

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 34 Track ID: JATR-1076-21 Rev. 1.1 10. Mechanical Dimensions See the Mechanical Dimensions notes on the next page.

Single-Chip/Port 10/100 Fast Ethernet PHYceiver with Auto MDIX 35 Track ID: JATR-1076-21 Rev. 1.1 10.1. Mechanical Dimensions Notes Notes: 1. To be determined at seating plane -c- Symbol Dimension in Inch Dimension in Millimeter 2. Dimensions D1 and E1 do not include mold protrusion. Min Nom Max Min Nom Max D1 and E1 are maximum plastic body size dimensions including mold mismatch. A - - 0.067 - - 1.70 3. Dimension b does not include dambar protrusion. lowest point of the package body. D 0.354 BSC 9.00 BSC 7. Controlling dimension: millimeter. D1 0.276 BSC 7.00 BSC 8. Reference document: JEDEC MS-026, BBC E 0.354 BSC 9.00 BSC TITLE: 48LD LQFP ( 7x7x1.4mm) E1 0.276 BSC 7.00 BSC PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm e 0.020 BSC 0.50 BSC LEADFRAME MATERIAL: L1 0.039 REF 1.00 REF VERSION 1 APPROVE PAGE OF θ1 0 ° - - 0° - - DWG NO. SS048 - P1 θ2 12 ° TYP 12 ° TYP CHECK DATE - θ3 12 ° TYP 12 ° TYP REALTEK SEMICONDUCTOR CORP.

Table 42. Ordering Information Note: See page 4 for package identification.