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10/100M FAST ETHERNET PHYCEIVER DATASHEET Rev. 1.24

04 November 2005

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw www.DataSheet4U.net

Single-Chip/Port 10/100 Fast Ethernet PHYceiver ii Track ID: JATR-1076-21 Rev. 1.24 COPYRIGHT ©2005 Realtek Semiconductor Corp. All rights reserv ed. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. www.DataSheet4U.net

Single-Chip/Port 10/100 Fast Ethernet PHYceiver iii Track ID: JATR-1076-21 Rev. 1.24

REVISION HISTORY

Revision Release Date Summary 1.0 2003/06/09 First release. 1.1 2003/09/26 Minor cosmetic changes. Modify LED Pin behavior. 1.2 2004/01/20 Add LED multi-mode definition (7.5 LED and PHY Address Configuration, page 19). Add Power dissipation info (Table 31). Bit <0:8> default setting changed to 0 (Table 9). Bit <0:13> default setting changed to 0 (Table 9). Bit <5:7> default setting changed to 0 (Table 14). Bit <17:5> default setting changed to 1 (Table 17). Bit <25:0> default setting changed to 0 (Table 20). Bit <25:1> default setting changed to 0 (Table 20). Bit <25:11~7> default setting changed to 00001 (Table 20). 1.21 2004/10/12 Package additions. See section 10, Ordering Information, page 33. 1.22 2005/04/11 Correction to Table 18, Register 18 RX_ER Counter (REC), page 13. Correction to Table 39, Transformer Characteristics, page 30. Added lead (Pb)-free package identification information on page 3 and on page 33. 1.23 2005/07/29 Corrected error in 7.8.3 10Base-T TX/RX, page 21 (10Base-T Transmit Function _ clock at 25MHz => clock at 2.5MHz). Corrections to Table 32, Input V oltage: Vcc, page 23. Vcc _ TTL V oh _ Minimum 0.9*Vcc => Minimum 0.65*Vcc Vcc _ TTL V ol _ Maximum 0.1*Vcc => Maximum 0.3*Vcc Vcc _ TTL Ioz _ Minimum -10uA => Minimum -110uA Vcc _ Iin _ Minimum -1.0uA => Minimum -110uA Vcc _ Iin _ Maximum 1.0uA => Maximum 100uA 1.24 2005/11/04 Revised Table 1, page 4 (pins 2, 3, 4, 5, 6, and 25). Corrected Table 17, page 12 (bits 17:6 and 17:5). Corrected Table 18, page 13 (mode). Revised Table 32, page 23 (IIN, IPL, IPH). Revised Table 33, page 24 (t8). Revised Table 34, page 25 (t6, t7, t9). www.DataSheet4U.net

Single-Chip/Port 10/100 Fast Ethernet PHYceiver iv Track ID: JATR-1076-21 Rev. 1.24 Table of Contents www.DataSheet4U.net

Single-Chip/Port 10/100 Fast Ethernet PHYceiver 1 Track ID: JATR-1076-21 Rev. 1.24 1. General Description The RTL8201CL is a single-chip/si ngle-port PHYceiver with an MII (M edia Independent Interface)/SNI (Serial Network Interface). It implements all 10/100M Ethernet P hysical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twiste d Pair Physical Medium Dependent Sublayer (TP-PMD), 10Base-Tx Encoder/ Decoder, and Twisted-Pair Media Access Unit (TPMAU). A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX fiber optical transceiver. The chip utilizes an advanced CMOS pro cess to meet low voltage and low power requirements. With on-chip DSP (Digital Signal Processing ) technology, the chip provides excellent performance under all operating conditions. The RTL8201CL can be used for applications such as those for a Network Interface Adapter, MAU (Media Access Unit), CNR (Communication and Network Riser), ACR (Advanced Communication Riser), an Ethernet hub, and an Ethernet switch. In addition, it can be used in any embedded system with an Ethernet MAC that needs a UTP physical conn ection or Fiber PECL in terface to an external 100Base-FX optical transceiver module. 2. Features The Realtek RTL8201CL is a Fast Ethernet PHYceiver with selectable MII or SNI interface to the MAC chip. It provides the following features: „ Pin-to-pin compatible with the RTL8201BL „ Supports MII and 7-wire SNI (Serial Network Interface) „ 10/100Mbps operation „ Full/half duplex operation „ Twisted pair or fiber mode output „ Auto-Negotiation „ Supports power down mode „ Supports operation under Link Down Power Saving mode „ Supports Base Line Wander (BLW) compensation „ Supports repeater mode „ Adaptive Equalization „ Network status LEDs „ Flow control support „ 25MHz crystal/oscillator as clock source „ IEEE 802.3/802.3u compliant „ Supports IEEE 802.3u clause 28; 1.8V operation with 3.3V IO signal tolerance „ Low dual power supply, 1.8V and 3.3V; 1.8V is generated by an internal regulator „ 0.18µm CMOS process „ 48-pin LQFP package www.DataSheet4U.net

Figure 1. Block Diagram

3 Level

Figure 2. Pin Assignments Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 2.

Table 1. MII Interface internal weak pull low resistor prevents the bus floating. asserted. An internal weak pull high resistor prevents the bus floating. signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode. COL LI/O 1 Collision Detect. COL is asserted high when a collision is detected on the media. to use an external 5.1KΩ pull high resistor to enable BL LED mode. This pin’s signal is asserted high if the media is not in Idle state. 5.1KΩ pull low resistor could be reserved to ensure operating at normal mode. RXDV O 22 Receive Data Valid. valid on the rising edge of the RXC.

symbol, this pin will go high. to use an external 5.1KΩ pull high resistor to enable fiber mode. After power on, the pin operates as the Receive Error pin. MDC I 25 Management Data Clock. 2.5MHz. An internal weak pull high resistor prevents the bus floating. MDIO IO 26 Management Data Input/Output. Table 2. SNI (Serial Network Interface) 10Mbps Only RXD0 O 21 Received Serial Data. Resolved from received data. TXD0 I 6 Transmit Serial Data. For MAC to indicate transmit operation. Table 3. Clock Interface X2 O 47 25MHz Crystal Output. external 25MHz oscillator drives X1. X1 I 46 25MHz Crystal Input.

Table 4. 10Mbps/100Mbps Network Interface waveform. When configured as 100Base-FX, the output is pseudo-ECL level. RTSET I 28 Transmit Bias Resistor Connection. on experimental results of the RTL8201CL. Table 5. Device Configuration Interface directly connected to GND or VCC. enable full duplex. This pin can be directly connected to GND or VCC. Modes, page 20, for more information. directly connected to GND or VCC. Address Configuration, page 19, for more information.

Table 6. LED Interface/PHY Address Configuration Lit when in Full Duplex operation. Blinking when transmitting or receiving data. Blinking when transmitting or receiving data. Blinks when collisions occur. Table 7. Power and Ground Pins A VDD33 P 36 3.3V Analog Power Input. 3.3V power supply for analog circuit; should be well decoupled. AGND P 29, 35 Analog Ground. Should be connected to a larger GND plane. DVDD33 P 14, 48 3.3V Digital Power Input. 3.3V power supply for digital circuit. DGND P 11, 17, 45 Digital Ground. Should be connected to a larger GND plane. Table 8. Reset and Other Pins PWFBOUT O 32 Power Feedback Output. 7.11 3.3V Power Supply and V oltage Conversion Circuit, page 22. PWFBIN I 8 Power Feedback Input. See the PWFBOUT description above.

This section describes the functions and usage of the registers available in the RTL8201CL. Table 9. Register 0 Basic Mode Control Register state. This bit is self-clearing. 0:13 Spd_Set This bit sets the network speed. After completing auto negotiation, this bit will reflect the Speed status. When 100Base-FX mode is enabled, this bit=1 and is read only. This bit enables/disables the NWay auto-negotiation function. 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored. speed and the data transfer mode, respectively. When 100Base-FX mode is enabled, this bit=0 and is read only. This bits allows the NWay auto-negotiation function to be reset.

Table 10. Register 1 Basic Mode Status Register Far End Fault Indication, page 22. Table 11. Register 2 PHY Identifier Register 1 Table 12. Register 3 PHY Identifier Register 2

Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR) CSMA/CD 00001 is specified. No other protocols are supported. content changes after a successful auto-negotiation if Next-pages are supported. Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)

This register contains additional status for NWay auto-negotiation. Table 15. Register 6 Auto-Negotiation Expansion Register (ANER) 6:15~5 Reserved This bit is permanently set to 0. 6:4 MLF Indicates whether a multiple link fault has occurred. 6:3 LP_NP_ABLE Indicates whether the link partner supports Next Page negotiation. Next Pages. Internal use only. link partner’s ability register (register 5) is read by management.

Table 16. Register 16 NWay Setup Register (NSR) Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR) 722 ms time-out’ to be reported.

Table 18. Register 18 RX_ER Counter (REC) received. The value is valid while a link is established. Table 19. Register 19 SNR Display Register Table 20. Register 25 Test Register

Single-Chip/Port 10/100 Fast Ethernet PHYceiver 14 Track ID: JATR-1076-21 Rev. 1.24 7. Functional Description The RTL8201CL PHYceiver is a physical layer device that integrates 10Base-T and 100Base-TX/100Base-FX functions, and some extra power management features into a 48-pin single chip that is used in 10/100 Fast Ethernet applications. This device supports the following functions:

  • MII interface with MDC/MDIO SMI management interface to communicate with MAC
  • IEEE 802.3u clause 28 Auto-Negotiation ability
  • Flow control ability support to cooperate with MAC
  • Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
  • Flexible LED configuration
  • 7-wire SNI (Serial Network Interface) support (only in 10Mbps mode)
  • Power Down mode support
  • 4B/5B transform
  • Scrambling/De-scrambling
  • NRZ to NRZI, NRZI to MLT-3
  • Manchester Encode and Decode for 10Base-T operation
  • Clock and Data recovery
  • Adaptive Equalization
  • Far End Fault Indication (FEFI) in fiber mode 7.1. MII and Management Interface 7.1.1. Data Transition To set the RTL8201CL for MII mode operation, pu ll the MII/SNIB pin high and set the ANE, SPEED, and DUPLEX pins. The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying a standard interface between the PHY and MAC layer. This interface operates at two frequencies – 25Mhz and 2.5Mhz to support 100Mbps/10Mbps bandwidth for both transmit and receive functions. Transmission The MAC asserts the TXEN signal. It then changes byt e data into 4-bit nibbles and passes them to the signal supplied by PHY – during the interval TXEN is asserted. Reception The PHY asserts the RXEN signal. It passes the r eceived nibble data RXD[ 0..3] clocked by RXC. CRS and COL signals are used for collision detection and handling. In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is recognized as IDLE it will be de-asserted. In 10Bas e-T mode, CRS will assert when the 10M preamble has been confirmed and will be de-asserted when the IDLE pattern has been confirmed. www.DataSheet4U.net

100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode. pin high. The SPEED and DUPLEX pins will set the ab ility content of the auto-negotiation register. pin and DUPLEX pin will change the media configuration of the RTL8201CL. Table 22. Setting the Medium Type and Interface Mode to MAC L H UTP mode and MII interface. L L UTP mode and SNI interface. H X Fiber mode and MII interface. Table 23. UTP Mode and MII Interface T /100Base-TX, half/full duplex mode operation.

Table 24. UTP Mode and SNI Interface X X L The duplex pin is pulled low to support the 10Base-T half duplex function. 10Base-T half duplex is the specified default mode in the SNI interface. pulled high to support 10Base-T full duplex function. Enable) and SPEED configuration is ignored when Fiber mode is enabled. Table 25. Fiber Mode and MII Interface X X H The duplex pin is pulled high to support 100Base-FX full duplex function. X X L The duplex pin is pulled low to support 100Base-FX half duplex function. recognize the Link partner’s NWay ability by examining bit 10 of ANLPAR (register 5).

shows the various pins and their settings. Table 26. Auto-Negotiation Mode Pin Settings Down, Power Saving, and Isolation Modes, page 20). 7.9 Repeater Mode Operation, page 22. Down, Link Down, Power Saving, and Isolation Modes, page 20). MII/SNIB Pull high to set RTL8201CL into MII mode operation, which is the default mode for the RTL8201. RTL8201CL will operate at 10Mbps (see 7.6 Serial Network Interface, page 20). Parallel Detection, page 16). Negotiation and Parallel Detection, page 16).

Figure 5. LED and PHY Address Configuration Table 27. LED Definitions

the default operation to 10Mbps and half-duplex mode. Note: The RTL8201CL also supports full-duplex mode operation if the DUPLEX pin has been pulled high. receive serial data, transmit enable, collision detect, and carry sense signals. Table 28. Power Saving Mode Pin Settings 100Mbps IDLE/10Mbps NLP again. This can cut power used by 60%~80% when the link is down. MDC/MDIO timing by itself (this is done by software). place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver.

Single-Chip/Port 10/100 Fast Ethernet PHYceiver 21 Track ID: JATR-1076-21 Rev. 1.24 The transmitter will first assert TXEN. Before transm itting the data pattern, it will send a /J/K/ symbol (Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame delimiter. The 4B/5B and the scramble process can be bypassed via a PHY register setting (see Table 1, page 4, Pin number 24). For better EMI performance, the seed of the scrambler is based on the PHY address. In a hub/switch environment, each RTL 8201CL will have different scrambler seeds and so spread the output of the MLT-3 signals. 100Base-TX Receive Function The received signal is compensated by the adaptive eq ualizer to make up for signal loss due to cable attenuation and Inter Symbol Interference (ISI). Ba seline Wander Correction mo nitors the process and dynamically applies corrections to th e process of signal equa lization. The PLL then recovers the timing information from the signals and from the receive clock. With this, the received signal is sampled to form NRZI data. The next steps are the NR ZI to NRZ process, unscrambling of the data, serial to parallel and 5B to 4B conversion, and passing of the 4B nibble to the MII interface. 7.8.2. 100Base-FX Fiber Mode Operation The RTL8201CL can be configured as 100Base-FX via hardware configuration. The hardware 100Base-FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX. 100Base-FX Transmit Function Di-bits of TXD are processed as 100Base-TX except wi thout a scrambler before the NRZI stage. Instead of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL signals, which enter the fiber transceiver in differential-pairs form. 100Base-FX Receive Function The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX. 7.8.3. 10Base-T TX/RX 10Base-T Transmit Function Transmit data in 4-bit nibbles (TXD[ 3:0]) clocked at 2.5MHz (TXC) is fi rst fed to a parallel-to-serial converter, then the 10Mbps NRZ si gnal is sent to a Manchester en coder. The Manchester encoder converts the 10Mbps NRZ data into a Manchester Enc oded data stream for the TP transmitter and adds a Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Fi nally, the encoded data stream is shaped by a bandlimited filter embedded in the RTL8201CL and then transmitted. 10Base-T Receive Function In 10Base-T receive mode, the Manchester decoder in the RTL8201CL converts the Manchester encoded data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data stream is converted to a parallel 4-bit nibble signal (RXD[0:3]). www.DataSheet4U.net

Single-Chip/Port 10/100 Fast Ethernet PHYceiver 22 Track ID: JATR-1076-21 Rev. 1.24 7.9. Repeater Mode Operation Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, sets the RTL8201CL into repeater mode. In repeater mode, the RTL8201CL w ill assert CRS high only when receiving a packet. In NIC mode, the RTL8201CL will assert CRS high both when transmitting and receiving packets. If using the RTL8201CL in a NIC or switch application, set to th e default mode. NIC/Switch mode is the default setting and has the RPTR pin pulled low, or bit 15 of register 17 is set to 0. 7.10. Reset, and Transmit Bias The RTL8201CL can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear the registers and re-initialize them. The media in terface will disconnect and restart the auto- negotiation/parallel detection process. The RTSET pin must be pulled low by a 2K Ω resister with 1% accuracy to establish an accurate transmit bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from other clock traces and transmit/receive paths to avoid signal interference. 7.11. 3.3V Power Supply and Voltage Conversion Circuit The RTL8201CL is fabricated in a 0.18 µm process. The core circuit needs to be powered by 1.8V, however, the digital IO and DAC ci rcuits need a 3.3V power supply. A regulator is embedded in the RTL8201CL to convert 3.3V to 1.8V. As with many commercial voltage c onversion devices, the 1.8V output pin (PWFBOUT) of this circu it requires the use of an output capacitor (22uF tantalum capacitor) as part of the device frequency compensation, a nd another small capacitor (0.1uF) for high frequency noise de-coupling. PWFBIN is fed with the 1.8V powe r from PWFBOUT through a ferrite bead as shown in the reference design schematic document (available for download from www.realtek.com.tw). Note: Do not supply 1.8V produced by any power device other than PWFBOUT and PWFBIN. The analog and digital ground planes should be as large and intact as possible. If the ground plane is large enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the total ground plane is not sufficiently large, partition of the ground plan e is not a good idea. In this case, all the ground pins can be connected together to a larger single and intact ground plane. 7.12. Far End Fault Indication The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled and indicates when a FEFI has been detected. FEFI is an alternativ e in-band signaling method which is composed of 84 consecutive ‘1’s followed by one ‘0 ’. When the RTL8201CL det ects this pattern three times, Reg.1.4 is set, which means the transmit path (t he Remote side’s receive path) has a problem. On the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201CL will start sending this pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path has a problem from the point of view of the RTL8201CL. The FE FI mechanism is used only in 100Base-FX mode. www.DataSheet4U.net

Table 29. Absolute Maximum Ratings Table 30. Operating Conditions Table 31. Power Dissipation Table 32. Input Voltage: Vcc

Figure 7. MII Transmission Cycle Timing-2 Table 34. MII Reception Cycle Timing

Single-Chip/Port 10/100 Fast Ethernet PHYceiver 31 Track ID: JATR-1076-21 Rev. 1.24 9. Mechanical Dimensions See the following page for drawing related notes. www.DataSheet4U.net

Single-Chip/Port 10/100 Fast Ethernet PHYceiver 32 Track ID: JATR-1076-21 Rev. 1.24 9.1. Mechanical Dimensions Notes Notes: 1.To be determined at seating plane -c- 2.Dimensions D1 and E1 do not include mold protrusion. Symbol Dimension in inchs Dimension in millimeters D1 and E1 are maximum plastic body size dimensions including mold mismatch. Min Nom Max Min Nom Max 3.Dimension b does not include dambar protrusion. A - - 0.067 - - 1.70 Dambar can not be located on the lower radius of the foot. the lowest point of the package body. D 0.354 BSC 9.00 BSC 8. Reference document: JEDEC MS-026, BBC D1 0.276 BSC 7.00 BSC E 0.354 BSC 9.00 BSC TITLE: 48LD LQFP (7x7x1.4mm) E1 0.276 BSC 7.00 BSC PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm e 0.020 BSC 0.50 BSC LEADFRAME MATERIAL: L1 0.039 REF 1.00 REF VERSION 1 APPROVE PAGE OF θ1 0 ° - - 0° - - DWG NO. SS048 - P1 θ2 12 ° TYP 12 ° TYP CHECK DATE θ3 12 ° TYP 12 ° TYP REALTEK SEMICONDUCTOR CORP. www.DataSheet4U.net

Table 40. Ordering Information Note: See page 3 for lead (Pb)-free package identification.