DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 23
Technical content
SINGLE-CHIP IEEE 802.11b/g/n 1T1R WLAN With SDIO INTERFACE DATASHEET (CONFIDENTIAL: Development Partners Only) Rev. 0.6 4 May. 2012 Track ID: Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller with SDIO Interface ii Track ID: JATR-2265-11 Rev. 0.6 COPYRIGHT ©2012 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind. Realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engi neer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary 0.1 2013/12/17 Preliminary release
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller with SDIO Interface iii Track ID: JATR-2265-11 Rev. 0.6 Table of Contents
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller with SDIO Interface 1 Track ID: JATR-2265-11 Rev. 0.7 1. General Description The Realtek RTL8189ETV is a highly integrated single-chip 802.11n Wireless LAN (WLAN) network SDIO interface (SDIO 1.1/ 2.0/ 3.0 compliant) contro ller. It is a WLAN MAC, a 1T1R capable WLAN baseband, and WLAN RF in a singl e chip. The RTL8189ETV provides a complete solution for a high throughput performance integrated wireless LAN device. The RTL8189ETV WLAN baseband implements Ort hogonal Frequency Division Multiplexing (OFDM) with 1 transmit and 1 receive path and is compatible with the IEEE 802.11n specification. Features include one spatial stream transmission, short guard interval (GI) of 400ns, spatial spreading, and transmission over 20MHz and 40MHz bandwidth. For legacy compatibility, Direct Sequence Spread Spectrum (DSSS), Complementary Code Keying (CCK) and OFDM baseband processing are included to support all IEEE 802.11b and 802.11g data rates. Differential phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability, are available, and CCK provides support for legacy data rates, with long or short preamble. The high-speed FFT/IFFT paths, combined with BPSK, QPSK, 16QAM, and 64QAM modulation of the individual subcarriers and rate compatible punctured convolutional coding with coding rate of 1/2, 2/3, 3/4, and 5/6, provide higher data rates of 54Mbps and 150Mbps for IEEE 802.11g and 802.11n OFDM respectively. The RTL8189ETV WLAN Controller builds in an enhanced signal detector, an adaptive frequency domain equalizer, and a soft-decision Viterbi decoder to alleviate severe multi-path effects and mutual interference in the reception of multiple streams. Robust interference detection and suppression are provided to protect against Bluetooth, cordless phone, and microwave oven interference. Efficient IQ-imbalance, DC offset, phase noise, fre quency offset, and timing offset compensations are provided for the radio frequency front-end. Selectable digital transmit and receive FIR filters are provided to meet transmit spectrum mask requirements and to reject adjacent channel interference, respectively. The RTL8189ETV WLAN Controller supports fast r eceiver Automatic Gain Control (AGC) with synchronous and asynchronous control loops among ante nnas, antenna diversity functions, and adaptive transmit power control function to obtain the better performance in the analog portions of the transceiver.
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller with SDIO Interface 2 Track ID: JATR-2265-11 Rev. 0.7 The RTL8189ETV WLAN MAC supports 802.11e for multim edia applications, 802.11i for security, and 802.11n for enhanced MAC protocol e fficiency. Using packet aggrega tion techniques such as A-MPDU with BA and A-MSDU, protocol efficiency is signi ficantly improved. Power saving mechanisms such as Legacy Power Save, and U-APSD, reduce the power wasted during idle time, and compensates for the extra power required to transmit OFDM. The RTL8189ETV provides simple legacy and 20MHz/40MHz co-existence mechanisms to ensure backward and network compatibility.
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller with SDIO Interface 3 Track ID: JATR-2265-11 Rev. 0.7 2. Features General 32-pin QFN CMOS MAC, Baseband PHY, and RF in a single chip for IEEE 802.11b/g/n compatible WLAN Complete 802.11n solution for 2.4GHz band 72.2Mbps receive PHY rate and 72.2Mbps transmit PHY rate using 20MHz bandwidth 150Mbps receive PHY rate and 150Mbps transmit PHY rate using 40MHz bandwidth Compatible with 802.11n specification Backward compatible with 802.11b/g devices while operating in 802.11n mode Host Interface Complies with SDIO 1.1/ 2.0/ 3.0 for WLAN with clock rate up to 100MHz GSPI interface for configurable endian for WLAN Standards Supported IEEE 802.11b/g/n compatible WLAN IEEE 802.11e QoS Enhancement (WMM) 802.11i (WPA, WPA2). Open, shared key, and pair-wise key authentication services WLAN MAC Features Frame aggregation for increased MAC efficiency (A-MSDU, A-MPDU) Low latency immediate High-Throughput Block Acknowledgement (HT-BA) PHY-level spoofing to enhance legacy compatibility Power saving mechanism Channel management and co-existence Transmit Opportunity (TXOP) Short Inter-Frame Space (SIFS) bursting for higher multimedia bandwidth WLAN PHY Features IEEE 802.11n OFDM One Transmit and one Receive path (1T1R) 20MHz and 40MHz bandwidth transmission Short Guard Interval (400ns) DSSS with DBPSK and DQPSK, CCK modulation with long and short preamble OFDM with BPSK, QPSK, 16QAM, and 64QAM modulation. Convolutional Coding Rate: 1/2, 2/3, 3/4, and 5/6 Maximum data rate 54Mbps in 802.11g and 150Mbps in 802.11n Switch diversity for DSSS/CCK Hardware antenna diversity in per packet base
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller with SDIO Interface 4 Track ID: JATR-2265-11 Rev. 0.7 Selectable receiver FIR filters Programmable scaling in transmitter and receiver to trade quantization noise against increased probability of clipping Fast receiver Automatic Gain Control (AGC) On-chip ADC and DAC Peripheral Interfaces General Purpose Input/Output (8 pins) One configurable LED pins
40 MHz
2.4 GHz
Figure 1. Single-Band 11n (1x1) Solution
33 GND (Exposed Pad)
Figure 2. Pin Assignments
Figure 22. The version is shown in the location marked ‘V’, e.g., B=Version B
Table 1. SDIO Interface
level section of SDIO interface selection can be referred to subsection 6.5.1, “SDIO/GSPI Signal Level”. Table 2. GSPI Interface referred to subsection 6.5.1, “SDIO/GSPI Signal Level”.
Table 3. Power Pins Table 4. RF Interface Table 5. LED Interface
26 LED Pins (Active Low)
Table 6. Clock and Other Pins used by 8189ETV to request Crystal Clock from the host.
- Electrical and Thermal Characteristics
Table 7. Temperature Limit Ratings Table 8. Temperature Limit Ratings Table 9. DC Characteristics Table 10. 3.3V GPIO DC Characteristics
Table 11. 2.8V GPIO DC Characteristics Table 12. 1.8V GPIO DC Characteristics
Figure 3. SDIO Interface Timing Table 13. SDIO Interf ace Timing Parameters targeting power level to RTL8189ETV SDIO and GSPI interface via VIO_UART pin (pin # 50).
non_rdy: SDIO not ready duration, in this state, R TL8189ES may respond command without ready bit set. After ready bit set, host will initiate complete card detection procedure. T18ramp: The 1.8V main power ramp up duration. executed. After driver loaded, normal command 52 and 53 are then used. Table 14. SDIO Interface Power On Timing Parameters
write SPI_CFG register. SPI_CFG register is to control SPI endian and word length. Table 15. SPI Interface Po wer On Timing Parameters
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller with SDIO Interface 17 Track ID: JATR-2265-11 Rev. 0.7 Mechanical Dimensions
Single-Chip IEEE 802.11b/g/n 1T1R WLAN Controller with SDIO Interface 18 Track ID: JATR-2265-11 Rev. 0.7 7.1. Mechanical Dimensions Notes Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A3 0.20 REF 0.008 REF A4 0.10 REF 0.004 REF D/E 5.00 BSC 0.020 BSC e 0.50 BSC 0.020 BSC Note1: CONTROLLING DIMENSION: MILLIMETER (mm). Note2: REFERENCE DOCUMENT: JEDEC MO-220.
Table 16. Ordering Information Note: See page 6 for package identification.