RTL8169SC REALTEK | Alldatasheet
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INTEGRATED GIGABIT ETHERNET CONTROLLER (NIC) (MiniPCI) DATASHEET Rev. 1.2
22 December 2005
Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) i i Track ID: JATR-1076-21 Rev. 1.2 COPYRIGHT ©2005 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. USING THIS DOCUMENT This document is intended for use by the software engineer when programming for Realtek RTL8169SC controller chips. Information pertaining to the hardwa re design of products using these chips is contained in a separate document. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary 1.0 2003/11/17 First release. 1.1 2005/11/14 Corrected e values on page 40. Revised section 9 Ordering Information, page 41. 1.2 2005/12/22 Revise section 9 Ordering Information, page 41.
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) iii Track ID: JATR-1076-21 Rev. 1.2 Table of Contents
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) i v Track ID: JATR-1076-21 Rev. 1.2
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 1 Track ID: JATR-1076-21 Rev. 1.2 1. General Description The Realtek RTL8169SC Gigabit Et hernet controllers combine a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Et hernet transceiver, 32-bi t PCI bus controller, and embedded memory. With state-of-t he-art DSP technology and mixed-m ode signal technology, they offer high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive equa lization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. The devices support the PCI v2.3 bus interface for host communications with power management, and comply with the IEEE 802.3 specification for 10/100M bps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. They also support an auxi liary power auto-detec t function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. They support the Advanced Configuration Power ma nagement Interface (ACPI)--power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)--to achieve the most efficient power management possible. PCI Message Signaled Interrupt (MSI) is also supported. In addition to the ACPI feature, the devices su pport remote wake-up (inc luding AMD Magic Packet, Re-LinkOk, and Microsoft ® Wake-up frame) in both ACPI a nd APM (Advanced Power Management) environments. The LWAKE pin provides four different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the LWAKE pin provides motherboards with main power is off and only auxiliary exists), the a uxiliary power source must be able to provide the required power for the RTL8169SC. The devices are fully compliant with Microsoft ® NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and support IEEE 802 IP Laye r 2 priority encoding a nd 802.1Q Virtual bridged Local Area Network (VLAN). The above features c ontribute to lowering CPU utilization, especially benefiting performance when in operation on a ne twork server. Also, the devices boost their PCI performance by supporting PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when receiving. To better qualify for server use, the RTL8169SC support the PCI Dual Address Cycle (DAC) command when th e assigned buffers reside at a physical memory address higher than 4 Gigabytes. See section 9, Ordering Information, page 41 for package type details.
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 2 Track ID: JATR-1076-21 Rev. 1.2 2. Features Integrated 10/100/1000 transceiver Auto-Negotiation with Next Page capability Supports PCI rev.2.3, 32-bit, 33/66MHz Supports pair swap/polarity/skew correction Crossover Detection & Auto-Correction Wake-on-LAN and remote wake-up support Microsoft® NDIS5 Checksum Offload (IP, TCP, UDP) and largesend offload support Supports Full Duplex flow control (IEEE 802.3x) Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab Supports IEEE 802.1P Layer 2 Priority Encoding Supports IEEE 802.1Q VLAN tagging Serial EEPROM Supports up to 128Kbytes Boot ROM 3.3V signaling, 5V PCI I/O tolerant Transmit/Receive FIFO (72K) Supports power down/link down power saving Supports PCI Message Signaled Interrupt (MSI) Various 128-pin package types available 3. System Applications Gigabit Ethernet Network Interface Card Gigabit Ethernet MiniPCI Card
3 AVDDL
4 VSS
5 MDI1+
6 MDI1-
7 AVDDL
8 CTRL25
38 VSSPST
37 PCIAD28
36 PCIAD29
29 GNTB
28 PCICLK
27 PCIRSTB
26 VDD33
25 INTAB
20 AVDDL
39 PCIAD27
40 PCIAD26
41 VDD33
42 PCIAD25
43 PCIAD24
44 CBEB3
45 VDD12
46 IDSEL
47 PCIAD23
48 GND
49 PCIAD22
50 PCIAD21
51 VSSPST
52 GND
53 PCIAD20
54 VDD12
55 PCIAD19
56 VDD33
57 PCIAD18
58 PCIAD17
59 PCIAD16
61 FRAMEB
62 GND
63 IRDYB
64 VDD12
66 VSSPST
67 TRDYB
68 DEVSELB
69 STOPB
70 PERRB
71 VDD33
73 GND
75 SERRB
76 PAR
77 CBEB1
78 VDD12
79 PCIAD15
80 GND
81 VSSPST
82 PCIAD14
83 PCIAD13
128 VSS
127 RSET
126 VDD12A
125 CTRL12
124 VSS
123 VSS
122 XTAL2
121 XTAL1
120 AVDDH
119 VSSPST
118 GND
117 LED0
116 VDD12
115 LED1
114 LED2
113 LED3
112 GND
111 EESK
110 VDD12
109 EEDI
108 EEDO
107 VDD33
106 EECS
105 LANWAKE
104 PCIAD0
103 PCIAD1
102 PCIAD2
101 VSSPST
100 GND
99 VDD12
98 PCIAD3
97 PCIAD4
96 PCIAD5
95 PCIAD6
94 VDD33
93 PCIAD7
92 CBEB0
91 VSSPST
90 PCIAD8
89 PCIAD9
88 M66EN
87 PCIAD10
86 PCIAD11
85 PCIAD12
84 VDD33
Figure 1. RTL8169SC 128-Pin QFP Pin Assignments
T/S: Tri-State bi-directional input/output pin. Table 1. Power Management/Isolation O/D 31 Power Management Event: Open drain, active low. that a power management event has occurred. I 23 Isolate Pin: Active low. PCIRSTB and PCICLK) as long as the Isolate pin is asserted. CONFIG bits: LWACT(Config1.4) and LWPTN(Config4.2).
0 Active high Active low LWPTN
1 Positive pulse Negative pulse
when PMEB asserts and ISOLATEB is low.
Table 2. PCI Interface those clocks where both IRDYB and TRDYB are asserted. PCIADPIN16-0 are shared with Boot ROM address pins. input to the PCI device. Supports up to a 66MHz PCI clock. recognizes its target address after FRAMEB is asserted. FRAMEB is de-asserted, the transaction is in the final data phase. check if the current transaction is addressed to it. input is used when the device is acting as a bus master. ownership of the bus from the central arbiter. configuration read/write transactions are intended for it.
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 6 Track ID: JATR-1076-21 Rev. 1.2 Symbol Type Pin No Description IRDYB S/T/S 63 Initiator Ready: This indicates the initiating agent’s ability to complete the current data phase of the transaction. As a bus master, this signal will be asserted low when the device is ready to complete the current data phase transaction. This signal is used in conjunction with the TRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low. As a target, this signal indicates that the master has put data on the bus. TRDYB S/T/S 67 Target Ready: This indicates the target agent’s ability to complete the current phase of the transaction. As a bus master, this signal indicates that the target is ready for the data during write operations, or is ready to provide the data during read operations. As a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYB signal. Data transaction takes place at the rising edge of CLK, when both IRDYB and TRDYB are asserted low. PAR T/S 76 Parity: This signal indicates even parity across PCIADPIN31-0 and CBEB3-0 including the PAR pin. PAR is stable and valid one clock after each address phase. For data phase, PAR is stable and valid one clock after either IRDYB is asserted on a write transaction or TRDYB is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. As a bus master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. M66EN I 88 66MHZ_ENABLE: This pin indicates to the device whether the bus segment is operating at 66 or 33MHz. When this pin (active high) is asserted, the current PCI bus segment that the device resides on operates in 66MHz mode. If this pin is de-asserted, the current PCI bus segment operates in 33MHz mode. PERRB S/T/S 70 Parity Error: This pin is used to report data parity errors during all PCI transactions except a Special Cycle. PERRB is driven active (low) two clocks after a data parity error is detected by the device receiving data, and the minimum duration of PERRB is one clock for each data phase with parity error detected. SERRB O/D 75 System Error: If an address parity error is detected and Configuration Space Status register bit 15 (detect parity error) is enabled, the device asserts the SERRB pin low and bit 14 of the Status register in Configuration Space. STOPB S/T/S 69 Stop: Indicates that the current target is requesting the master to stop the current transaction. PCIRSTB I 27 Reset: When PCIRSTB is asserted low, the device performs an internal system hardware reset. PCIRSTB must be held for a minimum period of 120ns.
Table 3. EEPROM EESK O 111 Serial data clock. AUX: Input pin to detect if Aux. Power exists or not on initial power-on. assumes that no Aux. Power exists. EEDO I 108 Input from serial data output pin of EEPROM. EECS/BROMCSB O 106 EECS: EEPROM chip select. BROMCSB: This is the chip select signal of the Boot PROM. Table 4. Transceiver Interface the transmit pair in 10Base-T and 100Base-TX. pair in 10Base-T and 100Base-TX. is the transmit pair in 10Base-T and 100Base-TX. pair in 10Base-T and 100Base-TX. In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair.
Table 5. Clock Xtal1 I 121 Input of 25MHz clock reference. Xtal2 O 122 Output of 25MHz clock reference. Table 6. Regulator & Reference CTRL25 O 8 Regulator Control. V oltage control to external 2.5V regulator. CTRL12 O 125 Regulator Control. V oltage control to external 1.2V regulator. RSET I 127 Reference. External Resistor Reference. Table 7. LEDs Note 1: LED0 is also BROMOEB to enable BROM’ s output buffer during BROM read operation. Note 2: During power down mode, the LED signals are logic high. Note 3: LEDS1-0’ s initial value comes from 93C46/93C56/93C66.
Table 8. Power & Ground VDD12A Power 126 Analog 1.2V power supply. A VDDL Power 3, 7, 16, 20 Analog 2.5V power supply. A VDDH Power 10, 12, 120 Analog 3.3V power supply. Table 9. NC (Not Connected) Pins
Rev. 2.3. When internal registers ar e being accessed, the RTL8169SC acts as a PCI target (slave mode). Local Bus Specifications Rev. 2.3, March 29, 2002. little-endian or big-endian orderi ng through the use of the ENDIAN b it of the C+ Command Register. to big-endian or little-endian mode. Figure 2. Little-Endian Byte Ordering
Figure 3. Big-Endian Byte Ordering Interrupts are performed by asynchronously asserting the INTAB pin. This pin is an open drain output. Mask Register. This allows the system to defer interrupt processing as needed. RTL8169SC deasserts FRAMEB prior to count expiration, the content of the latency timer is ignored. is deasserted. Software is able to read or write to LTR, and the default value is 00H. through software. The RTL8169SC only supports 32-bit addressing as a target.
system must tri-state the address bus, and convert the C/BE bus to byt e enables after th e address cycle. described above, but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until FRAMEB is detected as deasserted. Figure 4. Target Read Operation
TRDYB. STOPB will remain asserted until FRAMEB is detected as deasserted. Figure 5. Target Write Operation
will be generated on the clock following GNTB. RTL8169SC will never force a wait state during a read operation. Figure 6. Master Read Operation
will be generated on the clock following GNTB. RTL8169SC will never force a wait state during a write operation. Figure 7. Master Write Operation
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 1 6 Track ID: JATR-1076-21 Rev. 1.2 6.2.5. Configuration Access Configuration register accesses are similar to target reads and writes in that they are single data word transfers and are initiated by the system. For the system to initiate a Configuration access, it must also generate IDSEL as well as the correct Comma nd (1010b or 1011b) during the Address phase. The RTL8169SC will respond as it does during Target operations. Configuration reads must be 32-bits wide, but writes may access individual bytes.
sections describe the different LED actions. driven high, indicating that no network connection exists. In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring. Figure 8. Rx LED
In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. Figure 9. Tx LED
Figure 10. Tx/Rx LED
operating properly. When this LED is high for extended periods, it indicates that a link problem exists. Figure 11. LINK/ACT LED
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 2 1 Track ID: JATR-1076-21 Rev. 1.2 6.4. PHY Transceiver 6.4.1. PHY Transmitter In 10Mbps mode, the Tx MAC retrieves packet data from the Tx Buffer Manager and sends it out through the transmitting physical layer in terface. The transmit 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. Th en, the 10Mbps serial data is converted into a Manchester-encoded data stream and is transmitted onto the media by the DAC converter. In 100Mbps mode, the transmitted 4-bit nibbles (TXD[ 3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code via 4B/5B coding technology, sc rambling, and serializing before being converted to 125MHz NRZ and NRZI signals. Af ter that, the NRZI signal is passed to the MLT-3 encoder, then to the DAC converter for transmission onto the media. In 1000Mbps mode, the RTL8169SC’s PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continu ous code-groups through 4D-PAM5 coding technology. Then those code groups are passed through a waveform shaping filter to minimize EMI effects, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a DAC. 6.4.2. PHY Receiver In MII (10Mbps) mode, the received differential si gnal is converted into a Manchester-encoded data stream. The stream is processed with a Manchester de coder, and is de-serialized into 4-bit wide nibbles. The 4-bit nibbles are presented to the MII interf ace at a clock speed of 2.5MHz. In 100Mbps mode, the MLT-3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT-3 and NRZI decoder, descrambler, 4B/5B decoder, and then is presented to the MII interface in 4-bit wide nibbles at a clock speed of 25MHz. In GMII mode, the input signal from the media fi rst passes through the on-ch ip sophisticated hybrid circuit to subtract the transmitted signal from the i nput signal for effective reduction of near-end echo. Afterwards, the received signal is processed with adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellati on, echo cancellation, timing recover y, error correction, and 4D-PAM5 decoding. Then the 8-bit wide data is recovered and is sent to the GM II interface at a clock speed of 125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the Rx Buffer Manager.
Reg8 as defined in IEEE 802.3ab. ability for the RTL8169SC to read from and write data to an external serial EEPROM device. of EESK, EECS, EEDO, and EEDI. Table 10. EEPROM Interface EECS 93C46 (93C56/93C66) chip select. EESK EEPROM serial data clock. EEDI/Aux Input data bus/Input pin to detect if Aux. Power exists or not on initial power-on.
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 2 3 Track ID: JATR-1076-21 Rev. 1.2 6.7. Power Management The RTL8169SC is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class Power Management Referen ce Specification (V1.0a), such as to support an Operating System-Directed Power Management (OSPM) environment. The RTL8169SC can monitor the ne twork for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via PME# when such a packet or event occurs. Then, the whole system can be restored to a normal state to process incoming jobs. When the RTL8169SC is in power down mode (D1 ~ D3):
- The Rx state machine is stopped, and the RTL8169SC monitors the network for wakeup events such as a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8169SC will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx FIFO buffer.
- The FIFO status and packets that have already been received into the Rx FIFO before entering power down mode are held by the RTL8169SC.
- Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.
- After restoration to a D0 state, the RTL8169SC transfers data that was not moved into the Tx FIFO buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. The D3cold_support_PME bit (bit15, PMC register) a nd the Aux_I_b2:0 bits (bit8 :6, PMC register) in PCI configuration space depend on the existence of Aux power (bit15, PMC) = 1. If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s. Example: If EEPROM D3c_support_PME = 1:
- If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 F7, then PCI PMC = C2 F7)
- If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 F7, then PCI PMC = 02 76) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C2 F7 (Realtek EEPROM default value).
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 2 4 Track ID: JATR-1076-21 Rev. 1.2 If EEPROM D3c_support_PME = 0:
- If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 77, then PCI PMC = C2 77)
- If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 77, then PCI PMC = 02 76) In the above case, if wakeup support is not desired wh en main power is off, it is suggested that the EEPROM PMC be set to 02 76. Link Wakeup occurs only when the following conditions are met:
- The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be asserted in the current power state. Magic Packet Wakeup occurs only when the following conditions are met:
- The destination address of the received Magic Packet is acceptable to the RTL8169SC, e.g. a broadcast, multicast, or unicast packet addressed to the current RTL8169SC adapter.
- The received Magic Packet does not contain a CRC error.
- The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the PME# can be asserted in the current power state.
- The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid (Fast) Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met:
- The destination address of the received Wakeup Frame is acceptable to the RTL8169SC, e.g. a broadcast, multicast, or unicast address to the current RTL8169SC adapter.
- The received Wakeup Frame does not contain a CRC error.
- The PMEn bit (CONFIG1#0) is set to 1.
- The 16-bit CRC* of the received Wakeup Frame matches the 16-bit CRC* of the sample Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8169SC is configured to allow direct packet wakeup, e.g. a broadcast, multicast, or unicast network packet. *16-bit CRC: The RTL8169SC supports two normal wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet).
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 2 5 Track ID: JATR-1076-21 Rev. 1.2 The PME# signal is asserted only when the following conditions are met:
- The PMEn bit (bit0, CONFIG1) is set to 1.
- The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
- The RTL8169SC may assert PME# in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space.
- A Magic Packet, LinkUp, or Wakeup Frame has been received.
- Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8169SC to stop asserting a PME# (if enabled). When the device is in power down mode, e.g. D1 -D3, the IO, MEM, and Boot ROM spaces are all disabled. After a RST# assertion, th e device’s power state is restored to D0 automatically if the original power state was D3 cold. There is no hardware delay at the devi ce’s power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The setting may be changed from the EEPROM, if required. The RTL8169SC also s upports the legacy LAN WAKE-UP function. The LWAKE pin is used to notify legacy motherboards to execute the wake-up proc ess whenever the device receives a wakeup event, such as Magic Packet. The LWAKE signal is asserted according to the following settings: 1. LWPME bit (bit4, CONFIG4):
- LW AKE can only be asserted when PMEB is asserted and ISOLATEB is low.
- LW AKE is asserted whenever a wakeup event occurs. 2. Bit1 of DELAY byte (offset 1Fh, EEPROM):
- LW AKE signal is enabled.
- LW AKE signal is disabled.
Table 11. Absolute Maximum Ratings Table 12. Recommended Operating Conditions Table 13. Crystal Requirements fundamental mode, AT-cut type.
25 MHz
fundamental mode, AT-cut type. Ta=25°C. fundamental mode, AT-cut type.
Table 14. Thermal Characteristics Table 15. DC Characteristics
Figure 12. Serial EEPROM Interface Timing Table 16. EEPROM Access Timing Parameters
Table 17. PCI Bus Timing Parameters
Figure 27. Parity Operation – One Example
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 3 9 Track ID: JATR-1076-21 Rev. 1.2 8. Mechanical Dimensions See the Mechanical Dimensions notes on the next page.
Integrated Gigabit Ethernet Controller (NIC) (MiniPCI) 4 0 Track ID: JATR-1076-21 Rev. 1.2 8.1. Mechanical Dimensions Notes Symbol Dimensions in inches Dimensions in mm Notes: Min Typical Max Min Typical Max 1. Dimensions D & E do not include interlead flash. A - - 0.134 - - 3.40 2. Dimension b does not include dambar protrusion/intrusion. v i s u a l i n s p e c t i o n . e 0.020 BSC 0.50 BSC LEADFRAME MATERIAL y - - 0.004 - - 0.10 DATE θ 0° - 12° 0° - 12° REALTEK SEMICONDUCTOR CORP.
Table 20. Ordering Information Note: See page 3 for package identification.