RTL8168B

RTL8111B REALTEK | Alldatasheet

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INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS™ APPLICATIONS REGISTERS DATASHEET Rev. 1.0

26 January 2006

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.0 COPYRIGHT ©2006 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s register information on the Realtek RTL8111B and RTL8168B chips. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2006/01/26 First release.

Integrated Gigabit Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.0 Table of Contents

Integrated Gigabit Ethernet Controller for PCI Express iv Track ID: JATR-1076-21 Rev. 1.0

Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.0 1. General Description The Realtek RTL8111B/RTL8168B Gigabit Ethernet controllers combine a triple-speed IEEE 802.3 compliant Media Access Controller (M AC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and embedded memory. With state-of -the-art DSP technology and mixed-mode signal technology, the RTL8111B/RTL8168B offer high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. The devices support the PCI Express 1.0a bus interface for host communications with power management and comply with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. They also support an auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. Advanced Configuration Power management Interface (ACPI)—power management for modern operating systems that are capable of Operating System-d irected Power Management (OSPM)—is supported to achieve the most efficient power management possibl e. PCI Message Signaled Interrupt (MSI) is also supported. In addition to the ACPI feature, remote wake-up (including AMD Magic Packet ™ , Re-LinkOK, and Microsoft® Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8111B/RTL8168B. The RTL8111B/RTL8168B fully comply with Microsoft ® NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and support IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. The devices also features next-generation inte rconnect PCI Express technology. PCI Express is a high-bandwidth, low-pin-count, serial interconnect technology that offers significant improvements in performance over conventional PCI, and also main tains software compatibility with existing PCI infrastructure. The RTL8168B supports the attachment of a 64Kbyte external Serial Peripheral Interface (SPI) Flash. The AT25F512 interface permits the RTL8168B to read from, and write data to, an external SPI Flash device, and provides 64Kbytes of serial re-programmable Flash memory. Note: The RTL8111B does not support SPI. The RTL8111B/RTL8168B is suitable for multiple market segments and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications.

Table 1. MAC Registers 0000h IDR0 RW ID Register 0. autoloaded from the EEPROM EthernetID field. 0008h MAR7 RW Multicast Address Register 7. The MAR register 0-7 are only permitted to read/write via 4-byte access. responsible for initializing these registers.

Integrated Gigabit Ethernet Controller for PCI Express 3 Track ID: JATR-1076-21 Rev. 1.0 Offset Tag RW Description 0048h-004Bh TCTR RW Timer CounT Register: This register contains a 32-bit general-purpose timer. Writing any value to this 32-bit register will reset the original timer and begin the count from zero. This counter is based on the PCI clock connected. For PCI-E NICs, the internal PCI clock is 125MHz. Therefore, the unit of TCTR of the RTL8111B/RTL8168B is 8ns. 004Ch-004Fh - - Reserved 0050h 9346CR RW 93C46 Command Register 0051h CONFIG0 RW Configuration Register 0 0052h CONFIG1 RW Configuration Register 1 0053h CONFIG2 RW Configuration Register 2 0054h CONFIG3 RW Configuration Register 3 0055h CONFIG4 RW Configuration Register 4 0056h CONFIG5 RW Configuration Register 5 0057h - - Reserved 0058h-005Bh TimerInt R /W Timer Interrupt Register. Once having written a non-zero value to this register, the Timeout bit of the ISR register will be set whenever the TCTR reaches that value. The Timeout bit will never be set whilst the TimerInt register is zero. 005Ch-005Fh - - Reserved 0060h-0063h PHYAR RW PHY Access Register 0064h-006Bh - - Reserved 006Ch PHYStatus R PHY Status Register 006Dh~0083h - - Reserved 0084h–008Bh Wakeup0 RW Power Manage ment wakeup frame0 (64bit) 008Ch–0093h Wakeup1 RW Power Manage ment wakeup frame1 (64bit) 0094h–009Bh Wakeup2LD RW Power Management wakeup frame2 (128bit), Low DWord 009Ch–00A3h Wakeup2HD RW Power Manage ment wakeup frame2, High DWord 00A4h–00ABh Wakeup3LD RW Power Manageme nt wakeup frame3 (128bit), Low DWord 00ACh–00B3h Wakeup3HD RW Power Manage ment wakeup frame3, High DWord 00B4h–00BBh Wakeup4LD RW Power Manageme nt wakeup frame4 (128bit), Low DWord 00BCh–00C3h Wakeup4HD RW Power Manage ment wakeup frame4, High DWord 00C4h-00C5h CRC0 RW 16-bit CRC of wakeup frame 0 00C6h-00C7h CRC1 RW 16-bit CRC of wakeup frame 1 00C8h-00C9h CRC2 RW 16-bit CRC of wakeup frame 2 00CAh-00CBh CRC3 RW 16-bit CRC of wakeup frame 3 00CCh-00CDh CRC4 RW 16-bit CRC of wakeup frame 4 00CEh-00D9h - - Reserved 00DAh-00DBh RMS RW Rx packet Maximum Size 00DCh-00DFh - - Reserved 00E0h-00E1h C+CR RW C+ Command Register 00E2h-00E3h - - Reserved 00E4h-00EBh RDSAR RW Receive Descriptor Star t Address Register (256-byte alignment) 00ECh MTPS RW Max Transmit Packet Size Register 00EDh-00FFh - - Reserved

Table 2. DTCCR: Dump Tally Counter Command (Offset 0010h-0017h, RW) 0 TxOk 64-bit counter of Tx Ok packets. 8 RxOk 64-bit counter of Rx Ok packets.

16 TxER 64-bit packet counter of Tx errors

underrun, and out of window collision.

24 RxEr 32-bit packet counter of Rx errors

28 MissPkt 16-bit counter of missed packets (CRC

Ok) resulted from Rx FIFO full.

30 FAE 16-bit counter of Frame Alignment Error

32 Tx1Col 32-bit counter of Tx Ok packets with

only 1 collision before Tx Ok.

36 TxMCol 32-bit counter of Tx Ok packets with

40 RxOkPhy 64-bit counter of Rx Ok packets with

48 RxOkBrd 64-bit counter of Rx Ok packets with

56 RxOkMul 32-bit counter of Rx Ok packets with

60 TxAbt 16-bit counter of Tx abort packets.

62 TxUndrn 16-bit counter of Tx underrun and discard

packets (only possible on jumbo frames).

3 Cmd RW Command: When set, the RTL8111B/RTL8168B begins dumping 13 Tally counters to

the address specified above. When this bit is reset by the RTL8111B/RTL8168B, the dumping has been completed.

Table 3. Command (Offset 0037h, RW)

4 RST RW Reset: Set this bit to 1 to force the RTL8111B/RTL8168B into a software reset

3 RE RW Receiver Enable

2 TE RW Transmitter Enable

Table 4. TPPoll: Transmit Priority Polling (Offset 0038h, RW)

7 HPQ W High Priority Queue polling: Writing a ‘1’ to this bit will notify the

RTL8111B/RTL8168B that there is a high priority packet(s) waiting to be transmitted. packets have been transmitted. Writing a ‘0’ to this bit has no effect.

6 NPQ W Normal Priority Queue polling: Writing a ‘1’ to this bit will notify the

normal priority packets have been transmitted. Writing a ‘0’ to this bit has no effect.

0 FSWInt W Forced Software Interrupt: Writing a ‘1’ to this bit will trigger an interrupt, and the

SWInt bit (bit8, ISR, offset3Eh-3Fh) will set. Writing a ‘0’ to this bit has no effect. Table 5. Interrupt Mask (Offset 003Ch-003Dh, RW)

14 TimeOut RW Time Out Interrupt:

9 FEmp RW Rx FIFO empty under FIFO full Status Interrupt:

8 SWInt RW Software Interrupt:

7 TDU RW Tx Descriptor Unavailable Interrupt:

6 FOVW RW Rx FIFO Overflow Interrupt:

one to FOVW of ISR to clear this bit.

5 LinkChg RW Link Change Interrupt:

4 RDU RW Rx Descriptor Unavailable Interrupt:

3 TER RW Tx Error Interrupt:

2 TOK RW Tx OK:

1 RER RW Rx Error Interrupt:

0 ROK RW Rx OK Interrupt:

Table 6. Interrupt Status (Offset 003Eh-003Fh, RW)

14 TimeOut RW Time Out: This bit is set to 1 wh en the TCTR register reaches the value of the

9 FEmp RW Rx FIFO empty under FIFO full Status Interrupt: When set, this bit indicates

that the Rx FIFO is empty after an Rx FIFO full indication.

8 SWInt RW Software Interrupt: This bit is set to 1 whenever a ‘1’ is written by software to

FSWInt (bit0, offset D9h, TPPoll register).

7 TDU RW Tx Descriptor Unavailable: When set, this bit indicates that the Tx descriptor is

6 FOVW RW Rx FIFO Overflow: This bit set to 1 is caused by RDU, poor PCI performance,

5 LinkChg RW Link Change: This bit is set to 1 when link status is changed.

4 RDU RW Rx Descriptor Unavailable: When set to 1, this bit indicates that the Rx

3 TER RW Transmit (Tx) Error: This bit set to 1 indicates that a packet transmission was

aborted, due to excessive collisions.

2 TOK RW Transmit (Tx) OK: When set to 1, th is bit indicates that a packet transmission

has been completed successfully.

1 RER RW Receive (Rx) Error: When set to 1, this bit indicates that a packet has either a

0 ROK RW Receive (Rx) OK: In normal mode, this bit set to 1 indicates the successful

completion of a packet reception. Note: Writing 1 to any bit in the ISR will reset that bit. Table 7. Transmit Configuration (Offset 0040h-0043h, RW) 26 HWVERID1 R Hardware Version ID1: Please refer to HWVERID0 (above). 23 HWVERID2 R Hardware Version ID2: Pleas e refer to HWVERID0 (bits 29-28 above).

19 IFG2 RW InterFrameGap2

Integrated Gigabit Ethernet Controller for PCI Express 8 Track ID: JATR-1076-21 Rev. 1.0 Bit Symbol RW Description 31-30 - - Reserved Hardware Version ID0: Bit29 Bit28 Bit26 Bit23 RTL8111B/RTL8168B 1 1 0 0 RTL8100E 1 1 0 1 RTL8101E 1 1 1 0 29-28 HWVERID0 R 27 - - Reserved 26 HWVERID1 R Hardware Version ID1: Please refer to HWVERID0 (above). InterFrame Gap Time: This field allows the InterFrame gap time to be longer than the standards of 9.6µs for 10Mbps, 960ns for 100Mbps, and 96ns for 1000Mbps. The time can be programmed from 9.6µs to 14.4µs (10Mbps), 960ns to 1440ns (100Mbps), and 96ns to 144ns (1000Mbps). The setting of the InterFrame gap is: IFG[2:0] IFG@1000MH z (ns) IFG@100MHz (ns) IFG@10MHz (us) 0 1 1 96 960 9.6 1 0 1 96 + 8 960 + 8 * 10 9.6 + 8 * 0.1 1 1 1 96 + 16 960 + 16 * 10 9.6 + 16 * 0.1 0 0 1 96 + 24 960 + 24 * 10 9.6 + 24 * 0.1 0 1 0 96 + 48 960 + 48 * 10 9.6 + 48 * 0.1 25-24 IFG1, 0 RW Other values are reserved. 18, 17 LBK1, LBK0 RW Digital Loopback test: The digital loopback function is independent of the current link status. For analog loopback tests, software must force the phyceiver into loopback mode through PHYAR register while the RTL8111B/RTL8168B operates normally. 00 : Normal operation 01 : MAC loopback mode 10 : Reserved 11 : Reserved

16 TX_NOCRC RW NO CRC: Setting this bit to 1 means that there is no CRC appended at the end

of a packet. Setting to 0 means that there is a CRC appended at the end of a packet. 15-11 - - Reserved 10-8 MXDMA2, 1, 0 RW Max DMA Burst Size per Tx DMA Burst: This field sets the maximum size of transmit DMA data bursts according to the following table: 000: 16 bytes 001: 32 bytes 010: 64 bytes 011: 128 bytes 100: 256 bytes 101: 512 bytes 110: 1024 bytes 111: Unlimited 7-0 - - Reserved

26 HWVERID1 R Hardware Version ID1: Please refer to HWVERID0 (above). Table 8. Receive Configuration (Offset 0044h-0047h, RW) after having received a whole packet in the FIFO.

Integrated Gigabit Ethernet Controller for PCI Express 10 Track ID: JATR-1076-21 Rev. 1.0 Bit Symbol RW Description 10-8 MXDMA2, 1, 0 RW Max DMA Burst Size per Rx DMA Burst: This field sets the maximum size of the receive DMA data bursts according to the following list: 000: Reserved 001: Reserved 010: 64 bytes 011: 128 bytes 100: 256 bytes 101: 512 bytes 110: 1024 bytes 111: Unlimited 7 - - Reserved 6 9356SEL R This bit reflects what type of EEPROM is used. 1: The EEPROM used is 9356. 0: The EEPROM used is 9346.

5 AER RW Accept Error Packet:

When set to 1, all packets with CRC error, alignment error, and/or collided fragments will be accepted. When set to 0, all packets with CRC error, alignment error, and/or collided fragments will be rejected.

4 AR RW Accept Runt: This bit set to 1 a llows the receiver to accept packets that are

smaller than 64 bytes. The packet must be at least 8 bytes long to be accepted as a runt.

3 AB RW Accept Broadcast Pack ets: 1: Accept, 0: Reject

2 AM RW Accept Multicast Packet s: 1: Accept, 0: Reject

1 APM RW Accept Physical Match P ackets: 1: Accept, 0: Reject

0 AAP RW Accept All Packets with Destin ation Address: 1: Accept, 0: Reject

Table 9. 9346CR: 93C46 (93C56) Command (Offset 0050h, RW) network and host bus master operations are disabled. EEDI, & EEDO pins respectively.

3 EECS RW

2 EESK RW

1 EEDI RW

0 EEDO R

Note: EESK, EEDI and EEDO are valid after boot ROM complete.

Table 10. CONFIG 0 (Offset 0051h, RW) Table 11. CONFIG 1 (Offset 0052h, RW) value of these bits comes from the 93C46/93C56. 3 MEMMAP R Memory Mapping: The operational registers are mapped into PCI memory space. 2 IOMAP R I/O Mapping: The operational re gisters are mapped into PCI I/O space. 1 VPD R Vital Product Data: Set to enable Vital Product Data.

0 PMEn R Power Management Enable:

Table 12. CONFIG 2 (Offset 0053h, RW)

4 Aux_Status R Auxiliary Power Present Status:

The value of this bit is fixed after each PCI reset. Table 13. CONFIG 3 (Offset 0054h, RW)

6 VPDSel RW VPD Offset Select:

system when a Magic Packet is received. Destination address + Source address + data + CRC. multicast address, which includes the broadcast address. IEEE MAC address match the address of the ID register.

Table 14. CONFIG 4 (Offset 0055h, RW) Table 15. CONFIG 5 (Offset 0056h, RW)

6 BWF RW Broadcast Wakeup Frame:

The power-on default value of this bit is 0.

5 MWF RW Multicast Wakeup Frame:

which is a multicast address. The power-on default value of this bit is 0.

4 UWF RW Unicast Wakeup Frame:

which is its own physical address. The power-on default value of this bit is 0. Table 16. PHYAR: PHY Access (Offset 0060h-0063h, RW)

31 Flag RW Flag bit, used as PCI VPD access method:

RTL8111B/RTL8168B has completed writing to the specified MII register. RTL8111B/RTL8168B has completed retrieving data from the specified MII register. RW 5-bit GMII/MII register address. 15-0 Data15-0 RW 16-bit GMII/MII register data.

Table 17. PHYStatus: PHY Status (Offset 006Ch, R) 6 TxFlow R Transmit Flow Control: 1: Enabled, 0: Disabled. 5 RxFlow R Receive Flow Contro l: 1: Enabled, 0: Disabled. 4 1000MF R Link speed is 1000Mbps and in full-duplex (GMII mode only). 3 100M R Link speed is 100Mbps (GMII or MII mode only). 2 10M R Link speed is 10Mbps (GMII or MII mode only). 1 LinkSts R Link Status. 1: Link Ok, 0: No Link. 0 FullDup R Full-Duplex Status: 1: Full-duplex mode, 0: Half-duplex mode. Note1: This register is updated continuously at maximum periods of 300µs. Note2: MII registers polling cycle: 320ns * (32 MDC clock + 32 MDC clock) * 6 registers. Table 18. RMS: Receive (Rx) Packet Maximum Size (Offset 00DAh-00DBh, R) The maximum Rx packet size supported is 16000 bytes. although both RWT and RES bits are set in the corresponding Rx Status Descriptor. Table 19. C+CR: C+ Command (Offset 00E0h-00E1h, RW) 6 RxVLAN RW Receive VLAN De-tagging Enable: 1: Enable. 0: Disable. 5 RxChkSum RW Receive Checksum Offloa d Enable: 1: Enable. 0: Disable. Note1: This register is the key before configuring other registers and descriptors. Note2: This register is word access only. Byte access to this register has no effect.

Table 20. RDSAR: Receive Descriptor Start Address (Offset 00E4h-00EBh, RW) 63-0 RDSA RW Receive Descriptor Start Address: 64-bit address, 256-byte alignment address. Bit[31:0]: Offset E7h-E4h, low 32-bit address. Bit[63:32]: Offset EBh-E8h, high 32-bit address. Table 21. MTPS: Max Transmit Packet Size (Offset 00ECh, RW) RTL8111B/RTL8168B is to transmit. These fields count from 000001 to 111111 in unit of 128 bytes. bytes, this field must be larger than the max packet size. E.g., 0x0C. value other than 0 for correct operation. Do not set to this value. larger than the maximum packet transmitted. packet of size up to 7440 bytes. Ex., 0x3B (7552) bytes. transmitted can not exceed 7440 (7436 + CRC) bytes. platforms to prevent from Tx underruns.

Table 22. PHY Register Definitions

0 RW BMCR Basic mode control register

1 RO BMSR Basic mode status register

2 RO PHYAD1 PHY identifier register 1

3 RO PHYAD2 PHY identifier register 2

4 RW ANAR Auto-negotiati on advertising register

5 RW ANLPAR Auto-negotiation link partner ability register

6 RW ANER Auto-negotiation expansion register

7 RW ANNPTR Auto-negotiation ne xt page transmit register

8 RW ANNRPR Auto-negotiation ne xt page receive register

9 RW GBCR 1000Base-T control register

10 RO GBSR 1000Base-T status register

15 RO GBESR 1000Base-T extended status register

Table 23. BMCR (Address 0x00)

15 Reset RW 0 Reset:

1: Initiate software Reset / Reset in Process. has begun or the device has entered its forced mode.

14 Loopback RW 0 Loopback:

Integrated Gigabit Ethernet Controller for PCI Express 18 Track ID: JATR-1076-21 Rev. 1.0 Bit Name RW Default Description

13 Speed[0] RW 0 Speed Select:

When Auto-Negotiation is disabled, bits 6 and 13 select device speed selection per table below: Speed[1] Speed[0] Speed Enabled 11: Reserved 10: 1000 Mb/s 01: 100 Mb/s 00: 10 Mb/s

12 ANE RW 1 Auto-Negotiation Enable:

1: Auto-Negotiation Enabled - bits 6, 8 and 13 of this register are ignored when this bit is set. 0: Auto-Negotiation Disabled - bits 6, 8 and 13 determine the link speed and mode.

11 PWD RW 0 Power Down:

1: Power down (only Management Interface and logic active.) 0: Normal operation.

10 Isolate RW 0 Isolate:

1: Isolates the Port from the MII with the exception of the serial management. 0: Normal operation.

9 Restart_AN RW 0 Restart Auto-Negotiation:

1: Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 0: Normal operation.

8 Duplex RW 1 Duplex Mode:

1: Full Duplex operation. Duplex selection is allowed only when Auto-Negotiation is disabled (bit 12 = 0). 0: Half Duplex operation.

7 Reserved RW 0

6 Speed[1] RW 1 Speed Select: See description for bit 13. 5:0 Reserved RO 000000 Reserved by IEEE

Table 24. BMSR (Address 0x01) 1: Device able to perform 100Base-T4 mode. 0: Device not able to perform 100Base-T4 mode. should always be read back as ‘0’. 1: Device able to perform 100Base-TX in full duplex mode. 0: Device unable to perform 100Base-TX in full duplex mode. 1: Device able to perform 100Base-TX in half duplex mode. 0: Device unable to perform 100Base-TX in half duplex mode. 1: Device able to perform 10Base-T in full duplex mode. 0: Device unable to perform 10Base-T in full duplex mode. 1: Device able to perform 10Base-T in half duplex mode. 0: Device unable to perform 10Base-T in half duplex mode. 1: Device able to perform 100Base-T2 Full Duplex mode. 0: Device unable to perform 100Base-T2 Full Duplex mode. should always be read back as ‘0’. 1: Device able to perform 100Base-T2 Half Duplex mode. 0: Device unable to perform 100Base-T2 Full Duplex mode. should always be read back as ‘0’. 1: Device supports Extended Status Register 0x0F (15).

7 Reserved RO 0 Reserved

6 Preamble

invalid opcode or invalid turnaround.

5 Auto-Negotiation

0: Auto-Negotiation process not complete.

4 Remote Fault RO 0 Remote Fault:

1: Remote Fault condition detected (cleared on read or by reset). Link Partner of Remote Fault. 0: No remote fault condition detected.

3 Auto-Negotiation

1: Device is able to perform Auto-Negotiation. 0: Device is not able to perform Auto-Negotiation.

2 Link Status RO 0 1: Link is up

This bit indicates if link was lost since the last read.

1 Jabber detect RO 0 1: Jabber condition detected

0 Extended

Table 25. PHY Identifier Register 1 (Address 0x02) Table 26. PHY Identifier Register 2 (Address 0x03)

Table 27. ANAR (Address 0x04)

15 NextPage RW 0 1: Advertise

14 Resv RO 0

13 Remote fault RW 0 1: Set Remote Fault bit

12 Resv RW 0

11 Asymmetric PAUSE RW 0 1: Asymmetric Pause

10 PAUSE RW 0 1: MAC PAUSE implemented

Table 28. ANLPAR (Address 0x05)

15 Next Page RO 0 Recei ved Code Word Bit 15

14 ACK RO 0 Received Code Word Bit 14

13 Remote Fault RO 0 Received Code Word Bit 13

Table 29. ANER (Address 0x06)

4 Parallel Detection Fault RO 0 1: A fault has been detected via the Parallel Detection

3 Link Partner Next

2 Local Next Pageable RO 1 1: Local Device is Next Page able

1 Page Received RO 0 1: A New Page has been received

0 Link Partner

Table 30. ANNPTR (Address 0x07)

15 Next Page RW 0 Transmit Code Word Bit 15

14 Resv RO 0 Transmit Code Word Bit 14

13 Message Page RW 1 Transmit Code Word Bit 13

12 Acknowledge 2 RO 0 Transmit Code Word Bit 12

11 Toggle RO 0 Transmit Code Word Bit 11

Table 31. ANNPRR(Address 0x08)

15 Reserved RO 0 Received Code Word Bit 15

14 Acknowledge RO 0 Recei ved Code Word Bit 14

13 Message Page RO 0 R eceived Code Word Bit 13

12 Acknowledge 2 RO 0 Recei ved Code Word Bit 12

11 Toggle RO 0 Receive d Code Word Bit 11

Table 32. GBCR (Address 0x09)

12 MASTER/SLAVE

11 MASTER/SLAVE

10 Port Type RW 0 1: Prefer multi-port device (MASTER)

Table 33. GBSR (Address 0x0A)

15 MASTER/SLAVE

14 MASTER/SLAVE

13 Local Receiver Status RO 0 1: Local Receiver OK

12 Remote Receiver Status RO 0 1: Remote Receiver OK

11 Link Partner

10 Link Partner

Table 34. GBESR (Address 0x0F)

1. EEPROM (93C46/93C56) Contents

9346CR Register, or using PCI VPD. EEPROM read operations from the 93C46 (93C56) Address 00h to 3Fh. We recommend you obtain Realtek approval before changing the default settings of the EEPROM. Table 35. EEPROM Contents the PCI configuration space are "10ECh" and "8129h". 02h-03h VID PCI Vendor ID: PCI conf iguration space offset 00h-01h. 04h-05h DID PCI Device ID: PCI conf iguration space offset 02h-03h. 06h-07h SVID PCI Subsystem Vendor ID: PCI configuration space offset 2Ch-2Dh. 08h-09h SMID PCI Subsystem ID: PCI c onfiguration space offset 2Eh-2Fh. 0Ah BAR2 PCI BAR2[7:0] : 04h for 64-bit MEM, 00h for 32-bit MEM. 0Bh BAR0 PCI BAR0[7:0] : 01h for IO. 0Dh CONFIG3 RTL8111B/RTL8168B Configuration regi ster 3: Operational register offset 54h. loads Ethernet ID to IDR0-IDR5 of the RTL8111B/RTL8168B's I/O registers. 14h CONFIG0 RTL8111B/RTL8168B Configuration register 0: Operational registers offset 51h.

Integrated Gigabit Ethernet Controller for PCI Express 25 Track ID: JATR-1076-21 Rev. 1.0 Bytes Contents Description 15h CONFIG1 RTL8111B/RTL8168B Configuration register 1: Operational registers offset 52h. 16h-17h PMC Reserved: Do not change this field without Realtek approval. Power Management Capabilities. PCI configuration space addresses 42h and 43h. 18h Express Cap [7] => memory space offset 6D bit [7] [6:5] =>Reserved. [4] => configuration space offset 62h bit[4] [3:0] => memory space offset 6D bit [3:0] 19h CONFIG4 Reserved: Do not change this field without Realtek approval. RTL8111B/RTL8168B Configuration register 4, operational registers offset 55h. 1Ah PCIE configura tion space offset 64h 1Bh Express Device Capability PCIE configuration space offset 65h 1Ch PCIE configura tion space offset 70h 1Dh Link Control / Status PCIE configuration space offset 73h 1Eh PCIE Link Cap [3:2] => PCIE conf iguration space offset 6Dh bit[3:2] 1Fh CONFIG_5 Do not change this field without Realtek approval. 20h-27h Serial Number PCIE conf iguration space offset 14Ch-153h 28h PCIE configurati on space offset B4h 29h PCIE configurati on space offset B5h 2Ah PCIE configura tion space offset B6h 2Bh PM Exit Control PCIE configuration space offset B7h 2Ch PCIE configura tion space offset B8h 2Dh Active PM Timer PCIE configuration space offset B9h 2Eh EPHY2 [7:3] => EPHY Register Offset 0x01 bit[15:11] [2:0] => EPHY Register Offset 0x00 bit[5:3] 2Fh ROMBAR PCI Expansion ROM BAR Offset 30h 30h VSR P Credit PCIE configuration space offset 96h 31h EPHY0 [7:4] => EPHY Register Offset 0x07 bit[15,14,10,9] [3:2] => EPHY Register Offset 0x00 bit[7:6] [1] => EPHY Register Offset 0x01 bit[4] [0] => EPHY Register Offset 0x07 bit[11] 32h-33h CheckSum Reserved: Do not change this field without Realtek approval. Checksum of the EEPROM content. 34h PCIE configura tion space offset 94h 35h VSR P Credit PCIE configuration space offset 95h 36h PCIE configura tion space offset 99h 37h VSR NP Credit PCIE configuration space offset 9Ah 38h PCIE configurati on space offset 9Ch 39h VSR CPL Credit PCIE configuration space offset 9Dh 3Ah PCIE configura tion space offset B2h 3Bh VSR Link Timer PCIE configuration space offset B3h 3Ch EPHY1 [7:3] => EPHY Register Offset 0x06 bit[14:12,8:7] 3Dh PCIE configura tion space offset B1h 3Eh VSR Link Timer PCIE configuration space offset B0h

3Fh PXE_Para Reserved: Do not change this field without Realtek approval. 40h-7Fh VPD_Data VPD data field: Offset 40h is the start address of the VPD data. Table 36. EEPROM Related MAC Registers Note: Registers marked with type = 'W*' can be written only if bits EEM1=EEM0=1. Table 37. EEPROM Related Power Management Registers

running at 2.5GHz signaling rate with X1 link width, i. e., one transmit and one receive differential pairs. and link reversal are also supported to ease PCB layout constraints. and DC balance by sacrificing the 25 percent overhead to the system through the addition of 2 extra bits. data and transmitted onto PCB trace to its upstream device via differential driver. to generate parallel data. The receiver’s PLL circuits are resynchronized to maintain bit and symbol lock. Table 38. PCI Configuration Space Table

Integrated Gigabit Ethernet Controller for PCI Express 28 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 06h Status R 0 0 0 1 IntSt 0 0 0 07h R DPERR SSERR RMABT RTABT STABT 0 0 DPD W DPERR SSERR RMABT RTABT STABT - - DPD 08h Revision ID R 0 0 0 0 0 0 0 1 09h PIFR R 0 0 0 0 0 0 0 0 0Ah SCR R 0 0 0 0 0 0 0 0 0Bh BCR R 0 0 0 0 0 0 1 0 0Ch CLS RW CLS7 CLS6 CLS5 CLS4 CLS3 CLS2 CLS1 CLS0 0Dh LTR R 0 0 0 0 0 0 0 0 0Eh HTR R 0 0 0 0 0 0 0 0 0Fh BIST R 0 0 0 0 0 0 0 0 10h IOAR R 0 0 0 0 0 0 0 IOIN W - - - - - - - - 11h RW IOAR15 IOAR14 IOAR13 IOAR12 IOAR11 IOAR10 IOAR9 IOAR8 12h RW IOAR23 IOAR22 IOAR21 IOAR20 IOAR19 IOAR18 IOAR17 IOAR16 13h RW IOAR31 IOAR30 IOAR29 IOAR28 IOAR27 IOAR26 IOAR25 IOAR24 14h- 17h Reserved 18h R 0 0 0 0 MEM64 0 0 0 19h RW MEM15 MEM14 MEM13 MEM 12 MEM11 MEM10 MEM9 MEM8 1Ah RW MEM23 MEM22 MEM21 ME M20 MEM19 MEM18 MEM17 MEM16 1Bh RW MEM31 MEM30 MEM29 ME M28 MEM27 MEM26 MEM25 MEM24 1Ch RW MEM39 MEM38 MEM37 ME M36 MEM35 MEM34 MEM33 MEM32 1Dh RW MEM47 MEM46 MEM45 ME M44 MEM43 MEM42 MEM41 MEM40 1Eh RW MEM55 MEM54 MEM53 ME M52 MEM51 MEM50 MEM49 MEM48 1Fh MEM 64 BAR RW MEM63 MEM62 MEM61 MEM 60 MEM59 MEM58 MEM57 MEM56 20h- 27h RESERVED 28h- 2Bh CISPtr CardBus CIS Pointer 2Ch SVID R SVID7 SVID6 SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 2Dh R SVID15 SVID14 SVID13 SV ID12 SVID11 SVID10 SVID9 SVID8 2Eh SMID R SMID7 SMID6 SMID5 SMID4 SMID3 SMID2 SMID1 SMID0 2Fh R SMID15 SMID14 SMID13 SM ID12 SMID11 SMID10 SMID9 SMID8 30h BMAR R 0 0 0 0 0 0 0 BROMEN W - - - - - - - BROMEN 31h R BMAR15 BMAR14 BMAR13 BMAR12 BMAR11 0 0 0 W BMAR15 BMAR14 BMAR13 BMAR12 BMAR11 - - - 32h RW BMAR23 BMAR22 BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16 33h RW BMAR31 BMAR30 BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24 34h Cap_Ptr R 0 1 0 0 0 0 0 0 35h- 3Bh RESERVED 3Ch ILR RW IRL7 ILR6 ILR5 ILR4 ILR3 ILR2 ILR1 ILR0 3Dh IPR R 0 0 0 0 0 0 0 1 3Eh MNGNT R 0 0 0 0 0 0 0 0

Integrated Gigabit Ethernet Controller for PCI Express 29 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 3Fh MXLAT R 0 0 0 0 0 0 0 0 40h PMID R 0 0 0 0 0 0 0 1 41h NextPtr R 0 1 0 0 1 0 0 0 42h R Aux_I_b1 Aux_I_b0 DSI Reserved PMECLK Version 43h PMC R PME_D3 cold PME_D3 hot PME_D2 PME_D1 PME_D0 D2 D1 Aux_I_b2 R 0 0 0 0 0 0 Power State 44h W - - - - - - Power State R PME_Status - - - - - - PME_En 45h PMCSR W PME_Status - - - - - - PME_En 46-4 Reserved 48h VPDID R 0 0 0 0 0 0 1 1 49h NextPtr R 0 1 0 1 0 0 0 0 4Ah Flag VPD Address RW VPDADDR VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD 4Bh RW Flag VPDADDR VPDADD R13 VPDADD R12 VPDADD R11 VPDADD R10 VPDADD VPDADD 4Ch RW Data7 Data6 Data5 Da ta4 Data3 Data2 Data1 Data0 4Dh RW Data15 Data14 Data13 Da ta12 Data11 Data10 Data9 Data8 4Eh RW Data23 Data22 Data21 Da ta20 Data19 Data18 Data17 Data16 4Fh VPD Data RW Data31 Data30 Data29 Data 28 Data27 Data26 Data25 Data24 50h MSIID R 0 0 0 0 0 1 0 1 51h NextPtr R 0 1 1 0 0 0 0 0 R 64-bit Address Capable Multiple Message Enable 0 0 1 MSI Enable 52h W - Multiple Message Enable - - 1 MSI Enable 53h Message Control Reserved. Always return 0 54h- 57h Message Address Low RW 64-bit Interrupt Message Address Low 58h- 5Bh Message Address High RW 64-bit Interrupt Message Address High 5Ch- 5Dh Message Data RW 16-bit Message Data 5E-5 Fh RESERVED 60h PCIEID R 0 0 0 1 0 0 0 0 61h NextPtr R 1 0 0 0 0 1 0 0 R 0 0 0 Legacy 0 0 0 1 62h- 63h PCIE Cap. R 0 0 0 0 0 0 0 0 R L0s_acpt_ latency[1] L0s_acpt_ latency[0] Entend_ tag_ support 0 0 Max_payload_size_support 64h- 67h Device Capability Register R 0 Pwr_ind_ present Attn_ind_ present Attn_ button_ present L1s_acpt_ latency[2] L1s_acpt_ latency[1] L1s_acpt_ latency[0] L0s_acpt_ latency[2]

Integrated Gigabit Ethernet Controller for PCI Express 30 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 RW Max_payload_size Relaxed_ ordering_ en Unsupport _rqst_rpt_ en Fatal_err_ rpt_en Non_fatal _err_rpt_ en Correct- able_err_ rpt_en 68h- 69h Device Control Register RW 0 Max_read_request_size No_snoop _en Auxpwr_ PM_en

0 Entend_

tag_en R 0 0 Transact_ ion_ pending AuxPwr_ det Upsupport _rqst_det Fatal_err_ det Non_fatal _err_det Correct- able_err_ det 6Ah W 0 0 - - Upsupport _rqst_det Fatal_err_ det Non_fatal _err_det Correcta- ble_err_ det 6Bh Device Status Register R 0 0 0 0 0 0 0 0 6Ch R 0 0 0 1 0 0 0 1 6Dh R L1_exit_ lat[0] L0s_exit_ lat[2] L0s_exit_ lat[1] L0s_exit_ lat[0] ASPM_support 0 0 6Eh R 0 0 0 0 0 0 L1_exit_ lat[2] L1_exit_ lat[1]0 6Fh Link Capability Register R 0 0 0 0 0 0 0 0 R Extended_ sync Common_ clock 0 0 0 0 ASPM_control 70h W Extended_ sync Common_ clock 0 0 0 0 ASPM_control 71h Link Control Register R 0 0 0 0 0 0 0 0 72h R 0 0 0 1 0 0 0 1 73h Link Status Register R 0 0 0 Slot_clock _cfg 0 0 0 0 74h- 83h Reserved 84h SpecificID R 0 0 0 0 1 0 0 1 85h NextPtr R 0 0 0 0 0 0 0 0 86h Byte_Len R 0 1 0 0 1 1 0 0 87h Version R 0 0 0 0 0 0 0 1 88h R 0 0 0 0 0 0 0 1 89h Receive Capability R 0 0 0 1 1 1 0 0 8Ah R 0 0 0 0 0 0 0 0 8Bh Receive Control R 0 0 0 0 0 0 0 0 8Ch- 8Eh Error Mask register RW RX_Error_mask 8Fh ROM BAR Mask R 0 0 ROM_BAR_MASK 90h R 0 0 0 0 1 0 0 0 91h R 0 0 1 0 0 0 0 0 92h R 1 0 0 0 0 0 0 0 93h BAR MASK Register R 0 0 0 0 0 0 0 0 94h R PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0] 95h Allocated Posted R PH[3] PH[2] PH[1] PH[0] PD [11] PD[10] PD[9] PD[8]

Integrated Gigabit Ethernet Controller for PCI Express 31 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 96h R 0 0 0 0 PH[7] PH[6] PH[5] PH[4] 97h Credit R 0 0 0 0 0 0 0 0 98h R ND[7] ND[6] ND[5] ND[4] ND[3] ND[2] ND[1] ND[0] 99h R NH[3] NH[2] NH[1] NH[0] ND[11] ND[10] ND[9] ND[8] 9Ah R 0 0 0 0 NH[7] NH[6] NH[5] NH[4] 9Bh Allocated Nonposted Credit R 0 0 0 0 0 0 0 0 9Ch R CPLD[7] CPLD[6] CPLD[5] CPLD [4] CPLD[3] CPLD[2] CPLD[1] CPLD[0] 9Dh R 0 0 0 0 CPLD[11] CPLD[10] CPLD[9] CPLD[8] 9Eh R 0 0 0 0 0 0 0 0 9Fh R 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 1 0 A0h- A1h Transmit Capability R 0 0 1 0 1 0 0 0 R 1 1 1 1 1 1 1 1 A2h- A3h Transmit Control R 0 0 0 0 0 0 0 1 A4h R Tag[7] Tag[6] Tag[5] Tag[4] Tag[3] Tag[2] Tag[1] Tag[0] A5h R 0 0 Class[2] Class[1] Cl ass[0] Tag[10] Tag[9] Tag[8] A6h R 0 0 0 0 0 0 0 0 R Txer_flag Txer[4] Txer[3] Txer[2] Txer[1] Txer[0] 0 0 A7h Transmit First Error Report W Txer_flag Txer[4] Txer[3] Txer[2] Txer[1] Txer[0] 0 0 A8h- A9h Transmit Buffer Top R TX_buffer_address AAh -AB h Reserved ACh R 0 0 0 0 0 0 1 1 ADh Aux Capability R 0 0 0 0 0 0 0 0 AEh R 0 0 0 0 0 0 1 1 AFh Aux Control R 0 0 0 0 0 0 0 0 B0h RW Replay[7] Replay[6] Replay[5] Replay [4] Replay[3] Replay[2] Replay[1] Replay[0] B1h RW Ack_Nack [5] Ack_Nack [4] Ack_Nack [3] Ack_Nack [2] Ack_Nack [1] Ack_Nack [0] Repaly[9] Replay[8] B2h RW Flow_ctrl [3] Flow_ctrl [2] Flow_ctrl [1] Flow_ctrl [0] Ack_Nack [9] Ack_Nack [8] Ack_Nack [7] Ack_Nack [6] B3h Link Timer RW Receive_ flow_ctrl[1] Receive_ flow_ctrl[0] Flow_ctrl [9] Flow_ctrl [8] Flow_ctrl [7] Flow_ctrl [6] Flow_ctrl [5] Flow_ctrl [4] B4h R Common_N_FTS B5h R 0 0 Common_L1_exit Common_L0s_exit B6h R Non_common_N_FTS B7h PM Exit Control R 0 0 Non_common_L1_exit Non_common_L0s_exit B8h RW L1_idle_time_required B9h RW L0s_idle_time_required BAh Active PM Timer RW 0 0 0 0 0 0 L1_scale L0s_scale BBh R Attn_ind_state Power_ind_state 0 0 0 0 BCh- BFh R Aux Header Log 1 C0h- C3h Aux Header Log R Aux Header Log 2

Integrated Gigabit Ethernet Controller for PCI Express 32 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 C4h- C7h R Aux Header Log 3 C8h- CBh R Aux Header Log 4 CCh R Error type Indicator CDh CFh Aux Error Type/ Report R Reserved D0h- FFh Reserved 100h R 0 0 0 0 0 0 0 1 101h Adv Error Report ID R 0 0 0 0 0 0 0 0 102h R 1 1 0 0 0 0 0 1 103h Offset / Version R 0 0 0 1 0 0 1 0 104h RW 0 0 0 Data_Link _err_st 0 0 0 0 105h RW CPL_abort_ st CPL_ timeout_st FlowCtrl_ err_st Poisoned_ TLP_st 0 0 0 0 106h RW 0 0 0 Unsupport _rqst_st

0 Malform_

TLP_st Rx_over- flow_st Unexpect_ CPL_st 107h Uncorrect- able Error Status R 0 0 0 0 0 0 0 0 108h RW 0 0 0 Data_Link _err_msk 0 0 0 0 109h RW CPL_abort_ msk CPL_time- out_msk FlowCtrl_ err_msk Poisoned_ TLP_msk 0 0 0 0 10A h RW 0 0 0 Unsupport _rqst_msk TLP_msk Rx_over- flow_msk Unexpect_ CPL_msk 10Bh Uncorrect- able Error Mask R 0 0 0 0 0 0 0 0 10Ch RW 0 0 0 Data_Link _err_sev 0 0 0 1 10D h RW CPL_abort_ sev CPL_time- out _sev FlowCtrl_ err_sev Poisoned_ TLP_sev 0 0 0 0 10Eh RW 0 0 0 Unsupport _rqst_sev TLP_sev Rx_overfl ow_sev Unexpect_ CPL_sev 10Fh Uncorrect- able Error Severity R 0 0 0 0 0 0 0 0 110h RW Bad_DLLP _st Bad_TLP_ st 0 0 0 0 0 Receive_ err_st 111h RW 0 0 0 Replay_ti meout_st 0 0 0 Replay_ro llover_st 112h -113 h Correct- able Error Status R Reserved 114h RW Bad_DLLP _msk Bad_TLP_ msk 0 0 0 0 0 Receive_ err_msk 115h RW 0 0 0 Replay_ timeout_ msk 0 0 0 Replay_ rollover_ msk 116h -117 h Correct- able Error Mask R Reserved 118h Capability R 0 0 0 First_error_pointer

Integrated Gigabit Ethernet Controller for PCI Express 33 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 119h -11B h / Control Reserved 11Ch -12B h Header Log R Header Log Register 12Ch R 0 0 0 0 0 0 1 0 12D h VC ID R 0 0 0 0 0 0 0 0 12Eh R 1 0 0 0 0 0 0 1 12Fh Offset / Version R 0 0 0 1 0 1 0 0 130h R 0 0 0 0 0 0 0 0 131h R 0 0 0 0 0 0 0 0 132h -133 h Port VC capability Reg1 R Reserved 134h -13F H Reserved 140h RW TC_VC [7] TC_VC [6] TC_VC [5] TC_VC [4] TC_VC [3] TC_VC [2] TC_VC [1] 141h R 0 0 0 0 0 0 0 0 142h R 0 0 0 0 0 0 0 0 143h VC Resource Control Reg0 R 1 0 0 0 0 0 0 0 144h -145 h R Reserved 146h R 0 0 0 0 0 0 Nego_ pending 147h VC Resource Status Reg0 R 0 0 0 0 0 0 0 0 148h R 0 0 0 0 0 0 1 1 149h Serial No ID R 0 0 0 0 0 0 0 0 R 0 1 0 0 0 0 0 1 14A h-14 Bh Offset / Version R 0 0 0 1 0 1 0 1 14Ch -153 h Serial number R Serial Number[63:0] 154h R 0 0 0 0 0 1 0 0 155h Power Budget ID R 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 1 156h -157 h Offset / Version R 0 0 0 0 0 0 0 0 158h RW Data Select 159h -15B h Data select Reserved 15Ch R Base power 15D h R Type[0] PM_state PM_substate Data_scale 15Eh Data R 0 0 0 Power_rail Type[2] Type[1]

functions. The functions of the RTL8111B/RTL8168B's configuration space are described below. Semiconductor's PCI Vendor ID. DID: Device ID. This field will be set to a value corresponding to PCI Device ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 8129h. to generate and respond to PCI cycles. Table 39. Command Register in PCI Configuration Space

10 IntDisable Interrupt Disable:

This Bit enables/disables the RTL8111B/RTL8168B to assert Int# signal. 1: Force RTL8111B/RTL8168B not to assert Int# signal. 0: Enable RTL8111B/RTL8168B to assert Int# signal. It’s also the default value after PCI reset. 9 FBTBEN Fast Back-To-Back Enable: Does not apply to PCI Express. Must be hardwired to 0. or through the PCI-Express specific bits in the Device Control register. 7 ADSTEP Address/Data Stepping: Does not apply to PCI Express. Must be hardwired to 0.

6 PERRSP Parity Error Response: In the Status register, the Master Data Parity Error bit is set by a

• If the Requester receives a poisoned Completion.
• If the Requester poisons a write request.

If the Parity Error Response bit is cleared, the Master Data Parity Error status bit is never set. 5 VGASNOOP VGA palette SNOOP: Does not apply to PCI Express. Must be hardwired to 0.

3 SCYCEN Special Cycle Enable: Does not apply to PCI Express. Must be hardwired to 0.

2 BMEN Bus Master Enable: When set to 1, the RTL8111B/RTL8168B is capable of acting as a PCI bus

master. When set to 0, it is prohibited from acting as a bus master. For normal operations, this bit must be set by the system BIOS.

1 MEMEN Memory Space Access: When set to 1, the RTL8111B/RTL8168B responds to memory space

accesses. When set to 0, the RTL8111B/RTL8168B ignores memory space accesses. 0 IOEN I/O Space Access: When set to 1, th e RTL8111B/RTL8168B responds to IO space accesses. When set to 0, the RTL8111B/RTL8168B ignores I/O space accesses. Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. Table 40. Status Register in PCI Config Space

15 DPERR Detected Parity Error: This bit is set by the RTL8111B/RTL8168B whenever it receives a Poisoned

TLP, regardless of the state the Parity Error Enable bit. Default value of this field is 0.

14 SSERR Signaled System Error: This bit is set when the RTL8111B/RTL8168B sends an ERR_FATAL or

13 RMABT Received Master Abort: This bit is set wh en the RTL8111B/RTL8168B receives a Completion with

Unsupported Request Completion Status. Default value of this field is 0.

12 RTABT Received Target Abort: This bit is set wh en the RTL8111B/RTL8168B receives a Completion with

Completer Abort Completion Status. Default value of this field is 0.

11 STABT Signaled Target Abort: This bit is set when the RTL8111B/RTL8168B completes a Request using

Completer Abort Completion Status. Default value of this field is 0. 10-9 DST1-0 Device Select Timing: Does not apply to PCI Express. Must be hardwired to 0. If the Parity Error Enable bit is cleared, this bit is never set. Default value of this field is 0. 7 FBBC Fast Back-To-Back Capable: Does not apply to PCI Express. Must be hardwired to 0. 5 66MHz 66MHz Capable: Does not apply to PCI Express. Must be hardwired to 0. devices are required to implement the PCI Express capability structure, this bit must be set to 1.

Integrated Gigabit Ethernet Controller for PCI Express 36 Track ID: JATR-1076-21 Rev. 1.0 Bit Symbol Description

3 IntSt Interrupt Status:

This bit reflects the interrupt status of RTL8111B/RTL8168B. Unlike ISR bits, this bit is a read-only bit and can’t be reset by writing a 1 to this bit. The only way to reset this bit is to reset ISR register. The setting of the ‘Interrupt Disable’ bit in Command Register has no effect on the state of the ‘Interrupt Status’ bit. Only when the ‘Interrupt Disable’ bit is a 0 and the ‘Interrupt Status’ bit is a 1, will the RTL8111B/RTL8168B’s Int# signal be asserted. 0 - Reserved RID: Revision ID Register The Revision ID register is an 8-bit register th at specifies the RTL8111B/RTL8168B controller revision number. PIFR: Programming Interface Register The programming interface register is an 8-bit regist er that identifies the programming interface of the RTL8111B/RTL8168B controller. The PCI specification reversion 2.1 doesn't define any other specific value for network devices. So PIFR = 00h. SCR: Sub-Class Register The Sub-class register is an 8-bit register th at identifies the functi on of the RTL8111B/RTL8168B. SCR=00h indicates that the RTL8111B/RTL8168B is an Ethernet controller. BCR: Base-Class Register The Base-class register is an 8-bit register that broadly classifies the function of the RTL8111B/RTL8168B. BCR = 02h indicates that the RTL8111B/RTL8168B is a network controller. CLS: Cache Line Size This field is implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no impact on any PCI Express device functionality. LTR: Latency Timer Register This register is also referred to as primary latenc y timer for Type 1 Configuration Space header devices. The primary/master latency timer does not apply to PCI Express. This register must be hardwired to 0. HTR: Header Type Register Reads will return a 0, writes are ignored.

Reads will return a 0, writes are ignored. Table 41. IOAR Register in PCI Config Space 31-8 IOAR31-8 BASE IO Address: This is set by software to the Base IO address for the operational register map. RTL8111B/RTL8168B requires 256 bytes of IO space. RTL8111B/RTL8168B's register with memory access. Table 42. MEMAR Register in PCI Config Space 31-7 MEMAR Base Memory Address: This is set by software to the base address for the operational register map. 3 MEMPF Memory Prefetchable: Read only. Set to 0 by the RTL8111B/RTL8168B. the base register is 64-bits wide and can be located anywhere in 264 memory space. capable of being mapped into memory space. Realtek Semiconductor's PCI Subsystem Vendor ID. EEPROM. If there is no EEPROM, this field will default to a value of 8129h. RTL8111B/RTL8168B's registers with memory access.

Table 43. BMAR Register in PCI Configuration Space 0 BROMEN Boot ROM Enable: This is used by th e PCI BIOS to enable accesses to Boot ROM. by the RTL8111B/RTL8168B. The RTL8111B/RTL8168B uses INTA interrupt pin. Read only. IPR = 01h. read-only and must be hardwired to 0. Table 44. Default Values After EEPROM Autoload

Integrated Gigabit Ethernet Controller for PCI Express 39 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0Bh BCR R 0 0 0 0 0 0 1 0 0Ch CLS R 0 0 0 0 0 0 0 0 0Dh LTR R 0 0 0 0 0 0 0 0 0Eh HTR R 0 0 0 0 0 0 0 0 0Fh BIST R 0 0 0 0 0 0 0 0 10h IOAR R 0 0 0 0 0 0 0 IOIN 11h R 0 0 0 0 0 0 0 0 12h R 0 0 0 0 0 0 0 0 13h R 0 0 0 0 0 0 0 0 14h- 17h Reserved 18h R 0 0 0 0 MEM64 0 0 0 19h R 0 0 0 0 0 0 0 0 1Ah R 0 0 0 0 0 0 0 0 1Bh R 0 0 0 0 0 0 0 0 1Ch R 0 0 0 0 0 0 0 0 1Dh R 0 0 0 0 0 0 0 0 1Eh R 0 0 0 0 0 0 0 0 1Fh MEM 64 BAR R 0 0 0 0 0 0 0 0 20h- 27h RESERVED 28h- 2Bh CISPtr 32’h0000_0000 2Ch SVID R SVID7 SVID6 SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 2Dh R SVID15 SVID14 SVID13 SVID12 SVID11 SVID1 SVID9 SVID8 2Eh SMID R SMID7 SMID6 SMID5 SMID4 SMID3 SMID2 SMID1 SMID0 2Fh R SMID15 SMID14 SMID13 SMID12 SMID11 SMID1 SMID9 SMID8 30h BMAR R 0 0 0 0 0 0 0 BROME N 31h R 0 0 0 0 0 0 0 0 32h R 0 0 0 0 0 0 0 0 33h R 0 0 0 0 0 0 0 0 34h Cap_Ptr R 0 1 0 0 0 0 0 0 35h- 3Bh RESERVED 3Ch ILR R 0 0 0 0 0 0 0 0 3Dh IPR R 0 0 0 0 0 0 0 1 3Eh MNGNT R 0 0 0 0 0 0 0 0 3Fh MXLAT R 0 0 0 0 0 0 0 0 40h PMID R 0 0 0 0 0 0 0 1 41h NextPtr R 0 1 0 0 1 0 0 0 42h PMC R Aux_I_b1 Aux_I_b0 DSI Reserved PMECLK Version

Integrated Gigabit Ethernet Controller for PCI Express 40 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 43h R PME_ D3cold PME_ D3hot PME_D2 PME_D1 PME_D0 D2 D1 Aux_I_b2 44h R 0 0 0 0 0 0 2’h0 45h PMCSR R 0 0 0 0 0 0 0 0 46-4 Reserved 48h VPDID R 0 0 0 0 0 0 1 1 49h NextPtr R 0 1 0 1 0 0 0 0 4Ah Flag VPD Address R 0 0 0 0 0 0 0 0 4Bh R 0 0 0 0 0 0 0 0 4Ch R 0 0 0 0 0 0 0 0 4Dh R 0 0 0 0 0 0 0 0 4Eh R 0 0 0 0 0 0 0 0 4Fh VPD Data R 0 0 0 0 0 0 0 0 50h MSIID R 0 0 0 0 0 1 0 1 51h NextPtr R 0 1 1 0 0 0 0 0 52h R 1 3’h0 0 0 1 0 53h Message Control Reserved. Always return 0 54h- 57h Message Address Low R 32’h0 58h- 5Bh Message Address High R 32’h0 5Ch -5D h Message Data R 16'0 5E-5 Fh RESERVED 60h PCIEID R 0 0 0 1 0 0 0 0 61h NextPtr R 1 0 0 0 0 1 0 0 R 0 0 0 Legacy 0 0 0 1 62h- 63h PCIE Cap. R 0 0 0 0 0 0 0 0 R L0s_acpt_ latency[1] L0s_acpt_ latency[0] Entend_ tag_ support 0 0 Max_payload_size_support R 0 Pwr_ind_ present Attn_ind _present Attn_ button_ present L1s_ acpt_ latency [2] L1s_ acpt_ latency [1] L1s_ acpt_ latency [0] L0s_ acpt_ latency [2] R 0 0 0 0 0 0 0 0 64h- 67h Device Capability Register R 0 0 0 0 0 0 0 0 R 3’h0 1 0 0 0 0 68h- 69h Device Control Register R 0 3’h2 1 0 0 0

Integrated Gigabit Ethernet Controller for PCI Express 41 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 6Ah R 0 0 AuxPwr_ det 0 0 0 0 6Bh Device Status Register R 0 0 0 0 0 0 0 0 6Ch R 0 0 0 1 0 0 0 1 6Dh R L1_exit_ lat[0] L0s_exit_ lat[2] L0s_exit _lat[1] L0s_exit _lat[0] ASPM_support 0 0 6Eh R 0 0 0 0 0 0 L1_exit_ lat[2] L1_exit_ lat[1]0 6Fh Link Capability Register R 0 0 0 0 0 0 0 0 70h R Extended_ sync Common_ clock 0 0 0 0 ASPM_control 71h Link Control Register R 0 0 0 0 0 0 0 0 72h R 0 0 0 1 0 0 0 1 73h Link Status Register R 0 0 0 Slot_ clock_cfg 0 0 0 0 74h- 83h Reserved 84h SpecificID R 0 0 0 0 1 0 0 1 85h NextPtr R 0 0 0 0 0 0 0 0 86h Byte_Len R 0 1 0 0 1 1 0 0 87h Version R 0 0 0 0 0 0 0 1 88h R 0 0 0 0 0 0 0 1 89h Receive Capability R 0 0 0 1 1 1 0 0 8Ah R 0 0 0 0 0 0 0 0 8Bh Receive Control R 0 0 0 0 0 0 0 0 8Ch -8Eh Error Mask Register R 24’hFF_FFFB 8Fh ROM BAR Mask R 0 0 8’hE 90h R 0 0 0 0 1 0 0 0 91h R 0 0 1 0 0 0 0 0 92h R 1 0 0 0 0 0 0 0 93h BAR MASK Register R 0 0 0 0 0 0 0 0 94h R PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0] 95h R PH[3] PH[2] PH[1] PH[0] PD[11] PD[10] PD[9] PD[8] 96h R 0 0 0 0 PH[7] PH[6] PH[5] PH[4] 97h Allocated Posted Credit R 0 0 0 0 0 0 0 0 98h R ND[7] ND[6] ND[5] ND[4] ND[3] ND[2] ND[1] ND[0] 99h R NH[3] NH[2] NH[1] NH[0] ND[11] ND[10] ND[9] ND[8] 9Ah R 0 0 0 0 NH[7] NH[6] NH[5] NH[4] 9Bh Allocated Non- posted Credit R 0 0 0 0 0 0 0 0 9Ch R CPLD [7] CPLD [6] CPLD [5] CPLD [4] CPLD [3] CPLD [2] CPLD [1] CPLD [0]

Integrated Gigabit Ethernet Controller for PCI Express 42 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 9Dh R 0 0 0 0 CPLD [11] CPLD [10] CPLD [9] CPLD[8] 9Eh R 0 0 0 0 0 0 0 0 9Fh R 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 1 0 A0h -A1 h Transmit Capability R 0 0 1 0 1 0 0 0 R 1 1 1 1 1 1 1 1 A2h -A3 h Transmit Control R 0 0 0 0 0 0 0 1 A4h R 0 0 0 0 0 0 0 0 A5h R 0 0 0 0 0 0 0 0 A6h R 0 0 0 0 0 0 0 0 A7h Transmit First Error Report R 0 0 0 0 0 0 0 0 A8h -A9 h Transmit Buffer Top R 16’h0800 AAh -AB h Reserved ACh R 0 0 0 0 0 0 1 1 ADh Aux Capability R 0 0 0 0 0 0 0 0 AEh R 0 0 0 0 0 0 1 1 AFh Aux Control R 0 0 0 0 0 0 0 0 B0h R 0 0 0 0 0 0 0 0 B1h R 0 0 0 0 0 0 0 0 B2h R 0 0 0 0 0 0 0 0 B3h Link Timer R 0 0 0 0 0 0 0 0 B4h R Common_N_FTS B5h R 0 0 Common_L1_exit Common_L0s_exit B6h R Non_common_N_FTS B7h PM Exit Control R 0 0 Non_common_L1_exit Non_common_L0s_exit B8h RW L1_idle_time_required B9h RW L0s_idle_time_required BAh Active PM Timer R 0 0 0 0 0 0 L1_scale L0s_scale BBh R 2’h0 2’h0 0 0 0 0 BCh -BF h R 32’h0 C0h -C3 h R 32’h0 C4h -C7 h Aux Header Log R 32’h0

Integrated Gigabit Ethernet Controller for PCI Express 43 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 C8h -CB h R 32’h0 CCh R 8’h0 CDh CFh Aux Error Type/ Report R Reserved D0h -FFh Reserved 100 h R 0 0 0 0 0 0 0 1 101 h Adv Error Report ID R 0 0 0 0 0 0 0 0 102 h R 1 1 0 0 0 0 0 1 103 h Offset / Version R 0 0 0 1 0 0 1 0 104 h R 0 0 0 0 0 0 0 0 105 h R 0 0 0 0 0 0 0 0 106 h R 0 0 0 0 0 0 0 0 107 h Uncorrect -able Error Status R 0 0 0 0 0 0 0 0 108 h R 0 0 0 0 0 0 0 0 109 h R 0 0 0 0 0 0 0 0 10A h R 0 0 0 0 0 0 0 0 10B h Uncorrect -able Error Mask R 0 0 0 0 0 0 0 0 10C h R 0 0 0 1 0 0 0 1 10D h R 0 0 1 0 0 0 0 0 10E h R 0 0 0 0 0 1 1 0 10F h Uncorrect -able Error Severity R 0 0 0 0 0 0 0 0 110 h R 0 0 0 0 0 0 0 0 111 h R 0 0 0 0 0 0 0 0 112 h-11 Correct- able Error Status R Reserved

Integrated Gigabit Ethernet Controller for PCI Express 44 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 114 h R 0 0 0 0 0 0 0 0 115 h R 0 0 0 0 0 0 0 0 116 h-11 Correct- able Error Mask R Reserved 118 h R 0 0 0 5’h0 119 h-11 Bh Capability / Control Reserved 11C h-12 Bh Header Log R All 0’s 12C h R 0 0 0 0 0 0 1 0 12D h VC ID R 0 0 0 0 0 0 0 0 12E h R 1 0 0 0 0 0 0 1 12F h Offset / Version R 0 0 0 1 0 1 0 0 130 h R 0 0 0 0 0 0 0 0 131 h R 0 0 0 0 0 0 0 0 132 h-13 Port VC capability Reg1 R Reserved 134 h-13 FH Reserved 140 h R 1 1 1 1 1 1 1 1 141 h R 0 0 0 0 0 0 0 0 142 h R 0 0 0 0 0 0 0 0 143 h VC Resource Control Reg0 R 1 0 0 0 0 0 0 0 144 h-14 R Reserved 146 h R 0 0 0 0 0 0 0 0 147 h VC Resource Status Reg0 R 0 0 0 0 0 0 0 0

Integrated Gigabit Ethernet Controller for PCI Express 45 Track ID: JATR-1076-21 Rev. 1.0 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 148 h R 0 0 0 0 0 0 1 1 149 h Serial No ID R 0 0 0 0 0 0 0 0 R 0 1 0 0 0 0 0 1 14A h-14 Bh Offset / Version R 0 0 0 1 0 1 0 1 14C h-15 Serial number R Serial Number[63:0] 154 h R 0 0 0 0 0 1 0 0 155 h Power Budget ID R 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 1 156 h-15 Offset / Version R 0 0 0 0 0 0 0 0 158 h RW 8’h0 159 h-15 Bh Data select Reserved 15C h R 8’h0 15D h R 0 2’h0 3’h0 2’h0 15E h R 0 0 0 3’h0 0 0 15F h Data R 0 0 0 0 0 0 0 0 160 h R 0 0 0 0 0 0 0 0 161 h-16 Capability Reserved 164 h-FF Fh Reserved

Integrated Gigabit Ethernet Controller for PCI Express 46 Track ID: JATR-1076-21 Rev. 1.0 5.5. Power Management Function The RTL8111B/RTL8168B complies with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class Power Management Refere nce Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8111B/RTL8168B can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via a PCI Express Power Management Event (PME) Message, Beacon, or LANWAKEB pin when such a packet or event occurs. Then the system can be restored to a normal state to process incoming jobs. When the RTL8111B/RTL8168B is in power down mode (D1 ~ D3):

• The Rx state machine is stopped. The RTL8111B/RTL8168B monitors the network for wakeup events such as a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8111B/RTL8168B will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx on-chip buffer.
• The on-chip buffer status and packets that have already been received into the Rx on-chip buffer before entering power down mode are held by the RTL8111B/RTL8168B.
• Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held.
• After being restored to D0 state, the RTL8111B/RTL8168B transmits data that was not moved into the Tx on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI configuration space depend on the existence of Aux power (bit15, PMC) = 1. If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0 in binary. Example: If EEPROM D3c_support_PME = 1:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 F7, then PCI PMC = C2 F7)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 F7, then PCI PMC = 02 76) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C2 F7 (Realtek EEPROM default value). If EEPROM D3c_support_PME = 0:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 77, then PCI PMC = C2 77)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 77, then PCI PMC = 02 76)

Integrated Gigabit Ethernet Controller for PCI Express 47 Track ID: JATR-1076-21 Rev. 1.0 In the above case, if wakeup support is not desired wh en main power is off, it is suggested that the EEPROM PMC be set to 02 76. Link Wakeup occurs only when the following conditions are met:

• The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANW AKEB) can be asserted in the current power state. Magic Packet Wakeup occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8111B/RTL8168B, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8111B/RTL8168B adapter.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANW AKEB) can be asserted in the current power state.
• The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid (Fast) Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame is acceptable to the RTL8111B/RTL8168B, e.g., a broadcast, multicast, or unicast address to the current RTL8111B/RTL8168B adapter.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 16-bit CRCA of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8111B/RTL8168B is configured to allow direct packet wakeup, e.g., a broadcast, multicast, or unicast network packet. Note: 16-bit CRC: The RTL8111B/RTL8168B supports two normal wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). The corresponding wake-up method (message, beacon, or LANWAKEB) is asserted only when the following conditions are met:
• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8111B/RTL8168B may assert the corresponding wake-up method (message, beacon, or LANW AKEB) in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wakeup Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8111B/RTL8168B to stop asserting the corresponding wake-up method

Integrated Gigabit Ethernet Controller for PCI Express 48 Track ID: JATR-1076-21 Rev. 1.0 (message, beacon, or LANW AKEB) (if enabled). When the device is in power down mode, e.g. D1-D3, the IO, MEM, and Boot ROM spaces are all disabled. After a PERSTB assertion, the device’s power state is restored to D0 automatically if the original power state was D3cold. There is no hardware delay at the device’s power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto loaded from EEPROM. The setting may be changed from the EEPROM, if required). 5.6. Vital Product Data (VPD) Bit 31 of the Vital Product Da ta (VPD) capability structure in the RTL8111B/RTL8168B’s PCI Configuration Space is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data between the VPD data register and the 93C46/93C56 has completed or not. Write VPD register: (write data to the 93C46/93C56) Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When the flag bit is reset to 0 by the RTL8111B/RTL8168B, th e VPD data (4 bytes per VPD access) has been transferred from the VPD data register to EEPROM. Read VPD register: (read data from the 93C46/93C56) Reset the flag bit to 0 at the same time the VPD a ddress is written to retrieve VPD data from EEPROM. When the flag bit is set to 1 by the RTL8111B/RTL8168B, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data register. Note1: Refer to the PCI 2.2 Specifications for further information. Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.2 Specifications. VPD data is always consecutive 4-byte data starting from the VPD address specified. Note3: Realtek reserves offset 40h to 7Fh in EEPROM, mainly for VPD data to be stored. Note4: The VPD function of the RTL8111B/RTL8168B is designed to be able to access the full range of the 93C46/93C56 EEPROM.

Figure 1. Message Signaled Interrupt (MSI) when the DAC function is enabled.

Table 45. Message Control

7 RO 64-bit address capable 1: DAC is enabled

auto-load to the DAC bit in the C+CR register. (equal to or less than the number of requested messages/vectors). This field after PCI reset is ‘000’.

110 Reserved

111 Reserved

RTL8111B/RTL8168B requested vectors. one vector is used at a time, the other is used as a backup.

0 RW MSI Enable 1: Enable MSI (Also the INTx pin is disabled automatically, MSI

Table 46. Message Address 31::02 RW Message Address System-specified message/vector address. Low DWORD aligned address for MSI memory write transaction. AD[1::0] are always ‘00’ during the address phase. 01::00 RO Reserved Always return ‘00’.

Table 47. Message Upper Address 31::00 RW Message Upper Address System-specified message/vector upper address. Upper 32 bits of a 64-bit message/vector address. Table 48. Message Data phase of the memory write transaction.

Integrated Gigabit Ethernet Controller for PCI Express 52 Track ID: JATR-1076-21 Rev. 1.0 6. Functional Description 6.1. Transmit & Receive Operations The RTL8111B/RTL8168B supports a descriptor-based buffer management that significantly reduces host CPU utilization and is highly suitable for server applications. The new buffer management algorithm provides Microsoft Large-Send offload, IP check sum offload, TCP checksum offload, UDP checksum offload, and IEEE802.1P, 802.1Q VLAN tagging capabilities. The RTL8111B/RTL8168B supports up to 1024 consecutive descriptors in memory (separated transmit and receive), which means there might be 3 descriptor rings, one high priority transmit descriptor ring, a normal priority transmit descriptor ring, and a receive descriptor ring. Each descriptor ring may consist of up to 1024 4-double-word consecutive descriptors. Each descriptor array consists of 4 consecutive double-word descriptors. The start address of each descriptor group should be 256-byte alignment. Software must pre-allocate enough buffers and configur e all descriptor rings before transmitting and/or receiving packets. Descriptors can be chained to form a packet in both Tx and Rx. Padding: The RTL8111B/RTL8168B will automatically pad any packets less than 64 bytes (including 4 bytes CRC) to 64-byte long (including 4-byte CRC) before transmitting that packet onto network medium. The padded data are all 0x00. If a packet consists of 2 or more descriptors, then each of the descriptors in command mode should have the same configuration, except EOR, FS, LS bits. 6.1.1. Transmit This portion implements the transmit portion of IEEE-802.3 Media Access Control. The Tx MAC retrieves packet data from the Tx Buffer Manager and sends it out through the transmit physical layer interface. Additionally, the Tx MAC provides MIB control information for transmit packets. The Tx MAC has the capability to insert a 4-byte VLAN tag in the transmit packet. If Tx VLAN Tag insertion is enabled, the MAC will insert the 4 bytes , as specified in the VTAG register, following the source and destination addresses of the packet. Th e VLAN tag insertion can be enabled on a global or per-packet basis. When operating in Gigabyte mode, the RTL8111B/RTL8168B operates in full duplex mode only. The Tx MAC supports task offloading of IP, TCP, and UDP checksum generation. It is capable of calculating the checksums and inserting them into the packet. The checksum calculation can be enabled on a global or per-packet basis. The following information describes the structure of the Tx descriptor, depending on different states in each Tx descriptor. The minimum Tx buffer should be at least of the size of 1 byte.

Table 49. Large-Send Task Offload Tx Command Descriptor-1 Table 50. Large-Send Task Offload Tx Command Descriptor-2 bit when the relative buffer data is transmitted. In this case, OWN=1. 0 30 EOR End of Descriptor Ring. This bit, when set, indicates that this is the last descriptor in descriptor ring. 0 29 FS First Segment Descriptor. this descriptor is pointing to the first segment of the packet. 0 28 LS Last Segment Descriptor. is pointing to the last segment of the packet. the NIC to offload the Large send operation. In this case, LGSEN=1.

Integrated Gigabit Ethernet Controller for PCI Express 54 Track ID: JATR-1076-21 Rev. 1.0 Offset# Bit# Symbol Description 0 26-16 MSS Maximum Segmentation Size. An 11-bit long command field, the driver passes Large-Send MSS to the NIC through this field. 0 15-0 Frame_Length Transmit Frame Length. This field indicates the Tx frame length in the TX buffer, in bytes, to be transmitted. The maximum Large-Send frame length supported is 16-1(64KB-1). 4 31-18 RSVD Reserved 4 17 TAGC VLAN Tag Control Bit. 1: Enable. 0: Disable. 1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating that this is a IEEE 802.1Q VLAN packet) is inserted after the source address, and 2 bytes are inserted after the tag protocol ID in the VLAN_TAG field of the transmit descriptor. 0: Packet remains unchanged when transmitting, i.e., the packet transmitted is the same as it was when passed down by the upper layer. 4 16 RSVD Reserved 4 15-0 VLAN_TAG The 2-byte VLAN_TAG contains information, from the upper layer, of user priority, canonical format indication, and VLAN ID. Please refer to IEEE 802.1Q for more VLAN tag information. VIDH: The high 4 bits of a 12-bit VLAN ID. VIDL: The low 8 bits of a 12-bit VLAN ID. PRIO: 3-bit 8-level priority. CFI: Canonical Format Indicator. 8 31-0 TxBuffL Low 32-bit address of transmit buffer 12 31-0 TxBuffH High 32-bit address of transmit buffer

transmitting, OWN=1, LGSEN=0, Tx command mode 1). Table 51. Normal Tx Command Descriptor-1 Table 52. Normal Tx Command Descriptor-2 bit when the relative buffer data is transmitted. In this case, OWN=1. 0 30 EOR End of Descriptor Ring. This bit, when set, indicates that this is the last descriptor in the descriptor ring. 0 29 FS First Segment Descriptor. this descriptor is pointing to the first segment of the packet. 0 28 LS Last Segment Descriptor. is pointing to the last segment of the packet. the NIC to offload the Large send operation. In this case, LGSEN=1. 0 18 IPCS IP Checksum Offload.

Integrated Gigabit Ethernet Controller for PCI Express 56 Track ID: JATR-1076-21 Rev. 1.0 Offset# Bit# Symbol Description 0 17 UDPCS UDP Checksum Offload. A command bit. The driver sets this bit to ask the NIC to offload the UDP checksum. 0 16 TCPCS TCP Checksum Offload Enable: A command bit. The driver sets this bit to ask the NIC to offload the TCP checksum. 0 15-0 Frame_Length Transmit Frame Length: This field indicates the length of the TX buffer, in bytes, to be transmitted 4 31-18 RSVD Reserved 4 17 TAGC VLAN Tag Control Bit. 1: Enable. 0: Disable. 1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating that this is a IEEE 802.1Q VLAN packet) is inserted after the source address, and 2 bytes are inserted after the tag protocol ID in the VLAN_TAG field of the transmit descriptor. 0: Packet remains unchanged when transmitting. I.e., the packet transmitted is the same as it was when passed down by the upper layer. 4 16 RSVD Reserved 4 15-0 VLAN_TAG VLAN Tag. The 2-byte VLAN_TAG contains information from the upper layer, of user priority, canonical format indication, and VLAN ID. Refer to IEEE 802.1Q for more VLAN tag information. VIDH: The high 4 bits of a 12-bit VLAN ID. VIDL: The low 8 bits of a 12-bit VLAN ID. PRIO: 3-bit 8-level priority. CFI: Canonical Format Indicator. 8 31-0 TxBuffL Low 32-bit address of transmit buffer 12 31-0 TxBuffH High 32-bit address of transmit buffer

After having transmitted, the Tx descriptor turns into a Tx status descriptor. Table 53. Tx Status Descriptor-1 Table 54. Tx Status Descriptor-2 the data related to this descriptor. 4 17 TAGC VLAN Tag Control Bit: 1: Enable. 0: Disable. inserted after the tag protocol ID from VLAN_TAG field in transmit descriptor. same as it was passed down by the upper layer.

Integrated Gigabit Ethernet Controller for PCI Express 58 Track ID: JATR-1076-21 Rev. 1.0 Offset# Bit# Symbol Description 4 15-0 VLAN_TAG VLAN Tag: The 2-byte VLAN_TAG contains information from the upper layer, of user priority, canonical format indicator, and VLAN ID. Refer to IEEE 802.1Q for more VLAN tag information. VIDH: The high 4 bits of a 12-bit VLAN ID. VIDL: The low 8 bits of a 12-bit VLAN ID. PRIO: 3-bit 8-level priority. CFI: Canonical Format Indicator. 8 31-0 TxBuffL Low 32-bit address of transmit buffer 12 31-0 TxBuffH High 32-bit address of transmit buffer 6.1.2. Receive The receive portion implements the receive porti on of IEEE-802.3 Media Access Control. The Rx MAC retrieves packet data from the receive portion and sends it to the Rx Buffer Manager. Additionally, the Rx MAC provides MIB control information and packet address data for the Rx Filter. The Rx MAC can detect packets containing a 4-byte VLAN tag, and remove the VLAN tag from the received packet. If Rx VLAN Tag Removal is en abled, then the 4 bytes following the source and destination addresses will be stripped out. The VLAN status can be returned in the VLAN Tag field. The Rx MAC supports IP checksum verification. It can validate IP checksums as well as TCP and UDP checksums. Packets can be discarded based on detecting checksum errors. The following information describes what the Rx descriptor may look like, depending on different states in each Rx descriptor. Any Rx buffer pointed to by one of the Rx descriptors should be at least 8 bytes in length, and should be 8-byte alignment in memory. The length of each Rx buffer should be a multiple of 8 bytes.

Table 55. Rx Command Descriptor-1 Table 56. Rx Command Descriptor-2 driver. In this case, OWN=1. descriptor ring after this descriptor is used by packet reception. maximum value of this field is 0x1FF8, and bit2-0 and bit13 should always be 0. IEEE802.1Q VLAN TAG (0x8100) available packet.

the TAG value of this field in the Rx descriptor. VIDH: The high 4 bits of a 12-bit VLAN ID. VIDL: The low 8 bits of a 12-bit VLAN ID. PRIO: 3-bit 8-level priority. CFI: Canonical Format Indicator. lowest 3 LSB bits should be 0. When a packet is received, the Rx command descriptor becomes an Rx status descriptor. Table 57. Rx Status Descriptor-1 Table 58. Rx Status Descriptor-2 0 31 OWN Ownership: This bit, when set, indicates that the descriptor is owned by the NIC. of a packet. In this case, OWN=0.

Integrated Gigabit Ethernet Controller for PCI Express 61 Track ID: JATR-1076-21 Rev. 1.0 Offset# Bit# Symbol Description 0 30 EOR End of Rx Descriptor Ring: This bit, set to 1, indicates that this descriptor is the last descriptor of the Rx descriptor ring. Once the NIC’s internal receive descriptor pointer reaches here, it will return to the first descriptor of the Rx descriptor ring after this descriptor is used by packet reception. 0 29 FS First Segment descriptor: When set, indicates that this is the first descriptor of a received packet, and this descriptor is pointing to the first segment of the packet. 0 28 LS Last Segment Descriptor: When set, indicates that this is the last descriptor of a received packet, and this descriptor is pointing to the last segment of the packet. 0 27 MAR Multicast Address Packet Received: Wh en set, indicates that a multicast packet has been received. 0 26 PAM Physical Address Matched: When set, indicates that the destination address of this Rx packet matches the value in the RTL8111B/RTL8168B’s ID registers. 0 25 BAR Broadcast Address Received: When se t, indicates that a broadcast packet has been received. BAR and MAR will not be set simultaneously. 0 24 RSVD Reserved, always 0. 0 23 RSVD Reserved, always 1. 0 22 RWT Receive Watchdog Timer E xpired: This bit is set whenever the received packet length exceeds 8192 bytes. 0 21 RES Receive Error Summary: When set, i ndicates that at least one of the following errors has occurred: CRC, RUNT, RWT, FAE. This bit is valid only when LS (Last segment bit) is set 0 20 RUNT Runt Packet: When set, indicates th at the received packet length is smaller than 64 bytes. RUNT packets can only be received when RCR_AR is set. 0 19 CRC CRC Error: When set, indicates th at a CRC error has occurred on the received packet. A CRC packet can only be received when RCR_AER is set. Protocol ID1, Protocol ID0: These 2 bits indicate the protocol type of the packet received. PID1 PID0 Non-IP 0 0 TCP/IP 0 1 UDP/IP 1 0 IP 1 1 0 18, 17 PID1, PID0 0 16 IPF IP Checksum Failure: 1: Failure, 0: No failure. 0 15 UDPF UDP Checksum Failure: 1: Failure, 0: No failure. 0 14 TCPF TCP Checksum Failure: 1: Failure, 0: No failure. 0 13-0 Frame_Length When OWN=0 and LS =1, th ese bits indicate the received packet length including CRC, in bytes. 4 31-17 RSVD Reserved 4 16 TAVA Tag Available: When set, the r eceived packet is an IEEE-802.1Q VLAN TAG (0x8100) available packet.

Integrated Gigabit Ethernet Controller for PCI Express 62 Track ID: JATR-1076-21 Rev. 1.0 Offset# Bit# Symbol Description 4 15-0 VLAN_TAG VLAN Tag: If the TAG of the packet is 0x8100, The RTL8111B/RTL8168B extracts four bytes from after the source ID, sets TAVA bit to 1, and moves the TAG value to this field in the Rx descriptor. VIDH: The high 4 bits of a 12-bit VLAN ID. VIDL: The low 8 bits of a 12-bit VLAN ID. PRIO: 3-bit 8-level priority. CFI: Canonical Format Indicator. 8 31-0 RxBuffL Low 32-bit Address of Receive Buffer. 8-byte alignment is required. 12 31-0 RxBuffH High 32-bit Address of Receive Buffer 6.2. Flow Control The RTL8111B/RTL8168B supports IEEE 802.3X flow control, based on the results of N-Way, to improve performance in full-duplex mode. It detects and sends PAUSE packets to achieve the flow control task. Results from the N-Way process with the link partner determine if flow control is supported for the current connection. 6.2.1. Control Frame Transmission When the RTL8111B/RTL8168B is runni ng out of receive descriptors in full duplex mode, it sends a PAUSE packet (with pause_time=FFFFh) to inform the source station to stop transmission for the specified period of time. Once the receive descriptors are available again, the RTL8111B/RTL8168B sends another PAUSE packet (with pause_time=0000h) to wake up the source station to restart transmission. 6.2.2. Control Frame Reception The RTL8111B/RTL8168B enters backoff state for the specified period of time when it receives a valid PAUSE packet (with pause_time=n) in full duplex m ode. If the PAUSE packet is received while the RTL8111B/RTL8168B is transmitting, the RTL8111B/RTL 8168B starts to backoff after the current transmission is completed. The RTL8111B/RTL8168B is free to transmit packets when it receives a valid PAUSE packet (with pause_time=0000h) or the backoff timer(=n*512 bit time) elapses. The PAUSE operation cannot be used to inhibit tr ansmission of MAC Control frames (e.g. a PAUSE packet). The N-way flow control capability can be disabled. Refer to Section 4, EEPROM (93C46/93C56) Contents, page 24 for further information.

following sections describe the different LED actions. driven high indicating that no network connection exists. In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring. Figure 2. Rx LED

In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. Figure 3. Tx LED

Figure 4. Tx/Rx LED

linked and operating properly. This LED high for extended periods indicates that a link problem exists. Figure 5. LINK/ACT LED

Integrated Gigabit Ethernet Controller for PCI Express 67 Track ID: JATR-1076-21 Rev. 1.0 6.4. PHY Transceiver 6.4.1. PHY Transmitter Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the RTL8111B/RTL8168B operates at 10/100/1000Mbps over standard CAT.5 UTP cable (100/1000Mbps), and CAT.3 UTP cable (10Mbps). GMII (1000Mbps) Mode The RTL8111B/RTL8168B’s PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continuous code-gr oups through 4D-PAM5 coding technology. These code groups are passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a D/A converter. MII (100Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125Mhz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media. MII (10Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. The 10Mbps serial data is convert ed into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter. 6.4.2. PHY Receiver GMII (1000Mbps) Mode Input signals from the media pass through the sophis ticated on-chip hybrid circuit to subtract the transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received signal is processed with state-of-the-art tec hnology, e.g., adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5 decoding. Then, the 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the Rx Buffer Manager. MII (100Mbps) Mode The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz.

presented to the MII interface at a clock speed of 2.5MHz. write data to, an external serial EEPROM device. interface consists of EESK, EECS, EEDO, and EEDI. Table 59. EEPROM Interface EEDI/Aux Input data bus/Input pin to detect whether Aux. Power exists on initial power-on. is not pulled high to Aux. Power, the RTL8111B/RTL8168B assumes that no Aux.

Integrated Gigabit Ethernet Controller for PCI Express 69 Track ID: JATR-1076-21 Rev. 1.0 7. Driver Programming Note A-1 MAC Registers Configuration Sequence The ‘C+ Command ’ and ‘Command’ registers are the key parameters before any other registers or descriptors are configured. The MAC registers must be configured as follows: Step1. Configure C+ Command Register (Offset 00E0h-00E1h) Step2. Configure Command Register (Offset 0037h) Step3. Configure Other Registers A-2 Multicast Registers Configuration Multicast Registers Configuration (MAR) registers configuration is the same as that of the NE2000 driver. A-3 Checksum Offload Tx Descriptor Note To transmit an Ethernet packet, the upper layer might split this packet to several transmit buffers. Each transmit buffer corresponds to a Tx descriptor. If it transmits a packet with the Checksum Task Offload, it is necessary to set the related checksum offload bits of all Tx descriptors with this packet. Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw