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INTEGRATED 10/100M ETHERNET CONTROLLER FOR USB APPLICATIONS DATASHEET (CONFIDENTIAL: Development Partners Only) Rev. 1.0

21 March 2013

Track ID: JATR-8275-15 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com

Integrated 10/100M Ethernet Controller for USB Applications ii Track ID: JATR-8275-15 Rev. 1.0 COPYRIGHT ©2013 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. LICENSE This product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and US6,327,625. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.

REVISION HISTORY

Revision Release Date Summary 1.0 2013/03/21 First release.

Integrated 10/100M Ethernet Controller for USB Applications iii Track ID: JATR-8275-15 Rev. 1.0 Table of Contents

Integrated 10/100M Ethernet Controller for USB Applications 1 Track ID: JATR-8275-15 Rev. 1.0 1. General Description The Realtek RTL8152B-VB-CG 10/ 100M Ethernet controller comb ines an IEEE 802.3u compliant Media Access Controller (MAC), USB bus controll er, and embedded memory. A linear regulator (LDO) is incorporated for reduced BOM cost. With state-of-the-art DSP technology and mixe d-mode signal technology, the RTL8152B-VB offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection and Auto-Co rrection, polarity correction, adap tive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capabilities. The RTL8152B-VB features embedded One-Time-Programmable (OTP) memory. Advanced Configuration Power management In terface (ACPI)—power mana gement for modern operating systems that are capable of Operati ng System-directed Power Management (OSPM)—is supported to achieve the most efficient power manage ment possible. In addition to the ACPI feature, remote wake-up (including AMD Magi c Packet and Microsoft Wake-Up Frame) is supported in both ACPI and APM (Advanced Power Management) environments. The RTL8152B-VB supports Microsoft Wake Packet Detection (WPD) to provide Wake-Up Frame information to the OS, e.g., PatternID, OriginalPack etSize, SavedPacketSize, SavedPacketOffset, etc. WPD helps prevent unwanted/unauthorized wake-up of a sleeping computer. The RTL8152B-VB supports ‘RealWoW!’ technology that enables remote wake-up of a sleeping PC through the Internet. This feature allows PCs to reduce power consumption by remaining in low power sleeping state until needed. Note: The ‘RealWoW!’ service requires registration on first time use. The RTL8152B-VB is fully compliant with Microsoft NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP) Checksum features, and supports IEEE 802 IP Laye r 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above f eatures contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. The RTL8152B-VB supports Protocol offload. It offloads some of th e most common protocols to NIC hardware in order to prevent spurious wake -up and further reduce power consumption. The RTL8152B-VB can offload ARP (IPv4) and NS (IPv6) protocols while in the D3 power saving state.

Integrated 10/100M Ethernet Controller for USB Applications 2 Track ID: JATR-8275-15 Rev. 1.0 The RTL8152B-VB supports the ECMA (European Co mputer Manufacturers A ssociation) proxy for sleeping hosts standard. The standa rd specifies maintenance of netw ork connectivity and presence via proxies in order to extend the sleep duration of higher-powered hosts. It handles some network tasks on behalf of the host, allowing the host to remain in sleep mode for longer pe riods. Required and optional behavior of an operating proxy includes generating reply packets, ignoring packets, and waking the host. The RTL8152B-VB supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE). IEEE 802.3az operates with the IEEE 802.3 Media Access Cont rol (MAC) Sublayer to support operation in Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both sides of the link to save power. The device also features USB 2.0 technology. It provi des higher bandwidth and improved protocols for data exchange between the host an d the device. In addition, USB 2.0 offers a more aggressive power management feature that enables selective suspend to save energy. The RTL8152B-VB is suitable for multiple market segm ents and emerging applications, such as desktop, mobile, workstation, server, communications platforms, docking station, and embedded applications.

Integrated 10/100M Ethernet Controller for USB Applications 3 Track ID: JATR-8275-15 Rev. 1.0 2. Features Hardware „ Integrated 10/100M transceiver „ Auto-Negotiation with Next Page capability „ Supports USB 2.0 and 1.1 „ Supports pair swap/polarity/skew correction „ Crossover Detection & Auto-Correction „ Supports Wake-On-LAN and ‘RealWoW!’ (Wake-On-WAN) Technology (see note 1) „ Supports ECMA-393 ECMA ProxZzzy Standard for sleeping hosts (see note 1) „ XTAL-Less Wake-On-LAN „ Supports 25MHz or 48MHz external clock (from oscillator or system clock source) „ Supports power down/link down power saving „ Transmit/Receive on-chip buffer support „ Embedded OTP memory „ Built-in linear regulator (LDO) „ Supports Customizable LEDs „ Controllable LED Blinking Frequency and Duty Cycle „ Supports hardware CRC (Cyclic Redundancy Check) function „ LAN disable with GPIO pin „ Supports LPM (Link Power Management) „ SPI Flash Interface „ Supports CDC-ECM „ 24-pin QFN ‘Green’ package Software Offload „ Microsoft NDIS5, NDIS6 Checksum Offload (IPv4, IPv6, TCP, UDP) and Segmentation Task-offload (Large send v1 and Large send v2) support IEEE „ Supports Full Duplex flow control (IEEE 802.3x) „ Fully compliant with IEEE 802.3, IEEE 802.3u „ Supports IEEE 802.1P Layer 2 Priority Encoding „ Supports IEEE 802.1Q VLAN tagging „ Supports IEEE 802.3az-2010 (EEE) Microsoft AOAC (Always On Always Connected) „ Supports 16-set 128-byte Wake-Up Frame pattern exact matching „ Supports link change wake up „ Supports Microsoft WPD (Wake Packet Detection) „ Supports Protocol Offload (ARP & NS) Intel CPPM (Converged Platform Power Management) „ Supports L1 with 3ms BESL „ Supports selective suspend Note 1. Select between RealWoW! or ECMA, only one feature can be active at a time.

Figure 1. Pin Assignments

Table 1. Power Management Pin Table 2. USB Interface Pins USB 2.0/USB 1.1 Differential Signal Pair. Table 3. Transceiver Interface Pins pair in 10Base-T and 100Base-TX. transmit pair in 10Base-T and 100Base-TX.

Table 4. Clock Pins CKXTAL1 I 21 Input of 25MHz Clock Reference. CKXTAL2 IO 22 Output of 25MHz Clock Reference. Input of 25MHz or 48MHz External Clock Source. XTALDET/SPISDI I 18 Power-Up Strapping Pin. clock is used the XTALDET pin must be pulled low by a resistor during power-up. Table 5. LDO Regulator and Reference Pins A VDD33 P 10 Linear Regulator (LDO) 3.3V Output. not provide this power source to other devices. A VDD10 P 23 Linear Regulator (LDO) 1.05V Output. not provide this power source to other devices. DVDD10_UPS P 12 Linear Regulator (LDO) 1.05V Output. not provide this power source to other devices. RSET I 24 Reference. External resistor reference. Table 6. SPI Flash Pins SPICSB O 15 SPI Flash Chip Select. SPISDO I 20 Input from SPI Flas h Serial Data Output Pin. SPISDI/XTALDET O 18 Output to SPI Flash Serial Data Input Pin. SPISCK O 17 SPI Flash Serial Data Clock.

Table 7. LED Pins See section 6.2 Customizable LED Configuration, page 8 for details. Note: During power down mode, the LED signals are logic high. Table 8. Power and Ground Pins VDD5 P 11 Analog 5.0V Power Supply. A VDD33 P 1, 10 Analog 3.3V Power Supply. DVDD33 P 13 Digital 3.3V Power Supply. A VDD10 P 23 Analog 1.05V Power Supply. DVDD10 P 16 Digital 1.05V Power Supply. DVDD10_UPS P 12 Digital 1.05V Uninterruptible Power Supply. U2VDD10 P 9 USB 2.0/USB 1.1 Digital 1.05V Power Supply. U2GND P 6 USB 2.0/USB 1.1 Ground. GND P 25 Ground (Exposed Pad). Note: Refer to the latest schematic circuit for correct configuration. Table 9. GPIO Pin GPIO IO 14 General Purpose Input/Output Pin.

Integrated 10/100M Ethernet Controller for USB Applications 7 Track ID: JATR-8275-15 Rev. 1.0 6. Functional Description 6.1. USB Interface The SIE (Serial Interface Engine) employs a robust hardwired USB prot ocol implementation so that the entire USB interface operation can be done without firmware interven tion. For all three types of End Points (Bulk-IN, Bulk-OUT, and Interrupt-IN), appropriate respons es and handshake signals are generated by the SIE. The SIE analog transceiver comp lies fully with driver and receiver characteristics defined in USB Specification Rev. 2.0 6.1.1. USB Configurations The RTL8152B-VB supports two networking configurations, ECM (Ethernet Networking Control Model) configuration, and in-house confi guration. The ECM configuration co mplies with CDC-ECM, and is a general Ethernet networking model that enables network communication without installing additional vendor specific drivers. The in-hous e configuration requires a vendor specific driver to support enhanced features and optimized performance. 6.1.2. Endpoint 0 All USB devices support a common access mechanis m for accessing information through this control pipe. Associated with the control pipe at endpoint 0 is the information required to completely describe the USB device. This pipe also provides the register read and write to the RTL8152B-VB. 6.1.3. Endpoint 1 Bulk-IN The maximum Bulk-IN packet size is 512 bytes. Each Et hernet packet is transferred to the HOST by this Endpoint. If the Ethernet packet is larger than 512 bytes, the RTL8152B-VB splits the Ethernet packet into multiples of 512 bytes. The HOST treats USB pack ets that are less than 512 bytes or are equal to zero as End of Ethernet packets. 6.1.4. Endpoint 2 Bulk-OUT The HOST sends the USB packet to Ethernet. If the Ethernet packet is larger than 512 bytes, the Host will send the Ethernet packet in multiples of 512 bytes. A USB packet that is less than 512 bytes or is equal to zero is treated as an End of Ethernet packet. The Ethernet packet (containing multiple USB packet s) will be queued in the TX FIFO and transmitted when possible. If the Ethernet packet is transmitted without error, the TX FIFO space that was occupied by the transmitted Ethernet packet will be released. If the 2K TX FIFO is full, the RTL8152B-VB will respond with a NYET when the host tries to Bulk-OUT more USB packets. It is possible to have multiple Ethernet packets in the TX FIFO simultaneously. If an Ethernet packet is to be transmitted but experiences collisions more than 16 times (default), this is called a transmit abort and the packet will be skipped for transmission by the RTL8152B-VB. 6.1.5. Endpoint 3 Interrupt-IN The Interrupt Endpoint (EP3) can be used to poll the current link speed and link ok status of the RTL8152B-VB.

The RTL8152B-VB supports customizable LED opera tion modes via OCP register offset 0xDD90h. Table 10 describes the different LED actions. Table 10. LED Select

  • LED 0: On only in 10M mode, with no blinking during TX/RX
  • LED 1: On only in 100M mode, with TX/RX blinking

Table 11. Customized LEDs Table 12. LED Feature Control-1

0 LED0 Low Active LED1 Low Active RSVD Indicates Option 1 of Table 14

1 LED0 High Active LED1 High Active RSVD Indicates Option 2 of Table 14

Table 13. LED Feature Control-2 Note 1: ACT means blinking TX and RX. LINK indicates Link 10M and Link 100M.

Table 14. LED Option 1 & Option 2 Settings Act10 = LED blinking when Ethernet packets transmitted/received at 10Mbps. Act100 = LED blinking when Ethernet packets transmitted/received at 100Mbps. Link10 = LED lit when Ethernet connection established at 10Mbps. Link100 = LED lit when Ethernet connection established at 100Mbps. register offset 0xDD92 is 0x0B (00001011b), the LED blinking frequency is 80ms and duty cycle is 75%. The LED state is shown in Figure 2 (assumes the LED is low active). Table 15. LED Blinking Frequency Control Figure 2. LED Blinking Frequency and Duty Cycle

Integrated 10/100M Ethernet Controller for USB Applications 10 Track ID: JATR-8275-15 Rev. 1.0 6.3. PHY Transceiver Based on state-of-the-art DSP technology and mixed-mode signa l processing technology, the RTL8152B-VB operates at 10/100Mbps over standard CAT.5 UTP cable (100 Mbps), and CAT.3 UTP cable (10Mbps). 6.3.1. PHY Transmitter MII (100Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MA C, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125MHz NRZ and NRZI signals. The NRZI signals are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media. MII (10Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. The 10Mbps serial data is convert ed into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter. 6.3.2. PHY Receiver MII (100Mbps) Mode The MLT3 signal is processed with an ADC, e qualizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B /5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz. MII (10Mbps) Mode The received differential signal is converted into a Manchester-encoded st ream first. Next, the stream is processed with a Manchester decoder and is de-seria lized into 4-bit-wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz. 6.3.3. Link Down Power Saving Mode The RTL8152B-VB implements link-down power sa ving mode, greatly improving power consumption when the network cable is disconnected. The R TL8152B-VB automatically enters link down power saving mode within three seconds af ter the cable is disconnected from it. Once it enters link down power saving mode, it transmits normal link pulses on its TX pins and continues to monitor the RX pins to detect incoming signals. After it detects an inco ming signal, it wakes up from link down power saving mode and operates in normal mode according to the result of the connection.

transferred with the MSB first and start with a high-to-low transition. pins, and the IC package size, reducing the cost of making, assembling, and testing the electronics. Table 16. SPI Flash Interface SCK SPI Flash Serial Data Clock. without dropping/corrupting frames. and to select the best set of parameters common to both devices. Refer to http://www.ieee802.org/3/az/index.html for more details. Low Power State, some of the circuits are disabled. Refer to http://www.usb.org/developers/docs/.

Integrated 10/100M Ethernet Controller for USB Applications 12 Track ID: JATR-8275-15 Rev. 1.0 6.7. LAN Disable Mode The RTL8152B-VB supports ‘LAN Disa ble Mode’, which uses an external signal to control whether the NIC is enabled or disabled. 6.8. Power Management The RTL8152B-VB complies with ACPI (Rev 1.0, 1.0b, 2.0), Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8152B-VB can monitor the network for a Wa ke-Up Frame or a Magic Packet, and notify the system via the USB interface when such a packet or event occurs. The system is then restored to a normal state to process incoming jobs. When the RTL8152B-VB is in power down mode:

  • The RX state machine is stopped. The RTL8152B-VB monitors the network for wake-up events such as a Magic Packet and Wake-Up Frame in order to wake up the system. When in power down mode, the RTL8152B-VB will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the RX on-chip buffer.
  • The on-chip buffer status and packets that have already been received into the RX on-chip buffer before entering power down mode are held by the RTL8152B-VB.
  • Transmission is stopped. USB transactions are stopped. The TX on-chip buffer is held.
  • After being restored to D0 state, the RTL8152B-VB transmits data that was not moved into the TX on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. Magic Packet Wake-Up occurs only when the following conditions are met:
  • The destination address of the received Magic Packet is acceptable to the RTL8152B-VB, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8152B-VB adapter.
  • The received Magic Packet does not contain a CRC error.
  • The Magic Packet pattern matches, i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid Ethernet packet.

Integrated 10/100M Ethernet Controller for USB Applications 13 Track ID: JATR-8275-15 Rev. 1.0 A Wake-Up Frame event occurs only when the following conditions are met:

  • The destination address of the received Wake-Up Frame is acceptable to the RTL8152B-VB, e.g., a broadcast, multicast, or unicast address to the current RTL8152B-VB adapter.
  • The received Wake-Up Frame does not contain a CRC error.
  • The 16-bit CRC of the received Wake-Up Frame matches the 16-bit CRC of the sample Wake-Up Frame pattern given by the local machine’s OS. Or, the RTL8152B-VB is configured to allow direct packet wake-up, e.g., a broadcast, multicast, or unicast network packet.
  • The 128-byte of the received Wake-Up Frame matches the 128-byte of the sample Wake-Up Frame pattern given by the local machine’s OS. Note 1: 16-bit CRC: The RTL8152B-VB supports 16- set 16-bit CRC wake-up frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). CRC16 polynomial=x16+x12+x5+1. Note 2: 128-byte Wake-Up Fr ame: The RTL8152B-VB supports 16- set 128-byte wake-up frames. If enabled, the 16-bit CRC wake-up match will be disabled. 6.9. Protocol Offload Protocol offload is a task offload supported by Micros oft Windows 7. It maintains a network presence for a sleeping higher power host. Protoc ol offload prevents spurious wa ke-up and further reduces power consumption. It maintains connectivity while hosts ar e asleep, including receiving requests from other nodes on the network, ignoring packets, generating packets while in th e sleep state (e.g., the Ethernet Controller will generate ARP re sponses if the same MAC and IPv4 address are provided in the configuration data), and intel ligently wake-up host systems. Th e RTL8152B-VB supports the ECMA (European Computer Manufacturer s Association) specification including proxy configuration and management, IPv4 ARP, IPv6 NDP, and wake-up pack ets. The RTL8152B-VB also supports optional ECMA items such as QoS tagged packets and duplicate address detection. 6.10. XTAL-Less Wake-On-LAN The RTL8152B-VB supports board level design with an external 25MHz or 48MHz clock source instead of the crystal. The external clock source may stop generating the cl ock when in suspend mode (S3/S4/S5). To support the Wake-On-LAN function without the external clock source, the RTL8152B -VB will automatically change its source clock from the external clock to an internal self-oscillating auxiliary clock when it enters suspend mode. Note that when in suspend m ode, the auxiliary clock can establish on ly a 10Mbps link and does not support ARP/NS offload and ECMA ProxZzzy.

Integrated 10/100M Ethernet Controller for USB Applications 14 Track ID: JATR-8275-15 Rev. 1.0 6.11. Wake Packet Detection (WPD) The RTL8152B-VB supports Microsoft Wake Packet Detection (WPD) to provide Wake-Up Frame information to the OS, e.g., PatternID, OriginalPack etSize, SavedPacketSize, SavedPacketOffset, etc. WPD helps prevent unwanted/unauthorized wake-up of a sleeping computer. Refer to the Microsoft Wake Packet Detect ion (WPD) Interface Specification for details 6.12. ‘RealWoW!’ (Wake-On-WAN) Technology The RTL8152B-VB supports Realtek 'RealWo W!' technology that allows the RTL8152B-VB to send keep alive packets to the Wake Server when the PC is in sleeping mode. Realtek 'RealWoW!' can pass wake-up packets through a NAT (Network Address Translation) device. This feature allows PCs to reduce power cons umption by remaining in low power sleeping state until needed. Users can login into the Wake Server via the Internet to wake the selected sleeping PC. Registration of Account information to the Wake Server is required on first time use. 6.13. Always On Always Connected The RTL8152B-VB supports Microsoft’s AOAC (Alw ays On Always Connected) model. The AOAC platform can enter the system state ‘Connected Standby’ and allow the RTL8152B-VB to enter a low-power state. The RTL8152B-VB will maintain Layer 2 connectivity and generate a wake signal when one of the following conditions is satisfied:

  • Link status becomes ‘connected’
  • Link status becomes ‘disconnected’
  • Receives a WOL pattern
  • Receives a wildcard pattern 7. LDO Regulator The RTL8152B-VB incorporates three linear Low-Dr opout (LDO) regulators that feature high power supply ripple rejection and low output noise. The RTL8152B-VB embedded LDO regulators do not require power inductors on the PCB; only an out put capacitor between its output and analog ground for phase compensation, which saves cost and PCB real estate. The output capacitors (and bypass capacito rs) should be placed as close as possible to the power pins for adequate filtering. Note 1: The embedded LDO is desi gned for RTL8152B-VB internal use only. Do not provide this power source to other devices. Note 2: The LDO 1.05V output pin (DVDD10_UPS) must be separated from the other LDO 1.05V output pin (AVDD10).

Table 17. Absolute Maximum Ratings Note: Refer to the latest schematic circuit for correct configuration. Table 18. Recommended Operating Conditions Note: Refer to the latest schematic circuit for correct configuration.

Table 19. Crystal Requirements fundamental mode, AT-cut type. tolerance, fundamental mode, AT-cut type. Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above. Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps. Note 3: The ESR maximum value of 70ohm is based on shunt capacitance (Co) less than 7pF . crystal and ground. To match this use the load capacitance specified by the crystal manufacturer of 16~20pF . Table 20. Oscillator Requirements Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above. Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps. Table 21. Environmental Characteristics

Table 22. DC Characteristics Note: Refer to the latest schematic circuit for correct configuration. Table 23. Reflow Profile Recommendations Ramp-Up Rate (TL to Tp) 3°C/second max. 3°C/second max. Ramp-Down Rate (Tp to TL) 6°C/second max. 6°C/second max. Time 25°C to Peak Temperature (Tp) 6 minutes max. 8 minutes max. Note 1: All temperatures refer to the topside of the package, measured on the package body surface. Note 2: Tolerance for Tp is defined as a supplier’ s minimum and a user’ s maximum. Note 3: Reference document: IPC/JEDEC J-STD-020D.1.

Table 25. SPI Flash Type Supported Note 1: The Flash clock frequency should be 33MHz or higher.

Integrated 10/100M Ethernet Controller for USB Applications 21 Track ID: JATR-8275-15 Rev. 1.0 9. Mechanical Dimensions Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A2 - 0.65 0.70 - 0.026 0.028 A3 0.20REF 0.008REF D/E 4.00BSC 0.158BSC e 0.50BSC 0.020BSC Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). Note 2: REFERENCE DOCUMENT: JEDEC MO-220.

Table 26. Ordering Information Note: See page 3 for package ID information.