RTL8111E-VL-CG

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w RTL8111E-VL-CG INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONS DATASHEET (CONFIDENTIAL: Development Partners Only) Rev. 1.1

07 October 2010

Track ID: JATR-2265-11 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com

Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-2265-11 Rev. 1.1 COPYRIGHT ©2010 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. LICENSE This product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and US6,327,625. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.

REVISION HISTORY

Revision Release Date Summary 1.0 2010/06/23 First release. 1.1 2010/10/07 Revised section 6.2.6 Customizable LED Configuration, page 12. Revised Table 18 Absolute Maximum Ratings, page 21. Revised Table 19 Recommended Operating Conditions, page 21.

Integrated Gigabit Ethernet Controller for PCI Express iii Track ID: JATR-2265-11 Rev. 1.1 Table of Contents

Integrated Gigabit Ethernet Controller for PCI Express iv Track ID: JATR-2265-11 Rev. 1.1

Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-2265-11 Rev. 1.1 1. General Description The Realtek RTL8111E-VL-CG Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a trip le-speed Ethernet transceiver, PCI Express bus controller, and embedded memory. With state- of-the-art DSP technology and mixed-mode signal technology, the RTL8111E offers high-speed tran smission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossove r Detection and Auto-Corr ection, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. The RTL8111E supports the PCI Express 1.1 bus interface for host communications with power management, and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. It also s upports an auxiliary power auto-detect function, and will auto-configure rela ted bits of the PCI power management registers in PCI configuration space. The RTL8111E features embedded One-Time-Program mable (OTP) memory to replace the external EEPROM (93C46/93C56/93C66). Advanced Configuration Power management In terface (ACPI)—power mana gement for modern operating systems that are capable of Operati ng System-directed Power Management (OSPM)—is supported to achieve the most ef ficient power management possibl e. PCI MSI (Message Signaled Interrupt) and MSI-X are also supported. In addition to the ACPI feature, remote wake-up (including AMD Magic Packet and Microsoft Wake-up frame) is supported in both ACPI and APM (Adva nced Power Management) environments. To support WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8111E. The RTL8111E is fully compliant with Microsoft NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP) Checksum and Segmentation Task-offload (Large send and Giant send) features, and supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Vi rtual bridged Local Area Networ k (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. The RTL8111E supports Receive Side Scaling (RSS) to hash incoming TCP connections and load-balance received data processing across multiple CPUs. RSS improves the number of transactions per second and number of connections per second, for increased network throughput. The RTL8111E supports Protocol o ffload. It offloads some of th e most common protocols to NIC hardware in order to prevent spurious wake up and further reduce power consumption. The RTL8111E can offload ARP (IPv4) and NS (IPv6) protocols while in the D3 power saving state.

Integrated Gigabit Ethernet Controller for PCI Express 2 Track ID: JATR-2265-11 Rev. 1.1 The RTL8111E supports IEEE 802.3az Dr aft 3.0, also known as Energy Efficient Ethernet (EEE). IEEE 802.3az operates with the IEEE 802.3 Media Access Cont rol (MAC) Sublayer to support operation in Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both sides of the link to save power. The device also features inter-connect PCI E xpress technology. PCI Expres s is a high-bandwidth, low-pin-count, serial, interconnect technology that offers significant improvements in performance over conventional PCI and also maintains software compatibility with existing PCI infrastructure. The RTL8111E is suitable for multiple market segm ents and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications.

Integrated Gigabit Ethernet Controller for PCI Express 3 Track ID: JATR-2265-11 Rev. 1.1 2. Features „ Integrated 10/100/1000 transceiver „ Auto-Negotiation with Next Page capability „ Supports PCI Express 1.1 „ Supports pair swap/polarity/skew correction „ Crossover Detection & Auto-Correction „ Wake-on-LAN and remote wake-up support „ Microsoft NDIS5, NDIS6 Checksum Offload (IPv4, IPv6, TCP, UDP) and Segmentation Task-offload (Large send v1 and Large send v2) support „ Supports Full Duplex flow control (IEEE 802.3x) „ Supports jumbo frame to 9K bytes „ Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab „ Supports IEEE 802.1P Layer 2 Priority Encoding „ Supports IEEE 802.1Q VLAN tagging „ Supports IEEE 802.3az Draft 3.0 (EEE) „ Embedded OTP memory can replace the external EEPROM „ Serial EEPROM „ Transmit/Receive on-chip buffer support „ Supports power down/link down power saving „ Built-in switching regulator „ Supports PCI MSI (Message Signaled Interrupt) and MSI-X „ Supports quad core Receive-Side Scaling (RSS) „ Supports Protocol Offload (ARP & NS) „ Supports Customized LEDs „ Supports 1-Lane 2.5Gbps PCI Express Bus „ Supports hardware ECC (Error Correction Code) function „ Supports hardware CRC (Cyclic Redundancy Check) function „ 48-pin QFN ‘Green’ package 3. System Applications „ PCI Express Gigabit Ethernet on Motherboard, Notebook, or Embedded systems

Figure 1. Pin Assignments

Table 1. Power Management/Isolation Power Management Event: Open drain, active low. Used to reactivate the PCI Express slot’s main power rails and reference clocks. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins. PCI Express input as long as the Isolate pin is asserted. Table 2. PCI Express Interface REFCLK_N I 20 PCI Express Differential Reference Clock Source: 100MHz ± 300ppm. HSON O 23 PCI Express Transmit Differential Pair. HSIN I 18 PCI Express Receive Differential Pair. PCI Express Reset Signal: Active low. Reference Clock Request Signal. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins.

Table 3. Transceiver Interface the transmit pair in 10Base-T and 100Base-TX. the receive pair in 10Base-T and 100Base-TX. pair in 10Base-T and 100Base-TX. In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair. Table 4. Clock CKXTAL1 I 43 Input of 25MHz Clock Reference. CKXTAL2 IO 44 Input of External Clock Source. Output of 25MHz Clock Reference. Table 5. Regulator and Reference REGOUT O 36 Switching Regulator 1.0V Output. ENSWREG I 33 3.3V: Enable switching regulator. 0V: Disable switching regulator. VDDREG P 34, 35 Digital 3.3V Power Supply for Switching Regulator. RSET I 46 Reference. External resistor reference. Note: See section 7, page 20 for switching regulator.

Table 6. EEPROM EESK O 37 Serial Data Clock. EEDI: Output to serial data input pin of EEPROM. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins. EEDO I 31 Input from Serial Data Output Pin of EEPROM. 30 EECS: EEPROM Chip Select. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins. Table 7. LEDs See section 6.2.6 Customizable LED Configuration, page 12 for details. Note 1: During power down mode, the LED signals are logic high. Table 8. SMBus Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins.

Table 9. Power and Ground DVDD33 P 27, 39 Digital 3.3V Power Supply. DVDD10 P 13, 29, 41 Digital 1.0V Power Supply. A VDD10 P 3, 6, 9, 45 Analog 1.0V Power Supply. EVDD10 P 21 Analog 1.0V Power Supply. A VDD33 P 12, 42, 47, 48 Analog 3.3V Power Supply. GND P 49 Ground (Exposed Pad). Note: Refer to the latest schematic circuit for correct configuration. Table 10. GPO Pin GPO O/D 38 General Purpose Output Pin. This pin reflects the link up or link down state. Refer to the reference schematic for strapping pin information. All strapping pins are power-on-latch pins.

Integrated Gigabit Ethernet Controller for PCI Express 9 Track ID: JATR-2265-11 Rev. 1.1 6. Functional Description 6.1. PCI Express Bus Interface The RTL8111E complies with PCI Express Base Specification Revision 1.1, and runs at a 2.5GHz signaling rate with X1 link width, i.e., one transmit and one receiv e differential pair. The RTL8111E supports four types of PCI Express messages: inte rrupt messages, error messages, power management messages, and hot-plug messages. To ease PCB layout c onstraints, PCI Express lane polarity reversal and link reversal are also supported. 6.1.1. PCI Express Transmitter The RTL8111E’s PCI Express block receives digital da ta from the Ethernet interface and performs data scrambling with Linear Feedback Shift Register (L FSR) and 8B/10B coding tec hnology into 10-bit code groups. Data scrambling is used to reduce the possibili ty of electrical resona nce on the link, and 8B/10B coding technology is used to benefit embedded clocki ng, error detection, and DC balance by adding an overhead to the system through the addition of 2 extr a bits. The data code gr oups are passed through its serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB trace to its upstream device via a differential driver. 6.1.2. PCI Express Receiver The RTL8111E’s PCI Express block receives 2.5Gbps seri al data from its upstream device to generate parallel data. The receiver’s PLL circuits are re-synchronized to main tain bit and symbol lock. Through 8B/10B decoding technology and data de-scrambling, the original digital data is re covered and passed to the RTL8111E’s internal Ethernet MAC to be transmitted onto the Ethernet media. 6.2. LED Functions The RTL8111E supports three LED signals in four conf igurable operation modes. The following sections describe the various LED actions. 6.2.1. Link Monitor The Link Monitor senses link integrity, su ch as LINK10, LINK100, LINK1000, LINK10/ACT, LINK100/ACT, or LINK1000/ACT. Whenever link status is established, the specific link LED pin is driven low. Once a cable is disc onnected, the link LED pin is driven high, indicating that no network connection exists.

describes the different LED actions. Table 11. LED Select (IO Register Offset 18h~19h)

• LED 0: On only in 10M mode, with blinking during TX/RX
• LED 1: On only in 100M mode, with blinking during TX/RX
• LED 3: On only in 1000M mode, with blinking during TX/RX

Table 12. Customized LEDs LED OFF Mode: Set all bits to 0. All LED pin output become floating (power saving). Fixed LED Mode: Set Option 1 LED table Mode: LED0=LED1=LED2=1 or 2 (see Table 13). Table 13. Fixed LED Mode Note: ‘X’ indicates ‘irrelevant’.

Table 14. Feature Control Table-1

0 LED0 Low Active LED1 Low Active LED2 Low Active Option 1 LED Table Selected

1 LED0 High Active LED1 High Active LED2 High Active Option 2 LED Table Selected

Table 15. Feature Control Table-2 Table 16. Option 1 & Option 2 LED Table 10 = LED blinking when Ethernet packets transmitted/received at 10Mbps. Act100 = LED blinking when Ethernet packets transmitted/received at 100Mbps. Act1G = LED blinking when Ethernet packets transmitted/received at 1000Mbps. Link10 = LED lit when Ethernet connection established at 10Mbps. Link100 = LED lit when Ethernet connection established at 100Mbps. Link1G = LED lit when Ethernet connection established at 1000Mbps.

Integrated Gigabit Ethernet Controller for PCI Express 14 Track ID: JATR-2265-11 Rev. 1.1 6.3. PHY Transceiver 6.3.1. PHY Transmitter Based on state-of-the-art DSP t echnology and mixed-mode signal processing technology, the RTL8111E operates at 10/100/1000Mbps over standard CA T.5 UTP cable (100/1000Mbps), or CAT.3 UTP cable (10Mbps). GMII (1000Mbps) Mode The RTL8111E’s PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continuous code -groups through 4D-PAM5 coding technology. These code groups are passed through a waveform-shaping filter to minimize EMI effects, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a D/A converter. MII (100Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MA C, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125MHz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media. MII (10Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. The 10Mbps serial data is convert ed into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter. 6.3.2. PHY Receiver GMII (1000Mbps) Mode Input signals from the media pass through the sophi sticated on-chip hybrid ci rcuit to separate the transmitted signal from the input signal for effectiv e reduction of near-end echo. Afterwards, the received signal is processed with state-of -the-art technology, e.g., adaptive e qualization, BLW (Baseline Wander) correction, cross-talk cancellati on, echo cancellation, timing recover y, error correction, and 4D-PAM5 decoding. Then, the 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz. The RX MAC retrieves the packet data from the receive MII/GMII interface and sends it to the RX Buffer Manager. MII (100Mbps) Mode The MLT3 signal is processed with an ADC, e qualizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B /5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz. MII (10Mbps) Mode The received differential signal is converted into a Manchester-encoded st ream first. Next, the stream is processed with a Manchester decoder and is de-seria lized into 4-bit-wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz.

Reg8 as defined in IEEE 802.3ab. data to, an external serial EEPROM device. space and I/O space to be overridden following a power-on or software EEPROM auto-load command. consists of EESK, EECS, EEDO, and EEDI. The correct EEPROM (i.e., 93C46/93C56/93C66) must be used in order to ensure proper LAN function. Table 17. EEPROM Interface EECS 93C46/93C56/93C66 Chip Select. EESK EEPROM Serial Data Clock. EEDI Output to Serial Data Input Pin of EEPROM.

Integrated Gigabit Ethernet Controller for PCI Express 16 Track ID: JATR-2265-11 Rev. 1.1 6.6. Power Management The RTL8111E complies with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), PCI Express Active State Power Management (ASPM) , and Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8111E can monitor the network for a Wakeup Frame or a Magic Packet, and notify the system via a PCI Express Power Management Event (PME) Message, Beacon, or the LANWAKEB pin when such a packet or event occurs. Then the system can be restored to a normal state to process incoming jobs. When the RTL8111E is in power down mode (D1~D3):

• The RX state machine is stopped. The RTL8111E monitors the network for wakeup events such as a Magic Packet and Wakeup Frame in order to wake up the system. When in power down mode, the RTL8111E will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the RX on-chip buffer.
• The on-chip buffer status and packets that have already been received into the RX on-chip buffer before entering power down mode are held by the RTL8111E.
• Transmission is stopped. PCI Express transactions are stopped. The TX on-chip buffer is held.
• After being restored to D0 state, the RTL8111E transmits data that was not moved into the TX on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI configuration space depend on the existence of Aux power . If aux. power is absent, the above 4 bits are all 0 in binary. Example: If EEPROM D3c_support_PME = 1:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C3 FF, then PCI PMC = C3 FF)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C3 FF, then PCI PMC = 03 7E) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C3 FF (Realtek EEPROM default value).

Integrated Gigabit Ethernet Controller for PCI Express 17 Track ID: JATR-2265-11 Rev. 1.1 If EEPROM D3c_support_PME = 0:

• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C3 7F, then PCI PMC = C3 7F)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C3 7F, then PCI PMC = 03 7E) In the above case, if wakeup support is not desired wh en main power is off, it is suggested that the EEPROM PMC be set to 03 7E. Magic Packet Wakeup occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8111E, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8111E.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state.
• The Magic Packet pattern matches, i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame is acceptable to the RTL8111E, e.g., a broadcast, multicast, or unicast address to the current RTL8111E.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 16-bit CRC* of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8111E is configured to allow direct packet wakeup, e.g., a broadcast, multicast, or unicast network packet. Note: 16-bit CRC: The RTL8111E supports eight long- wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet).

Integrated Gigabit Ethernet Controller for PCI Express 18 Track ID: JATR-2265-11 Rev. 1.1 The corresponding wake-up method (message or LA NWAKEB) is asserted only when the following conditions are met:

• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8111E may assert the corresponding wake-up method (message or LANWAKEB) in the current power state or in isolation state, depending on the PME_Support (bit15~11) setting of the PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wakeup Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8111E to stop asserting the corresponding wake-up method (message or LANWAKEB) (if enabled). When the RTL8111E is in power down mode, e.g., D1~D3, the IO, and MEM accesses to the RTL8111E are disabled. After a PERSTB assertion, the device’s pow er state is restored to D0 automatically if the original power state was D3 cold. There is almost no hardware delay at the device’s power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto -loaded from EEPROM). The setting may be changed from the EEPROM, if required. 6.7. Vital Product Data (VPD) Bit 31 of the Vital Product Data (VPD) capability st ructure in the RTL8111E’s PCI Configuration Space is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data between the VPD data register and the 93C46/93C56/93C66 has completed or not. Write VPD register: (write data to the 93C46/93C56/93C66): Set the flag bit to 1 at the same time the VPD addr ess is written to write VPD data to EEPROM. When the flag bit is reset to 0 by the RTL8111E, the VPD data (4 bytes per VPD access) has been transferred from the VPD data register to EEPROM. Read VPD register: (read data from the 93C46/93C56/93C66): Reset the flag bit to 0 at the same time the VPD addr ess is written to retrieve VPD data from EEPROM. When the flag bit is set to 1 by the RTL8111E, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data register. Note1: Refer to the PCI 2.3 Specifications for further information. Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.3 Specifications. VPD data is always consecutive 4-byte data starting from the VPD address specified. Note3: Realtek reserves offset 60h to 7Fh in EEPROM mainly for VPD data to be stored. Note4: The VPD function of the RTL8111E is designed to be able to access the full range of the 93C46/93C56/93C66 EEPROM.

Integrated Gigabit Ethernet Controller for PCI Express 19 Track ID: JATR-2265-11 Rev. 1.1 6.8. Receive-Side Scaling (RSS) The RTL8111E complies with the Network Driv er Interface Specification (NDIS) 6.0 Receive-Side Scaling (RSS) technology for the Microsoft Windows family of operating systems. RSS allows packet receive-processing from a network adapter to be balanced across th e number of available computer processors, increasing performance on multi-CPU platforms. 6.8.1. Receive-Side Scaling (RSS) Initialization During RSS initialization, the Window s operating system will inform th e RTL8111E that it should store the following parameters: hash function, hash type, hash bits, indirection table, BaseCPUNumber, and the secret hash key. Hash Function The default hash function is the Toeplitz hash function. Hash Type The hash types indicate which field of the packet n eeds to be hashed to get the hash result. There are several combinations of these fields, mainl y, TCP/IPv4, IPv4, TCP/IPv6, IPv6, and IPv6 extension headers.

• TCP/IPv4 requires hash calculations over the IPv4 source address, the IPv4 destination address, the source TCP port and the destination TCP port.
• IPv4 requires hash calculations over the IPv4 source address and the IPv4 destination address.
• TCP/IPv6 requires hash calculations over the IPv6 source address, the IPv6 destination address, the source TCP port and the destination TCP port.
• IPv6 requires hash calculations over the IPv6 source address and the IPv6 destination address (Note: The RTL8111E does not support the IPv6 extension header hash type in RSS). Hash Bits Hash bits are used to index the hash result into the indirection table Indirection Table The Indirection Table stores values that are added to the BaseCPUNumber to enable RSS interrupts to be restricted from some CPUs. The OS will update the Indirection Table to rebalance the load. BaseCPUNumber The lowest number CPU to use for RSS. BaseCPUNumber is added to the result of the indirection table lookup. Secret Hash Key The key used in the Toeplitz function. For different hash types, the key size is different.

Integrated Gigabit Ethernet Controller for PCI Express 20 Track ID: JATR-2265-11 Rev. 1.1 6.8.2. Protocol Offload Protocol offload is a task offload supported by Micr osoft Windows 7. It maintains a network presence for a sleeping higher power host. Protocol offload prev ents spurious wake up a nd further reduces power consumption. It maintains connectivity while hosts ar e asleep, including receiving requests from other nodes on the network, ignoring packets, generating packets while in th e sleep state (e.g., the Ethernet Controller will generate ARP re sponses if the same MAC and IPv4 address are provided in the configuration data), and intelligently waking up host systems. 6.8.3. RSS Operation After the parameters are set, the RTL8111E will st art hash calculations on each incoming packet and forward each packet to its correct qu eue according to the hash result. If the incoming packet is not in the hash type, it will be forwarded to the primary queue. The hash result plus the BaseCP UNumber will be indexed into the indirection table to get the correct CPU number. Th e RTL8111E uses three methods to inform the system of incoming packets: inline inte rrupt, MSI, and MSIX. Periodically the OS will update the indirection table to rebalance the load across the CPUs. 6.9. Energy Efficient Ethernet (EEE) The RTL8111E supports IEEE 802.3az Draft 3.2, also kno wn as Energy Efficien t Ethernet (EEE), at 10Mbps, 100Mbps, and 1000Mbps. It provides a protocol to coordinate transitions to/from a lower power consumption level (Low Power Idle mode) based on link utilization. When no packets are being transmitted, the system goes to Low Power Idle mode to save power. Once packets need to be transmitted, the system returns to normal mode, a nd does this without changing the link status and without dropping/corrupting frames. To save power, when the system is in Low Power Idle mode, most of the circuits are disabled, however, the transition time to/from Low Power Idle mode is kept small enough to be transparent to upper layer protocols and applications. EEE also specifies a negotiation method to enable li nk partners to determine whether EEE is supported and to select the best set of parameters common to both devices. Refer to http://ieee802.org/3/interims/index.html for more details. 7. Switching Regulator The RTL8111E incorporates a state-of-the-art sw itching regulator that requires a well-designed PCB layout in order to achieve good power efficiency a nd lower the output voltage ripple and input overshoot. Note that the switching regulator 1.0V output pi n (REGOUT) must be connected only to DVDD10, AVDD10, and EVDD10 (do not provide this power source to other devices). Note: Refer to the separate RTL8111E layout guide for details.

Table 18. Absolute Maximum Ratings Note: Refer to the most updated schematic circuit for correct configuration. Table 19. Recommended Operating Conditions Note: Refer to the most updated schematic circuit for correct configuration.

Table 20. Crystal Requirements Note1: The CLK source can come from other places in the system, but it must accord with the parameters above. Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps. Table 21. Oscillator Requirements Note 1: The CLK source can come from other places in the system, but it must accord with the parameters above. Note 2: Broadband RMS=9ps; 25KHz to 25MHz RMS=3ps.

Table 22. Environmental Characteristics Table 23. DC Characteristics Note 1: Refer to the latest schematic circuit for correct configuration. Note 2: All Supply Mean Voltage power noise <±5% of Mean Voltage.

Figure 6. Serial EEPROM Interface Timing Table 24. EEPROM Access Timing Parameters

Table 25. Differential Transmitter Parameters Note1: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter. requires the two communicating ports be modulated such that they never exceed a total of 600ppm difference.

Table 26. Differential Receiver Parameters Note: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter. Table 27. REFCLK Parameters

Integrated Gigabit Ethernet Controller for PCI Express 27 Track ID: JATR-2265-11 Rev. 1.1 Symbol Parameter 100MHz Input M i n M a x Units Note Duty Cycle Duty Cycle 40 60 % 2 Rise-Fall Matching Rising Edge Rate (REFCLK+) to Falling Edge Rate (REFCLK-) Matching - 20 % 1, 14 ZC-DC Clock Source DC Impedance 40 60 Ω 1, 11 Note1: Measurement taken from single-ended waveform. Note2: Measurement taken from differential waveform. Note3: Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Figure 10, page 29. Note4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. See Figure 7, page 28. Note5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Figure 7, page 28. Note6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. See Figure 9, page 28. Note7: Defined as the maximum instantaneous voltage including overshoot. See Figure 7, page 28. Note8: Defined as the minimum instantaneous voltage including undershoot. See Figure 7, page 28. Note9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS for any particular system. See Figure 7, page 28. Note10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding ppm considerations. Note11: System board compliance measurements must use the test load card described in Figure 13, page 30. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load CL=2pF . Note12: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to droop back into the VRB ±100mV differential range. See Figure 12, page 29. Note13: PPM refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly, or 100Hz. For 300ppm then we have an error budget of 100Hz/ppm*300ppm=30kHz. The period is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±300ppm applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread Spectrum there is an additional 2500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800ppm. Note14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 8, page 28. Note15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment setting of each parameter.

Integrated Gigabit Ethernet Controller for PCI Express 31 Track ID: JATR-2265-11 Rev. 1.1 9. Mechanical Dimensions Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A3 0.20REF 0.008REF D/E 6.00BSC 0.236BSC e 0.40BSC 0.016BSC Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). Note 2: REFERENCE DOCUMENT: JEDEC MO-220.

Table 29. Ordering Information Note: See page 4 for package identification information.