RTL8111-LF

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INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS™ APPLICATIONS DATASHEET Rev. 1.2

24 March 2005

Track ID: JATR-1076-21 RTL8111

Integrated Gigabit Ethernet Controller for PCI Express i i Track ID: JATR-1076-21 Rev. 1.2 COPYRIGHT ©2005 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2004/08/19 First release. 1.1 2004/11/05 Package changes. See section 8, Mechanical Dimensions, page 23, and section 9, Ordering Information, page 24. 1.2 2005/03/24 Changed Table 8, Power & Ground, page 6. Changed Table 6, Regulator & Reference, page 5. Added lead (Pb)-free package identification information on page 3 and on page 24.

Integrated Gigabit Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.2 Table of Contents

Integrated Gigabit Ethernet Controller for PCI Express i v Track ID: JATR-1076-21 Rev. 1.2

Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.2 1. General Description The Realtek RTL8111 Gigabit Ethern et controller combines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethern et transceiver, PCI Express bus controller, and embedded memory. With state-of-t he-art DSP technology and mixed-m ode signal technology, they offer high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, a nd error correction are implemented to provide robust transmission and reception capability at high speeds. The device supports the PCI Express 1.0a bus interface for host communications with power management and is compliant with the I EEE 802.3u specification for 10/100M bps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-d etect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. Advanced Configuration Power management Interface (ACPI)--power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)—is also supported to achieve the most efficient power management possible. PCI Message Signaled Interrupt (MSI) is also supported. In addition to the ACPI feature, remote wake -up (including AMD Magic Packet™, Re-LinkOk, and Microsoft® Wake-up frame) is supported in both AC PI and APM (Advanced Power Management) only auxiliary exists), the auxiliar y power source must be able to provide the needed power for the RTL8111. The RTL8111 is fully compliant with Microsoft ® NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and supports IEEE 802 IP Laye r 2 priority encoding and 802.1Q Virtual bridged Local Area Network (VLAN). The above features c ontribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. The device features next-gener ation PCI Express interconnect technology. PCI Express is a high-bandwidth, low pin count, serial , interconnect technol ogy that offers significant improvements in performance over conventional PCI and also maintains software co mpatibility with existing PCI infrastructure. The RTL8111 is suitable for multiple market segments and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications.

Integrated Gigabit Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.2 2. Features „ Integrated 10/100/1000 transceiver „ Auto-Negotiation with Next Page capability „ Supports PCI Express™ 1.0a „ Supports pair swap/polarity/skew correction „ Crossover Detection & Auto-Correction „ Wake-on-LAN and remote wake-up support „ Microsoft® NDIS5 Checksum Offload (IP, TCP, UDP) and Largesend Offload support „ Supports Full Duplex flow control (IEEE 802.3x) „ Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab „ Supports IEEE 802.1P Layer 2 Priority Encoding „ Supports IEEE 802.1Q VLAN tagging „ Serial EEPROM „ Transmit/Receive on-chip buffer (8KB/16KB) support „ Supports power down/link down power saving „ Supports PCI Message Signaled Interrupt (MSI) „ 128-pin DHS-QFP package 3. System Applications „ PCI Express™ Gigabit Ethernet on Moth erboard, Notebook, or Embedded system

Figure 1. Pin Assignments Lead (Pb)-free package is indicated by an “L” in the location marked “T” in Figure 1.

Table 1. Power Management/Isolation LANWAKEB O/D 36 Power Management Event: Open drain, active low. Used to reactivate the PCI Express slot’s main power rails and reference clocks. Express input as long as the Isolate pin is asserted. Table 2. PCI Express Interface REFCLK_N I 51 PCI Express Differential Reference Clock Source: 100MHz ± 300ppm. HSON O 55 PCI Express Transmit Differential Pair. HSIN I 48 PCI Express Receive Differential Pair. PCI Express Reset Signal: Active low. the de-assertion of the PERSTB. Table 3. EEPROM EESK O 75 Serial data clock. EEDI: Output to serial data input pin of EEPROM. AUX: Input pin to detect if Aux. Power exists or not on initial power-on. assumes that no Aux. Power exists. EEDO I 72 Input from serial data output pin of EEPROM. EECS O 71 EECS: EEPROM chip select.

Table 4. Transceiver Interface transmit pair in 10Base-T and 100Base-TX. the transmit pair in 10Base-T and 100Base-TX. pair in 10Base-T and 100Base-TX. In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair. Table 5. Clock CKXTAL1 I 125 Input of 25MHz clock reference. CKXTAL2 O 126 Output of 25MHz clock reference. Table 6. Regulator & Reference VCTRL25 O 12 Regulator Control. V oltage control to external 2.5V power transistor. VCTRL20 O 15 Regulator Control. V oltage control to external 2.1V power transistor. VCTRL18 O 1 Regulator Control. V oltage control to external 1.8V power transistor. RSET I 3 Reference. External resistor reference. Note: Refer to the most updated schematic circuit for correct configuration.

Table 7. LEDs Note 1: During power down mode, the LED signals are logic high. Note 2: LEDS1-0’ s initial value comes from the 93C46. If there is no 93C46, the default values = 1, 1. Table 8. Power & Ground VDD33 Power 33, 73, 98, 115 Digital 3.3V power supply. 110, 121 Digital 1.8V power supply. A VDD25 Power 7, 11, 20, 24 Analog 2.5V power supply. GVDD21 Power 16, 128 Analog 2.1V power supply. EVDD18 Power 46, 52, 53 Analog 1.8V power supply. A VDD33 Power 14, 124 Analog 3.3V power supply. EGND Power 49, 56 Analog Ground. Note: Refer to the most updated schematic circuit for correct configuration. Table 9. NC (Not Connected) Pins

Integrated Gigabit Ethernet Controller for PCI Express 7 Track ID: JATR-1076-21 Rev. 1.2 6. Functional Description 6.1. PCI Express Bus Interface The RTL8111 is compliant with PCI Express Base Specification Revision 1.0a, and runs at a 2.5GHz signaling rate with X1 link width, i.e., one tran smit and one receive diffe rential pair. The RTL8111 supports four types of PCI Express messages: inte rrupt messages, error messages, power management messages, and hot-plug messages. The PCI Express la ne polarity reversal and link reversal are also supported to ease PCB layout constraints. 6.1.1. PCI Express Transmitter The RTL8111’s PCI Express block receives digital data from the Ethernet interface and performs data scrambling with Linear Feedback Shift Register (L FSR) and 8B/10B coding tec hnology into 10-bit code groups. Data scrambling is used to reduce the possibili ty of electrical resona nce on the link, and 8B/10B coding technology is used to benefit embedded clocking, error detection, and DC balance by sacrificing a 25 percent overhead to the system through the additi on of 2 extra bits. The data code groups are passed through its serializer for packet framing. The genera ted 2.5Gbps serial data is transmitted onto the PCB trace to its upstream device via a differential driver. 6.1.2. PCI Express Receiver The RTL8111’s PCI Express block receives 2.5Gbps serial data from its upstream device to generate parallel data. The receiver’s PLL circuits are resync hronized to maintain bit and symbol lock. Through 8B/10B decoding technology and data descrambling, the original digital data is recovered and passed to the RTL8111’s internal Ethernet MAC to be transmitted onto the Ethernet media. 6.2. LED Functions The RTL8111 supports 4 LED signals in 4 different configurable operation modes. The following sections describe the various LED actions. 6.2.1. Link Monitor The Link Monitor senses link integrity, su ch as LINK10, LINK100, LINK1000, LINK10/100/1000, LINK10/ACT, LINK100/ACT, or LINK 1000/ACT. Whenever link status is established, the specific link LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no network connection exists.

Figure 4. Tx/Rx LED

operating properly. When this LED is high for extended periods, it indicates that a link problem exists. Figure 5. LINK/ACT LED

Integrated Gigabit Ethernet Controller for PCI Express 1 1 Track ID: JATR-1076-21 Rev. 1.2 6.3. PHY Transceiver 6.3.1. PHY Transmitter Based on state-of-the-art DSP t echnology and mixed-mode signal pr ocessing technology, the RTL8111 operates at 10/100/1000Mbps over standard CA T.5 UTP cable (100/1000Mbps), and CAT.3 UTP cable (10Mbps). GMII (1000Mbps) Mode The RTL8111’s PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continuous code -groups through 4D-PAM5 coding technology. These code groups are passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a D/A converter. MII (100Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125Mhz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media. MII (10Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. The 10Mbps serial data is convert ed into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter. 6.3.2. PHY Receiver GMII (1000Mbps) Mode Input signals from the media pass through the sophi sticated on-chip hybrid circuit to subtract the transmitted signal from the input signal for effectiv e reduction of near-end echo. Afterwards, the received signal is processed with state-of -the-art technology, e.g., adaptive e qualization, BLW (Baseline Wander) correction, cross-talk cancellati on, echo cancellation, timing recover y, error correction, and 4D-PAM5 decoding. Then, the 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the Rx Buffer Manager. MII (100Mbps) Mode The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B /5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz. MII (10Mbps) Mode The received differential signal is converted into a Manchester-encoded st ream first. Next, the stream is processed with a Manchester decoder and is de-seria lized into 4-bit-wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz.

Reg8 as defined in IEEE 802.3ab. consists of EESK, EECS, EEDO, and EEDI. Table 10. EEPROM Interface EECS 93C46/93C56 chip select. EESK EEPROM serial data clock. Input data bus/Input pin to detect if Aux. Power exists on initial power-on. pulled high to Aux. Power, the RTL8111 assumes that no Aux. Power exists.

Integrated Gigabit Ethernet Controller for PCI Express 1 3 Track ID: JATR-1076-21 Rev. 1.2 6.6. Power Management The RTL8111 is compliant with ACPI (Rev 1. 0, 1.0b, 2.0), PCI Power Management (Rev 1.1), PCI Express Active State Power Management (ASPM) , and Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8111 can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via a PCI Express Power Management Event (PME) Message, B eacon, or LANWAKEB pin when such a packet or event occurs. Then the system can be restored to a normal state to process incoming jobs. When the RTL8111 is in power down mode (D1 ~ D3):

• The Rx state machine is stopped. The RTL8111 monitors the network for wakeup events such as a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8111 will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx on-chip buffer.
• The on-chip buffer status and packets that have already been received into the Rx on-chip buffer before entering power down mode are held by the RTL8111.
• Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held.
• After being restored to D0 state, the RTL8111 transmits data that was not moved into the Tx on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI configuration space depend on the existence of Aux power (bit15, PMC) = 1. If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s. Example: If EEPROM D3c_support_PME = 1:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 F7, then PCI PMC = C2 F7)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 F7, then PCI PMC = 02 76) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C2 F7 (Realtek EEPROM default value). If EEPROM D3c_support_PME = 0:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 77, then PCI PMC = C2 77)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 77, then PCI PMC = 02 76)

Integrated Gigabit Ethernet Controller for PCI Express 1 4 Track ID: JATR-1076-21 Rev. 1.2 In the above case, if wakeup support is not desired wh en main power is off, it is suggested that the EEPROM PMC be set to 02 76. Link Wakeup occurs only when the following conditions are met:

• The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponded wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state. Magic Packet Wakeup occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8111, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8111 adapter.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state.
• The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame is acceptable to the RTL8111, e.g., a broadcast, multicast, or unicast address to the current RTL8111 adapter.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 16-bit CRCA of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8111 is configured to allow direct packet wakeup, e.g., a broadcast, multicast, or unicast network packet. Note: 16-bit CRC: The RTL8111 supports two normal wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). The corresponding wake-up method (message, beacon, or LANWAKEB) is asserted only when the following conditions are met:
• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8111 may assert the corresponding wake-up method (message, beacon, or LANWAKEB) in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wakeup Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8111 to stop asserting the corresponding wake-up method (message, beacon, or LANWAKEB) (if enabled).

Integrated Gigabit Ethernet Controller for PCI Express 1 5 Track ID: JATR-1076-21 Rev. 1.2 When the RTL8111 is in power down mode, e.g., D1-D3, the IO and MEM accesses to the RTL8111 are disabled. After a PERSTB assertion, the device’s power state is restored to D0 automatically if the original power state was D3cold. There is almost no hardware delay at th e device’s power state transition. When in ACPI mode, the device does not support PME (Power Ma nagement Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The setting may be changed from the EEPROM, if required. 6.7. Vital Product Data (VPD) Bit 31 of the Vital Product Data (VPD) capability st ructure in the RTL8111’s PCI Configuration Space is used to issue VPD read/write commands and is also a fl ag used to indicate whet her the transfer of data between the VPD data register and the 93C46/93C56 has completed or not. 1. Write VPD register: (write data to the 93C46/93C56) Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When the flag bit is reset to 0 by the RTL8111, the VPD data (4 bytes per VPD access) has been transferred from the VPD data register to EEPROM. 2. Read VPD register: (read data from the 93C46/93C56) Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM. When the flag bit is set to 1 by the RTL8111, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data register. Note 1: Refer to the PCI 2.2 Specifications for further information. Note 2: The VPD address must be a DWORD-aligne d address as defined in the PCI 2.2 Specifications. VPD data is always consecutive 4-byte data starting from the VPD address specified. Note 3: Realtek reserves offset 40h to 7Fh in EEPROM mainly for VPD data to be stored. Note 4: The VPD function of the RTL8111 is designed to be able to access the full range of the 93C46/93C56 EEPROM.

Table 11. Absolute Maximum Ratings

• Refer to the most updated schematic circuit for correct configuration.

Table 12. Recommended Operating Conditions

• Refer to the most updated schematic circuit for correct configuration.

Table 13. Crystal Requirements fundamental mode, AT-cut type.

Table 14. Thermal Characteristics Table 15. DC Characteristics

• Refer to the most updated schematic circuit for correct configuration.

Figure 6. Serial EEPROM Interface Timing Table 16. EEPROM Access Timing Parameters

Table 17. Differential Transmitter Parameters Note 1: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter. which requires the two communicating ports be modulated such that they never exceed a total of 600 ppm difference.

Table 18. Differential Receiver Parameters Note: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter. Table 19. REFCLK Parameters Note 1: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter. must meet the absolute and relative crossing point specifications simultaneously. Note 3: The nominal single-ended swing for each clock is 0 to 0.7V with a nominal frequency of 100MHz ±300 PPM. Note 4: The reference clocks may support spread spectrum clocking. The minimum clock period cannot be violated.

Figure 10. REFCLK V cross Range Table 20. Auxiliary Signal Timing Parameters

3.3 Vaux

Figure 11. Auxiliary Signal Timing

Integrated Gigabit Ethernet Controller for PCI Express 2 3 Track ID: JATR-1076-21 Rev. 1.2 8. Mechanical Dimensions SEE DETAIL “A” SEE DETAIL “F” GAGE PLANE DETAIL “A” BASE METAL WITH PLATING SEATING PLANEDETAIL “F” See the Mechanical Dimensions notes on the next page.

Min Typical Max Min Typical Max 1. Dimensions D & E do not include interlead flash. A - - 0.134 - - 3.40 2. Dimension b does not include dambar rotrusion/intrusion. θ 0° - 12° 0° - 12° REALTEK SEMICONDUCTOR CORP. Table 21. Ordering Information Note: See page 3 for lead (Pb)-free package ID information. Industrial Park, Hsinchu, 300, Taiwan, R.O.C.