RTL8102E-GR

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INTEGRATED FAST ETHERNET CONTROLLER FOR PCI EXPRESS™ APPLICATIONS DATASHEET Rev. 1.0

15 June 2007

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw RTL8102E-GR

Integrated Fast Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.0 COPYRIGHT ©2007 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2007/06/15 First Release

Integrated Fast Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.0 Table of Contents

Integrated Fast Ethernet Controller for PCI Express iv Track ID: JATR-1076-21 Rev. 1.0

Integrated Fast Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.0 1. General Description The Realtek RTL8102E-GR Fast Ethernet contro ller combines an IEEE 802.3 10/100Base-T compliant Media Access Controller (MAC), PCI Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8102E-GR offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP ( 10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polar ity correction, adaptive equaliza tion, cross-talk cancellation, echo cancellation, timing recovery, and error correction ar e implemented to provide robust transmission and reception capability at high speeds. The device supports the PCI Express 1.1 bus interface fo r host communications with power management and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet. It also supports an auxiliary power auto-detect function, and will auto-c onfigure related bits of the PCI power management registers in PCI configuration space. Advanced Configuration Power management In terface (ACPI)—power mana gement for modern operating systems that are capable of Operati ng System-directed Power Management (OSPM)—is supported to achieve the most ef ficient power management possibl e. PCI MSI (Message Signaled Interrupt) and MSI-X are also supported. In addition to the ACPI feature, remo te wake-up (including AMD Magic Packet ™ and Microsoft ® Wake-up frame) is supported in both ACPI and AP M (Advanced Power Management) environments. To support WOL from a deep power down state (e.g., D3co ld, i.e. main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8102E-GR. The RTL8102E-GR is fully compliant with Microsoft ® NDIS5, NDIS6(IPv4, IPv6, TCP, UDP) Checksum and Segmentation Task-offload(Large send and Giant send) features, and supports IEEE 802 IP Layer 2 priority encoding a nd IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. The RTL8102E-GR supports Receive Side Scaling (RSS) to hash incomi ng TCP connections and load-balance received data processing across multiple CPUs. RSS improves the number of transactions per second and number of connections per second, for increased network throughput. The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low pin count, serial, interconnect tec hnology that offers significant improvements in performance over conventional PCI and also maintains software compatib ility with existin g PCI infrastructure. The device embeds an adaptive equalizer in the PCIe PHY for eas e of system integration and excellent link quality. The equalizer enables the length of the PCB traces to reach 40 inches. The RTL8102E-GR is suitable for multiple market segm ents and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications.

Integrated Fast Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.0 2. Features „ Integrated 10/100 transceiver „ Auto-Negotiation with Next Page capability „ Supports PCI Express™ 1.1 „ Supports pair swap/polarity/skew correction „ Crossover Detection & Auto-Correction „ Wake-on-LAN and remote wake-up support „ Microsoft® NDIS5, NDIS6 Checksum Offload (IPv4, IPv6, TCP, UDP) and Segmentation Task-offload (Large send and Giant send) support „ Supports Full Duplex flow control (IEEE 802.3x) „ Fully complies with IEEE 802.3, IEEE 802.3u „ Supports IEEE 802.1P Layer 2 Priority Encoding „ Supports IEEE 802.1Q VLAN tagging „ Serial EEPROM „ Transmit/Receive on-chip buffer support „ Supports power down/link down power saving „ Supports PCI MSI (Message Signaled Interrupt) and MSI-X „ Supports Receive-Side Scaling (RSS) „ 64-pin QFN package (Green package) „ Embeds an adaptive equalizer in PCI express PHY (PCB traces to reach 40 inches) 3. System Applications „ PCI Express™ Fast Ethernet on Mother board, Notebook, or Embedded system

65 GND ( Exposed

Figure 1. Pin Assignments Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.

Table 1. Power Management/Isolation LANWAKEB O/D 19 Power Management Event: Open drain, active low. Used to reactivate the PCI Express slot’s main power rails and reference clocks. sample its PCI Express input as long as the Isolate pin is asserted. Table 2. PCI Express Interface REFCLK_N I 27 PCI Express Differential Reference Clock Source: 100MHz ± 300ppm. HSON O 30 PCI Express Transmit Differential Pair. HSIN I 24 PCI Express Receive Differential Pair. PCI Express Reset Signal: Active low. after the de-assertion of the PERSTB. request starting of the PCI Express reference clock.

Table 3. EEPROM EESK O 48 Serial data clock. EEDI: Output to serial data input pin of EEPROM. AUX: Input pin to detect if Aux. Power exists or not on initial power-on. RTL8102E-GR assumes that no Aux. Power exists. EEDO I 45 Input from serial data output pin of EEPROM. EECS O 44 EECS: EEPROM chip select. Table 4. Transceiver Interface pair in 10Base-T and 100Base-TX. pair in 10Base-T and 100Base-TX. Table 5. Clock CKTAL1 I 60 Input of 25MHz clock reference. CKTAL2 O 61 Output of 25MHz clock reference. Table 6. Regulator & Reference RSET I 64 Reference. External resistor reference.

Table 7. LEDs Note 1: During power down mode, the LED signals are logic high. default value of the (LEDS1, LEDS0) = (1, 1). Table 8. Power & Ground VDD33 Power 16, 37, 46, 53 Digital 3.3V power supply. DVDD12 Power 15, 21, 43, 58 Digital 1.2V power supply. A VDD12 Power 5, 8 Analog 1.2V power supply. EVDD12 Power 22, 28 Analog 1.2V power supply. A VDD33 Power 2 Analog 3.3V power supply. EGND Power 25, 31 Analog Ground. GND Power 65 Ground (Exposed Pad). VCTRL12D O 63 1.2 voltage output supplies power to the DVDD12 power pin. VCTRL12A O 1 1.2 voltage output supplies power to the A VDD12 power pin. Note: Refer to the most updated schematic circuit for correct configuration. Table 9. GPIO Pins Output GPIO Pin. This pin reflects the link up or link down state.

Table 10. JTag TRSTB I 42 Test Reset (Active Low). Table 11. NC (Not Connected) Pins

Integrated Fast Ethernet Controller for PCI Express 8 Track ID: JATR-1076-21 Rev. 1.0 6. Functional Description 6.1. PCI Express Bus Interface The RTL8102E-GR complies with PCI Express Base Sp ecification Revision 1.1, and runs at a 2.5GHz signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The RTL8102E-GR supports four types of PCI Express messages: inte rrupt messages, error messages, power management messages, and hot-plug messages. To ease PCB layout c onstraints, PCI Express lane polarity reversal and link reversal are also supported. 6.1.1. PCI Express Transmitter The RTL8102E-GR’s PCI Express block receives digital data from the Ethernet interface and performs data scrambling with Linear Feedback Shift Regi ster (LFSR) and 8B/10B c oding technology into 10-bit code groups. Data scrambling is used to reduce the possibility of el ectrical resonance on the link, and 8B/10B coding technology is used to benefit embedded cloc king, error detection, and DC balance by adding an overhead to the system through the addition of 2 extra bits. The data code groups are passed through its serializer for packet framing. The genera ted 2.5Gbps serial data is transmitted onto the PCB trace to its upstream device via a differential driver. 6.1.2. PCI Express Receiver The RTL8102E-GR’s PCI Express block receives 2.5Gbps serial data from its upstream device to generate parallel data. The receiver’s PLL circuits ar e re-synchronized to maintain bit and symbol lock. Through 8B/10B decoding technology a nd data de-scrambling, the original digital data is recovered and passed to the RTL8102E-GR’s internal Ethernet MAC to be transmitted onto the Ethernet media. 6.2. LED Functions The RTL8102E-GR supports four LED signals in four different configurable operation modes. The following sections describe the various LED actions. 6.2.1. Link Monitor The Link Monitor senses link integrity, such as LINK10, LINK100, LINK10/100, LINK10/ACT, or LINK100/ACT. Whenever link status is established, the specific link LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no network connection exists.

Figure 4. Tx/Rx LED

operating properly. When this LED is high for extended periods, it indicates that a link problem exists. Figure 5. LINK/ACT LED

encoder, then to the D/A converter and transmitted onto the media. transmitted onto the media by the D/A converter. interface in 4-bit-wide nibbles at a clock speed of 25MHz. presented to the MII interface at a clock speed of 2.5MHz. to, an external serial EEPROM device. Data). The interface consists of EESK, EECS, EEDO, and EEDI. The correct EEPROM (i.e. 93C46/93C56) must be used in order to ensure proper LAN function. Table 12. EEPROM Interface EECS 93C46/93C56 chip select. EESK EEPROM serial data clock. Input data bus/Input pin to detect whether Aux. Power exists on initial power-on. not pulled high to Aux. Power, the RTL8102E-GR assumes that no Aux. Power exists.

Integrated Fast Ethernet Controller for PCI Express 13 Track ID: JATR-1076-21 Rev. 1.0 6.5. Power Management The RTL8102E-GR is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), PCI Express Active State Power Management (ASPM) , and Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8102E-GR can monitor the network for a Wakeup Frame, a Magic Packet, and notify the system via a PCI Express Power Management Event (PME) Message, Beacon, or LANWAKEB pin when such a packet or event occurs. Then the system can be restored to a normal state to process incoming jobs. When the RTL8102E-GR is in power down mode (D1 ~ D3):

• The Rx state machine is stopped. The RTL8102E-GR monitors the network for wakeup events such as a Magic Packet and Wakeup Frame in order to wake up the system. When in power down mode, the RTL8102E-GR will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx on-chip buffer.
• The on-chip buffer status and packets that have already been received into the Rx on-chip buffer before entering power down mode are held by the RTL8102E-GR.
• Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held.
• After being restored to D0 state, the RTL8102E-GR transmits data that was not moved into the Tx on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. The D3cold_support_PME bit (bit15, PMC register) a nd the Aux_I_b2:0 bits (bit8 :6, PMC register) in PCI configuration space depend on the existence of Aux power. If aux. pow er is absent, the above 4 bits are all 0 in binary. Example: If EEPROM D3c_support_PME = 1:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C3 FF, then PCI PMC = C3 FF)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C3 FF, then PCI PMC = 03 7E) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C3 F7 (Realtek EEPROM default value). If EEPROM D3c_support_PME = 0:
• If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C3 7F, then PCI PMC = C3 7F)
• If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C3 7F, then PCI PMC = 03 7E) In the above case, if wakeup support is not desired wh en main power is off, it is suggested that the EEPROM PMC be set to 03 7E.

Integrated Fast Ethernet Controller for PCI Express 14 Track ID: JATR-1076-21 Rev. 1.0 Magic Packet Wakeup occurs only when the following conditions are met:

• The destination address of the received Magic Packet is acceptable to the RTL8102E-GR, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8102E-GR adapter.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state.
• The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame is acceptable to the RTL8102E-GR, e.g., a broadcast, multicast, or unicast address to the current RTL8102E-GR adapter.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 16-bit CRC * of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8102E-GR is configured to allow direct packet wakeup, e.g., a broadcast, multicast, or unicast network packet. Note: 16-bit CRC: The RTL8102E-GR supports eight l ong wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). The corresponding wake-up method (message, beacon, or LANWAKEB) is asserted only when the following conditions are met:
• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8102E-GR may assert the corresponding wake-up method (message, beacon, or LANWAKEB) in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space.
• A Magic Packet, LinkUp, or Wakeup Frame has been received.
• Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8102E-GR to stop asserting the corresponding wake-up method (message, beacon, or LANWAKEB) (if enabled). When the RTL8102E-GR is in power down mode, e.g., D1-D3, the IO and MEM accesses to the RTL8102E-GR are disabled. After a PERSTB assertion, the device’s power state is restored to D0 automatically if the original power state was D3 cold. There is almost no hardware delay at the device’s power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The setting may be changed from the EEPROM, if required.

Integrated Fast Ethernet Controller for PCI Express 15 Track ID: JATR-1076-21 Rev. 1.0 6.6. Vital Product Data (VPD) Bit 31 of the Vital Product Data (VPD) capability structure in the RTL8102E-GR’s PCI Configuration Space is used to issue VPD read/write commands and is also a flag used to in dicate whether the transfer of data between the VPD data register and the 93C46/93C56/93C66 has completed or not. Write VPD register: (write data to the 93C46/93C56/93C66) Set the flag bit to 1 at the same time the VPD addr ess is written to write VPD data to EEPROM. When the flag bit is reset to 0 by the RTL8102E-GR, the VPD data (4 bytes per VPD access) has been transferred from the VPD data register to EEPROM. Read VPD register: (read data from the 93C46/93C56/93C66) Reset the flag bit to 0 at the same time the VPD addr ess is written to retrieve VPD data from EEPROM. When the flag bit is set to 1 by the RTL8102E-GR, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data register. Note1: Refer to the PCI 2.3 Specifications for further information. Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.3 Specifications. VPD data is always consecutive 4-byte data starting from the VPD address specified. Note3: Realtek reserves offset 60h to 7Fh in EEPROM mainly for VPD data to be stored. Note4: The VPD function of the RTL8102E-GR is designed to be able to access the full range of the 93C46/93C56/93C66 EEPROM.

Figure 6. Message Capability Structure

Table 13. Message Control

7 RO 64-bit address capable 1: The RTL8102E-GR is capable of generating a 64-bit

This bit is read only and the RTL8102E-GR is set to 1. the number of requested messages/vectors). This field after PCI reset is ‘000’.

110 Reserved

111 Reserved

RTL8102E-GR requested vectors. The RTL8102E-GR supports only one vector messages/vectors.

0 RW MSI Enable 1: Enable MSI (the INTx pin is disabled automatically as MSI and

INTx are mutually exclusive), this bit is set by system software. Table 14. Message Address 31:02 RW Message Address System-specified message/vector address. Low DWORD aligned address for MSI memory write transaction. 01:00 RO Reserved Always return ‘00’.

Table 15. Message Upper Address 31:00 RW Message Upper Address System-specified message/vector upper address. Upper 32 bits of a 64-bit message/vector address. Table 16. Message Data onto the lower word of the memory write transaction’s data phase.

Table 17. Message Control

15 RW MSI-X Enable If 1, and the MSI Enable bit in the MSI Message Control register

is prohibited from using its INTx# pin. This bit’s state after reset is 0 (MSI-X is disabled).

14 RW Function Mask If 1, all of the vector s associated with the function are masked,

regardless of their per-vector Mask bit states. 13:11 RO Reserved Always returns 0 on a read. A write operation has no effect. Table 18. Table Offset/BIR by software to form a 32bit QWORD-aligned offset.

the function’s MSI-X Table into Memory Space.

6 Reserved

7 Reserved

RTL8102E-GR located beginning at 20h. Table 19. PBA Offset/PBA BIR zero) by software to form a 32-bit QWORD-aligned offset. value definitions are identical to those for the MSI-X Table BIR. Table 20. Message Address for MSI-X Table Entries 31:02 RW Message Address System-sp ecified message lower address. address for the memory write transaction. zeroes to these two bits; otherwise the result is undefined. The state of these bits after reset must be 0. These bits are permitted to be read only or read/write.

Table 21. Message Upper Address for MSI-X Table Entries 31:00 RW Message Upper Address System-specified message upper address bits. Table 22. Message Data 31:00 RW Message Data System-specified message data. Table 23. Vector Control for MSI-X Table Entries

00 RW Mask Bit When this bit is set, the function is prohibited from sending a

Table 24. Pending Bits for MSI-X PBA Entries to Pending Bits, the result is undefined. Each Pending Bit’s state after reset is 0 (no message pending). These bits are permitted to be read only or read/write.

Integrated Fast Ethernet Controller for PCI Express 23 Track ID: JATR-1076-21 Rev. 1.0 6.9. Receive-Side Scaling (RSS) The RTL8102E-GR is compliant with the Netw ork Driver Interface Specification (NDIS) 6.0 Receive-Side Scaling (RSS) technology for the Micr osoft Windows family of operating systems. RSS allows packet receive-processing from a network adap ter to be balanced across the number of available computer processors, increasing performance on multi-CPU platforms. 6.9.1. Receive-Side Scaling (RSS) Initialization During RSS initialization, the Windows operating sy stem will inform the RTL8102E-GR to store the following parameters: hash function, hash type, hash bits, indirection table, BaseCPUNumber, and the secret hash key. Hash Function The default hash function is the Toeplitz hash function. Hash Type The hash types indicate which field of the packet n eeds to be hashed to get the hash result. There are several combinations of these fields, mainl y, TCP/IPv4, IPv4, TCP/IPv6, IPv6, and IPv6 extension headers.

• TCP/IPv4 requires hash calculations over the IPv4 source address, the IPv4 destination address, the source TCP port and the destination TCP port.
• IPv4 requires hash calculations over the IPv4 source address and the IPv4 destination address.
• TCP/IPv6 requires hash calculations over the IPv6 source address, the IPv6 destination address, the source TCP port and the destination TCP port.
• IPv6 requires hash calculations over the IPv6 source address and the IPv6 destination address (Note: The RTL8102E-GR does not support the IPv6 extension header hash type in RSS). Hash Bits Hash bits are used to index the hash result into the indirection table

Integrated Fast Ethernet Controller for PCI Express 24 Track ID: JATR-1076-21 Rev. 1.0 Indirection Table The Indirection Table stores values that are added to the BaseCPUNumber to enable RSS interrupts to be restricted from some CPUs. The OS will update the Indirection Table to rebalance the load. BaseCPUNumber The lowest number CPU to use for RSS. BaseCPUNumber is added to the result of the indirection table lookup. Secret hash key The key used in the Toeplitz function. For different hash types, the key size is different. 6.9.2. RSS Operation After the parameters are set, the RTL8102E-GR will start hash calculation on each incoming packet and forward each packet to its correct qu eue according to the hash result. If the incoming packet is not in the hash type, it will be forwarded to the primary queue. The hash result plus the BaseCP UNumber will be indexed into the indirection table to get the correct CP U number. The RTL8102E-GR uses three methods to inform the system of incoming packets: inline interrupt, MSI, and MSIX. Periodically the OS will update the indirection table to rebalance the load across the CPUs.

Table 25. Absolute Maximum Ratings

• Refer to the most updated schematic circuit for correct configuration.

Table 26. Recommended Operating Conditions

• Refer to the most updated schematic circuit for correct configuration.

Table 27. Crystal Requirements fundamental mode, AT-cut type.

Table 28. Thermal Characteristics Table 29. DC Characteristics

• Refer to the most updated schematic circuit for correct configuration.

Figure 10. Serial EEPROM Interface Timing

Table 30. EEPROM Access Timing Parameters

Table 31. Differential Transmitter Parameters Note1: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter.

Table 32. Differential Receiver Parameters Note: Refer to PCI Express Base Specification, rev.1.1, for correct measurement environment setting of each parameter. Table 33. REFCLK Parameters

Integrated Fast Ethernet Controller for PCI Express 31 Track ID: JATR-1076-21 Rev. 1.0 Symbol Parameter 100MHz Input M i n M a x Units Note Duty Cycle Duty Cycle 40 60 % 2 Rise-Fall Matching Rising edge rate (REFCLK+) to falling edge rate (REFCLK-) matching - 20 % 1,14 ZC-DC Clock source DC impedance 40 60 Ω 1,11 Note1: Measurement taken from single ended waveform. Note2: Measurement taken from differential waveform. Note3: Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. See Figure 14, page 33. Note4: Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. See Figure 10, page 27. Note5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Figure 10, page 27. Note6: Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread spectrum modulation. See Figure 13, page 32. Note7: Defined as the maximum instantaneous voltage including overshoot. See Figure 10, page 27. Note8: Defined as the minimum instantaneous voltage including undershoot. See Figure 10, page 27. Note9: Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS for any particular system. See Figure 11, page 32. Note10: Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations. Note11: System board compliance measurements must use the test load card described in Figure16. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load C L = 2 pF . Note12: TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is allowed to droop back into the VRB ±100 mV differential range. See Figure 15. Note13: PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly or 100 Hz. For 300 PPM then we have a error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency counter with measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread Spectrum there is an additional 2500 PPM nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800 PPM Note14: Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 12, page 32. Note15: Refer to PCI Express Card Electromechanical Specification, rev.1.1, for correct measurement environment setting of each parameter.

Figure 17. Reference Clock System Measurement Point and Loading Table 34. Auxiliary Signal Timing Parameters

3.3 Vaux

Figure 18. Auxiliary Signal Timing

Table 35. Ordering Information Note: See page 3 for Green package and version identification.