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SINGLE-CHIP FAST ETHERNET CONTROLLER AND MC’97 CONTROLLER WITH POWER MANAGEMENT DATASHEET Rev. 1.5

20 April 2006

Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com.tw

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management ii Track ID: JATR-1076-21 Rev. 1. 5 COPYRIGHT ©2006 Realtek Semiconductor Corp. A ll rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular pu rpose. Realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document provides detailed us er guidelines to achieve the best performance when implementing a 2-layer board PC design with the RTL8101L Single-Ch ip Fast Ethernet Controller and MC’97 Controller with Power Management control. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the productio n of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.5 2006/04/20 First official release.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management iii Track ID: JATR-1076-21 Rev. 1. 5 Table of Contents

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management ii Track ID: JATR-1076-21 Rev. 1. 5

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management iii Track ID: JATR-1076-21 Rev. 1. 5

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management iv Track ID: JATR-1076-21 Rev. 1. 5

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 1 Track ID: JATR-1076-21 Rev. 1. 5 1. General Description The Realtek RTL8101L is a highly integrated and cost-e ffective single-chip Fast Ethernet controller that provides 32-bit performance, PC I bus master capability, and full compliance with IEEE 802.3u 100Base-TX specifications and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface (ACPI), PCI power mana gement for modern operating systems that are capable of Operating System Dir ected Power Management (OSPM) to achieve the most efficient power management possible. The RTL8101L no longer supports CardBus mode (the RTL8139C does). In addition to the ACPI feature, the RTL8101L suppor ts remote wake-up (including AMD Magic Packet, LinkChg, and Microsoft ® wake-up frame) in both ACPI and APM environments. The RTL8101L is capable of performing an internal reset through the application of auxiliary power. When auxiliary power is applied and the main power remains off, the RTL8101L is ready and waiting for a Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8101L LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality. The RTL8101L also supports Analog Auto-Power-down, th at is, the analog part of the RTL8101L can be shut down temporarily according to user requirements or when the RTL8101L is in a power down state with the wakeup function disabled. In add ition, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), th en both the analog and digital pa rts stop functioning and the power consumption of the RTL8101L is negligible. The RTL8101L also supports an auxiliary power auto-detect function, and will auto-configure rela ted bits of their own PCI power management registers in PCI configuration space. PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the OEM brand name of the RTL8101L LAN card). The information may consist of part number, serial number, and other detailed information. To provide cost down support, the RTL8101L is capable of using a 25MHz crystal or OSC as its internal clock source. The RTL8101L keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps bandwidth possible at no additional cost. To improve compatibility with other brands’ products, the RTL8101L is also capable of re ceiving packets with InterFrameGa p no less than 40 Bit-Time. The RTL8101L is highly integrated and requires no ‘glue’ logic or external memory. The RTL8101L includes a PCI and Expansion Memory Share Interface (Realtek patent) for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of management.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 2 Track ID: JATR-1076-21 Rev. 1. 5 2. Features 2.1. Ethernet Controller Features „ 100 pin LQFP „ Integrated Fast Ethernet MAC, Physical chip, and transceiver in one chip „ 10Mbps and 100Mbps operation „ Supports 10Mbps and 100Mbps N-way Auto-negotiation „ PCI local bus single-chip Fast Ethernet controller „ Complies with PCI Revision 2.2 „ Supports PCI clock 16.75MHz-40MHz „ Supports PCI target fast back-to-back transaction „ Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of RTL8101L's operational registers „ Supports PCI VPD (Vital Product Data) „ Supports ACPI, PCI power management „ Supports 25MHz crystal or 25MHz OSC as the internal clock source. The frequency deviation of either crystal or OSC must be within 50 PPM. „ Complies with to PC99/PC2001 standard „ Supports Wake-On-LAN function and remote wake-up (Magic Packet, LinkChg and Microsoft® wake-up frame) „ Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse) „ Supports auxiliary power-on internal reset, for remote wake-up when main power remains off „ Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI configuration space „ Includes a programmable PCI burst size and early Tx/Rx threshold „ Supports a 32-bit general-purpose timer with the external PCI clock as clock source to generate a timer-interrupt „ Contains two large (2Kbyte) independent receive and transmit FIFOs „ Advanced power saving mode when LAN function or wakeup function is not used „ Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data „ Supports LED pins for various network activity indications „ Supports loopback capability „ Half/Full duplex capability „ Supports Full Duplex Flow Control (IEEE 802.3x) 3.3V power supply, 3.3V and 5V I/O tolerance „ Interface for 128K byte (max) Boot ROM for both EEPROM and Flash Memory

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 3 Track ID: JATR-1076-21 Rev. 1. 5 2.2. MC’97 Controller Features „ MC’97 compatible digital controller chip „ PCI local bus single-chip Fast Ethernet controller „ 32-bit PCI bus master and PCI v 2.2 compliant „ PCI Bus Power Management Interface Specification v 1.1 compliant „ High performance bus master DMA for data transfer „ AC’97 v 2.2 compliant „ Supports 16-bit modem line (LINE1) „ Full-duplex operation for simultaneous LINE1 transactions „ Low latency GPIO updated „ 8 double-WORD (16 samples) FIFO depth for each bus master of LINE1-OUT/IN „ 3.3V power supply, 3.3V and 5V I/O tolerance 3. System Applications „ Ethernet Network Interface Controller „ Lan On Motherboard „ Embedded System

3 Level

Figure 1. Block Diagram

Figure 2. Pin Assignments indicated by an ‘L’. The version is indicated by the letter shown in the location marked ‘V’.

T/S: Tri-State bi-directional input/output pin. Note that some pins have multiple functions. See Figure 2, on page 5, for a graphical representation. Table 1. Power Management/Isolation Interface O/D 57 Power Management Event. management event has occurred. I 74 Isolate Pin: Active low. LWAKE O 64 LAN WAKE-UP Signal. Signals to the motherboard that it should execute the wake-up process. LWAKE asserts only when PMEB asserts and ISOLATEB is low. This pin is a 3.3V signaling output pin.

Table 2. PCI Interface C/BE3-0 T/S 84, 17, 27, 38 PCI bus command and byte enables multiplexed pins. each phase. The clock frequency ranges from 0 to 33MHz. recognizes its target address after FRAMEB is asserted. a bus transaction. While FRAMEB is asserted, data transfer continues. address to check if the current transaction is addressed to it. central arbiter has granted ownership of the bus to the RTL8101L. This input is used when the RTL8101L is acting as a bus master. ownership of the bus from the central arbiter. when configuration read/write transactions are intended for it. Mask and Interrupt Enable registers. the current data phase of the transaction. current phase of the transaction. data during write operations and with the data during read operations.

RTL8101L asserts this PERRB pin low. Table 3. EEPROM Interface existence of Aux. power during initial power-on or a PCI reset. RTL8101L assumes that no Aux. power exists. programming or auto-load mode. programming or auto-load mode. EECS O 55 EEPROM chip select.

Table 4. Power Pins Table 5. LED Interface During power down mode, the LEDs are OFF. modem-only mode and a 93C46 is not necessary. Table 6. Attachment Unit Interface 10/100Base-T Transmit (TX) data. 10/100Base-T Receive (RX) data. X1 I 61 25MHz Crystal/OSC Input. X2 O 60 Crystal Feedback Output. X1 is driven with an external 25MHz oscillator.

Table 7. AC-Link Pins AC_RSTB O 1 MC’97 Reset: Hardware reset to Codec. AC_SYNC O 3 MC’97 SYNC: 48Khz fixed rate sample sync to Codec. AC_DOUT O 4 MC’97 Serial Data Out: Serial data output to Codec. AC_DIN I 5 MC’97 Serial Data In: Serial data input from Codec. AC_BCK I 7 MC’97 Bit Clock: 12.288Mhz serial data clock generated by Codec. INTBB O/D 79 INTBB is used for function 1 device (Modem) to request an interrupt. by bit0-1 of PCI GPIO Setup Register. Table 8. Test and Other Pins RTSET I/O 65 This pin must be pulled low by a resistor. asserted, and for driving it high to the negated (deasserted) state. output enable of the Boot PROM.

1. Ethernet Controller Register Descriptions

Table 9. Register Descriptions 0000h R/W IDR0 ID Register 0. ID registers 0-5 are only permitted to read/write via 4-byte access. value is auto-loaded from the EEPROM EthernetID field. 0001h R/W IDR1 ID Register 1. 0002h R/W IDR2 ID Register 2. 0003h R/W IDR3 ID Register 3. 0004h R/W IDR4 ID Register 4. 0005h R/W IDR5 ID Register 5. 0008h R/W MAR0 Multicast Address Register 0. driver is responsible for initializing these registers. 0009h R/W MAR1 Multicast Address Register 1. 000Ah R/W MAR2 Multicast Address Register 2. 000Bh R/W MAR3 Multicast Address Register 3. 000Ch R/W MAR4 Multicast Address Register 4. 000Dh R/W MAR5 Multicast Address Register 5. 000Eh R/W MAR6 Multicast Address Register 6. 000Fh R/W MAR7 Multicast Address Register 7. 0010h-0013h R/W TSD0 Transmit Status of Descriptor 0. 0014h-0017h R/W TSD1 Transmit Status of Descriptor 1. 0018h-001Bh R/W TSD2 Transmit Status of Descriptor 2. 001Ch-001Fh R/W TSD3 Transmit Status of Descriptor 3. 0020h-0023h R/W TSAD0 Transmit Start Address of Descriptor 0. 0024h-0027h R/W TSAD1 Transmit Start Address of Descriptor 1. 0028h-002Bh R/W TSAD2 Transmit Start Address of Descriptor 2. 002Ch-002Fh R/W TSAD3 Transmit Start Address of Descriptor 3. 0030h-0033h R/W RBSTART Receive (Rx) Buffer Start Address. 0034h-0035h R ERBCR Early Receive (Rx) Byte Count Register. 0036h R ERSR Early Rx Status Register. 0037h R/W CR Command Register. 0038h-0039h R/W CAPR Current Address of Packet Read. 003Ah-003Bh R CBR Current Buffer Address. 003Ch-003Dh R/W IMR Interrupt Mask Register.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 12 Track ID: JATR-1076-21 Rev. 1. 5 Offset R/W Tag Description 003Eh-003Fh R/W ISR Interrupt Status Register. 0040h-0043h R/W TCR Transmit (Tx) Configuration Register. 0044h-0047h R/W RCR Receive (Rx) Configuration Register. 0048h-004Bh R/W TCTR Timer CounT Register. This register contains a 32-bit general-purpose timer. Writing any value to this register will reset the original timer and start a count from zero. 004Ch-004Fh R/W MPC Missed Packet Counter. Indicates the number of packets discarded due to Rx FIFO overflow. It is a 24-bit counter. After s/w reset, MPC is cleared. Only the lower 3 bytes are valid. When any value is written, MPC will be reset also. 0050h R/W 9346CR 93C46 Command Register. 0051h R/W CONFIG0 Configuration Register 0. 0052h R/W CONFIG1 Configuration Register 1. 0053H - - Reserved. 0054h-0057h R /W TimerInt Timer Interrupt Register. Once having written a non-zero value to this register, the Timeout bit of the ISR register will be set whenever the TCTR reaches that value. The Timeout bit will never be set whilst the TimerInt register is zero. 0058h R/W MSR Media Status Register. 0059h R/W CONFIG3 Configuration register 3. 005Ah R/W CONFIG4 Configuration register 4. 005Bh - - Reserved. 005Ch-005Dh R/W MULINT Multiple Interrupt Select. 005Eh R RERID PCI Revision ID = 10h. 005Fh - - Reserved. 0060h-0061h R TSAD Transmit Status of All Descriptors. 0062h-0063h R/W BMCR Basic Mode Control Register. 0064h-0065h R BMSR Basic Mode Status Register. 0066h-0067h R/W ANAR Auto-Negotiation Advertisement Register. 0068h-0069h R ANLPAR Auto-Negotiation Link Partner Register. 006Ah-006Bh R ANER Auto-Negotiation Expansion Register. 006Ch-006Dh R DIS Disconnect Counter. 006Eh-006Fh R FCSC False Carrier Sense Counter. 0070h-0071h R/W NWAYTR N-way Test Register. 0072h-0073h R REC RX_ER Counter. 0074h-0075h R/W CSCR CS Configuration Register. 0076-0077h - - Reserved. 0078h-007Bh R/W PHY1_PARM PHY parameter 1. 007Ch-007Fh R/W TW_PARM Twister parameter. 0080h R/W PHY2_PARM PHY parameter 2. 0081-0083h - - Reserved. 0084h R/W CRC0 Power Management CRC register0 for wakeup frame 0.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 13 Track ID: JATR-1076-21 Rev. 1. 5 Offset R/W Tag Description 0085h R/W CRC1 Power Management CRC register1 for wakeup frame 1. 0086h R/W CRC2 Power Management CRC register2 for wakeup frame 2. 0087h R/W CRC3 Power Management CRC register3 for wakeup frame 3. 0088h R/W CRC4 Power Management CRC register4 for wakeup frame 4. 0089h R/W CRC5 Power Management CRC register5 for wakeup frame 5. 008Ah R/W CRC6 Power Management CRC register6 for wakeup frame 6. 008Bh R/W CRC7 Power Management CRC register7 for wakeup frame 7. 008Ch–0093h R/W Wakeup0 Power Management wakeup frame0 (64bit). 0094h–009Bh R/W Wakeup1 Power Management wakeup frame1 (64bit). 009Ch–00A3h R/W Wakeup2 Power Management wakeup frame2 (64bit). 00A4h–00ABh R/W Wakeup3 Power Management wakeup frame3 (64bit). 00ACh–00B3h R/W Wakeup4 Power Management wakeup frame4 (64bit). 00B4h–00BBh R/W Wakeup5 Power Management wakeup frame5 (64bit). 00BCh–00C3h R/W Wakeup6 Power Management wakeup frame6 (64bit). 00C4h–00CBh R/W Wakeup7 Power Management wakeup frame7 (64bit). 00CCh R/W LSBCRC0 LSB of the mask byte of wakeup frame0 within offset 12 to 75. 00CDh R/W LSBCRC1 LSB of the mask byte of wakeup frame1 within offset 12 to 75. 00CEh R/W LSBCRC2 LSB of the mask byte of wakeup frame2 within offset 12 to 75. 00CFh R/W LSBCRC3 LSB of the mask byte of wakeup frame3 within offset 12 to 75. 00D0h R/W LSBCRC4 LSB of the mask byte of wakeup frame4 within offset 12 to 75. 00D1h R/W LSBCRC5 LSB of the mask byte of wakeup frame5 within offset 12 to 75. 00D2h R/W LSBCRC6 LSB of the mask byte of wakeup frame6 within offset 12 to 75. 00D3h R/W LSBCRC7 LSB of the mask byte of wakeup frame7 within offset 12 to 75. 00D4h-00D7h - - Reserved. 00D8h R/W Config5 Configuration register 5. 00D9h-00FFh - - Reserved.

Table 10. Receive Status Register in RX Packet Header 15 R MAR Multicast Address Received. This bit set to 1 indicates that a multicast packet has been received. 14 R PAM Physical Address Matched. matches the value written in ID registers. 13 R BAR Broadcast Address Received. bit will not be set simultaneously. 5 R ISE Invalid Symbol Error (100Base-TX only). the reception of this packet. 4 R RUNT Runt Packet Received. 2 R CRC Cyclic Redundancy Check (CRC) Error. When set, indicates that a CRC error occurred on the received packet. 1 R FAE Frame Alignment Error. When set, indicates that a good packet was received. when software writes to these bits. These registers are only permitted to be written via double-word access. After a software reset, all bits except the OWN bit are reset to 0. Table 11. Transmit Status Register 31 R CRS Carrier Sense Lost.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 15 Track ID: JATR-1076-21 Rev. 1. 5 Bit R/W Symbol Description 30 R TABT Transmit Abort. This bit is set to 1 if the transmission of a packet was aborted. This bit is read only, writing to this bit is not affected. 29 R OWC Out of Window Collision. This bit is set to 1 if the RTL8101L encountered an ‘out of window’ collision during the transmission of a packet. 28 R CDH CD HeartBeat. The NIC watches for a collision signal (i.e., CD Heartbeat signal) during the first 6.4µs of the InterFrame Gap following a transmission. This bit is set if the transceiver fails to send this signal. This bit is cleared in 100Mbps mode. 27-24 R NCC3-0 Number of Collision Count. Indicates the number of collisions encountered during the transmission of a packet. 23-22 - - Reserved. 21-16 R/W ERTXTH5-0 Early Tx Threshold. Specifies the threshold level in the Tx FIFO to begin the transmission. When the byte count of the data in the Tx FIFO reaches this level, (or the FIFO contains at least one complete packet) the RTL8101L will transmit this packet. 000000 = 8 bytes These fields count from 000001 to 111111 in units of 32 bytes. This threshold must be prevented from exceeding 2k bytes. 15 R TOK Transmit OK. Set to 1 indicates that the transmission of a packet was completed successfully and no transmit underrun has occurred. 14 R TUN Transmit FIFO Underrun. Set to 1 if the Tx FIFO was exhausted during the transmission of a packet. The RTL8101L can re-transfer data if the Tx FIFO underruns. That is, when TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1). 13 R/W OWN OWN. The RTL8101L sets this bit to 1 when the Tx DMA operation of this descriptor has completed. The driver must set this bit to 0 when the Transmit Byte Count (bits 0-12) is written. The default value is 1. 12-0 R/W SIZE Descriptor Size. The total size in bytes of the data in this descriptor. If the packet length is more than 1792 bytes (0700h), the Tx queue will be invalid, i.e. the next descriptor will be written only after the OWN bit of that long packet’s descriptor has been set.

Table 12. ERSR: Early RX Status Register 3 R ERGood Early Rx Good packet. is good. Writing a 1 to this bit will clear it. 2 R ERBad Early Rx Bad packet. is bad. Writing a 1 to this bit will clear it. 1 R EROVW Early Rx OverWrite. another packet data from the beginning address of that error packet. Writing a 1 to this bit will clear it. simultaneously. Setting this bit will invoke an ROK interrupt.

transmitter and receiver are provided here. Table 13. Command Register will read back as a 1 whenever the receive state machine is active. 2 R/W TE Transmitter Enable. this bit. This bit will be reset after PCI reset deassertion. RX Buffer Empty. There are no packets stored in the RX buffer ring.

regardless of the state of the corresponding mask bit. Table 14. Interrupt Mask Register 15 R/W SERR System Error Interrupt. 14 R/W TimeOut Time Out Interrupt. 13 R/W LenChg Cable Length Change Interrupt. 6 R/W FOVW Rx FIFO Overflow Interrupt. 5 R/W PUN/LinkChg Packet Underrun/Link Change Interrupt. 4 R/W RXOVW Rx Buffer Overflow Interrupt. 3 R/W TER Transmit Error Interrupt. 2 R/W TOK Transmit OK Interrupt. 1 R/W RER Receive Error Interrupt. 0 R/W ROK Receive OK Interrupt.

corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR. Writing a 1 to any bit will reset that bit, but writing a 0 has no effect. Table 15. Interrupt Status Register Set to 1 when the RTL8101L signals a system error on the PCI bus. 13 R/W LenChg Cable Length Change. Cable length is changed after Receiver is enabled. 6 R/W FOVW Rx FIFO Overflow. Set when an overflow occurs on the Rx status FIFO. 5 R/W PUN/LinkChg Packet Underrun/Link Change. 4 R/W RXOVW Rx Buffer Overflow. 3 R/W TER Transmit (Tx) Error. collisions, according to the TXRR’s setting. Indicates that a packet transmission has completed successfully. 1 R/W RER Receive (Rx) Error. the length of the frame is shorter than 16 bytes. arriving packet exceeds the early Rx threshold.

Loopback, programmable InterFrame Gap, Fill and Drain Thresholds, and maximum DMA burst size. Table 16. Transmit Configuration Register Reserved Other combinations. 25, 24 R/W IFG1, 0 InterFrame Gap time. 23, 22 R HWVERID_B Hardware Version ID B. 18, 17 R/W LBK1, LBK0 Loopback test.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 21 Track ID: JATR-1076-21 Rev. 1. 5 Bit R/W Symbol Description 10~8 R/W MXDMA2, 1, 0 Max DMA Burst Size per Tx DMA Burst. This field sets the maximum size of transmit DMA data bursts according to the following table: 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = 2048 bytes 7-4 R/W TXRR Tx Retry Count. These are used to specify additional transmission retries in multiple of 16 (IEEE 802.3 CSMA/CD retry count). If the TXRR is set to 0, the transmitter will re-transmit 16 times before aborting due to excessive collisions. If the TXRR is set to a value greater than 0, the transmitter will re-transmit a number of times equals to the following formula before aborting: Total retries = 16 + (TXRR * 16) The TER bit in the ISR register or transmit descriptor will be set when the transmission fails and reaches to this specified retry count. 3-1 - - Reserved. 0 W CLRABT Clear Abort. Setting this bit to 1 causes the RTL8101L to retransmit the packet at the last transmitted descriptor when this transmission was aborted. Setting this bit is only permitted in the transmit abort state.

accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Table 17. Receive Configuration Register 27-24 R/W ERTH3, 2, 1, 0 Early Rx threshold bits. whilst the frame protocol is under the RTL8101L’s definition. 17 R/W MulERINT Multiple Early Interrupt select. according to the setting of MULINT<MISR[11:0]>. 16 R/W RER8 Receive Error 8 bytes. 1: The RTL8101L accepts error packets with a length of 8~64 bytes. 64 bytes. The power-on default is zero. RTL8101L receives an error packet with a length larger than 8 bytes. RER8 is irrelevant in this situation.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 23 Track ID: JATR-1076-21 Rev. 1. 5 Bit R/W Symbol Description 15~13 R/W RXFTH2, 1, 0 Rx FIFO Threshold. Specifies the Rx FIFO Threshold level. When the number of received data bytes from a packet that is being received into the RTL8101L’s Rx FIFO has reached this level (or the FIFO contains a complete packet), the receive PCI bus master function will begin to transfer the data from the FIFO to the host memory. This field sets the threshold level according to the following table: 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = No Rx threshold. The RTL8101L begins the transfer of data after receiving a whole packet in the FIFO. 12, 11 R/W RBLEN1, 0 Rx Buffer Length. This field indicates the size of the Rx ring buffer: 00 = 8k + 16 bytes 01 = 16k + 16 bytes 10 = 32K + 16 bytes 11 = 64K + 16 bytes 10~8 R/W MXDMA2, 1, 0 Max DMA Burst Size per Rx DMA Burst. This field sets the maximum size of the receive DMA data bursts: 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = Unlimited 7 R/W WRAP Wraps packet data into the beginning of the Rx buffer. 0: The RTL8101L will transfer the rest of the packet data into the beginning of the Rx buffer if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer. 1: The RTL8101L will keep moving the rest of the packet data into the memory immediately after the end of the Rx buffer, if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer. The software driver must reserve at least 1.5 Kbytes buffer to accept the remainder of the packet. We assume that the remainder of the packet is X bytes. The next packet will be moved into the memory from the X byte offset at the top of the Rx buffer. This bit is invalid when the Rx buffer is set to 64 Kbytes. 6 - - Reserved.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 24 Track ID: JATR-1076-21 Rev. 1. 5 Bit R/W Symbol Description 5 R/W AER Accept Error Packet. 1: Packets with CRC errors, alignment errors, and/or collided fragments will be accepted. 0: Packets with the above errors will be rejected. 4 R/W AR Accept Runt. This bit allows the receiver to accept packets that are smaller than 64 bytes. The packet must be at least 8 bytes long to be accepted as a runt. 1: Accept 0: Reject 3 R/W AB Accept Broadcast packets. 1: Accept 0: Reject 2 R/W AM Accept Multicast packets. 1: Accept 0: Reject 1 R/W APM Accept Physical Match packets. 1: Accept 0: Reject 0 R/W AAP Accept All Packets. Set to 1 to accept all packets with a physical destination address. 1: Accept 0: Reject

transmitter and receiver are also provided. Table 18. 9346CR: 93C46 Command Register 7-6 R/W EEM1-0 Operating Mode: These 2 bits set the RTL8101L operating mode. are reset to default values.

3 R/W EECS

2 R/W EESK

1 R/W EEDI

0 R EEDO

auto-load or 93C46 programming mode.

Table 19. CONFIG 0: Configuration Register 0 4-3 R PL1, PL0 10Mbps Medium Type. Select Boot ROM size (Auto-loaded from EEPROM).

Table 20. CONFIG 1: Configuration Register 1 7-6 R/W LEDS1-0 Refer to section 6.5 LED Interface, page 9, for a detailed LED pin description. The initial value of these bits comes from the 93C46. Software may use this bit to make sure that the driver has been loaded. configuration space are written, the RTL8101L will clear this bit automatically. output pulse width is about 150ms. the LWAKE pin is an active high signal.

0 Active high* Active low

4 R/W LWACT

Operational registers are mapped into PCI memory space. Operational registers are mapped into PCI I/O space. 1 R/W VPD Set to enable Vital Product Data. VPD data is stored in the 93C46 from within offset 40h-7Fh. 0 R/W PMEn Power Management Enable. Writable only when the 93C46CR register EEM1:0 = [1:1]. Configuration space offset 06H. Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H. Configuration space offset 50H. Configuration space offset 51H.

This register allows configuration of device and PHY options, and provides PHY status information. Table 21. Media Status Register

7 R/W TXFCE/

NWAY FLY mode: NWay with flow control capability. NWAY mode only: NWay without flow control capability. 6 R/W RXFCE RX Flow control Enable. 4 R Aux_Status Aux. Power present Status. The value of this bit is fixed after each PCI reset. 2 R LINKB Inverse of Link status. 1 R TXPF Transmit Pause Flag. RTL8101L sends a timer done packet. 0 R RXPF Receive Pause Flag. Reset when the pause state is cleared.

Table 22. CONFIG 3: Configuration Register3 Sets the Frame’s asserted time after the Grant signal has been asserted. Frame and Grant are PCI signals. 6 R/W PARM_En Parameter Enable (Used in 100Mbps mode only). PHY2_PARM, and TW_PARM registers to be written via software. executed each time the Link is OK in 100Mbps mode. This bit is valid when the PWEn bit of the CONFIG1 register is set. system when a Magic Packet is received. Destination address + Source address + data + CRC. a multicast address, which includes the broadcast address. address match the address of the ID register.

2 R CLKRUN_En CLKRUN Enable. 0 R FBtBEn Fast-Back-to-Back Enable. Set to 1 to enable Fast-Back-to-Back. Table 23. CONFIG 4: Configuration Register4 7 R/W RxFIFOAutoClr Receive FIFO buffer Auto-Clear. 6 R/W AnaOff Analog Power Off. This bit cannot be auto-loaded from EEPROM (93C46). 5 R/W LongWF Long Wake-up Frame. The initial value comes from EEPROM auto-load.

1. Wake-up frames 4, 5, 6, and 7 are merged into another 2 long

page 66, for a detailed description.

0 R/W PBWakeup Pre-Boot Wakeup. The initial value comes from EEPROM auto-load. invokes an early interrupt according to the MISR[11:0] setting in Early Mode. received data length in order to make an early Rx interrupt for the unfamiliar protocol. Table 24. Multiple Interrupt Select Register 11-0 R/W MISR11-0 Multiple Interrupt Select Register. Table 25. PCI Revision ID

Table 26. Transmit Status of All Descriptors (TSAD) Register 15 R TOK3 TOK bit of Descriptor 3. 14 R TOK2 TOK bit of Descriptor 2. 13 R TOK1 TOK bit of Descriptor 1. 12 R TOK0 TOK bit of Descriptor 0. 11 R TUN3 TUN bit of Descriptor 3. 10 R TUN2 TUN bit of Descriptor 2. 9 R TUN1 TUN bit of Descriptor 1. 8 R TUN0 TUN bit of Descriptor 0. 7 R TABT3 TABT bit of Descriptor 3. 6 R TABT2 TABT bit of Descriptor 2. 5 R TABT1 TABT bit of Descriptor 1. 4 R TABT0 TABT bit of Descriptor 0. 3 R OWN3 OWN bit of Descriptor 3. 2 R OWN2 OWN bit of Descriptor 2. 1 R OWN1 OWN bit of Descriptor 1. 0 R OWN0 OWN bit of Descriptor 0.

Table 27. Basic Mode Control Register

15 Reset This bit sets the status and control registers of the PHY (register

0062-0074H) to the default state. This bit is self-clearing. 13 Spd_Set This bit sets the network speed.

12 Auto Negotiation

This bit enables/disables the NWay auto-negotiation function. 1: Enable auto-negotiation, bit13 will be ignored. initial value comes from the 93C46.

9 Restart Auto

This bit allows the NWay auto-negotiation function to be reset. 8 Duplex Mode This bit sets the duplex mode.

Table 28. Basic Mode Status Register

5 Auto Negotiation

4 Remote Fault 1: Remote fault condition detected (cleared on read)

0: No remote fault condition detected.

3 Auto Negotiation 1: Link has not experienced fail state

2 Link Status 1: Valid link established

1 Jabber Detect 1: Jabber condition detected

0 Extended Capability 1: Extended register capability

Table 29. Auto-Negotiation Advertisement Register

14 ACK 1: Acknowledge reception of link partner capability data word 0, RO

10 Pause 1: Flow control supported by local node

9 T4 1: 100Base-T4 supported by local node

8 TXFD 1: 100Base-TX full-duplex supported by local node

7 TX 1: 100Base-TX supported by local node

Next Pages are supported, the content changes after a successful auto-negotiation. Table 30. Auto-Negotiation Link Partner Ability Register

14 ACK 1: Link partner acknowledges reception of local node’s capability

13 RF 1: Link partner is indicating a remote fault 0, RO

10 Pause 1: Flow control supported by link partner

9 T4 1: 100Base-T4 supported by link partner

8 TXFD 1: 100Base-TX full duplex is supported by link partner

7 TX 1: 100Base-TX supported by link partner

CSMA/CD <00001> is specified.

This register contains additional NWay auto-negotiation status information. Table 31. Auto-Negotiation Expansion Register

3 LP_NP_ABLE Status indicating whether the link partner supports Next Page

2 NP_ABLE This bit indicates whether the local node is able to send additional

1 PAGE_RX This bit is set when a new Link Code Word Page has been

negotiation link partner’s ability register (register 5) is read. Table 32. Disconnect Counter rolls over when full. It is cleared to zero by a read command. managed object class, Clause 30 of the IEEE 802.3u specification. Table 33. False Carrier Sense Counter is cleared to zero by a read command.

Table 34. NWay Test Register

7 NWLPBK 1: Set NWay to loopback mode 0, RW

3 ENNWLE 1: LED0 Pin indicates linkpulse 0, RW

2 FLAGABD 1: Auto negotiation experienced ability detect state 0, RO

1 FLAGPDF 1: Auto negotiation experienced parallel detection fault state 0, RO

0 FLAGLSC 1: Auto negotiation experienced link status check state 0, RO

Table 35. RX_ER Counter received. It is cleared to zero by a read command. Table 36. CS Configuration Register

15 Testfun 1: Auto negotiation to speed up internal timer 0, WO

link pulses and TPI maintains a good link state. 8 HEARTBEAT The HEARTBEAT function is only valid in 10Mbps mode.

7 JBEN 1: Enable jabber function

6 F_LINK_100 Used to login a forced good link at 100Mbps for diagnostics

3 Con_status This bit indicates the status of the connection.

2 Con_status_En Assertion of this bit configures the LED1 pin to indicate

need to enable the Config register write prior to writing to Config5. Table 37. Config5. Configuration Register 5 6 R/W BWF Broadcast Wakeup Frame. 5 R/W MWF Multicast Wakeup Frame. 4 R/W UWF Unicast Wakeup Frame. 3 R/W FIFOAddrPtr FIFO Address Pointer (Realtek internal use only). The power-on default value of this bit is 0. 2 R/W LDPS Link Down Power Saving mode. 1 R/W LANWake LANWake signal enable/disable. 0 R/W PME_STS PME_Status bit. Always sticky/can be reset by PCI RST# and software.

1. MC’97 Controller Register and Descriptor Descriptions

Table 38. MC’97 Registers Table 39. Starting Descriptor Index for LINE-Out Table 40. Current Descriptor Index for LINE-Out 4-0 R LO_CDILO Indicates the current descriptor is running.

Table 41. Last Descriptor Index for LINE-Out completed for this last descriptor, the LINE-Out bus master should stop. Table 42. LINE-Out DMA Status Register

0 R LO_LH The LINE-Out bus master is not active or the last descriptor has finished

transaction. This bit will be auto cleared by H/W when bus master is active. Table 43. LINE-Out DMA Control Register 11-8 R/W LO_DMA_TH LINE-OUT DMA Threshold Control. 0, 1: When the FIFO is empty, DMA will be triggered. 2, 3: When the sample number in FIFO < 2, DMA will be triggered. E, F: When the sample number in FIFO < 14, DMA will be triggered.

7 R/W LO_RS_DMA Set to clear all registers (offset at 0000h ~ 0007h) related to DMA, and

4 R/W FIFOUNIE FIFO Under-Run Interrupt Enable.

3 R/W LO_CDIE Current Descriptor Interrupt Enable:

2 R/W LO_LDIE Last Descriptor Interrupt Enable.

1 R/W LO_PDMA Pause LINE-Out DMA. 0 R/W LO_Start LINE-Out DMA Start/Stop. Table 44. Residual Samples Count in Current LINE-Out Descriptor Register Table 45. LINE-Out Descriptor Base Address Register LINE-Out Descriptor Base Address [1:0]. Hardwired to 0. Table 46. Starting Descriptor Index for LINE-In 4-0 R/W LI_SDILI Assign the first descriptor to be run when LINE-In bus master starts. Table 47. Current Descriptor Index for LINE-In 4-0 R LI_CDILI Indicates the current descriptor been running.

Table 48. Last Descriptor Index for LINE-In completed for this last descriptor, LINE-In bus master should stop. Table 49. LINE-In DMA Status Register

0 R LI_LH The LINE-In bus master is not active or the last descriptor has finished

Table 50. LINE-In DMA Control Register 0, 1: When the FIFO is empty, DMA will be triggered. 2, 3: When the sample number in FIFO >= 2, DMA will be triggered. E, F: When the sample number in FIFO >=14, DMA will be triggered. System memory until the samples number in FIFO is equal to threshold.

7 R/W LI_RS_DMA Set to clear all registers (offset at 0010h ~ 0017h) related to DMA, and

4 R/W FIFOOVIE FIFO Over-Run Interrupt Enable. 3 R/W LI_CDIE Current Descriptor Interrupt Enable. 2 R/W LI_LDIE Last Descriptor Interrupt Enable.

1 R/W LI_PDMA Pause LINE-In DMA. BU setting for the descriptor. 0 R/W LI_Start LINE-In DMA Start/Stop. Table 51. Residual Samples Count in Current LINE-In Descriptor Register current descriptor (sample: a 16-bit word). Table 52. Line-In Descriptor Base Address Register 31-2 R/W LINE-In Descriptor Base Address [31:2]. LINE-In Descriptor Base Address [1:0]. Hardwired to 0. DMA context stored in main memory. Table 53. MC’97-Link Control Register

7 R/W MCSDLB 1: MC97_SDATAIN source comes from MC97_SDATAOUT

5 R/W ACLINK_WPE AC-LINK Wake-up PME# Enable.

4 R/W ACLINK_WIE AC-LINK Wake-up Interrupt Enable.

3 R/W ACLINK_OFF AC-LINK Shut Off

2 R/W ACLINK_WRST MC’97 Warm Reset. This bit is auto cleared by hardware after warm reset had been issued. 1 R/W ACLINK_CRST MC’97 Cold Reset. This bit is auto set by hardware after cold reset had been issued. 0 R/W GPIE GPI Interrupt Enable. Note 1: AC-LINK wake-up event: AC97_SDATAIN is resumed high when AC-LINK signals are shut off. Note 2: Bit 5 and bit 3 are sticky bits preserved by consuming power from Vaux. Table 54. MC’97-Link Status and Index Register 15 R ACLINK_BZ AC-LINK busy.

13 R ACLINK_RTO AC-LINK Read Time-Out. from the MC’97 within 4 frames of the read command being issued. Note: Also cleared each time the Command Bit (ACLINK_CB) is written. 12 R ACLINK_RD AC-LINK Read Data is Available. the Command Bit (ACLINK_CB) is written. ignore the read back data in this case.

9 R GPIO_BZ¸

by hardware after the transaction on SDA TA-OUT slot-12 has completed. 8 R GPIO_INT GPIO Interrupt. This bit reflects the state of bit 0 in Slot 12 of SDATA-IN. is latched from SDATA-IN input slot 12 bit 0 when data is valid. 7 R/W ACLINK_CB AC-LINK Command Bit. Note: AC-LINK wake-up event. AC97_SDATAIN is resumed high when AC-LINK signals are shut off. Table 55. AC-Link Data Port 15-0 R/W ACLINK_DP Write: 16 bits of mixer data written to the MC’97. Read: 16 bits of mixer read from the MC’97. Note: The written data should be sent to MC’97 when writing to ACLINK_CB. from this port will always get mixer data from the MC’97.

Table 56. GPIO Control to MC’97 15-0 R/W GPIOOD MC’97’s GPIO output data. Note: Bit [15:0] controls the GPIO [15:0] output of MC97. Bit 15~0 are sent on SDATA-OUT slot-12 bit 19 to bit 4. changed, any pending data will be overwritten. Table 57. Real Time GPIO Input Data From MC’97 15-0 R GPIOID MC’97’s GPIO input data. input slot 12 bit 19~4 when data is valid. Note 2: These bits are real-time updated according to SDATA-IN slot-12 in every frame. Table 58. Interrupt Status Register 15 R/W SERR_IE SERR# Interrupt Enable. 14 R/W SERR_IS SERR# Interrupt Status. & (SERR# Status=1, Status[14] in configuration space). Write a ‘1’ to clear this bit and its interrupt.

9 R/W PCIGPIO1_IS·

status bit and its interrupt. 8 R/W PCIGPIO0_IS PCIGPIO0 Interrupt Status. Write 1 to clear this status bit and its interrupt.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 48 Track ID: JATR-1076-21 Rev. 1. 5 Bit R/W Symbol Description 7 R/W FIFO_ov LINE-In’s FIFO Over-run. 1: FIFO error indicates a FIFO over-run. This will cause an interrupt if the enable bit in the Control Register is set. This bit and its interrupt should be cleared by writing a ‘1’. Data received after overrun occurs will not enter into FIFO. 6 R/W LI_Curr_End Completion of current LINE-In’s descriptor. 1: The current descriptor has sent the last sample to system memory. This will cause an interrupt if the enable bit in Control Register is set. This bit and its interrupt should be cleared by writing a ‘1’ 5 R/W LI_Last_End Completion of the last LINE-In’s descriptor. 1: The last descriptor has sent the last sample to system memory. This will cause an interrupt if the enable bit in Control Register is set. This bit and its interrupt should be cleared by writing a ‘1’ 4 R/W ACLINK_WES AC-LINK Wake-up Event Status. 1: AC-LINK wake-up event occurred 0: No wake-up event This bit is set if ACLINK wake-up event is detected. This controller will generate an interrupt when (ACLINK_WES=1) & (ACLINK_WIE=1). Write a ‘1’ to clear this bit and its interrupt. This bit will not be set when ACLINK Shut-Off (ACCR.3) is 0. Once it is set by an ACLINK wake-up event, it can only be cleared after ACLINK Shut-Off is cleared. Note: Bit 4 is a sticky bit, preserved by consuming power from Vaux. 3 R/W FIFO_un LINE1-Out FIFO Under-run. 1: FIFO error indicates a FIFO under-run. This will cause an interrupt if the enable bit in LINE1-Out’s Control Register is set. This bit and its interrupt should be cleared by writing a ‘1’ 2 R/W LO_Curr_End Completion of current Line1-Out’s descriptor. 1: The current LINE1-Out’s descriptor has got the last sample from system memory. This will cause an interrupt if the enable bit in Control Register is set. This bit and its interrupt should be cleared by writing a ‘1’ 1 R/W LO_Last_End Completion of the last LINE1-Out’s descriptor. 1: The last descriptor has got the last sample from system memory. This will cause an interrupt if the enable bit in Control Register is set. This bit and its interrupt should be cleared by writing a ‘1’.

0 R/W GPIS

MC’97 GPIO Interrupt Status. 1: MC’97 GPIO interrupt. The GPIO_INT (ACSIR.8) has been set 0: No MC’97 GPIO interrupt This bit is set if GPIO_INT (ACSIR.8) has been set. This controller will generate an interrupt when (GPIS=1) & (GPIE=1). Writing a ‘1’ will clear this bit and it’s interrupt.

Table 59. PCI GPIO Setup Register 9 R/W PCIGPIO1_PEE PCIGPIO1 PME# Event Enable (when PCIGPIO1 is used as input). 8 R/W PCIGPIO0_PEE PCIGPIO0 PME# Event Enable (when PCIGPIO0 is used as input). 5 R/W PCIGPIO1_IE PCIGPIO1 interrupt Enable (when PCIGPIO1 is used as input). A low to high transaction PCIGPIO1 will trigger the PCI interrupt. 4 R/W PCIGPIO0_IE PCIGPIO0 interrupt Enable (when PCIGPIO0 is used as input). A low to high transaction PCIGPIO0 will trigger the PCI interrupt. 1 R/W PCIGPIO1_PC PCIGPIO1 Primitive Control. 0 R/W PCIGPIO0_PC PCIGPIO0 Primitive Control. Note: The PME# only be asserted when RTL8101L is in D3 state.

Table 60. PCI GPIO Status Register 9 R/W PCIGPIO1_PMES PCIGPIO1 PME# Event Status. 1: PCIGPIO1 PME# event has occurred in D3 state. 0: No PCIGPIO1 PME# event has occurred in D3 state. Write a 1 to clear this status bit. 8 R/W PCIGPIO0_PMES PCIGPIO0 PME# Event Status. 1: PCIGPIO0 PME# event has occurred in D3 state. 0: No PCIGPIO0 PME# event has occurred in D3 state. Write a 1 to clear this status bit. 1 R/W PCIGPIO1_IOS PCIGPIO1 Input/Output Status. 1: PCIGPIO1 is driven high by external device (input). / Drive PCIGPIO1 high (output). 0: PCIGPIO1 is driven low by external device (input). / Drive PCIGPIO1 low (output). PCIGPIO[1:0] are sticky bits and can be powered by V aux. 0 R/W PCIGPIO0_IOS PCIGPIO0 Input/Output Status. 1: PCIGPIO0 is driven high by external device (input). / Drive PCIGPIO0 high (output). 0: PCIGPIO0 is driven low by external device (input). / Drive PCIGPIO0 low (output). PCIGPIO[1:0] are sticky bits and can be powered by V aux.

Table 61. EEPROM (93C46) Command Register 7-6 R/W EEM1-0 Operating Mode: These 2 bits select the RTL8101L operating mode. auto-load operation will take about 2 ms. registers are reset to default values. auto-load or 93C46 programming mode.

Table 62. Context For Line-Out Descriptor Table 63. Context For Line-In Descriptor

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 53 Track ID: JATR-1076-21 Rev. 1. 5 8.26. Descriptor Definition DMA Address for Line1-Out/In Descriptor X LxDBA+00H~03H: 31 2 1 0 DMA Start Address [31:2] 0 0 Buffer Size for Line1-Out/In Descriptor X LxDBA+04H~07H: 31 30 29 15 14 1 0 I BU Reserved Buffer Length 0 DMA Start Address [31:0]: This is the physical start address for the descriptor’s DMA operation. When set to a 1 by S/W, the controller should issue an interrupt upon completion of this buffer. BU: If set to a 0, the controller should continuously send the last valid data when FIFO is under-run (keep the last data, and validate the tag bit for Slot-5 on AC_DOUT). If set to a 1, the controller continuously sends the last invalid data when FIFO is empty or under-run (keep the last data, but invalidate the tag bit for Slot-5 on AC_DOUT). Note: The BU bit is only effective for LINE1-Out master. Buffer Length [14:0]: The size of the data buffer is measured in 16-bit samples. The maximum number of samples is 32767. A value of 0 means there is no sample transferred into this buffer. To achieve an efficient PCI transaction, the buffer length must be an even number.

the RTL8101L performs a series of EEPROM read operations from the 93C46 addresses 00H to 31H. We recommend you obtain Realtek approval before changing the default settings of the EEPROM. Table 64. EEPROM (93C46) Contents 02h-05h - Reserved. The RTL8101L no longer supports auto-load of Vender ID and Device ID. The default values of VID and DID are hex 10EC and 8139, respectively. 06h-07h SVID PCI Subsystem Vendor ID, PCI configuration space offset 2Ch-2Dh. 08h-09h SMID PCI Subsystem ID, PCI configuration space offset 2Eh-2Fh. 0Ah MNGNT PCI Minimum Grant Timer, PCI configuration space offset 3Eh. 0Bh MXLAT PCI Maximum Latency Timer, PCI configuration space offset 3Fh. 0Dh CONFIG3 RTL8101L Configuration register 3, operational register offset 59H. Ethernet ID to IDR0-IDR5 of RTL8101L's I/O registers. 14h CONFIG0 RTL8101L Configuration register 0, operational registers offset 51h. 15h CONFIG1 RTL8101L Configuration register 1, operational registers offset 52h. 16h-17h PMC Reserved. Do not change this field without Realtek approval. Power Management Capabilities. PCI configuration space address 52h and 53h. 18h PMCSR Reserved. Do not change this field without Realtek approval. Power Management Control/Status. PCI configuration space address 55h. 19h CONFIG4 Reserved. Do not change this field without Realtek approval. RTL8101L Configuration register 4, operational registers offset 5Ah. 1Ah-1Dh PHY1_PARM_U Reserved. Do not change this field without Realtek approval. 1Eh PHY2_PARM_U Reserved. Do not change this field without Realtek approval. PHY Parameter 2-U for RTL8101L. Operational register of the RTL8101L is 80h.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 55 Track ID: JATR-1076-21 Rev. 1. 5 Bytes Contents Description Do not change this field without Realtek approval. 1Fh CONFIG_5 Bit7-6: Reserved. Bit5-4: Multi-function Select: 00b: Ethernet Controller Only 01b: MC’97 Controller Only 10b: Ethernet+MC’97 Controllers 11b:After ver F Ethernet+Auto-detect MC’97 Controllers If the RTL8101L detects the MC’97, the RTL8101L is set to Multi-function. Otherwise it set to Ethernet only. The MC’97 is only detected during power on or reset. Note: For versions A to E, 11b=Ethernet+MC’97 Controllers Bit3: Reserved. Bit2: Link Down Power Saving mode: Set to 1: Disable. Set to 0: Enable. When the cable is disconnected (Link Down), the analog part will power itself down (PHY Tx part and part of twister) automatically, except PHY Rx part and part of twister to monitor SD signal in case the cable is re-connected and the Link needs to be established again. Bit1: LANWake signal Enable/Disable Set to 1: Enable LANWake signal. Set to 0: Disable LANWake signal. Bit0: PME_Status bit properties Set to 1: The PME_Status bit can be reset by PCI reset or by software if D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a sticky bit. Set to 0: The PME_Status bit is always a sticky bit and can only be reset by software. 20h-21h MC97_VID Vendor ID of the MC’97 Controller. 22h-23h MC97_DID Device ID of the MC’97 Controller. 24h-25h MC97_SVID Sub-Vendor ID of the MC’97 Controller. 26h-27h MC97_SDID Sub-Device ID of the MC’97 Controller. 28h-2Bh PHY1_PARM_T Reserved. Do not change this field without Realtek approval. PHY Parameter 1-T for the RTL8101L. Operational registers of the RTL8101L are from 78h to 7Bh. 2Ch PHY2_PARM_T Reserved. Do not change this field without Realtek approval. 2Dh-31h - Reserved. 32h-33h CheckSum Reserved. Do not change this field without Realtek approval. Checksum of the EEPROM content. 34h-3Eh - Reserved. Do not change this field without Realtek approval. 3Fh PXE_Para Reserved. Do not change this field without Realtek approval. PXE ROM code parameter. 40h-7Fh VPD_Data VPD data field. Offset 40h is the start address of the VPD data.

Table 65. EEPROM Related Ethernet MAC Registers

• Registers marked with type = 'W *' can be written only if bits EEM1=EEM0=1.

Registers marked with type = 'W ' can be written only if bits EEM1=EEM0=1 and CONFIG3<PARM_EN> = 0. Table 66. EEPROM Related Power Management Registers

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 57 Track ID: JATR-1076-21 Rev. 1. 5 10. PCI Configuration Space Registers 10.1. PCI Configuration Space Registers No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00h VID R 1 1 1 0 1 1 0 0 01h R 0 0 0 1 0 0 0 0 02h DID R 0 0 1 1 1 0 0 1 03h R 1 0 0 0 0 0 0 1 04h Command R 0 PERRSP 0 0 - BMEN MEMEN IOEN W - PERRSP - - - BMEN MEMEN IOEN 05h R 0 0 0 0 0 - FBTBEN SERREN W - - - - - - - SERREN 06h Status R FBBC 0 0 NewCap - 0 0 0 07h R DPERR SSERR RMABT RTABT STABT DST1 DST0 DPD W DPERR SSERR RMABT RTABT STABT - - DPD 08h Revision ID R 0 0 0 0 0 0 0 0 09h PIFR R 0 0 0 0 0 0 0 0 0Ah SCR R 0 0 0 0 0 0 0 0 0Bh BCR R 0 0 0 0 0 0 1 0 0Ch CLS R 0 0 0 0 0 0 0 0 0Dh LTR R LTR7 LTR6 LTR5 LTR4 LTR3 LTP2 LTR1 LTR0 W LTR7 LTR6 LTR5 LTR4 LTR3 LTP2 LTR1 LTR0 0Eh HTR R 0 0 0 0 0 0 0 0 0Fh BIST R 0 0 0 0 0 0 0 0 10h IOAR R 0 0 0 0 0 0 0 IOIN W - - - - - - - - 11h R/W IOAR15 IOAR14 IOAR13 IOAR12 IOAR11 IOAR10 IOAR9 IOAR8 12h R/W IOAR23 IOAR22 IOAR21 IOAR20 IOAR19 IOAR18 IOAR17 IOAR16 13h R/W IOAR31 IOAR30 IOAR29 IOAR28 IOAR27 IOAR26 IOAR25 IOAR24 14h MEMAR R 0 0 0 0 0 0 0 MEMIN W - - - - - - - - 15h R/W MEM15 MEM14 MEM13 ME M12 MEM11 MEM10 MEM9 MEM8 16h R/W MEM23 MEM22 MEM21 ME M20 MEM19 MEM18 MEM17 MEM16 17h R/W MEM31 MEM30 MEM29 ME M28 MEM27 MEM26 MEM25 MEM24 18h-2 Bh RESERVED 2Ch SVID R SVID7 SVID6 SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 2Dh R SVID15 SVID14 SVID13 SVID 12 SVID11 SVID10 SVID9 SVID8 2Eh SMID R SMID7 SMID6 SMID5 SMID4 SMID3 SMID2 SMID1 SMID0 2Fh R SMID15 SMID14 SMID13 SMID 12 SMID11 SMID10 SMID9 SMID8 30h BMAR R 0 0 0 0 0 0 0 BROMEN W - - - - - - - BROMEN 31h R BMAR15 BMAR14 BMAR13 BMAR12 BMAR11 0 0 0 W BMAR15 BMAR14 BMAR13 BMAR12 BMAR11 - - - 32h R/W BMAR23 BMAR22 BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16 33h R/W BMAR31 BMAR30 BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 58 Track ID: JATR-1076-21 Rev. 1. 5 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 34h Cap_Ptr R 0 1 0 1 0 0 0 0 35h-3 Bh RESERVED 3Ch ILR R/W IRL7 ILR6 ILR5 ILR4 ILR3 ILR2 ILR1 ILR0 3Dh IPR R 0 0 0 0 0 0 0 1 3Eh MNGNT R 0 0 1 0 0 0 0 0 3Fh MXLAT R 0 0 1 0 0 0 0 0 40h– 4Fh RESERVED 50h PMID R 0 0 0 0 0 0 0 1 51h NextPtr R 0 0 0 0 0 0 0 0 52h PMC R Aux_I_b1 Aux_I_b0 DSI Reserved PMECLK Version 53h R PME_D3 cold PME_D3 hot PME_D2 PME_D1 PME_D0 D2 D1 Aux_I_b2 54h PMCSR R 0 0 0 0 0 0 Power State W - - - - - - Power State 55h R PME_Status - - - - - - PME_En W PME_Status - - - - - - PME_En 56h– 5Fh RESERVED 60h VPDID R 0 0 0 0 0 0 1 1 61h NextPtr R 0 0 0 0 0 0 0 0 62h Flag VPD Address R/W VPDADDR VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD 63h R/W Flag VPDADDR VPDADD R13 VPDADD R12 VPDADD R11 VPDADD R10 VPDADD VPDADD 64h R/W Data7 Data6 Data5 Data 4 Data3 Data2 Data1 Data0 65h R/W Data15 Data14 Data13 Data 12 Data11 Data10 Data9 Data8 66h R/W Data23 Data22 Data21 Data 20 Data19 Data18 Data17 Data16 67h VPD Data R/W Data31 Data30 Data29 Data 28 Data27 Data26 Data25 Data24 68h-F Fh RESERVED

functions. The functions of the RTL8101L’s configuration space are described below. VID: Vendor ID. This field defaults to a value of 10ECh (Realtek Semiconductor’s PCI Vendor ID). DID: Device ID. This field defaults to a value of 8139h. to generate and respond to PCI cycles. Table 67. PCI Configuration Space Functions bit controls whether or not a master can do fast back-to-back transactions to different devices. error on the address phase (AD<31:0> and CBEB<3:0> ). to 0, any detected parity error is ignored and the RTL8101L continues normal operation. Parity checking is disabled after hardware reset (RSTB). 5 VGASNOOP VGA palette SNOOP: Read as 0, write operation has no effect. 4 MWIEN Memory Write and Invalidate cycle Enable: Read as 0, write operation has no effect. 0, it is prohibited from acting as a PCI bus master. For normal operation this bit must be set by the system BIOS. set to 0, the RTL8101L ignores memory space accesses. RTL8101L ignores I/O space accesses.

Status: The status register is a 16-bit regi ster used to record status information of PCI bus related events. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. Table 68. PCI Configuration Space Status 15 DPERR Detected Parity Error. in the command register PERRSP bit. 14 SSERR Signaled System Error. When set indicates that the RTL8101L asserted the system error pin, SERRB. Writing a 1 clears this bit to 0. 13 RMABT Received Master Abort. When set indicates that the RTL8101L terminated a master transaction with master abort. Writing a 1 clears this bit to 0. 12 RTABT Received Target Abort. 11 STABT Signaled Target Abort. 10-9 DST1-0 Device Select Timing. will assert DEVSELB two clocks after FRAMEB is asserted. 8 DPD Data Parity error Detected.

• The RTL8101L asserts parity error (PERRB pin) or it senses the assertion of the PERRB pin by another device.
• The RTL8101L operates as a bus master for the operation that caused the error.
• The Command register PERRSP bit is set. Writing a 1 clears this bit to 0. 7 FBBC Fast Back-To-Back Capable. Config3<FbtBEn>=0, Read as 0. Write operation has no effect. Config3<FbtBEn>=1, Read as 1. 6 UDF User Definable Features. Read as 0. Write operation has no effect. The RTL8101L does not support UDF. 5 66MHz 66MHz Capable. Read as 0. Write operation has no effect. The RTL8101L has no 66MHz capability. 4 NewCap New Capability. Config3<PMEn>=0, Read as 0. Write operation has no effect. Config3<PMEn>=1, Read as 1. 0-3 - Reserved.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 61 Track ID: JATR-1076-21 Rev. 1. 5 RID: Revision ID Register The Revision ID register is an 8-bit register that specifies the RTL8101L controller revision number. PIFR: Programming Interface Register The programming interface register is an 8-bit register that identifies the programming interface of the RTL8101L controller. PIFR = 00h (the PCI specification does not define any specific value for network devices). SCR: Sub-Class Register The Sub-class register is an 8-bit register that identifies the function of the RTL8101L. SCR = 00h indicates that the RTL8101L is an Ethernet controller. BCR: Base-Class Register The Base-Class Register is an 8-bi t register that broadl y classifies the func tion of the RTL8101L. BCR = 02h indicates that the RTL8101L is a network controller. CLS: Cache Line Size Reads will return a 0, writes are ignored. LTR: Latency Timer Register Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8101L. When the RTL8101L asserts FRAMEB, its latency timer starts to count. If the RTL8101L deasserts FRAMEB prior to count expiration, the contents of the latency timer are ignored. Otherwise, after the count expires, the RTL8101L initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write, and the default value is 00H. HTR: Header Type Register Reads will return a 0, writes are ignored. BIST: Built-In Self Test Reads will return a 0, writes are ignored.

also specifies the number of bytes required as well as an indication that it can be mapped into IO space. Table 69. Input Output Address Register 31-8 IOAR31-8 Base IO Address. This is set by software to the base IO address for the operational register map. Read only. Set to 1 by the RTL8101L to indicate that it is capable of being mapped into IO space. Table 70. Base Memory Address for Memory Accesses 31-8 MEM31-8 Base Memory Address. This is set by software to the base address for the operational register map. These bits return 0, which indicates that the RTL8101L requires 256 bytes of Memory Space. 3 MEMPF Memory Pre-Fetchable. Read only. Set to 0 by the RTL8101L. 2-1 MEMLOC Memory Location Select. Read only. Set to 0 by the RTL8101L. 0 MEMIN Memory Space Indicator. no EEPROM, this field will default to a value of 8139h.

registers. This register must be initialized prior to accessing any RTL8101L register with memory access. Table 71. Base Memory Address for Memory Accesses 17-11 ROMSIZE These bits indicate how many Boot ROM spaces are to be supported. 0 BROMEN Boot ROM Enable: This is used by the PCI BIOS to enable accesses to Boot ROM. written by the POST software to set an interrupt line for the RTL8101L. RTL8101L uses an INTA interrupt pin. field will default to a value of 20h.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 64 Track ID: JATR-1076-21 Rev. 1. 5 Power Management Capabilities: Bit Type Function

15 R Read as 1 (PME# can be asserted from D3cold)

14 R Read as 1 (PME# can be asserted from D3hot)

13 R Read as 0 (PME# can not be asserted from D2)

12 R Read as 0 (PME# can not be asserted from D1)

11 R Read as 0 (PME# can not be asserted from D0)

10 R Read as 0 (Not support D2 state)

9 R Read as 0 (Not support D1 state)

8:6 R Read as 010 (consume maximum 100mA from Vaux)

5 R Read as 1 (Device Specific Initialization (DSI) required)

4 R Read as 0

3 R Read as 0 (PCI clock is not required for PME# operation)

2:0 R Read as 010b (PCI Power Management Interface Specification Revision 1.1) Once Vaux is not supplied, bit[15] reads as 0 to indicate PME# is not supported in D3(cold), and bit[8:6] reads as 000b. PMCSR: Bit Type Function 15 R/W PME_Status. 0: Normal 1: PME# asserted 14:13 R Data_Scale. Read as 00b 12:9 R Data_Select. Read as 0000b 8 R/W PME_En. 0: Disable 1: Enable 7:2 R Read as 0 1:0 R/W PowerState. 00: D0 01: Reserved 10: Reserved 11: D3 hot Writing ‘1’ to bit 15 will clear it and cause the function to stop asserting PME#. Write a ‘0’ has no effect. Note that bit 15 is independent of bit 8. Writing ‘01’ and ‘10’ to bit 1,0 has no effect on the RTL8101L. The RTL8101L terminates the cycle normally and discards the data (bit 1, 0 only). Bit 15 and bit 8 are sticky. The System OS should clear them after booting. These 2 bits consume power from Vaux. Bits except bit 15/8 consume power from normal power source. Because PCI 2.3 supports auxiliary power Vaux, the chip designer must pay attention to the interface of PME# related circuit and non-PME# related circuit.

Table 72. Default Values After Power-on (RSTB Asserted)

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 66 Track ID: JATR-1076-21 Rev. 1. 5 No. Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 35h 3Bh RESERVED(ALL 0) 3Ch ILR R/W 0 0 0 0 0 0 0 0 3Dh IPR R 0 0 0 0 0 0 0 1 3Eh MNGNT R 0 0 1 0 0 0 0 0 3Fh MXLAT R 0 0 1 0 0 0 0 0 40h FFh RESERVED(ALL 0) 10.5. PCI Power Management Functions The RTL8101L complies with ACPI (Rev 1.1), PCI Powe r Management (Rev 1.1), and the Device Class Power Management Reference Specification (V1.0a), su ch as to support an Operating System-Directed Power Management (OSPM) environment. To suppor t this, the RTL8101L pr ovides the following capabilities:

• The RTL8101L can monitor the network for a Wakeup Frame (AMD Magic Packet, LinkChg, Microsoft® wake-up frame), and notify the system via PME# should such a packet or event arrive. Then the system can be restored to a working state to process incoming jobs.
• The RTL8101L can be isolated from the PCI bus automatically via the auxiliary power circuit when the PCI bus is in B3 state, i.e. the power on the PCI bus is removed. The RTL8101L can be disabled when needed by pulling the isolate pin low to 0V . 10.5.1. Power Down Mode When the RTL8101L is in power down mode (D1 ~ D3):
• The Rx state machine is stopped and the RTL8101L monitors the network for wakeup events. The RTL8101L will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx FIFO.
• The FIFO status and the packets that are already in the Rx FIFO before entering power down mode are held by the RTL8101L during power down mode.
• Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.
• After restoration to a D0 state, PCI bus master mode transfers data to the Tx FIFO that was not moved into the Tx FIFO before the last break. A packet that was not transmitted completely before power down mode is transmitted again.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 67 Track ID: JATR-1076-21 Rev. 1. 5 D3cold_support_PME bit (bit15, PMC register) & Aux_I_b2:0 (bit8:6, PMC register) in PCI configuration space

• If 9346 D3cold_support_PME bit (bit15, PMC) = 1, the above 4 bits depend on the existence of Aux power.
• If 9346 D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s. Examples:

9346 D3c_support_PME = 1

• If Aux. power exists, then PMC in PCI config space is the same as 9346 PMC, i.e. if 9346 PMC = C2 F7, then PCI PMC = C2 F7.
• Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above 4 bits are all 0’s. I.e. if 9346 PMC = C2 F7, then PCI PMC = 02 76. Note: In this case, if wakeup support is desired when the main power is off, it is suggested that the EEPROM PMC be set to: C2 F7 (Realtek default value). It is not recommended to set the D0_support_PME bit to 1.

9346 D3c_support_PME = 0,

• If Aux. power exists, then PMC in PCI config space is the same as 9346 PMC, i.e. if 9346 PMC = C2 77, then PCI PMC = C2 77.
• If Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above 4 bits are all 0’s, i.e. if 9346 PMC = C2 77, then PCI PMC = 02 76. Note: In this case, if wakeup support is not desired when main power is off, it is suggested that the 9346 PMC be set to 02 76. It is not recommended to set the D0_support_PME bit to 1. Link Wakeup Link Wakeup occurs when the following conditions are met:
• The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8101L is in isolation state, or the PME# can be asserted in the current power state.
• The Link status is re-established. Magic Packet Wakeup A Magic Packet Wakeup occurs when the following conditions are met:
• The destination address of the received Magic Packet matches.
• The received Magic Packet does not contain a CRC error.
• The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8101L is in isolation state, or the PME# can be asserted in the current power state.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 68 Track ID: JATR-1076-21 Rev. 1. 5

• The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid (Fast) Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met:
• The destination address of the received Wakeup Frame matches.
• The received Wakeup Frame does not contain a CRC error.
• The PMEn bit (CONFIG1#0) is set to 1.
• The 8-bit CRC* (or 16-bit CRC**) of the received Wakeup Frame matches with the 8-bit CRC (or 16-bit CRC) of the sample Wakeup Frame pattern received from the local machine’s OS.
• The last masked byte* of the received Wakeup Frame matches with the last masked byte* of the sample Wakeup Frame pattern provided by the local machine’s OS (In Long Wakeup Frame mode, the last masked byte field is replaced with the high byte of the 16-bit CRC). *8-bit CRC: 8-bit CRC logic is used to generate an 8-bit CRC from the masked bytes of the received Wakeup Frame packet within offset 12 to 75. Software should calculate the 8-bit Power Management CRC for each specific sample wakeup frame and store the calculated CRC in the corresponding CRC register for the RTL8101L to check whether there is a Wakeup Frame coming in. 16-bit CRC: (Long Wakeup Frame mode, the mask bytes cover from offset 0 to 127) Long Wakeup Frame: The RTL8101L also supports 3 long Wakeup Frames. If the range of mask bytes of the sample Wakeup Frame, passed down by the OS to the driver, exceeds the range from offset 12 to 75, the related registers of wakeup frame 2 and 3 can be merged to support one long wakeup frame by setting the LongWF (bit0, CONFIG4). Thus, the range of effective mask bytes extends from offset 0 to 127. The low byte and high byte of the calculated 16-bit CRC s hould be put into regi ster CRC2 and LSBCRC2 respectively. The mask bytes (16 bytes) should be stored in register Wakeup2 and Wakeup3. The CRC3 and LSBCRC3 have no meaning in this case and should be reset to 0. Long Wakeup Frame pairs are frames 4 and 5, and frames 6 and 7. The CRC5, CRC7, LSBCRC 5, and LSBCRC7 have no meaning in this case and should be set to 0 if the RTL8101L is to support long Wakeup Frames . The RTL8101L supports 2 normal wakeup frames and 3 long wakeup frames. *Last Masked Byte: The last byte of the masked bytes of the received Wakeup Frame packet within offset 12 to 75 (in 8-bit CRC mode) should match the last byte of the masked byte s of the sample Wakeup Frame provided by the local machine’s OS.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 69 Track ID: JATR-1076-21 Rev. 1. 5 PME# Signal The PME# signal is asserted only when the following conditions are met:

• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8101L may assert PME# in current power state, or when the RTL8101L is in isolation state. Refer to 10.1 PCI Configuration Space , page 57, PME_Support (bit15-11) of the PMC register.
• A Magic Packet, LinkChg, or Wakeup Frame event has occurred. Writing a 1 to the PME_Status (bit15) of PMCSR register in the PCI Configuration Space will clear this bit and cause the RTL8101L to stop asserting a PME# (if enabled). When the RTL8101L is in power down mode, e.g. D1-D3, the IO, and MEM are all disabled. After RST# is asserted, the power state must be changed to D0 if the original power state was D3cold. There is no hardware enforced delays in the RTL8101L’s power state. When in ACPI mode, the RTL8101L does not support PME from D0 owing to the PMC register setting (this setting comes from EEPROM). LWAKE Signal The RTL8101L also supports th e LAN WAKE-UP function. The LWAK E pin is used to notify the motherboard to execute the wake-up process whenever the RTL8101L receives a wakeup event, such as a Magic Packet. The LWAKE signal is asserted according to the following setting:
• LWPME bit (bit4, CONFIG4) 0: LW AKE is asserted whenever a wakeup event occurs 1: LW AKE can only be asserted when PMEB is asserted and ISOLATEB is low
• Bit1 of DELAY byte (offset 1Fh, EEPROM) 0: LW AKE signal is disabled 1: LW AKE signal is enabled

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 70 Track ID: JATR-1076-21 Rev. 1. 5 10.6. VPD (Vital Product Data) Bit 31 of the VPD is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data between the VPD data register and the 93C46 has completed or not. Write VPD register (write data to the 93C46)

• Write the flag bit to 1 at the same time the VPD address is written. When the flag bit is set to 0 by the RTL8101L, the VPD data (all 4 bytes) has been transferred from the VPD data register to the 93C46. Read VPD register (read data from the 93C46)
• Write the flag bit to a zero at the same time the VPD address is written. When the flag bit is set to one by the RTL8101L, the VPD data (all 4 bytes) has been transferred from the 93C46 to the VPD data register.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 71 Track ID: JATR-1076-21 Rev. 1. 5 11. Functional Description 11.1. Transmit Operation The host CPU initiates a transmit by storing an entire pack et of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the RTL8101L is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the pr ogrammed threshold level, the RTL8101L begins packet transmission. 11.2. Receive Operation The incoming packet is placed in the RTL8101L’s Rx FIFO. Conc urrently, the RTL8101L performs address filtering of multicast packets according to the hash algorithms. When the amount of data in the Rx FIFO reaches the level defined in the Receive Configuration Register, the RTL8101L requests the PCI bus to begin transferring the data to the Rx buffer in PCI bus master mode. 11.3. Wander Compensation The RTL8101L is ANSI TP-PMD compliant and s upports Input Wander and Base Line Wander (BLW) compensation in 100Base-TX mode. The RTL8101L does no t require external attenu ation circuitry at its receive inputs, RD+/-. It accepts TP-PMD compliant waveforms directly, requiring only 100Ω termination and a 1:1 transformer. BLW is the change in the average DC content, over time, of an AC coupled di gital transmission over a given transmission medium and is a result of the interaction between the low frequency components of a transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission system. If the low-frequency content of the digital bit stream goes below the low-frequency pole of the AC coupling transformers, then the dro op characteristics of th e transformers will dominate, resulting in potentially serious BLW. If BLW is not compensated, packet loss can occur. 11.4. Signal Detect The RTL8101L supports signal detect in 100Base-TX mode. The reception of normal 10Base-T link pulses and fast link pulses (defined by IEEE 802.3u Auto-ne gotiation) by the 100Base-TX receiver do not cause the RTL8101L to assert signal detect. The signal detect function of the RTL8101L is inco rporated to meet the specifications mandated by the ANSI FDDI TP-PMD standard as well as the IEEE 802.3 100Base-TX standard for both voltage thresholds and timing parameters.

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 72 Track ID: JATR-1076-21 Rev. 1. 5 11.5. Line Quality Monitor The line quality monitor function is available in 100Base-TX mode. It is possible to determine the amount of Equalization being used by accessi ng certain test registers with the DSP engine. This provides a crude indication of connected cable length. This function allows for a quick and simple verification of the line quality in that any significant deviation from an exp ected register value (based on a known cable length) would indicate that the signal quality has deviated from the expected nominal case. 11.6. Clock Recovery Module The Clock Recovery Module (CRM) is supporte d in 100Base-TX mode. The CRM accepts 125Mbps MLT-3 data from the equalizer. The DPLL locks ont o the 125Mbps data stream and extracts a 125MHz recovered clock. The extracted and synchronized clock and data are us ed as required by the synchronous receive operations. 11.7. Loopback Operation Loopback mode is normally used to verify that th e logic operations up to th e Ethernet cable function correctly. In loopback mode for 100Mbps, the RTL8101L takes frames from the transmit descriptor and transmits them up to internal Twister logic. 11.8. Tx Encapsulation While operating in 100Base-TX mode, the RTL8101L encapsulates the frames that it transmits according to the 4B/5B code-groups table. The changes to the original packet data are listed below: The first byte of the preamble in the MAC frame is replaced with the JK symbol pair. After the CRC, the TR symbol pair is inserted. 11.9. Collision If the RTL8101L is not in full-duplex mode, a collision event occurs when the receive input is not idle while the RTL8101L transmits. If the collis ion was detected during the pream ble transmission, a jam pattern is transmitted after completing the preamble (including the JK symbol pair).

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 73 Track ID: JATR-1076-21 Rev. 1. 5 11.10. Rx Decapsulation The RTL8101L continuously monitors the network when reception is enabled. When activity is recognized it starts to process the incoming data. After detecting receive activity on the line, the RTL8101L starts to process the preamble bytes based on the mode of operation. While operating in 100Base-TX mode, the RTL8101L expects the frame to start with the symbol pair JK in the first byte of the 8-byte preamble. The RTL8101L checks the CRC bytes and checks whether the packet data ends with the TR symbol pair. If not, the RTL8101L reports an RSR CRC error. The RTL8101L reports an RSR CRC error in 100Base-TX mode if an invalid symbol (4B/5B Table) is received in the middle of the frame. The RSR<ISR> bit also sets. 11.11. Flow Control The RTL8101L supports IEEE 802.3X flow control fo r improved performance in full-duplex mode. It detects PAUSE packets to achieve flow control tasks. 11.11.1. Control Frame Transmission When the RTL8101L detects that it’s free receive buffer is less than 3K bytes, it sends a PAUSE packet with pause_time (=FFFFh) to inform the source station to stop transmission for the specified period of time. After the driver has pro cessed the packets in the receive buffer and updated the boundary pointer, the RTL8101L sends another PAUSE packet with pause_time (=0000h) to wake up the source station to restart transmission. 11.11.2. Control Frame Reception The RTL8101L enters a backoff state for a specified period of time when it receives a valid PAUSE packet with pause_time (=n). If the PAUSE packet is received while the RTL8101L is transmitting, the RTL8101L starts to back off after the current transmission completes. The RTL8101L is free to transmit the next packet when it receives a valid PAUSE pa cket with pause_time (=0000h) or the backoff timer (=n*512 bit time) elapses. Note: The PAUSE operation cannot be used to inhi bit transmission of MAC Control frames (e.g. PAUSE packet). NWay flow control capability can be dis abled. Refer to section 9 EEPROM (93C46) Contents, page 54.

The Link Monitor senses whether a station is connected and monitors link integrity. Note: In 10/100Mbps mode, LED function is the same as that of the RTL8139C(L). Figure 3. LED_RX

Figure 6. Application Diagram

Table 73. Thermal Characteristics

Figure 7. Target Read

Figure 18. Parity Operation - One Example

Single-Chip Fast Ethernet Controller and MC’97 Controller w/Power Management 85 Track ID: JATR-1076-21 Rev. 1. 5 14. Mechanical Dimensions Note: 1.To be determined at seating plane -c- 2.Dimensions D 1 and E1 do not include mold protrusion. Symbol Dimension in inch Dimension in mm D 1 and E1 are maximum plastic body size dimensions Min Nom Max Min Nom Max including mold mismatch. A - - 0.067 - - 1.70 3.Dimension b does not include dambar protrusion. D 0.630 BSC 16.00 BSC 7.Controlling dimension: millimeter. D1 0.551 BSC 14.00 BSC 8. Reference document: JEDEC MS-026 , BED. E 0.630 BSC 16.00 BSC TITLE: 100LD LQFP ( 14x14x1.4mm) E1 0.551 BSC 14.00 BSC PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm 0.020 BSC 0.50 BSC LEADFRAME MATERIAL: L1 0.039 REF 1.00 REF VERSION 1 θ 0° 3.5 ° 9 ° 0 ° 3.5 ° 9 ° PAGE OF θ 1 0° - - 0° - - CHECK DWG NO. LQ100 - P1 θ 2 12°TYP 12 °TYP DATE θ 3 12°TYP 12 °TYP REALTEK SEMICONDUCTOR CORP.

Table 75. Ordering Information Note: See page 5 for package identification.