RTL2832U

RTL2832U REALTEK | Alldatasheet

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DVB-T COFDM DEMODULATOR+USB 2.0 DATASHEET (CONFIDENTIAL: Development Partners Only) Rev. 1.4

01 November 2010

Track ID: JATR-2265-11 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan www.realtek.com

DVB-T COFDM Demodulator + USB 2.0 ii Track ID: JATR-2265-11 Rev. 1.4 COPYRIGHT ©2010 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Co rporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and soft ware engineer’s general information on the Realtek RTL2832U. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.

REVISION HISTORY

Revision Release Date Summary 1.0 2008/06/30 First release. 1.1 2009/02/06 Corrected typing errors. 1.2 2009/02/16 Revised ‘Connects a 12k ohm Resistor to ground’ to ‘Connects a 10k ohm Resistor to ground’, in the ADC section of Table 1 Pin Descriptions, page 5. Revised Figure 9, page 44. 1.3 2009/06/29 Corrected minor typing errors. 1.4 2010/11/01 Added Table 38 Crystal Conditions, page 43.

DVB-T COFDM Demodulator + USB 2.0 iii Track ID: JATR-2265-11 Rev. 1.4 Table of Contents

DVB-T COFDM Demodulator + USB 2.0 iv Track ID: JATR-2265-11 Rev. 1.4

DVB-T COFDM Demodulator + USB 2.0 1 Track ID: JATR-2265-11 Rev. 1.4 1. General Description The RTL2832U is a high-performance DVB-T COFDM demodulator that support s a USB 2.0 interface. The RTL2832U complies with NorDig Unified 1.0.3, D-Book 5.0, and EN300 744 (ETSI Specification). It supports 2K or 8K mode with 6, 7, and 8MHz ba ndwidth. Modulation parameters, e.g., code rate, and guard interval, are automatically detected. The RTL2832U supports tuners at IF (Intermedia te Frequency, 36.125MHz), low-IF (4.57MHz), or Zero-IF output using a 28.8MHz crystal. Embedde d with an advanced ADC (Analog-to-Digital Converter), the RTL2832U features high stability in portable reception. The state-of-the-art RTL2832U features Realtek proprietary algorithms (patent-pending), including superior channel estimation, co-cha nnel interface rejecti on, long echo channel reception, and impulse noise cancellation, and provide s an ideal solution for a wide range of applications for PC-TV, such as USB dongle and MiniCard/USB, and embedded system via USB interface.

DVB-T COFDM Demodulator + USB 2.0 2 Track ID: JATR-2265-11 Rev. 1.4 2. Features „ COFDM complying with Nordig Unified 1.0.3, D-book 5.0, and ETSI 300-744 „ Supports multiple IF frequencies (4.57MHz or 36.167MHz) and spectrum inversion „ Supports Zero-IF input „ Single low-cost crystal for clock generation (±100ppm) „ Automatic transmission mode and guard interval detection „ Impulse noise cancellation circuits „ Automatic carrier recovery over a wide range offset (±800KHz) „ Superior performance with pre/post/long echo profiles „ Embedded adjacent and co-channel interference rejection circuit „ Delayed AGC with programmable Take-Over Point (TOP) „ 7-bit ADC for RF signals level measurement „ Hardware MPEG-2 PID filters „ Infra-red port for remote control and wake-up, protocols supported are ‹ Microsoft RC6 protocol ‹ NEC, Sony, SIRC, RC-5 protocol „ Eight general purpose I/O ports „ USB 2.0 Interface ‹ Supports USB Full/High speed ‹ Configurable vendor information via external EEPROM ‹ Passes USB-IF certification „ Signal 3.3V external power is required „ 48-pin QFN (6x6 mm2) Green Package 3. System Applications „ Portable DTV device „ USB dongle „ MiniCard

28.8 MHz

Figure 1. Block Diagram

Figure 2. Pin Assignments (48-Pin QFN)

Table 1. Pin Descriptions

DVB-T COFDM Demodulator + USB 2.0 6 Track ID: JATR-2265-11 Rev. 1.4 Name Pin number Function Type VINR 6 Low Speed 7-bit ADC Single-Ended Input I USB Interface HSDP 40 USB D+ Signal I/O HSDM 41 USB D- Signal I/O UVDDA 42 USB 1.2V Analog Power Supply PS (1.2V) SEGND 39 Reference Ground GND Host Interface I2C_SCL 18 I 2C Interface Clock Output Pin (5 V oltage Tolerance) OD I2C_SDA 19 I 2C Interface Bi-Directional Data Pin (5 V oltage Tolerance) I/OD I2C_SCLT 16 Output SCLK Signal (5 V oltage Tolerance) for Tuner Control OD I2C_SDAT 17 Output SDA T Signal (5 V oltage Tolerance) for Tuner Control I/OD AGC_IF 13 Control Signal for IF AGC (5 V oltage Tolerance) OD AGC_RF 15 Control Signal for RF AGC (5 V oltage Tolerance) OD M_ERR 35 MPEG Error Output O GPIO Interface and IR IRRC 38 IR Signal Input I GPIO[0] 37 General Purpose I/O Pin-0 Tri GPIO[1] 32 General Purpose I/O Pin-1 Tri GPIO[2] 31 General Purpose I/O Pin-2 Tri GPIO[3] 36 General Purpose I/O Pin-3 Tri GPIO[4] 30 General Purpose I/O Pin-4 Tri GPIO[5] 29 General Purpose I/O Pin-5 Tri GPIO[6] 22 General Purpose I/O Pin-6 Tri GPIO[7] 21 General Purpose I/O Pin-7 Tri Internal 3.3V to 1.2V Switching Regulator ENSWREG 27 0V: Turn off switching regulator 3.3V: Turn on switching regulator (Tie high internally) I SW_VDD3 26, 25 3.3V Power Input PS (3.3V) REG_OUT 24 1.2V Power Output O FB 23 Regulated Feedback V oltage I

DVB-T COFDM Demodulator + USB 2.0 7 Track ID: JATR-2265-11 Rev. 1.4 7. Functional Description The block diagram of the RTL2832U DVB-T demodulat or is shown in Figure 1, page 3. The RTL2832U accepts IF or Zero IF input signals with the analog signal sampled by the internal ADC. The sampled data stream is then processed by OFDM demodulation. After decoding by an on-chip FEC (Viterbi and Reed-Solomon decoder) the USB 2.0 interface outputs packets with transport stream data. A detailed description of each block is given in this section. 7.1. Analog-to-Digital Conversion (ADC) The internal A/D converter can accep t tuner output with various bandwid ths (6, 7, 8MHz), different IF frequencies (4.57M or 36.167M,), Zero IF (I & Q channel) input and can perform spectrum reversion. Using a sampling clock generated by the internal PLL with a 28.8MHz clock source, the RTL2832U demodulates the received TV signal. 7.2. Automatic Gain Control (AGC) The AGC circuit is used to adjust received signal st rength to a moderate leve l for the ADC. This module supports two output paths, and both are sigma-delta modulated signals. The output signals need additional RC LPFs (Low-Pass Filters) before feeding to IF and RF VGA in the tuner The delayed AGC algorithm is described in section 8.1 Automatic Gain Control (AGC), page 11. 7.3. Digital Down Conversion The RTL2832U uses IF or Zero-IF sampling to pro cess received signals. The Digital Down Conversion (DDC) circuit converts the sampled IF signal to a complex base-band si gnal for further processing. The down conversion frequency and low-pa ss filter can be programmed accord ing to different IF frequency, sampling rates, and signal bandwidth.

DVB-T COFDM Demodulator + USB 2.0 8 Track ID: JATR-2265-11 Rev. 1.4 7.4. Resampler The Resampler circuit changes the received signal from a fixed ADC sampling rate to an Orthogonal Frequency Division Multiplexing (OFDM) sampling rate according to the signal bandwidth. The conversion ratio can be programmed via a register setting. 7.5. Guard Interval Removal In time domain modulation, there is a guard inte rval inserted between two Orthogonal Frequency Division Multiplexing (OFDM) signals. It is necessary to remove the guard interval before Fast Fourier Transform (FFT) processing. This module is used to moderate the OFDM symbol boundary for FFT according to the results of synchronization. 7.6. Fast Fourier Transform (FFT) The Fast Fourier Transform (FFT) ci rcuit converts a received time doma in signal to a frequency domain signal. Based on the ETSI 300-744 definition, FFT output contains continuous pilots, scattered pilots, Transmission Parameter Signal (TPS), and data signal. These signals can be us ed for synchronization, channel estimation, and data decision in further processing. 7.7. Synchronization The RTL2832U can measure and compensate for a larg e range of sampling frequency offsets and carrier frequency offsets before making a da ta decision. A moderate symbol bounda ry is utilized to avoid Inter- Symbol Interference (ISI).

DVB-T COFDM Demodulator + USB 2.0 9 Track ID: JATR-2265-11 Rev. 1.4 7.8. Channel Estimation A channel estimation circuit is used to estimate the channel condition of received signals. The estimated channel response can be used for equalization, and is updated symbol by symbol to support mobile channel variations. 7.9. Transmission Parameter Signal Decoder This module is used to decode and determine Transmission Parameter Signal (TPS) bits. The TPS carriers contain parameters for demodulation. These para meters are protected by Bose, Ray-Chaudhuri, Hocquenghem (BCH) encoding. After decoding, the RTL2832U demodulator further processes the decoded information. Parameters such as transmission mo de, guard interval value, code rate etc, can be pre-set by registers to overwrite the result of TPS decoding. 7.10. Equalization To handle various channel conditions, the equaliza tion circuit compensates for the signal degradation caused by different multi-path channel profiles. The data bit is detected based on the equalization output. 7.11. De-Interleaver, FEC Decoder, and Descrambler In accordance with ETSI 300-744, the RTL2832U uses a de-interleaver to re-order the decision data bit to the correct sequence. The Forward Error Correction (F EC) decoder circuit detects and corrects error bits in the received sequence. The descra mbler recovers the output of the decoder to a standard Transport Stream (TS) sequence.

Figure 3. IF or Zero-IF Tuner Interface

values to be programmed by user. optimal values of registers vtop and krf depend on the tuner used. the tuner as shown in Figure 3, page 10. Figure 4. Delayed AGC

DVB-T COFDM Demodulator + USB 2.0 12 Track ID: JATR-2265-11 Rev. 1.4 8.1.1. Register Name: loop_gain Analog Automatic Gain Control (AAG C) loop gain is set by register loop_gain2<3:0> and loop_gain2<4>. Register loop_gain2 can be set to 0~26. The valu e depends on the tuner. The recommended value is 20 (dec). A larger loop_gain value would get a slower AAGC locking time, but more stable AAGC control voltage. There are another loop_gain1 and loop_gain3 for special cases: use loop_gain1 for aagc unlock, and use loop_gain3 for existing interference. Table 2. AAGC Register Table

Description

polar_rf_agc 0 0x0E [1] RW 0 Inverse the AGC_RF Sigma-Delta Pin 0: Normal 1: Inverse polar_if_agc 0 0x0E [0] RW 0 Inverse the AGC_IF Sigma-Delta Pin 0: Normal 1: Inverse loop_gain2<3:0> 1 0x04 [4:1] RW 0 AGC Loop Gain (Bit0~Bit3) for AAGC Lock aagc_hold 1 0x04 [5] RW 0 Hold AAGC Value (Open AAGC Loop) 0: Disable 1: Enable en_rf_agc 1 0x04 [6] RW 1 Enable RF AGC Loop 1: Enable 0: Disable en_if_agc 1 0x04 [7] RW 1 Enable IF AGC Loop 1: Enable 0: Disable loop_gain2<4> 1 0x05 [7] RW 1 AAGC Loop Gain (Bit4) for AAGC Lock loop_gain1 1 0xC7 [5:1] RW C AAGC Loop Gain for AAGC Unlock loop_gain3 1 0xC8 [4:0] RW 1A AAGC Loop Gain for Existing Interference vtop1 1 0x06 [5:0] RW 10 u(6,5f) Set Take-Over Point1 vtop2 1 0xC9 [5:0] RW 30 u(6,5f) Set Take-Over Point2 vtop3 1 0xCA [5:0] RW 28 u(6,5f) Set Take-Over Point3 krf1 1 0xCB [7:0] RW 2 u(8,4f) Set RF AGC Gain Degrade Ratio1 krf2 1 0x07 [7:0] RW F u(8,4f) Set RF AGC Gain Degrade Ratio2 krf3 1 0xCD [7:0] RW 20 u(8,4f) Set RF AGC Gain Degrade Ratio3 krf4 1 0xCE [7:0] RW 30 u(8,4f) Set RF AGC Gain Degrade Ratio4 if_agc_min 1 0x08 [7:0] RW 80 s(8,7f) Set IF AAGC Minimum Gain

DVB-T COFDM Demodulator + USB 2.0 13 Track ID: JATR-2265-11 Rev. 1.4 Register Name Page Offset {LSB, MSB} Bits Used RW Default (Hex) if_agc_max 1 0x09 [7:0] RW 7F s(8,7f) Set IF AAGC Maximum Gain rf_agc_min 1 0x0A [7:0] RW 80 s(8,7f) Set RF AAGC Minimum Gain rf_agc_max 1 0x0B [7:0] RW 7F s(8,7f) Set RF AAGC Maximum Gain if_agc_val 3 {59,5A} [13:0] R - s(14, 13f) IF AAGC Value rf_agc_val 3 {5B,5C} [13:0] R - s(14, 13f) RF AAGC Value aagc_lock 3 0x50 [0] R - AAGC Lock 8.1.2. Register Name: if_agc_min/if_agc_max/rf_agc_min/rf_agc_max Format: s(8,7f) These registers limit the minimum and maximum va lue of RF/IF AGC. They are in 8-bit two’s complement format. The maximum value 127 (dec) means maximum output voltage. For example, if we want to lim it RF minimum/maximum, AGC output voltage would be 10%/90% of pull-high voltage. rf_agc_min=floor (10%*255-128)=-103 (dec) rf_agc_max=floor (90%*255-128)=101 (dec) 8.1.3. Register Name: Vtop Format: u(6,6f) The take-over point of RF VGA is set by register vtop. There are two special cases shown below. The optimal value depends on the tuner. vtop=0 (dec) Æ RF gain is always set on maximum value vtop=63 (dec)Æ RF gain does not delay For example, if we want to degrade RF VGA gain when IF VGA control voltage is smaller than 0.5*Vdd: vtop=floor (63*0.5)=31 (dec)

DVB-T COFDM Demodulator + USB 2.0 14 Track ID: JATR-2265-11 Rev. 1.4 8.1.4. Register Name: Krf Format: u(6,2f) The gain degrade ratio between the RF and IF AGC when input power exceeds the RF take-over point is set by register Krf. A larger krf means the RF Gain degrade ratio is larger. This means an equal gain degrade ratio between the RF and th e IF AGC. If we want RF gain to degrade quickly when input power is larger than the take-over point, krf should be set to a la rger value. If only IF AGC is controlled by the RTL2832U, registers vtop and krf are not used. 8.1.5. Register Name: if_agc_val/rf_agc_val Format: s(14,13f) The RF AAGC value and IF AAGC value are read from registers if_agc_val/rf_agc_val. They are in 14-bit two’s complement format. The minimum value is –8192 and maximum value is 8191. When rf/if_agc_val is set to the maximum value, it means the RF/IF AGC pin output is at the maximum control voltage. The real RF input power can be mapped from if_agc_val/rf_agc_val. The mapping can be to a table or an equation. Note that different vtop and krf settings map different tables and equations. 8.2. ADC Input (Tuner Output) Tuner IF or Zero IF output is AC coupled to th e RTL2832U differential ADC input. An external AC coupling capacitor is required. The schematic is shown in Figure 3, page 10.

Figure 5. Two-Wire Interface between the Tuner and RTL2832U to pull-high resisters (10k ohm) to pull-high the two-wire bus. Table 3. I 2C Repeater Register Table Note 1: IIC_repeat should be set to 1 before sending a command to the tuner. Note2: IIC_repeat is not automatically set to 0 after receiving a ‘STOP’ command.

shows the application circuit. The ENSWREG pin default power is 3.3V. Applying 0V turns off the switching regulator. Figure 6. Internal Switching Regulator Layout

DVB-T COFDM Demodulator + USB 2.0 17 Track ID: JATR-2265-11 Rev. 1.4 9. Register Descriptions (General) 9.1. Analog to Digital Converter (ADC) The RTL2832U can receive IF or Ze ro-IF signals from the tuner. Th e following registers set IF or Zero-IF mode. IF signal mode

• AD_EN_reg1 set 1
• AD_EN_reg0 set 0
• en_bbin set 0 Zero-IF signal mode
• AD_EN_reg1 set 1
• AD_EN_reg0 set 1
• en_bbin set 1

Table 4. ADC Registers AD_EN_reg1 0 0x08 [6] RW 0 1: Enable ADC_Q 0: Disable ADC_Q AD_EN_reg 0 0x08 [7] RW 0 1: Enable ADC_I 0: Disable ADC_I en_bbin 1 0xB1 [0] RW 1 1: Enable Zero-IF input 0: Disable Zero-IF input opt_adc_iq 0 0x06 [5:4] RW 0 0: Default ADC_I, ADC_Q datapath 1: Exchange ADC_I, ADC_Q datapath

DVB-T COFDM Demodulator + USB 2.0 18 Track ID: JATR-2265-11 Rev. 1.4 9.2. DC Cancellation and IQ Compensation In Zero-IF mode, the output signal of the tuner often has DC bias and IQ mismatch issues. The RTL2832U will compensate for these effects. DC cancellation and IQ compensation blocks are default enabled when en_bbin is set to 1. Table 5. DC Cancellation Registers en_dc_est 1 0xB1 [1] RW 1 1: Enable DC estimation and cancellation 0: Disable DC estimation and cancellation en_iq_comp 1 0xB1 [3] RW 1 1: Enable IQ compensation 0: Disable IQ compensation en_iq_est 1 0xB1 [4] RW 1 1: Enable IQ estimation for compensation 0: Disable IQ estimation for compensation Est_kq 1 {0x66,0x67} [11:0] R - Estimated Gain for IQ Gain Mismatch, u(12,11f) Est_sin 1 {0x68,0x69} [11:0] R - Estimated Sin for IQ θ Mismatch, s(12,10f)

DVB-T COFDM Demodulator + USB 2.0 19 Track ID: JATR-2265-11 Rev. 1.4 9.3. Digital Down Conversion (DDC) The Analog-to-Digital Conve rter (ADC) block sub-samples Interm ediate Frequency (IF) signals, and a Digital Down Conversion (DDC) block converts the IF to baseband signals. In normal cases, the tuner is high-side mixing and th e spectrum is inversed. The demodulator requires an inverse spectrum in the DDC (register spec_inv). In the RTL2832U there is an adjacent channel canceller that is enabled or disabled by register en_aci. The initial IF frequency should be set by register pset_iffreq. This register setting depends on th e crystal frequency. The equation of pset_iffreq is shown below: )4194304(_ ×−= crystal DIF f fflooriffreqpset Where: fIF_D: Intermediate Frequency (IF) after sub-sampling fcrystal: Crystal frequency Examples:

• fIF = 4.57M, fADC = 28.8M, pset_iffreq = -665554 Æ 2^22–665554 = 3528750 (two’s complement) = 0x35D82E pset_iffreq = -1072897 Æ 2^22–1072897 = 3121407 (two’s complement) = 0x2FA0FF pset_iffreq = -1066780 Æ 2^22–1066780 = 3127524 (two’s complement) = 0x2FB8E4
• fIF = 0M, fADC = 28.8M, pset_iffreq = 0x0
• DAB Mode, pset_iffreq = -1066988 = 3127316 (two’s complement) = 0x2FB814

DVB-T COFDM Demodulator + USB 2.0 20 Track ID: JATR-2265-11 Rev. 1.4 Table 6. Digital Down Conversion (DDC) Spec_inv 1 0x15 [0] RW 0 1: Spectrum inversion 0: Spectrum non-inversion En_aci 1 0x15 [1] RW 1 1: Enable adjacent channel rejection 0: Disable adjacent channel rejection pset_iffreq 1 {0x19,0x1B} [21:0] RW - Set IF Frequency 9.4. Resampler As the ADC sampling clock is larger than the symbol ratio, there is a re-sampler to convert sampling data to symbol ratio. The ratio can be set via register ‘ rsamp_ratio’. The rsamp_ratio is related to signal bandwidth and crystal frequency. The equation of rsamp_ratio is shown below: )4194304(_ ×= symbol crystal f ffloorratiorsamp Where: fcrystal = crystal frequency fsymbol = symbol ratio of different bandwidths

• BW: 8MHz Æ fsymbol = 64/7 MHz, fcrystal = 28.8MHz rsamp_ratio = 13212057 (dec) = 0x C99999
• BW: 7MHz Æ fsymbol = 8 MHz, fcrystal = 28.8MHz rsamp_ratio = 15099494 (dec) = 0x E66666
• BW: 6MHz Æ fsymbol = 48/7 MHz, fcrystal = 28.8MHz rsamp_ratio = 17616076 (dec) = 0x 10CCCC
• DAB mode rsamp_ratio = 14745600 (dec) = 0x E10000

Table 7. Resampler

DVB-T COFDM Demodulator + USB 2.0 21 Track ID: JATR-2265-11 Rev. 1.4 9.5. Co-Channel Interference Rejection Narrow band in-band interference is detected and rejected by Co-Channel Interference (CCI) rejection. Register en_cci enables or disables Co-Channel Interference Rejection. Table 8. Co-Channel Interference Rejection how many times impulse noise occur. Register inc_det_cnt_rst resets the counter inc_det_cnt. Table 9. Impulse Noise Cancellation en_inc 1 0x5D [0] RW 1 1: Enable impulse noise cancellation 0: Disable impulse noise cancellation inc_det_cnt_rst 1 0x5E [6] RW 0 Reset for inc_det_cnt 1: Reset 0: Normal inc_det_cnt 3 {0x28, 0x29} [8:0] R - Number of Impulse Noise Events

DVB-T COFDM Demodulator + USB 2.0 22 Track ID: JATR-2265-11 Rev. 1.4 9.7. Digital Automatic Gain Control (DAGC) The RTL2832U features Digital Automatic Gain Cont rol (DAGC) to adjust optimal signal levels. DAGC can be enabled or disabled via register en_dagc. The DAGC voltage gain is read from register dagc_val. Linear voltage gain of DAGC=dagc_val/16. Table 10. DAGC Registers en_dagc 1 0x11 [0] RW 1 1: Enable DAGC 0: Disable DAGC dagc_val 3 0x05 [7:0] R - Gain of DAGC 9.8. FFT Mode Detection The Fast Fourier Transform (FFT) mode and the Guard Interval are automatically detected by an auto mode detection algorithm. Auto mode detection can also be enabled or disabled by register. When auto mode detection is disabled, the correct FFT mode and Guard Interval can be set manually by register pset_mode_gi. Table 11. FTT Mode Detection dis_auto_scan 1 0x5F [0] RW 0 0: Enable auto mode detection 1: Disable auto mode detection pset_mode_gi 1 0x5F [3:1] RW 3 Pre-Set Guard Interval and FFT Mode 0: 2k, 1/32GI 1: 2k, 1/16GI 2: 2k, 1/8GI 3: 2k, ¼ mode_gi_idx 3 0x51 [2:0] R - Mode and GI Index 0: 2k, 1/32GI 1: 2k, 1/16GI 2: 2k, 1/8GI 3: 2k, ¼GI 4: 8k, 1/32GI 5: 8k, 1/16GI 6: 8k, 1/8GI 7: 8k, ¼GI

DVB-T COFDM Demodulator + USB 2.0 23 Track ID: JATR-2265-11 Rev. 1.4 9.9. Timing Recovery/Carrier Recovery The unique synchronization algorith m in the RTL2832U is capable of dealing with tough receiving conditions. The result of sampling frequency offset can be read from the register sfreq_off, which is denoted in ppm. The estimated carrier freq uency offset can be read from register cfreq_off, which is denoted in carrier spacing. Carr ier spacing depends on signal bandw idth and transmission mode. An example of the computation is shown below: For 8M bandwidth with 8K mode signal, the ca rrier spacing is approximately 1.116 KHz. If the sfreq_off = 0x200 (two’s complement)=512 (dec), cfreq_off=0xFB2E (two’s complement)=64302 (dec), then:

• Sampling frequency offset = sfreq_off / 224*1000000=512/16777216*1000000=30.5176ppm
• Carrier frequency offset = cfreq_off / 27*carrier spacing=64302/128*1.116KHz=560.63KHz In addition, to supporting different crys tal frequency sources, the register cfreq_off_ratio must be set according to the sampling frequency. The cfreq_off_ratio equation is shown below: )1048576(__ ×−= fs ffloorratiooffcfreq FFT Where: fFFT: FFT sampling rate fs: ADC sampling frequency E.g., fS = 28.8M, fFFT = 64/7M, cfrq_off_ratio = -floor (64/7/28.8*1048576) = -332881 (dec) = 0xAEBAF (two’s complement)
• 8M mode, fFFT = 64/7M: cfrq_off_ratio = 715695 (dec) = 0xAEBAF
• 7M mode, fFFT = 8M: cfrq_off_ratio = 757305 (dec) = 0xB8E39
• 6M mode, fFFT = 48/7M: cfrq_off_ratio = 798916 (dec) = 0xC30C4 Carrier Spacing
• 8M mode, fFFT = 64/7M: carrier spacing (8k) = fFFT / 8192 = 1.116071Hz carrier spacing (2k) = fFFT / 2048 = 4.464285Hz

DVB-T COFDM Demodulator + USB 2.0 24 Track ID: JATR-2265-11 Rev. 1.4 Table 12. Timing Recovery/Carrier Recovery cfreq_off_ratio 1 {0x9D, 0x9F} [23:4] RW s(20, 31f) AEBAF Set Carrier Frequency Offset Ratio cfreq_off 3 {0x5F, 0x61} [17:0] R s(18,7f) - Estimated Carrier Frequency Offset sfreq_off 3 {0x18, 0x19} [13:0] R s(14,24f) - Estimated Sampling Frequency Offset 9.10. Crystal The RTL2832U has superior timing offset tracking abili ty, allowing the use of a low-cost crystal as clock source. The timing offset tolerance is ±100 ppm. Th e RTL2832U also supports an oscillator (oscillator output should be connected to the XI pin). Note: For different crystal frequencies, registers such as rsamp_ratio, cfreq_off_ratio, and pset_iffreq need to be set accordingly. 9.11. PID Filter A PID (Packet Identifier) filtering capability allows th e reduction of the transport stream at the output of the demodulator. There are 32 PIDs that can be sele cted within the received multiplex. The following block diagram shows the PID filter functions, and the default register setting will let all PID transport streams pass through. Figure 7. PID Filter Function of the RTL2832U

DVB-T COFDM Demodulator + USB 2.0 25 Track ID: JATR-2265-11 Rev. 1.4 Table 13. PID Filter err_pass 0 0x61 [5] RW 1 Set 0 to Reject All Error Packets Set 1 to Pass All Error Packets mode_PID 0 0x61 [6] RW 1 Set 0 to Pass Matched PID Set 1 to Reject Matched PID enable_PID 0 0x61 [7] RW 1 Set 1 to Enable Output of PID Filter Set 0 No Output en_PID[7:0] 0 0x62 [7:0] RW 0 Enable (1) and Disable (0) Individual PID Filter 0~7 en_PID[15:8] 0 0x63 [7:0] RW 0 Enable (1) and Disable (0) Individual PID Filter 8~15 en_PID[23:16] 0 0x64 [7:0] RW 0 Enable (1) and Disable (0) Individual PID Filter 16~23 en_PID[31:24] 0 0x65 [7:0] RW 0 Enable (1) and Disable (0) Individual PID Filter 24~31 PID0 0 {0x66, 0x67} [12:0] RW 00 PID Value for PID Filter #0 PID1 0 {0x68, 0x69} [12:0] RW 01 PID Value for PID Filter #1 PID2 0 {0x6A, 0x6B} [12:0] RW 06 PID Value for PID Filter #2 PID3 0 {0x6C, 0x6D} [12:0] RW 11 PID Value for PID Filter #3 PID4 0 {0x6E, 0x6F} [12:0] RW 12 PID Value for PID Filter #4 PID5 0 {0x70, 0x71} [12:0] RW 13 PID Value for PID Filter #5 PID6 0 {0x72, 0x73} [12:0] RW 14 PID Value for PID Filter #6 PID7 0 {0x74, 0x75} [12:0] RW 15 PID Value for PID Filter #7 PID8 0 {0x76, 0x77} [12:0] RW 16 PID Value for PID Filter #8 PID9 0 {0x78, 0x79} [12:0] RW 17 PID Value for PID Filter #9 PID10 0 {0x7A, 0x7B} [12:0] RW 18 PID Value for PID Filter #10 PID11 0 {0x7C, 0x7D} [12:0] RW 19 PID Value for PID Filter #11 PID12 0 {0x7E, 0x7F} [12:0] RW 1A PID Value for PID Filter #12 PID13 0 {0x80, 0x81} [12:0] RW 1B PID Value for PID Filter #13 PID14 0 {0x82, 0x83} [12:0] RW 1C PID Value for PID Filter #14

DVB-T COFDM Demodulator + USB 2.0 26 Track ID: JATR-2265-11 Rev. 1.4 Register Name Page Offset {MSB,LSB} Bit Used RW Default (Hex) PID15 0 {0x84, 0x85} [12:0] RW 1D PID Value for PID Filter #15 PID16 0 {0x86, 0x87} [12:0] RW 1E PID Value for PID Filter #16 PID17 0 {0x88, 0x89} [12:0] RW 1F PID Value for PID Filter #17 PID18 0 {0x8A, 0x8B} [12:0] RW 20 PID Value for PID Filter #18 PID19 0 {0x8C, 0x8D} [12:0] RW 21 PID Value for PID Filter #19 PID20 0 {0x8E, 0x8F} [12:0] RW 22 PID Value for PID Filter #20 PID21 0 {0x90, 0x91} [12:0] RW 23 PID Value for PID Filter #21 PID22 0 {0x92, 0x93} [12:0] RW 24 PID Value for PID Filter #22 PID23 0 {0x94, 0x95} [12:0] RW 25 PID Value for PID Filter #23 PID24 0 {0x96, 0x97} [12:0] RW 26 PID Value for PID Filter #24 PID25 0 {0x98, 0x99} [12:0] RW 27 PID Value for PID Filter #25 PID26 0 {0x9A, 0x9B} [12:0] RW 28 PID Value for PID Filter #26 PID27 0 {0x9C, 0x9D} [12:0] RW 29 PID Value for PID Filter #27 PID28 0 {0x9E, 0x9F} [12:0] RW 2A PID Value for PID Filter #28 PID29 0 {0xA0, 0xA1} [12:0] RW 2B PID Value for PID Filter #29 PID30 0 {0xA2, 0xA3} [12:0] RW 2C PID Value for PID Filter #30 PID31 0 {0xA4, 0xA5} [12:0] RW 2D PID Value for PID Filter #31

1. Register Descriptions (8051 System)

The address is defined by offset value with base address 0x3000. Table 14. System Register Descriptions

DVB-T COFDM Demodulator + USB 2.0 28 Track ID: JATR-2265-11 Rev. 1.4 Address Offset Access Name Description FD05h - IR_MAX_DURATION1 Max Time Duration Configuration Register FD06h - IR_IDLE_LEN0 Idle Length Configuration Register FD07h - IR_IDLE_LEN1 Idle Length Configuration Register FD08h - IR_GLITCH_LEN Glitch Le ngth Configuration Register FD09h - IR_RX_BUFFER_CTRL IR RX Buffer Control Register FD0Ah - IR_RX_BUFFER_DA TA IR Buffer Data for MCU Access FD0Bh - IR_RX_BC Frame RX Byte Counter Register FD0Ch - IR_RX_CLK Frame RX Byte Counter Register. Not Available in Suspend FD0Dh - IR_RX_C_COUNT _L IR Received Carri er Count Register FD0Eh - IR_RX_C_COUNT_H IR R eceived Carrier Count Register FD0Fh - - Reserved FD10h - IR_SUSPEND_CTRL Suspend Control Register FD11h - IR_Err_Tolerance_CTRL IR Error Tolerance Control Register FD12h - IR_UNIT_LEN 1T Unit Length Register FD13h - IR_ERR_Tolerance_LEN High Level Unit Negative Tolerance Length Register FD14h - IR_MAX_H_Tolerance_LEN High Level Max Tolerance Length Register FD15h - IR_MAX_L_Tolerance_LEN Low Level Max Tolerance Length Register FD16h - IR_MASK_CTRL Mask Control Register FD17h - IR_MASK_DATA Mask Data Register FD18h - IR_RESUME_MASK_ADDR IR Resume Mask Address Register FD19h - IR_RESUME_MASK_T_LEN IR Resume Mask Length Register I2C Master Registers 0040h RW I2CCR I 2C Clock Register 0044h RW I2CMCR I 2C Master Control Register 0048h RW I2CMSTR I 2C Master SCL Timing Register 004Ch RW I2CMSR I 2C Master Status Register 0050h RW I2CMFR I 2C Master FIFO Register.

Table 15. Demodulator Control Register (DEMOD_CTL, 0000h)

1. GPIO [0]: Output for VDD1 power control. Default value 1 to turn off power.
2. GPIO [1]: Input for power-on latch to select clock source. Input value depends on the crystal on

board; default 0 for 28.8MHz.

1. GPIO [2]: Input for external I 2C mode, internal pull-down. This pi n is used for LED control after

8051 firmware runs, and will set to 0 to turn off the LED, or 1 to turn it on.

1. GPIO [3]: Input for USB remote wakeup. Input value 0 is to activate remote wakeup.

Output for tuner power control. Default value 1 to turn off power.

1. GPIO [4]: Output for antenna power c ontrol. Default value 0 to turn off power.
2. GPIO [5]: Input for power-on latch to select clock source, input value depends on the crystal on

board. Default 0 for 28.8MHz.

Table 16. GPIO Output Value Register (GPO, 0001h) 7 RW 0 Output Value of GPIO 7. Valid only when GPIO 7 is defined as output pin. 6 RW 0 Output Value of GPIO 6. Valid only when GPIO 6 is defined as output pin. 5 RW 0 Output Value of GPIO 5. Valid only when GPIO 5 is defined as output pin. 4 RW 1 Output Value of GPIO 4. Valid only when GPIO 4 is defined as output pin. 3 RW 1 Output Value of GPIO 3. Valid only when GPIO 3 is defined as output pin. 2 RW 0 Output Value of GPIO 2. Valid only when GPIO 2 is defined as output pin. 1 RW 0 Output Value of GPIO 1. Valid only when GPIO 1 is defined as output pin. 0 RW 0 Output Value of GPIO 0. Valid only when GPIO 0 is defined as output pin. Table 17. GPIO Input Value Register (GPI, 0002h) 7 R - Input Value of GPIO 7. Valid only when GPIO 7 is defined as input pin. 6 R - Input Value of GPIO 6. Valid only when GPIO 6 is defined as input pin. 5 R - Input Value of GPIO 5. Valid only when GPIO 5 is defined as input pin. 4 R - Input Value of GPIO 4. Valid only when GPIO 4 is defined as input pin. 3 R - Input Value of GPIO 3. Valid only when GPIO 3 is defined as input pin. 2 R - Input Value of GPIO 2. Valid only when GPIO 2 is defined as input pin. 1 R - Input Value of GPIO 1. Valid only when GPIO 1 is defined as input pin. 0 R - Input Value of GPIO 0. Valid only when GPIO 0 is defined as input pin.

Table 18. GPIO Output Enable Register (GPOE, 0003h)

7 RW 0

Output Enable for GPIO 7. Valid only when GPIO 7 is defined as output pin.

6 RW 0

Output Enable for GPIO 6. Valid only when GPIO 6 is defined as output pin.

5 RW 0

Output Enable for GPIO 5. Valid only when GPIO 5 is defined as output pin.

4 RW 1

Output Enable for GPIO 4. Valid only when GPIO 4 is defined as output pin.

3 RW 1

Output Enable for GPIO 3. Valid only when GPIO 3 is defined as output pin.

2 RW 0

Output Enable for GPIO 2. Valid only when GPIO 2 is defined as output pin.

1 RW 0

Output Enable for GPIO 1. Valid only when GPIO 1 is defined as output pin.

0 RW 1

Output Enable for GPIO 0. Valid only when GPIO 0 is defined as output pin. Table 19. GPIO Direction Control Register (GPD, 0004h)

4 RW 0

2 RW 1

1 RW 1

0 RW 0

Table 20. PAD Configuration Register for GPIO0~3 (GP_CFG0, 0007h) 7:6 RW 2h GP_PAD3. PAD configuration as internal pull-up or pull-down for GPIO3. 5:4 RW 1h GP_PAD2. PAD configuration as internal pull-up or pull-down for GPIO2. 3:2 RW 1h GP_PAD1. PAD configuration as internal pull-up or pull-down for GPIO1. 1:0 RW 2h GP_PAD0. PAD configuration as internal pull-up or pull-down for GPIO0. Table 21. PAD Configuration Register for GPIO4 (GP_CFG1, 0008h) 7:6 RW 1h GP_PAD7. PAD configuration as internal pull-up or pull-down for GPIO7. 5:4 RW 1h GP_PAD6. PAD configuration as internal pull-up or pull-down for GPIO6. 3:2 RW 1h GP_PAD5. PAD configuration as internal pull-up or pull-down for GPIO5. 1:0 RW 1h GP_PAD4. PAD configuration as internal pull-up or pull-down for GPIO4.

1. [0:0] – Normal No pull-up or pull-down.
2. [0:1] – 75kΩ resistor pull-down.
3. [1:0] – 75kΩ resistor pull-up.

Table 22. I 2C Clock Register (I2CCR, 0040h-0043h) FD10. Frequency 10M Divisor and 0 are forbidden. 10M=Bus clock/(FD10+1). Table 23. I 2C Master Control Register (I2CMCR, 0044h-0047h)

31 RW 0

30 RW 0

Does not include the slave address byte in the FIFO register.

24 RW 1

If TOR is required, the I2C rate must be constrained within 25kbps~400kbps. This constraint is due to the time-out register bit.

DVB-T COFDM Demodulator + USB 2.0 34 Track ID: JATR-2265-11 Rev. 1.4 Bits Access Reset Description 23:16 RW 3Ah TOR. Time-Out Register Time-out = TOR x 2 x ((FD10+1)/Bus clock) (For receive /transmit one bit). If time-out occurs, it will trigger the Transaction Error Interrupt Flag. Note: Time-out must > (1 SCL low period + repeat start setup time). 15:11 - - Reserved

10 RW 0

SBAIFD. Second Byte ACK in FRSIB Data SBAIFD indicates whether the master checks for ACK from slave after emitting second data in FRSIB data. 0: Check 1: Do not check

9 RW 0

FBAIFD. First Byte ACK in FRSIB Data FBAIFD indicates whether the master checks for ACK from slave after emitting first data in FRSIB data. 0: Check 1: Do not check 8:7 RW 0 SRSIB. Second Repeat Start Interval Byte After transmitting SRSIB bytes following the first repeat start command, the master will produce a second repeat start command. The slave address or device address byte is included in this interval. Default interval is one byte. 0=1 byte; 1=2 bytes, etc. Note: The eighth bit of slave address or device address byte followed by second repeat start command must be 1(means a Read CMD). 6:5 RW 0 FRSIB. First Repeat Start Interval Byte After transmitting FRSIB bytes following the original start command, the master will produce the first repeat start command. The original slave address or device address byte is included in this interval. Default interval is one byte. 0=1 byte; 1=2 bytes, etc. 4:3 RW 0 RSC. Repeat Start Count 00: No repeat start 01: One repeat start 10: Two repeat starts 11: Reserved 2 RW 0 TEIE. Transaction Error Interrupt Enable 1 RW 0 MRCIE. Master Receive Complete Interrupt Enable 0 RW 0 MTCIE. Master Transmit Complete Interrupt Enable

Table 24. I 2C Master SCL Timing Register (I2CMSTR, 0048h-004Bh) In repeat start, the setup time of SCL must match the I2C spec. time of SCL more than 300ns. SHPC must include rising time in the I2C. The I2C specification requires SHPC to include rising time. The I2C specification requires SLPC to include falling time. Table 25. I 2C Master Status Register (I2CMSR, 004Ch-004Fh) flag up and return the bus to idle. Write ‘1’ to clear. 1 RW 0 MRCIF. Master Receive Complete Interrupt Flag. Write ‘1’ to clear. 0 RW 0 MTCIF. Master Transmit Complete Interrupt Flag. Write ‘1’ to clear.

Table 26. I 2C Master FIFO Register (I2CMFR, 0050h-0053h) 7:0 RW 0 TDD. Target Device Data. Read for receive.

1. Register Descriptions (USB Interface)

configured to BULK mode or ISO mode. function is permitted on the host. Table 27. Vendor Commands

DVB-T COFDM Demodulator + USB 2.0 37 Track ID: JATR-2265-11 Rev. 1.4 Command bmRequestType (1 Byte) bRequest (1 Byte) wValue (2 Bytes) wIndex (2 Bytes) wLength (2 Bytes) SetUSBReg 0x40 x (BaseAdd)<<8 + OffsetAdd 0x0110 Length of registers to access GetSysReg 0xC0 x (BaseAdd)<<8 + OffsetAdd 0x0200 Length of registers to access SetSysReg 0x40 x (BaseAdd)<<8 + OffsetAdd 0x0210 Length of registers to access GetTunReg 0xC0 x (OffsetAdd)<<8+ IICAdd 0x0300 Length of registers to access SetTunReg 0x40 x (OffsetAdd)<<8+ IICAdd 0x0310 Length of registers to access GetROMCode 0xC0 x Rom Code Address 0x0400 Size of ROM Code GetSTDI2C 0xC0 x I 2C Device Address/ Device register address 0x0600 Length of registers to access SetSTDI2C 0x40 x I 2C Device Address/ Device register address 0x0610 Length of registers to access Note1: Demod registers are organized in 5 pages (page0~page4). ‘wIndex’ indicates the page’ s number. Note2: Before accessing the tuner, the 7 th bit of the first byte of the demodulator’ s page1 should be set to 1 (IIC_repeat bit). Table 28. Definition of ‘wIndex’ Note: To access the tuner, the command is issued within the DATA stage, ignoring the ‘wValue’ field value. The command depends on the tuner used.

Table 29. SIE Control Register

Table 30. USB System Control Register (USB_SYSCTL, 0000h)

3 RW 0

is less than the maximum packet size, SIE will NAK the IN request. Table 31. Endpoint A Configurat ion Register (USB_EPA_CFG, 0144h) definition as wMaxPacketSize[12:11] in standard Endpoint Descriptor). Must be set to 00 (means 1 transaction per microframe). 0: Disable Endpoint A 1: Enable Endpoint A.

4 R -

Table 32. Endpoint A Control Register (USB_EPA_CTL, 0148h) Table 33. Endpoint A Max Packet Size Register (USB_EPA_MAXPKT, 0158h) Defines the max packet size (in bytes) of endpoint A. Table 34. Endpoint A FIFO Configuration Register Counts blocks dropped (each is 188 bytes) due to full FIFO. Configures EPA FIFO size, in 188-byte blocks. Valid data range is 1~10.

Table 35. Absolute Maximum Ratings Table 36. DC Characteristics *: In case of 64QAM, Code rate=2/3, Guard Interval=1/4, Bandwidth=8MHz, bypass internal switching regulator.

Figure 8. Two-Wire Interface Timing Diagram Table 37. Two-Wire Interface Timing Note: Depends on the external bus pull high resistor.

Table 38. Crystal Conditions

without modifying this datasheet. Figure 9. Application Circuits

DVB-T COFDM Demodulator + USB 2.0 45 Track ID: JATR-2265-11 Rev. 1.4 14. Mechanical Dimensions

DVB-T COFDM Demodulator + USB 2.0 46 Track ID: JATR-2265-11 Rev. 1.4 14.1. Mechanical Dimensions Notes Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A3 0.20REF 0.008REF D/E 6.00BSC 0.236BSC D1/E1 5.75BSC 0.226BSC e 0.40BSC 0.016BSC θ 0 o - 14 o 0 o - 14 o Notes 1: DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. Notes 2: CONTROLLING DIMENSION: MILLIMETER (mm). Notes 3: REFERENCE DOCUMENT: JEDEC MO-220.

Table 39. Ordering Information Note: See page 4 for Green package and version identification.