RT9645

RT9645 RICHTEK | Alldatasheet

Document overview

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Technical content

Features

zzzzz Integrated 5 Channels Power Regulator zzzzz DC/DC Buck PWM Regulator (Driver Included) zzzzz DC/DC Buck PWM Controller zzzzz Linear Regulator Controller for FSB_VTT Power zzzzz 3.3VSB Linear Regulator Controller with 40mA Output Capability zzzzz 5VDL Switch Control zzzzz Conform to ACPI Specification, Supporting Power Management at S0, S3, and S5 State zzzzz 300kHz Fixed Frequency Oscillator zzzzz Low-Side R DS(ON) Current Sensing for Precision Over-Current Detection zzzzz Thermal Shutdown zzzzz Small 24-Lead VQFN Package zzzzz RoHS Compliant and 100% Lead (Pb)-Free

5 Channels ACPI Regulator

Applications

(TOP VIEW) VQFN-24L 4x4 Package Type QV : VQFN-24L 4x4 RT9645 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commer- cial Standard) Note : Richtek Pb-free and Green products are : \RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. \Suitable for use in SnPb or Pb-free soldering processes. \`100% matte tin (Sn) plating. SB3V_DRV VDD PWM2 SS2/EN2 COMP2 FB2 VTT_DRV VTT_SEN VTT_EN ISNS2 FB1 COMP1 LGATE BOOT UGATE PHASE PVIN ISNS VCC_DRV GND SB3V_SEN SB5V_DRV 21 20 19 89 1 0 1 2 24 2223 PGND

DS9645-00 August 2007www.richtek.com Functional Pin Description Pin No. Pin Name Function Description 1 SB3V_DRV Gate Drive for 3.3VSB Linear Controller. The pin will be high in S0, S3 and S5 state. 2 VDD IC Power Supply. 5VSB is generally applied for bias power for IC logics and gate driver control.

3 PWM2 Second PWM Output Signal

4 SS2/EN2 Second PWM Soft Start Ramp/Enable Control SS ramp slope is defined by

V/T = 5μA/CSS. 5 COMP2 Compensation pin of PWM2. Output of the PWM2 error amplifier. Connect compensation network between this pin and FB2. 6 FB2 The output feedback of PWM2. The pin is applied for voltage regulation and provide under-voltage protection.

7 BOOT The pin is applied for VDDQ PWM boot strapped power for the embedded driver

power. 8 UGATE High-Side Drive. High-side MOSFET driver output of VDDQ PWM. Connect to gate of high-side MOSFET. 9 PHASE Phase Node of VDDQ PWM. The pin is applied to sense phase node of VDDQ PWM for gates switch control. 10 ISNS Current Sense Input. Monitors the voltage drop across the low-side MOSFET for Over current protection. ROCSET1 x 40μA = RDS(ON) x IMAX 11 PVIN Apply to Driver Power Source and generate Internal Power Good Signal. 12 LGATE Low-Side Drive. The low-side MOSFET driver output. Connect to gate of low-side MOSFET.

13 COMP1

Compensation pin of VDDQ. Output of the VDDQ error amplifier. Connect compensation network between this pin and FB1 In AMD Application. This pin can be used to control VDDQ sequence. This pin needs to be pulled low ( < V DIS1) to disable the PWM. 14 FB1 The output feedback of PWM1. The pin is applied for voltage regulation, under-voltage and Over Voltage protection. 15 ISNS2 PWM2 Current Sense Input. Monitors the voltage drop across the low-side MOSFET for Over current protection. ROCSET2 x 40μA = RDS(ON) x IMAX 16 VTT_EN In AMD K8 Application, Connect this pin to VLDT_EN to control FSB_VTT Timing. 17 VTT_SEN Feedback for the FSB_VTT Linear Controller. The pin is applied for FSB_VTT LDO output regulation sense. 18 VTT_DRV Gate drive for FSB_VTT Linear Controller. The pin will be turned off in S3 and S5 state. 19 GND Signal Ground. 20 SB5V_DRV 5VSB Control Switch. The pin is applied to drive an external P-Channel MOSFET to switch 5VDL power to 5VSB in S3 state. The pin goes high in S0 and S5 States. 21 VCC_DRV VCC5 Control Switch. The pin is applied to driver an external N-Channel MOSFET low in S5 and S3 States. The pin goes high in S0 State. 22 S5 ACPI Control Signal. 23 S3 ACPI Control Signal. 24 SB3V_SEN Feedback for the 3.3VSB Linear Controller. The pin is applied for 3.3V LDO output regulation sense. Exposed Pad (25) PGND The exposed pad must be soldered to a large PCB and connected to PGND for maximum power dissipation.

DS9645-00 August 2007 www.richtek.com Function Block Diagram 40uA UV Digital & Peripheral Control COMP1FB COMP2 FB2 LGATE GND UGATE BOOT PHASE ISNS Oscillator EN_Detect 40uA ISNS2 EN_Detect SS2/EN2 SS PWM2 SB3V_SEN SB3V_DRV VTT_DRV PVIN Thermal shut_down Hiccup Back S5 SB3V Fault (UV &OC) VCC_DRV SB5V_DRV PVIN VDD VTT_SEN VDDQ OC S3 S5 IOC2 IOC1 VDD 70k 35k VTT_EN VREF VREF VDD PVIN VDDQ UV or FSB-VTT UV

DS9645-00 August 2007www.richtek.com

Electrical Characteristics

(VDD = 5V, PVIN = 12V, TA = 25°C, unless otherwise specification) To be continued Absolute Maximum Ratings (Note 1) z PHASE to GND z BOOT to GND z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 4) z ESD Susceptibility (Note 2) Recommended Operating Conditions (Note 3) Parameter Symbol Test Condition Min Typ Max Units Supply Current Nominal Supply Current I CC S0; no load for UGATE / LGATE and regulators -- 4 -- mA Power-On Reset Rising VDD POR Threshold V PORH_5V 3.9 4.1 4.3 V VDD POR Hysteresis V PORHYS_5V 0.06 0.1 -- V Rising PVIN POR Threshold V PORH_12V V DD = 5V 9 9.5 10 V PVIN POR Hysteresis V PORHYS_12V VDD = 5V 0.6 1 -- V

DS9645-00 August 2007 www.richtek.com Parameter Symbol Test Condition Min Typ Max Units Oscillator and Soft-Start PW M Frequency f OSC 265 300 345 kHz Ramp Amplitude ΔVOSC -- 1 .2 -- V Ramp Offset V OSC_OS -- 0 .9 -- V Soft-Start Interval T SS 4 8 - - ms Reference Voltage Reference Voltage V REF V REF 0.784 0.8 0.816 V VDDQ PWM1 Controller UGATE Source I UGA TEsc VBOOT −VPHASE = 12V; VUGATE − VPHASE = 6V 0.5 1 -- A UGATE Sink R UGA TEsk VBOOT −VPHASE = 12V; VUGATE − VPHASE = 1V -- 4 8 Ω LGATE Source I LGATEsc V PVIN = 12V; VLGATE = 6V 0.5 1 -- A LGATE Sink R LGATEsk V PVIN = 12V; VLGATE = 1V - - 3 5 Ω OC Current Source I OC1 V IS NS = 0V 34 40 46 μA Under Voltage Lockout V UV1 -- 75 -- % COMP1 Enable Threshold V EN1 0.1 0.2 -- V PWM2 Controller OC current source I OC2 V IS NS2 = 0V 34 40 46 μA Under Voltage Lockout V UV2 -- 75 -- % SS2/EN2 Source Current I SS2 V SS2/EN2 = 0V -- 5 -- μA Enable Threshold V EN2 -- 0 .5 -- V UV Protection Enable Threshold V PT_EN2 V DD = 5V -- 3.6 -- V FSB_VTT Regulator External Gate Driver V OH3 V PVIN = 12V 10.5 -- -- V Gate Source Current I SC3 V VTT_DRV = 3V -- 4 -- m A Gate Sink Current I SK3 V VTT DRV = 0.6V 15 22 -- mA Under Voltage Lockout V UV3 -- 75 -- % 3VSB Regulator Regulated Voltage V 3VSB 3.2 3.3 3.4 V Source Current I SC4 30 40 -- mA OC Current I OC4 40 80 -- mA Under Voltage Lockout V UV4 -- 75 -- % Others S3, S5 High Input Threshold VIL -- -- 0 .75 V S3, S5 Low Input Threshold V IH 2.2 -- -- V Ther mal Shutdown Limit T SHDN -- 140 -- °C

DS9645-00 August 2007www.richtek.com Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution is highly recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θ JA is measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of θJC is on the expose pad for the QFN package.

DS9645-00 August 2007 www.richtek.com Overview The RT9645 integrates two synchronous buck PWM controllers, two LDO controllers, and a dual power switching controller. It is primarily designed for computer applications powered from an ATX power supply. A 300kHz Synchronous Buck PWM controller with a precision 0.8V reference provides the proper Core voltage to the system main memory. A second 300kHz PWM Buck controller which requires an external MOSFET driver, provides the GMCH core voltage. One LDO controller regulates for FSB_VTT termination and other one is for the 3VSB power regulation. RT9645 also provides a dual power control 5VDL for S0 and S3 system power. Table 1 State VCC_DRV SB5V_DRV 5VDL S5 L H Off S3 L L On S0 H H On State FSB _VTT 3VSB VDDQ S5 Off On Off S3 Off On On S0 On On On ACPI State Transitions ACPI compliance is realized through the S3 and S5 sleep signals. Figure 3 shows how the RT9645 regulators are working during all state transitions. S5 to S0 Transition After AC power is plugged, the RT9645 stays in S5 state until the power button is pushed on. The S3 and S5 signals transit to HIGH and the +12V rail starts to ramp up. The RT9645 POR is executed as soon as PVIN voltage exceeds the threshold. In Intel mode, after an internal time delay T SS the VDDQ PWM will enable soft-start sequence and VCC_DRV will change to high. In AMD mode, VDDQ PWM is enabled after VDDQ_EN goes high. FSB_VTT soft-start will follow VDDQ soft-start with a time delay T SS in Intel mode, but in AMD mode FSB_VTT soft-start is triggered by VTT_EN becoming high. After VDDQ rail and the FSB_VTT soft- start completes, all RT9645 regulators work in normal operation. Refer to Figure 3 and Figure 4 for the detailed timing diagrams. OCSETOCSET DS(ON)

40 A RI R

μ×=

Application Information

When S3 goes LOW but S5 still HIGH ,the RT9645 will disable FSB_VTT regulators. SB5V_DRV and VCC_DRV will go low to continually power on 5VDL rail. The memory power V DDQ is also maintained. S3 to S0 Transition When S3 transits from LOW to HIGH with S5 keeps HIGH and after the PVIN exceeds its POR threshold, in Intel mode the RT9645 will wait a time delay T SS and then soft- starts FSB_VTT LDO. In AMD mode, FSB_VTT will soft- start after VTT_EN goes high. S0 to S5 Transition When the system transits from active state to shutdown (S0 to S5) state, the RT9645 keeps powering 3VSB and turn off the other power regulators. Fault Protection The RT9645 monitors the VDDQ ,PWM2 and 3VSB regulator for under voltage and over-current protection. The FSB_VTT LDO regulator is monitored for under voltage protection. If RT9645 detects thermal Shutdown, over current (or Under Voltage) of 3VSB, the RT9645 will immediately shutdown all regulators and jump to first system state to redo power sequence. When VDDQ issues Under Voltage or Over Current or FSB_VTT issues Under Voltage, the RT9645 will immediately enters into S5 sleep state.This can only be cleared by toggling the S5 signal. VDDQ and PWM2 Over Current Protection The RT9645 senses the current flowing through low side MOSFET for over current protection (OCP). A 40μA current source flows through the external resistor R OCSET to PHASE pin causes 40μA x ROCSET voltage drop across the resistor. OCP is triggered if the voltage at PHASE pin (drop of lower MOSFET V DS) is lower than Rocset voltage drop when low side MOSFET conducting. Accordingly inductor current threshold for OCP is a function of conducting resistance of lower MOSFET R DS(ON) as :

DS9645-00 August 2007 www.richtek.com 10 100 1K 10K 100K 1M 10M -60 -40 -20 100 Modulator Gain FLC FESR Closed Loop Gain Compensation Gain Open Loop Error AMP Gain 20LOG IN/ΔVOSC) 20LOG (R1/R2) FZ1 FZ2 FP1 FP2 Frequency (Hz) Gain (dB) Figure 8 Feedback Loop Design Procedure Use these guidelines for locating the poles and zeros of the compensation network : 1. Pick Gain (R2/R1) for desired 0dB crossing frequency (FC). 2. Place 1st zero F Z1 below modulator double pole F LC (~75% FLC). 3. Place 2nd zero FZ2 at modulator double pole FLC. 4. Place 1st pole FP1 at the ESR zero FZ_ESR 5. Place 2nd pole FP2 at half the switching frequency. 6. Check gain against error amplifier's open-loop gain. 7. Pick R FB for desired output voltage. 8. Estimate phase margin and repeat if necessary. Component Selection Components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum BOM cost and maximum reliability. Output Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. For a synchronous buck converter, the ripple current of inductor (%I L) can be calculated as follows : OUTLI N O U T IN OSC VI( V V ) VI LΔ= − × ×× Generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. Make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. Output Capacitor Selection The output capacitors determine the output ripple voltage (%V OUT) and the initial voltage drop after a high slew rate load transient. The selection of output capacitor depends on the output ripple requirement. The output ripple voltage is described as Equation (8). OUTOUT L OSC OUT V1V I ESR (1 D) 8 IL C Δ= Δ × + × − (7) (8) For electrolytic capacitor application, typically 90 to 95% of the output voltage ripple is contributed by the ESR of output capacitors. Paralleling lower ESR ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent ESR and consequently the ripple voltage. Input Capacitor Selection Use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the MOSFETs. The buck converter draws pulsewise current from the input capacitor during the on time of upper MOSFET. The RMS value of ripple current flowing through the input capacitor is described as : IN(RMS) OUTII D ( 1 D )=× × − The input bulk capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. Appropriate high frequency ceramic capacitors physically near the MOSFETs effectively reduce the switching voltage spikes. MOSFET Selection of PWM Buck Converter The selection of MOSFETs is based upon the considerations of R DS(ON), gate driving requirements, and thermal management requirements. The power loss of upper MOSFET consists of conduction loss and switching loss and is expressed as : UPPER COND _UPPER SW _UPPER OUT DS(ON) OUT IN RISE FALL OSC PP P 1IR D IV ( T T ) I 2

DS9645-00 August 2007www.richtek.com where TRISE and TFALL are rising and falling time of VDS of upper MOSFET respectively. RDS(ON) and QG should be simultaneously considered to minimize power loss of upper MOSFET. The power loss of lower MOSFET consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is expressed as : LOWER COND _LOWER RR DIODE OUT DS(ON) RR IN OSC OUT f DIODE OSC PP P P IR ( 1 D ) Q V f 1 + I V T f2 =+ + ×× × where TDIODE is the conducting time of lower body diode. Special control scheme is adopted to minimize body diode conducting time. As a result, the R DS(ON) loss dominates the power loss of lower MOSFET. Use MOSFET with adequate R DS(ON) to minimize power loss and satisfy thermal requirements. MOSFET Selection of LDO The main criteria for selection of the LDO pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature. The power dissipated in the linear regulator is : P D = IOUT(MAX) x (VIN - VOUT) where IOUT(MAX) is the maximum output current and VOUT is the nominal output voltage of LDO. Layout Consideration Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. First, place the PWM power stage components. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of Buck, inductor, and output capacitor should be as close to each other as possible. This can reduce the radiation of EMI due to the high frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. Place the input capacitor directly to the drain of high-side MOSFET. The MOSFETs of linear regulator should have wide pad to dissipate the heat. In multilayer PCB, use one layer as power ground and have a separate control signal ground as the reference of the all signal. To avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. Furthermore, follows below guide lines can get better performance of IC : \The IC needs a bypassing ceramic capacitor as a R-C filter to isolate the pulse current from power stage and supply to IC, so the ceramic capacitor should be placed adjacent to the IC. \Place the high frequency ceramic decoupling close to the power MOSFETs. \The feedback part should be placed as close to IC as possible and keep away from the inductor and all noise sources. \The components of bootstraps should be closed to each other and close to MOSFETs. \The PCB trace from Ug and Lg of controller to MOSFETs should be as short as possible and can carry 1A peak current. \Place all of the components as close to IC as possible.

DS9645-00 August 2007 www.richtek.com Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com Outline Dimension A D E L be SEE DETAIL A Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e 0.500 0.020 L 0.350 0.450 0.014 0.018 V-Type 24L QFN 4x4 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2