RT9629BZQW

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Technical content

Features

 Drive Six N-MOSFETs for 3-Phase Buck PWM Control  Shoot Through Protection  Embedded Bootstrap Diode  Support High Switching Frequency  Fast Output Rising Time  Tri-State PWM Input for Output Shutdown  Small 24-Lead WQFN Package  RoHS Compliant and Halogen Free Simplified Application Circuit Marking Information RT9629BZQW : Product Number YMDNN : Date CodeRT9629B ZQW YMDNN VCCx PHASE1 RT9629B 12V VOUT VIN PHASE2 PWM1 PWM2 PWM1 PWM2 GND PHASE3PWM3PWM3

DS9629B-06 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Function Pin Description Pin No. Pin Name Pin Function 1, 12, 19 UGATE3, UGATE1, UGATE2 High Side Gate Drive Outputs for Phase 3, Phase 1, and Phase 2. Connect this pin to the Gate of high side power MOSFET. 2, 11, 20 BOOT3, BOOT1, BOOT2 Bootstrap Power Pins for Phase 3, Phase 1, and Phase 2. This pin powers the high side MOSFET driver. Connect this pin to the junction of the bootstrap capacitor and the cathode of the bootstrap diode. 3, 14, 23, 25 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 4, 6, 8 NC No Internal Connection. 5, 7, 9 PWM3, PWM2, PWM1 PWM Signal Input. Connect this pin to the PWM output of the controller. 10 POR Power On Reset Signal. 13, 18, 24 PHASE1, PHASE2, PHASE3 Switch Nodes of High Side Driver 1, Driver 2, and Driver 3. Connect this pin to the high side MOSFET Source together with the low side MOSFET Drain and the inductor. 15, 17, 22 LGATE1, LGATE2, LGATE3 Low Side Gate Drive Output for Phase 1, Phase 2, and Phase 3. This pin drives the Gate of low side MOSFET. 16, 21 VCC1, VCC2 Supply Input Pin. VCC1 supplies current for Channel 1 and Channel 2 gate drivers. VCC2 supplies current for Channel 3 gate driver.

Ordering Information

Note : Richtek products are :  RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering processes. (TOP VIEW) WQFN-24L 5x5 Pin Configurations Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) RT9629B Package Type QW : WQFN-24L 5x5 (W-Type) UGATE3 NC GND BOOT3 PHASE2 LGATE1 VCC1 LGATE2 NC PWM1 POR BOOT1 GND LGATE3 VCC2 BOOT2 NC PWM3 PHASE1 GND PWM2 PHASE3 UGATE1 UGATE2 GND 89 1 0 1 1 23 22 21 20

DS9629B-06 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Function Block Diagram Shoot-Through Protection Turn Off Detection Shoot-Through Protection Tri-State Detect VCC1 PWM1 Internal VDD BOOT1 UGATE1 PHASE1 LGATE1 GND VCC1 POR Bootstrap ControlPOR VCC2 Shoot-Through Protection Turn Off Detection Shoot-Through Protection Tri-State Detect VCC1 PWM2 Internal VDD BOOT2 UGATE2 PHASE2 LGATE2 GND VCC1 Bootstrap Control Shoot-Through Protection Turn Off Detection Shoot-Through Protection Tri-State Detect VCC2 PWM3 Internal VDD BOOT3 UGATE3 PHASE3 LGATE3 GND VCC2 Bootstrap Control

DS9629B-06 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Operation POR (Power On Reset) POR block detects the voltage at VCC1 pin and VCC2 pin. When the VCC1 and VCC2 pin voltage is higher than POR rising threshold, POR pin output voltage (POR output) is high. POR output is low when VCC1 and VCC2 are not both higher than POR rising threshold. When the POR pin voltage is high, UGATEx and LGATEx can be controlled by PWMx pin voltage. With low POR pin voltage, both UGATEx and LGATEx will be pulled to low. Tri-State Detect When the POR block output voltage is high, UGATEx and LGATEx can be controlled by PWMx input. There are three PWMx input modes, which are high, low, and shutdown state. If PWMx input is within the shutdown window, both UGATEx and LGATEx output are low. When PWMx input is higher than its rising threshold, UGATEx is high and LGATEx is low. When PWMx input is lower than its falling threshold, UGATEx is low and LGATEx is high. Bootstrap Control Bootstrap control block controls the integrated bootstrap switch. When LGATEx is high (low side MOSFET is turned on), the bootstrap switch is turned on to charge the bootstrap capacitor connected to BOOTx pin. When LGATEx is low (low side MOSFET is turned off), the bootstrap switch is turned off to disconnect VCCx pin and BOOTx pin. Turn-Off Detection Turn-off detection block detects whether high side MOSFET is turned off by monitoring PHASEx pin voltage. To avoid shoot through between high side and low side MOSFETs, low side MOSFET can be turned on only after high side MOSFET is effectively turned off. Shoot-Through Protection : Shoot-through protection block implements the dead time when both high side and low side MOSFETs are turned off. With shoot-through protection block, high side and low side MOSFET are never turned on simultaneously. Thus, shoot through between high side and low side MOSFETs is prevented.

DS9629B-06 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit Power Supply Voltage V CC 4.5 -- 13.2 V Power Supply Current I VCC V BOOTx = 12V, PWMx Floating -- 250 -- A Power On Reset (POR) POR Rising Threshold V POR_r V CCx Rising -- 4 4.4 V POR Falling Threshold V POR_f V CCx Falling 3 3.5 -- V POR Pin High Voltage V POR_H -- 3.5 4 V POR Pin Low Voltage V POR_L -- -- 0.5 V (VCCx = 12V, TA = 25°C unless otherwise specified) Absolute Maximum Ratings (Note 1)  PHASEx to GND  LGATEx to GND  UGATEx to GND  Power Dissipation, PD @ TA = 25°C  Package Thermal Resistance (Note 2)  ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)

DS9629B-06 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 °C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit PWM Input Maximum Input Current I PWM V PWMx = 0V or 5V -- 160 -- A PWMx Floating Voltage V PWM_fl PWMx = Open -- 1.8 -- V PWMx Rising Threshold V PWM_rth 2.3 2.8 3.2 V PWMx Falling Threshold V PWM_fth 0.7 1.1 1.4 V Timing UGATEx Rising Time t UGATEr 3nF load -- 25 -- ns UGATEx Falling Time t UGATEf 3nF load -- 12 -- ns LGATEx Rising Time t LGATEr 3nF load -- 24 -- ns LGATEx Falling Time t LGATEf 3nF load -- 10 -- ns tUGATEpgh -- 60 -- tUGATEpdl VBOOTx VPHASEx = 12V See Timing Diagram -- 22 -- ns tLGATEpdh -- 30 -- Propagation Delay tLGATEpdl See Timing Diagram -- 8 -- ns Output UGATEx Drive Source R UGATEsr V BOOT  VPHASE = 12V , ISo urce = 100mA -- 1.7 --  UGATEx Drive Sink R UGATEsk V BOOT  VPHASE = 12V , ISi nk = 100mA -- 1.4 --  LGATEx Drive Source R LGATEsr I So urce = 100mA -- 1.6 --  LGATEx Drive Sink R LGATEsk I Si nk = 100mA -- 1.1 -- 

DS9629B-06 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Application Circuit Timing Diagram PWMx UGATEx LGATEx tUGATEpdh tLGATEpdl tUGATEpdl tLGATEpdh 90% 90% 1.5V 1.5V 1.5V 1.5V VCC2 PWM1 GND BOOT1 UGATE1 PHASE1 LGATE1 RT9629B QUG112V PWM1 VOUT QLG1 CVCC CBOOT1 CPH1 RVCC RBOOT1 RUG1 RLG1 RPH1 2.2 1µF 1µF 2.2 0 2.2 3.3nF PWM2PWM2 PWM3PWM3 BOOT2 QUG2 QLG2 CBOOT2 CPH2 RBOOT2 RUG2 RLG2 RPH2 1µF 2.2 0 2.2 3.3nF BOOT3 QUG3 QLG3 CBOOT3 CPH3 RBOOT3 RUG3 RLG3 RPH3 1µF 2.2 0 2.2 3.3nF VIN VIN COUT CIN UGATE2 PHASE2 LGATE2 UGATE3 PHASE3 LGATE3 3, 14, 23, 25 (Exposed Pad) VCC116 POR10 270µF x 3 820µF x 6 12V VIN

DS9629B-06 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Time (20ns/Div) Dead Time No Load (5V/Div) UGATE PHASE LGATE Time (20ns/Div) PWM Rising Edge UGATE (20V/Div) PHASE (10V/Div) PWM (10V/Div) LGATE (10V/Div) Time (20ns/Div) PWM Falling Edge UGATE (20V/Div) PHASE (10V/Div) PWM (10V/Div) LGATE (10V/Div) Time (20ns/Div) Dead Time (5V/Div) UGATE PHASE LGATE Full Load Time (20ns/Div) Dead Time (5V/Div) Full Load UGATE PHASE LGATE Time (20ns/Div) Dead Time No Load (5V/Div) UGATE PHASE LGATE

DS9629B-06 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (20ns/Div) Short Pulse No Load UGATE PHASELGATE UGATE − PHASE (5V/Div)

DS9629B-06 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.

Application Information

The RT9629B is a high frequency, triple-channel synchronous rectified. MOSFET driver containing Richtek's advanced MOSFET driver technologies. The RT9629B is designed to be able to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. Supply Voltage and Power On Reset The RT9629B can be utilized under both V CCx = 5V or VCCx = 12V applications which may happen in different fields of electronics application circuits. In terms of efficiency, higher V CCx equals higher driving voltage of UGATEx/LGATEx which may result in higher switching loss and lower conduction loss of power MOSFETs. The choice of V CCx = 12V or V CCx = 5V can be a tradeoff to optimize system efficiency. And VCC1 pin must be directly connected to VCC2 pin. The RT9629B controls both high side and low side N- MOSFETs of three half-bridge power according to three external input PWMx control signals. It has Power On Reset (POR) function which held UGATEx and LGATEx low before the VCCx voltage rises to higher than rising threshold voltage. When V CC1 and VCC2 exceed the POR threshold voltage, the voltage at the POR pin will be pulled high. Tri-state PWM Input After the initialization, the PWMx signal takes the control. The rising PWMx signal first forces the LGATEx signal to turn low then UGATEx signal is allowed to go high just after a non-overlapping time to avoid shoot through current. The falling of PWMx signal first forces UGATEx to go low. When UGATEx and PHASEx signal reach a predetermined low level, LGATEx signal is allowed to turn high. The PWMx signal is acted as “ High” if the signal is above the rising threshold and acted as “ Low” if the signal is below the falling threshold. When PWM signal level enters and remains within the shutdown window, the output drivers are disabled and both MOSFET gates are pulled and held low. If the PWMx signal is left floating, the pin will be kept around 1.8V by the internal divider and provide the PWMx controller with a recognizable level. Bootstrap Power Switch The RT9629B builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate PCB design and reduce total BOM cost of the system. Hence, no external bootstrap diode is required in real applications. Non-overlap Control To prevent the overlap of the gate drivers during the UGATEx pull low and the LGATEx pull high, the non-overlap circuit monitors the voltages at the PHASEx node and high side gate drive (UGATEx − PHASEx). When the PWMx input signal goes low, UGATEx begins to pull low (after propagation delay). Before LGATEx is pulled high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1V. Once the monitored voltages fall below 1.1V, LGATEx begins to turn high. By waiting for the voltages of the PHASEx pin and high side gate driver to fall below 1.1V, the non-overlap protection circuit ensures that UGATEx is low before LGATEx pulls high. Also to prevent the overlap of the gate drivers during LGATEx pull low and UGATEx pull high, the non-overlap circuit monitors the LGATEx voltage. When LGATEx goes below 1.1V, UGATEx goes high after propagation delay. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When V gs1 or Vgs2 is at 12V or 5V, the gate draws the current only for few nano-amperes. Thus once the gate has been driven up to “ ON” level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows.

©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 1. Equivalent Circuit and Waveforms (VCC = 12V) turned on before high side MOSFETs turn on. It is helpful to calculate these currents in a typical case. be calculated as following equations. required from the turned off MOSFET.

DS9629B-06 July 2015www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.250 0.350 0.010 0.014 D 4.950 5.050 0.195 0.199 D2 3.100 3.400 0.122 0.134 E 4.950 5.050 0.195 0.199 E2 3.100 3.400 0.122 0.134 e 0.650 0.026 L 0.350 0.450 0.014 0.018 D A E2E be D2 SEE DETAIL A L W-Type 24L QFN 5x5 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2