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Technical content
Features
Drive Six N-MOSFETs for 3-Phase Buck PWM Control Adaptive Shoot-Through Protection Support High Switching Frequency Fast Output Rising/Falling Time Propagation Delay 40ns Tri-State Input for Bridge Shutdown Upper MOSFET Direct Short Protection Small 24-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free
Applications
CPU Core Voltage Supplies on Motherboard High Frequency Low Profile DC/DC Converters High Current Low Voltage DC/DC Converters Triple-Channel Synchronous-Rectified Buck MOSFET Driver
Ordering Information
For marking information, contact our sales representative directly or through a Richtek distributor located in your area. Pin Configurations (TOP VIEW) VQFN-24L 4x4 Note : Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. UGATE1 GND GND LGATE3 PVCC3 BOOT2 UGATE2 GND PWM2 PWM1 NC BOOT1 987 1 01 11 2 23 22 21 20 19 PWM3 VDD BOOT3 UGATE3 PHASE3 GND PHASE1 LGATE1 PVCC1 PVCC2 LGATE2 PHASE2 GND Package Type QV : VQFN-24L 4x4 (V-Type) (Exposed Pad-Option 1) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) RT9605B
DS9605B-04 May 2014www.richtek.com All brandname or trademark belong to their owner respectively Typical Application Circuit Functional Pin Description UGATE1 (Pin 1), UGATE2 (Pin 17), UGATE3 (Pin 10) Upper Gate Drive Output. Should be connected to the upper MOSFET gate. BOOT1 (Pin 2), BOOT2 (Pin 16), BOOT3 (Pin 9) Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. NC (Pin 3) No connected. PWM1 (Pin 4), PWM2 (Pin 5), PWM3 (Pin 7) PWM input control signal. Connect this pin to the PWM output of the controller. If the PWM signal enters and remains within the shutdown window, are both UGATE and LGATE are drived low, disabling the output MOSFETs. GND (Pin 6, 12, 13, 18 ) Chip power ground. VDD (Pin 8) Supply Input. Connect to +5V stand-by power. Place a bypass capacitor between this pin and GND. PHASE1 (Pin 24), PHASE2 (Pin 19), PHASE3 (Pin 11) Upper driver return. Should be connected to the common node of upper and lower MOSFETs. The PHASE voltage is monitored for adaptive shoot-through protection. LGATE1 (Pin 23), LGATE2 (Pin 20), LGATE3 (Pin 14) Lower Gate Drive Output. Should be connected to the lower MOSFET gate. PVCC1 (Pin 22), PVCC2 (Pin 21), PVCC3 (Pin 15) Supply Input. Connect to +12V supply. Place a bypass capacitor between this pin and PGND. Exposed Pad Exposed pad should be soldered to PCB board and connected to GND. PHASE3 PHASE2 PHASE1 PI DACQ DACFB PGOOD PWM3 PWM2 ISP3 ISP2 FB COMP VDD PWM1 RT DVD ICOMMON ISP1 VID0 VID2 VID3 VID4 VID1 VID5 3.3V 12V VCORE 5VSB 81 2 1316 GND 15k 10nF 33pF 4.7µF Optional Optional Optional 1µF 1µF 1µF 430 3k 16k 27k 10k 1.8k 110k 56k 27k 13k 6.8k 3.3k R R R RT8800 5.1k BOOT2 PWM3 PWM2 PWM1 BOOT1 LGATE3 PVCC3 PHASE3 UGATE3 BOOT3 UGATE2 PVCC2 PHASE2 LGATE2 NC UGATE1 PVCC1 PHASE1 LGATE1 VDD 12V 5VSB PHASE1 VIN PHASE2 VCORE PHASE3 12 4 2 2 2 3 20211917 GND 12V 12V 12V VIN 1µF1000µF 1µH 01µF 1µF 1µF 3.3nF 2.2 1µF 01µF 0 3.3µF2.2 0.5µH 0.5µH 0.5µH 1µF 3.3nF 2.2 1µF 10µF x 4 1000µF x 12 RT9605B 1500µF x 4 VIN Optional Optional RDROOP RICOMMON1 RICOMMON2 R10 R11 R12 R13 R14 R15 R16 R17 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 C8 C9 C10 to C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 to C35 C36 to C39 Q1 Q2 Q4 Q5
DS9605B-04 May 2014 www.richtek.com All brandname or trademark belong to their owner respectively Function Block Diagram Timing Diagram Control Logic BOOT1 UGATE1 PHASE1 PVCC1 LGATE1 GND BOOT2 UGATE2 PHASE2 PVCC2 LGATE2 GND BOOT3 UGATE3 PHASE3 PVCC3 LGATE3 GND PWM1 PWM2 PWM3 Short-Through Protection Short-Through Protection Short-Through Protection VDD VDD VDD PWM UGATE LGATE TRUGATE TPDUGATE TFUGATE TRLGATE TFLGATE TPDLGATE 90% 10% 90% 10% 90% 10% 90% 10%
DS9605B-04 May 2014www.richtek.com All brandname or trademark belong to their owner respectively Absolute Maximum Ratings (Note 1) PHASE to GND LGATE PVCC + 0.3V) UGATE Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3)
Electrical Characteristics
Recommended Operating Conditions (Note 4) (Recommended Operating Conditions, T A = 25 °C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VDD Supply Current Operation Current IVDD Frequency = 250kHz -- -- 10 mA Power On Reset PVCC POR Threshold VPVCC Rising 7.2 8 8.8 V PVCC Hysteresis -- 1.1 -- V VDD Threshold V DD Rising 3.7 4 4.3 V PWM Input VPWM_IN = 0V 500 600 700 Input Current IPWM VPWM_IN = 5V 200 350 500 Floating Voltage VPWMFL 1.4 1.8 2.2 V To be continued
DS9605B-04 May 2014 www.richtek.com All brandname or trademark belong to their owner respectively Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θ JA is measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit VPW MRTH PWM_IN Rising 2.7 3.1 3.5 V PWM Threshold VPWMFTH PWM_IN Falling 0.8 1 1.3 V Output UGATE Rise Time t RUGATE PV CC = 12V, 3nF load -- 80 -- ns UGATE Fall Time t FUGATE PV CC = 12V, 3nF load -- 40 -- ns LGATE Rise Time t RLGATE PV CC = 12V, 3nF load -- 40 -- ns LGATE Fall Time t FLGATE PV CC = 12V, 3nF load -- 25 -- ns UGATE Turn-Off Propagation Delay t PDUGATE PV CC = 12V, 3nF load -- 30 -- ns LGATE Turn-Off Propagation Delay t PDLGATE PV CC = 12V, 3nF load -- 25 -- ns Shutdown Window 0.8 -- 3.5 V
DS9605B-04 May 2014www.richtek.com All brandname or trademark belong to their owner respectively Typical Operating Characteristics VIN = 12V, unless otherwise specified. Dead Time Time (50ns/Div) Phase 2, Falling VOUT = 1.4V, IOUT = 30A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 1, Falling V OUT = 1.4V, IOUT = 0A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 1, Rising V OUT = 1.4V, IOUT = 0A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 1, Falling V OUT = 1.4V, IOUT = 30A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 1, Rising V OUT = 1.4V, IOUT = 30A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 2, Falling V OUT = 1.4V, IOUT = 0A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div)
DS9605B-04 May 2014 www.richtek.com All brandname or trademark belong to their owner respectively Dead Time Time (50ns/Div) Phase 3, Rising VOUT = 1.4V, IOUT = 0A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 3, Falling V OUT = 1.4V, IOUT = 30A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 3, Falling V OUT = 1.4V, IOUT = 0A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 2, Rising V OUT = 1.4V, IOUT = 30A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 2, Rising V OUT = 1.4V, IOUT = 0A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div) Dead Time Time (50ns/Div) Phase 3, Rising V OUT = 1.4V, IOUT = 30A LGATE (5V/Div) UGATE (5V/Div) PHASE (5V/Div)
DS9605B-04 May 2014www.richtek.com All brandname or trademark belong to their owner respectively Power On Time (2.5ms/Div) VOUT = 1.4V, IOUT = 90A VIN (10V/Div) UGATE (20V/Div) LGATE (10V/Div) VOUT (2V/Div) Power On Time (2.5ms/Div) VOUT = 1.4V, IOUT = 0A VIN (10V/Div) UGATE (20V/Div) LGATE (10V/Div) VOUT (2V/Div) Power Off Time (25ms/Div) VOUT = 1.4V, IOUT = 90A VIN (10V/Div) UGATE (20V/Div) LGATE (10V/Div) VOUT (2V/Div) Power Off Time (25ms/Div) VOUT = 1.4V, IOUT = 0A VIN (10V/Div) UGATE (20V/Div) LGATE (10V/Div) VOUT (2V/Div) Efficiency vs. Output Curreent 76% 78% 80% 82% 84% 86% 88% 90% 0 1 02 03 04 05 06 07 08 09 0 1 0 0 Output Curreent (A) Efficiency (%) VIN = 12V, f = 300kHz VOUT = 1.45V
DS9605B-04 May 2014 www.richtek.com All brandname or trademark belong to their owner respectively
Application Information
The RT9605B is designed to drive three sets of both high side and low side N-MOSFET through externally input PWM control signal. It has power-on protection function which held UGATE and LGATE low before PV CC rising across the threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE turns low then UGATE is allowed to go high just after a non-overlapping time to avoid shoot- through. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE reach a predetermined low level, LGATE is allowed to turn high. The non- overlapping function is also presented between UGATE and LGATE signal transient. The PWM signal is acted as "High" if above the rising threshold and acted as "Low" if below the falling threshold. Any signal level remaining within the shutdown window is considered as "tri-state", the output drivers are disabled and both MOSFET gates are pulled and held low. If the PWM signal floating, the pin will be kept at 2.1V by the internal divider and provide the PWM controller with a recognizable level. The RT9605B typically operates at frequency of 200kHz to 300kHz. It shall be noted that to place a 1N4148 or schottky diode between the PVCC and BOOT pin as shown in the typical application circuit. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When V gs at 12V, the gate draws the current only few nano-amperes. Thus once the gate has been driven up to "ON" level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large current to source and sink the gate rapidly. It also needs to switch drain current on and off with high speed. The required gate drive currents are calculated as follows. In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging C gd and Cgs. Cgs1 and Cgs2 are the capacitances from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the C gs is referred as "Ciss" which is the input capacitance. Cgd1 and Cgd2 are the capacitances from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as "C rss" the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current I gs1 and Igs2 are showed below : Figure 1. Equivalent Circuit and Associated Waveforms
DS9605B-04 May 2014www.richtek.com All brandname or trademark belong to their owner respectively When layout the PC board, it should be very careful. The power-circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close. Next, the trace from UGATE, and LGATE to the gates of MOSFET should also be short to decrease the noise of the driver output signals. The bypass capacitor C4 should be connected to GND directly. Furthermore, the bootstrap capacitors (C B) should always be placed as close to the pins of the IC as possible. The trace from PHASE to the common node of the two MOSFETs should be kept wide since it usually carries large current.
DS9605B-04 May 2014 www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Outline Dimension V-Type 24L QFN 4x4 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2 Min. Max. Min. Max. 0.800 1.000 0.031 0.039 0.000 0.050 0.000 0.002 0.175 0.250 0.007 0.010 0.180 0.300 0.007 0.012 3.950 4.050 0.156 0.159 Option 1 2.400 2.500 0.094 0.098 Option 2 2.650 2.750 0.104 0.108 3.950 4.050 0.156 0.159 Option 1 2.400 2.500 0.094 0.098 Option 2 2.650 2.750 0.104 0.108 0.350 0.450 0.014 0.018 0.500 0.020 L b D E e Symbol Dimensions In Millimeters Dimensions In Inches A