RT9470

RT9470 RICHTEK | Alldatasheet

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Technical content

Features

⚫ High Efficiency, 1.5MHz, Synchronous Switch-Mode Buck Charger  92% Charge Efficiency at 2A from 5V Input and 3.8V Battery  Support 3.9V to 13.5V Input Voltage Range  Average Input Current Regulation (AICR)  Minimum Input Voltage Regulation (MIVR)  Minimum Input Voltage Regulation Track (MIVR Track)  Charge Current Regulation (CCR)  Charge Voltage Regulation (CVR)  Charge Voltage Regulation Track (CVR Track)  Junction Thermal Regulation (JTR) ⚫ Supports USB On-The-Go (OTG)  92% Boost Efficiency at 1A with 3.8V Battery and 5.15V Output  OTG Current Limit Regulation (OCLR)  OTG Voltage Limit Regulation (OVLR) ⚫ Protection  Over-Temperature Protection (OTP)  VBUS Over-Voltage Protection (VBUS OVP)  Battery Over-Voltage Protection (VBAT OVP)  System Over-Voltage Protection (VSYS OVP)  System Under-Voltage Protection (VSYS UVP)  System Over-Load Protection (VSYS OLP)  Cycle-by-Cycle Over-Current Protection (OCP)  OTG Low Battery Protection (OTG LBP) Simplified Application Circuit BAT VBUS PMID Host BTST SW SYS TS Battery Pack System QON USB RT9470/D VAC CBUS CSYS CBTST L CBAT Host control I2C BUS REGN

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Marking Information 1N : Product Code YMDNN : Date Code RT9470WSC 1N YM DNN 1P : Product Code YMDNN : Date Code 1P YM DNN RT9470DWSC Pin Configuration (TOP VIEW) INTBATSNSSYSBAT SCL SDACESYSBAT STAT QONTSSYSBAT PG REGNBTSTSYSBAT PSEL VBUSPMIDSWGND NC VBUSPMIDSWGND VAC F4F3F2F1 F5 E4E3E2E1 E5 D4D3D2D1 D5 C4C3C2C1 C5 B4B3B2B1 B5 A4A3A2A1 A5 WL-CSP-30B 2.1x2.5 (BSC) (RT9470) INTBATSNSSYSBAT SCL SDACESYSBAT STAT QONTSSYSBAT D- REGNBTSTSYSBAT D+ VBUSPMIDSWGND NC VBUSPMIDSWGND VAC F4F3F2F1 F5 E4E3E2E1 E5 D4D3D2D1 D5 C4C3C2C1 C5 B4B3B2B1 B5 A4A3A2A1 A5 WL-CSP-30B 2.1x2.5 (BSC) (RT9470D) Functional Pin Description Pin No. Pin Name I/O Pin Function RT9470 RT9470D A1, B1 A1, B1 GND P Power ground. A2, B2 A2, B2 SW P Switching node connecting to output inductor. Internally SW is connected to the source of the high-side switching MOSFET (Q2) and the drain of the low -side switching MOSFET (Q3). Connect a 47nF bootstrap capacitor from SW to BTST. A3, B3 A3, B3 PMID P Connected to the drain of the reverse blocking MOSFET (Q1) and the drain of high -side switching MOSFET (Q2). Connect 10F capacitor from PMID to GND. A4, B4 A4, B4 VBUS P Charger input voltage. The internal reverse block MOSFET (Q1) is connected between VBUS and PMID with VBUS on source. Connect a 1 F capacitor from VBUS to GND and place it as close as possible to IC. A5 A5 VAC AI Input voltage sensing. This pin must be tied to VBUS. B5 B5 NC -- No internal connection.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Pin No. Pin Name I/O Pin Function RT9470 RT9470D C1, D1, E1, F1 C1, D1, E1, F1 BAT P Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 F capacitor closely to the BAT pin. C2, D2, E2, F2 C2, D2, E2, F2 SYS P Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect two 10F capacitors closely to the SYS pin. C3 C3 BTST P PWM high -side driver positive supply. Internally, the BTST is connected to the cath ode of the boos t-strap diode. Connect the 47nF bootstrap capacitor from SW to BTST. C4 C4 REGN P PWM low -side driver and internal supply output. Internally, REGN is connected to the a node of the bootstrap diode. Connect a 4.7 F capacitor from REGN to GND. The capacitor should be placed close to the IC. C5 -- PSEL DI Power source selection input. High indicates 0.5A input current limit. Low indicates 2.4A input current limit. Once the device gets into host mode, the host can program different input current limit to AICR register. -- C5 D+ AIO Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detections in BC1.2. D3 D3 TS AI Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin voltage is out of range. When TS pin is not used, connect a 10k  resistor from REGN to TS and a 10k resistor from TS to GND. D4 D4 QON DI BATFET (Q4) enable control input. When BATFET is in ship mode, a logic low duration turns on BATFET (Q4) to exit shipping mode. When no VBUS, a logic low for tQON_RST, the BATFET turns off for tBATFET_RST, and then re -enable BATFET to provide system reset. Pull-High to internal bias circuit via 250k resistor. D5 -- PG DO Open-drain active low power good indicator. Connect the PG pin to a logic rail via 2.2k to 10k resistor. -- D5 D- AIO Negative line of the USB data line pair. D+/D – based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detections in BC1.2. E3 E3 CE DI Charge enable pin. When this pin is driven low, battery charging is enabled. E4 E4 SDA DIO I2C interface clock. Connect SDA to the logic rail through a 10k resistor. E5 E5 STAT DO Open-drain charger status output. Connect the STAT pin to a logic rail via 2.2k  to 10k resistor. The STAT pin indicates charger status.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Pin No. Pin Name I/O Pin Function RT9470 RT9470D F3 F3 BATSNS AI Battery voltage sensing pin for charge current regulation. The BATNS pin must be connected to the battery pack as close as possible. F4 F4 INT DO Open-drain active low interrupt output. Connect the INT to a logic rail through 10k  resistor. The INT pin sends active low pulse to host to report charger device status and fault. F5 F5 SCL DI I2C interface clock. Connect SCL to the logic rail through a 10k resistor. Functional Block Diagram RT9470 Functional Block Diagram VBUS BTST GND SWConverter Control REGN REGN PMID REGN LDOQ1 Control Digital Control BAT SYS Power Path Control QON Power Select BATPMID Protection Input Source Detection I2C Interface SDA SCL INT CE JEITA Control STAT REGN TS Switching- well Control PSEL TS Sensing VDDAPG SensingVAC BATSNS

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com RT9470D Functional Block Diagram VBUS BTST GND SWConverter Control REGN REGN PMID REGN LDOQ1 Control Digital Control BAT SYS Power Path Control QON Power Select BATPMID Protection Input Source Detection I2C Interface SDA SCL INT CE JEITA Control STAT REGN TS Switching- well Control TS Sensing VDDA SensingVAC BATSNS

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Absolute Maximum Ratings (Note 1) ⚫ Power Dissipation, PD @ TA = 25C ⚫ Package Thermal Resistance (Note 2) ⚫ ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com

Electrical Characteristics

(VBUS_MIN_RISE < VAC < VAC_OVP_RISE and VAC > VBAT + VSLEEP_RISE, TA = 25C, unless otherwise specified) (Note 5) Parameter Symbol Test Conditions Min Typ Max Unit Quiescent Current Battery Discharge Current (BAT) in Q4 Disabled IBAT_Q4_DIS VBAT = 4.5V, High -Z mode and I 2C disabled, Q4 disabled -- 15 32 A Battery Discharge Current (BAT) in Q4 Enable IBAT_Q4_EN VBAT = 4.5V, High -Z mode and I 2C disabled, Q4 enabled -- 55 85 A Input Supply Current (VBUS) in Buck Mode IBUS_HIZ VBUS = 5V, High-Z mode and no battery -- 50 86 VBUS = 12V, High-Z mode and no battery -- 52 88 Input Supply Current (VBUS) in Buck Mode IBUS_BUCK VBUS > VBUS_MIN_RISE, VBUS > VBAT, converter switching, VBAT = 3.8V, ISYS = 0A -- 5 7 mA Battery Discharge Current (BAT) in Boost Mode IBAT_BOOST VBAT = 4.2V, boost mode, IBUS = 0A, converter switching -- 4 5 mA VAC, VBUS and BAT Power VBUS Operating Range VBUS_OP VBUS rising 3.9 -- 13.5 V REGN Turn Off Level with Only VBUS VBUS_UVLO VBUS falling 3.0 3.3 3.6 V Sleep Mode Falling Threshold VSLEEP_FALL VAC falling, VAC – VBAT 10 60 120 mV Sleep Mode Rising Threshold VSLEEP_RISE VAC rising, VAC – VBAT 160 250 340 mV VAC 5.8V Over-Voltage rising threshold VAC_OVP_RISE VAC rising 5.5 5.8 6.1 V VAC 6.5V Over-Voltage rising threshold VAC rising 6.2 6.5 6.8 VAC 10.9V Over-Voltage Rising Threshold VAC rising 10.3 10.9 11.5 VAC 14V Over-Voltage Rising Threshold VAC rising 13.3 14 14.7 VAC 5.8V Over-Voltage Hysteresis VAC_OVP_HYS VAC falling -- 300 -- mV VAC 6.5V Over-Voltage Hysteresis VAC falling -- 300 -- VAC 10.9V Over-Voltage Hysteresis VAC falling -- 300 -- VAC 14V Over-Voltage Hysteresis VAC falling -- 300 -- BAT for Active I2C, No Adapter VBAT_UVLO VBAT rising 2 2.2 2.4 V

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Parameter Symbol Test Conditions Min Typ Max Unit Battery Depletion Falling Threshold VBAT_DPL_FALL VBAT falling 2.15 2.38 2.65 V Battery Depletion Rising Threshold VBAT_DPL_RISE VBAT rising 2.4 2.6 2.8 V Battery Depletion Rising Hysteresis VBAT_DPL_HYS VBAT rising -- 220 -- mV Bad Adapter Detection Rising Threshold VBUS_MIN_RISE VBUS rising 3.6 3.8 4 V Bad Adapter Detection Hysteresis VBUS_MIN_HYS VBUS falling -- 200 -- mV Bad Adapter Detection Current Source IBADSRC Sink current from VBUS to GND -- 40 -- mA Power Path System Regulation Voltage VSYS_MIN VBAT < VSYS_MIN = 3.5V, Q4 disabled/enable 3.5 3.5 +0.2 -- V VSYS ISYS = 0A, VBAT > VSYS_MIN = 3.5V, Q4 disabled -- VBAT +0.05 -- Top Reverse Blocking MOSFET On-Resistance Between VBUS and PMID Top Switching MOSFET On- Resistance Between PMID and SW RON(Q2) VREGN = 5V, −40°C ≤ TA ≤ 125°C -- 46 -- m Bottom Switching MOSFET On-Resistance Between SW and GND RON(Q3) VREGN = 5V, −40°C ≤ TA ≤ 125°C -- 51 -- m SYS-BAT MOSFET On-Resistance RON(BAT-SYS) Measured from BAT to SYS, VBAT = 4.2V, TJ = 25°C -- 14 -- m Battery Charger Charge Voltage Range VBAT_REG_RANGE Default = 4.2V 3.9 -- 4.7 V Charge Voltage Step VBAT_REG_STEP -- 10 -- mV Charge Voltage Setting Accuracy VBAT_REG_ACC –0.5 -- 0.5 % Charge Current Regulation Range ICHG_REG_RANGE Default = 2000mA 0 -- 3150 mA Charge Current Regulation Step ICHG_REG_STEP -- 50 -- mA Charge Current Regulation Accuracy ICHG_REG_ACC VBAT = 3.8V, ICHG_REG < 150mA –20 -- 20 % VBAT = 3.8V, 150mA ≤ I CHG_REG < 750mA –10 -- 10 VBAT = 3.8V, ICHG_REG ≥ 750mA –5 -- 5 Pre-Charge Falling Threshold VPRE_CHG_FALL ICHG = 200mA, VPRE_CHG = 3.1V 2.75 2.9 3.05 V Pre-Charge Rising Threshold VPRE_CHG_RISE Pre-charge to fast charge, VPRE_CHG = 3.1V 2.95 3.1 3.25 V

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Pre-Charge Current Range IPRE_CHG_RANGE Default = 150mA 50 -- 800 mA Pre-Charge Current Step IPRE_CHG_STEP -- 50 -- mA Pre-Charge Accuracy IPRE_CHG_ACC VBUS = 5V, IPRE_CHG = 150mA –15 -- 25 % End-Of-Charge Current Range IEOC_CHG_RANGE Default = 200mA 50 -- 800 mA End-Of-Charge Current Step IEOC_CHG_STEP -- 50 -- mA End-Of-Charge Accuracy IEOC_CHG_ACC ICHG_REG > 700mA, IEOC_CHG = 200mA, VBAT = 4.2V −20 -- 20 % ICHG_REG ≤ 700mA, IEOC_CHG = 200mA, VBAT = 4.2V −10 -- 10 ICHG_REG = 600mA, IEOC_CHG = 50mA, VBAT = 4.2V −25 -- 25 Trickle-Charge Falling Threshold VTRICKLE_CHG_ FALL VBAT falling 1.8 2 2.2 V Trickle-Charge Rising Threshold VTRICKLE_CHG_ RISE VBAT rising 2.05 2.25 2.45 V Trickle-Charge Current ITRICKLE_CHG VBAT < VTRICKLE_CHG_RISE 80 100 120 mA Re-Charge Threshold Below VBAT_REG VRE_CHG VBAT falling, VRECHG = 100mV 70 100 130 mV VBAT falling, VRECHG = 200mV 170 200 230 System Discharge Load Current ISYS_LOAD VSYS = 4.2V -- 30 -- mA Input Voltage and Current Regulation Minimum Input Voltage Regulation Range VMIVR_RANGE Default = 4.5V 3.9 -- 5.4 V Minimum Input Voltage Regulation Step VMIVR_STEP -- 100 -- mV Minimum Input Voltage Regulation Accuracy VMIVR_ACC VMIVR = 3.9V and 4.4V −1.5 -- 1.5 % MIVR Tracking VBAT VMIVR_BAT_TRACK VMIVR = 3.9V, VMIVR_BAT_TRACK = 300mV, VBAT = 4V -- 4.3 -- V MIVR Tracking VBAT Accuracy VMIVR_BAT_TRACK _ACC −3 -- 3 % Average Input Current Regulation Range IAICR_RANGE Default = 0.5A 0.05 -- 3.2 A Average Input Current Regulation Step IAICR_STEP -- 50 -- mA Average Input Current Regulation Accuracy IAICR_ACC VBUS = 5V, IAICR = 500mA 450 470 500 mA VBUS = 5V, IAICR = 900mA 780 840 900 VBUS = 5V, IAICR = 1500mA 1300 1400 1500 VBUS = 5V, IAICR > 1500mA −15 -- 0 % BAT Over-Voltage Protection

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Parameter Symbol Test Conditions Min Typ Max Unit Battery Over-Voltage Rising VBAT_OVP_RISE VBAT rising, as percentage of VBAT_REG 103 104 105 % Battery Over-Voltage Falling VBAT_OVP_FALL VBAT falling, as percentage of VBAT_REG 101 102 103 % Input Reverse Blocking NFET and Regulation Junction Thermal Regulation Range TJ_THREG_RANGE Default = 120°C 100 -- 120 °C Junction Thermal Regulation Step TJ_THREG_STEP -- 20 -- °C Thermal Shutdown Rising TOTP Temperature rising -- 160 -- °C Thermal Shutdown Hysteresis TOTP_HYS Temperature falling -- 30 -- °C NTC Monitor (Charger Mode) Battery Temperature COLD Threshold (0°C) VVTS_COLD VTS rising, the ratio of VREGN 72.5 73.5 74.5 % Battery Temperature COOL Threshold (10°C) VVTS_COOL VTS rising, the ratio of VREGN 67.5 68.5 69.5 % Battery Temperature WARM Threshold (45°C) VVTS_WARM VTS falling, the ratio of VREGN 44 45 46 % Battery Temperature HOT Threshold (60°C) VVTS_HOT VTS falling, the ratio of VREGN 33.5 34.5 35.5 % Battery Temperature Hysteresis VVTS_HYS -- 1.5 -- % NTC Monitor (OTG Mode) Battery Temperature COLD Threshold OTG mode (−20°C) VVTS_COLD_OTG VTS rising, the ratio of VREGN 79 80 81 % Battery Temperature HOT Threshold OTG mode (60°C) VVTS_HOT_OTG VTS falling, the ratio of VREGN 33.5 34.5 35.5 % Battery Temperature Hysteresis OTG mode VVTS_HYS_OTG -- 1.5 -- % Charger Over-Current Threshold UGFET Cycle-by-Cycle Over-Current Threshold IOCP_UG 5.5 6.5 7.5 A System Over-Load Threshold IOCP_BATFET 6 -- -- A USB On-The-Go (OTG) OTG Low Battery Protection VOTG_LBP VBAT falling, VOTG_LBP = 2.8V 2.65 2.8 2.95 V VBAT rising, VOTG_LBP = 2.8V 2.75 2.9 3.05 VBAT falling, VOTG_LBP = 2.5V 2.35 2.5 2.65 VBAT rising, VOTG_LBP = 2.5V 2.45 2.6 2.75

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit OTG Voltage Limit Regulation Range VOTG_CV_RANGE Default = 5.15V 4.85 -- 5.3 V OTG Voltage Limit Regulation Step VOTG_CV_STEP -- 150 -- mV OTG Voltage Limit Regulation Accuracy VOTG_CV_ACC VBAT = 3.8V, IPMID = 0A, V OTG_REG = 5.15V −3 -- 3 % OTG Current Limit Regulation Accuracy IOTG_CC IOTG_LIMIT_REG_SEL = 1.2A 1.2 1.4 1.6 A IOTG_LIMIT_REG_SEL = 0.5A 0.5 0.6 0.7 OTG Over-Voltage Threshold VOTG_OVP VAC rising, VAC_OVP = 6.5V 6.2 6.5 6.8 V OTG Capacitive Load COTG_LOAD VBAT = 3.8V, VOTG_REG = 5.15V, capacitive load plug in -- -- 300 F PWM PWM Switching Frequency fSW_BUCK Oscillator frequency, buck mode 1350 1500 1650 kHz fSW_BOOST Oscillator frequency, boost mode 1350 1500 1650 Maximum PWM Duty Cycle DMAX -- 97 -- % REGN REGN LDO Output Voltage VREGN VBUS = 9V, IREGN = 40mA 4.5 4.9 5.3 V VBUS = 5V, IREGN = 20mA 4.5 4.9 5 Control I/O Pin (CE, PSEL, SCL and SDA) Input High Threshold Voltage VIH_CTRL 1.3 -- -- V Input Low Threshold Voltage VIL_CTRL -- -- 0.4 V High Level Leakage Current IBIAS Pull high to 1.8V -- -- 1 A Control I/O Pin (PG, STAT and INT) Output Low Threshold Voltage VOL_CTRL -- -- 0.4 V INT Pull Low Time tINT_PULL_LOW INT pull low time -- 256 -- s D+/D- Detection Data Detect Voltage VDAT_REF 0.25 0.325 0.4 V D- Current Sink ID-_ISNK 50 100 150 A D+D- Leakage Current ID+D-_LKG −1 -- 1 A D- Pull Down for Connection Check RD-_19K 14.25 19.53 24.8 k D+D- Threshold for Non-Standard Adapter (1.2V) D+D- Threshold for Non-Standard Adapter (2V) VD+D-_2P0 -- 2 -- V

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Parameter Symbol Test Conditions Min Typ Max Unit D+D- Threshold for Non-Standard Adapter (2.8V) Timing Requirements VAC OVP Reaction Time tVAC_OVP -- 200 -- ns Bad Adapter Detection Duration tBAD_AD_ DETECTION -- 30 -- ms Deglitch Time for Charger EOC tEOC_DGL -- 256 -- ms Deglitch Time for Re-Charge tRE_CHG_DGL -- 256 -- ms Charge Safe Timer tCHG_SAFE_TMR Timer = 10hr 9 10 11 hr Back-Ground Charge Timer tBG_CHG_TMR Timer = 30min 29 30 31 min QON Timing QON Low Time to Exit Shipping Mode tSHIPMODE_EXIT 0.9 1.1 1.3 s QON Low Time to Reset System tQON_RST 9 10 11 s BATFET Reset Time tBATFET_RST 430 453 480 ms Enter Shipping Mode Delay Time tSHIP_MODE_ ENTER 11 12 13 s I2C Clock and Watchdog Timer SCL Clock fSCL MHz 100pF < CB ≤ 400pF -- -- 1.7 Watchdog Timer tWDT Default = 40s -- 40 -- s Watchdog Reset Wait Time tWDT_WAIT -- 500 -- ms Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured under natural convection (still air) at T A = 25°C with the component mounted on a high effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Specification is guaranteed by design and/or correlation with statistical process control.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Typical Application Circuit RT9470 BAT VBUS PMID Host SCL SDA INT REGN BTST SW SYS TS Battery Pack REGN System QON CE PSEL STAT PG REGN USB GND REGN RT9470 C1,D1,E1,F1 C2,D2,E2,F2 A2,B2 A1,B1 VAC A4,B4 A3,B3 BATSNS F3 CBUS 1µF CPMID 10µF CREGN 4.7µF CBTST 47nF L 1µH CSYS 10µF x 2 CBAT 10µF 10kΩ VREF RPULL-UP1 RPULL-UP2 RPULL-UP3 10kΩ 10kΩ RTS1 5.23kΩ/1% 30.1kΩ/1% RTS2 2.2kΩ 2.2kΩ RT9470D BAT VBUS SCL SDA INT REGN BTST SW SYS TS Battery Pack REGN System QON CE STAT REGN USB GND RT9470D 17,18 VAC Host PMID BATSNS A4,B4 A3,B3 C1,D1,E1,F1 C2,D2,E2,F2 A2,B2 CBUS 1µF CPMID 10µF CREGN 4.7µF CBTST 47nF L 1µH CSYS 10µF x 2 CBAT 10µF 10kΩ VREF RPULL-UP1 RPULL-UP2 RPULL-UP3 10kΩ 10kΩ D2 R1 2.2kΩ RTS1 5.23kΩ/1% 30.1kΩ/1% RTS2

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Below are recommended components information Name Description Part Number Package Manufacturer CBUS 1F/25V/X5R GRM155R61E105KA12 0402 muRata CPMID 10F/25V/X5R GRM188R61E106MA73 0603 muRata CBTST 47nF/16V/X5R GRM033R61C473KE84 0201 muRata CSYS 10F/6.3V/X5R GRM185R60J106ME15 0603 muRata CBAT 10F/6.3V/X5R GRM185R60J106ME15 0603 muRata CREGN 4.7F/6.3V/X5R GRM155R60J475ME47 0402 muRata L 1H/20% CIGT252010EH1R0MNE 2.5 x 2.0 x 1.0mm Samsung D1 PTVSHC3N12VU TVS Diode DFN2x2-3L Prisemi

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Typical Operating Characteristics Charger Efficiency vs. Charging Current Charging Current (A) Charger Efficiency (%) VBUS = 5V VBUS = 9V VBUS = 12V VBAT = 3.8V, fSW = 1.5MHz, LDCR = 26m Charger Efficiency vs. Charging Current Charging Current (A) Charger Efficiency (%) VBAT = 4.2V, fSW = 1.5MHz, LDCR = 26m VBUS = 5V VBUS = 9V VBUS = 12V MIVR Tracking VBAT 4.4 4.5 4.6 4.7 4.8 4.9 VBAT Set (V) VBUS (V) VBAT + 300mV VBAT + 250mV VBAT + 200mV Boost Efficiency vs. Output Current Output Current (A) Boost Efficiency (%) VBUS = 5.15V, fSW = 1.5MHz, LDCR = 26m VBAT = 4.35V VBAT = 4.2V VBAT = 3.8V VBAT = 3.5V VBUS = 5V, VBAT = 3.8V, ICHG = 2A REGN (2V/Div) VSYS (2V/Div) RT9470 Power-UP with VBUS Plug In Time (100ms/Div) VBUS (2V/Div) IBAT (2A/Div) REGN (2V/Div) VSYS (2V/Div) RT9470D Power-UP with VBUS Plug In Time (100ms/Div) VBUS = 5V, VBAT = 3.8V, ICHG = 2A, DCP VBUS (2V/Div) IBAT (2A/Div)

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 VSW (5V/Div) ILX (500mA/Div) Buck Switching Time (4s/Div) VBUS = 5V, VBAT = 3.8V, ISYS = 50mA, charging disableVSYS (100mV/Div) Time (4s/Div) Buck Switching VBUS = 9V, VBAT = 3.8V, ISYS = 50mA, charging disable VSW (5V/Div) ILX (500mA/Div) VSYS (100mV/Div) VBUS = 12V, VBAT = 3.8V, ISYS = 50mA, charging disable Buck Switching Time (4s/Div) VSW (5V/Div) ILX (500mA/Div) VSYS (100mV/Div) Buck Switching Time (1s/Div) VBUS = 5V, VBAT = 3.8V, ICHG = 2A VSW (5V/Div) ILX (2A/Div) VSYS (100mV/Div) Time (1s/Div) Buck Switching VBUS = 9V, VBAT = 3.8V, ICHG = 2A VSW (5V/Div) ILX (2A/Div) VSYS (100mV/Div) Time (1s/Div) Buck Switching VBUS = 12V, VBAT = 3.8V, ICHG = 2A VSW (5V/Div) ILX (2A/Div) VSYS (100mV/Div)

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com CE (2V/Div) IBAT (2A/Div) Charge Enable Time (5ms/Div) VBUS = 5V, VBAT = 3.8V, ICHG = 2A STAT (2V/Div) VSW (5V/Div) Time (5ms/Div) Charge Disable VBUS = 5V, VBAT = 3.8V, ICHG = 2A CE (2V/Div) IBAT (2A/Div) STAT (2V/Div) VSW (5V/Div) Time (4s/Div) Boost Switching VBUS (100mV/Div) VSW (5V/Div) OTG_CV = 5.15V, VBAT = 3.8V, IBUS = 10mA ILX (500mA/Div) Time (1s/Div) Boost Switching OTG_CV = 5.15V, VBAT = 3.8V, IBUS = 1A VBUS (100mV/Div) VSW (5V/Div) ILX (1A/Div) PMID (2V/Div) VSW (2V/Div) Boost Start-Up Time (2ms/Div) OTG_CV = 5.15V, VBAT = 3.8V, CBUS = 300F VBUS (2V/Div) IBUS (200mA/Div) Time (50ms/Div) AICC Enable VBUS = 5V, IBUS limit = 500mA, MIVR = 4.5V VBUS (1V/Div)

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Register Descriptions I2C Slave Address : 1010011 (53H) R : Read only R/W : Read and write RWSC : Read and write, also automatically set/clear by particular condition Register Address : 0x00, Register Name : OTG_CONFIG Bit Bit Name Default WDT RST REG RST Type Description 7:6 OTG_CV 10 N Y R/W OTG voltage limit regulation 00 : 4.85V 01 : 5.0V 10 : 5.15V (default) 11 : 5.3V 5:2 Reserved 0000 NA NA R Reserved

1 OTG_LBP 0 N Y R/W

OTG low battery protection 0 : 2.8V (default) 1 : 2.5V

0 OTG_CC 1 Y Y R/W

OTG current limit regulation 0 : 0.5A 1 : 1.2A (default) Register Address : 0x01, Register Name : TOP Bit Bit Name Default WDT RST REG RST Type Description

7 QON_RST_

0 : QON = 0 for 10s will NOT do anything 1 : QON = 0 for 10s will turn off BATFET (default)

6 STAT_EN 1 N Y R/W 0 : STAT pin function disable

1 : STAT pin function enable (default) 5:4 Reserved 00 NA NA R Reserved

3 DIS_I2C_TO 0 Y Y R/W 0 : Enable I2C time-out function (default)

1 : Disable I2C time-out function

2 WDT_CNT_

0 : No action 1 : Reset watchdog counter (Notice : Back to 0 after watchdog reset) 1:0 WDT 01 Y Y R/W 00 : Disable watchdog timer reset function 01 : 40s (default) 10 : 80s 11 : 160s

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Register Address : 0x02, Register Name : FUNCTION Bit Bit Name Default WDT RST REG RST Type Description

7 BATFET_DIS 0 N Y RWSC

0 : Allow BATFET turn on (default) 1 : Force BATFET turn off (Notice : Clear by VBUS plug in or QON = 0 for 1s,auto set BATFET_DIS = 1 by system overload from BAT to SYS)

6 BATFET_DIS_

0 : BATFET turn off immediately while BATFET_DIS = 0 1 : BATFET turn off with 12s delay while BATFET_DIS = 1 (default)

5 HZ 0 Y Y RWSC

0 : Normal mode (default) 1 : HZ mode (Notice : Clear by VBUS plug in)

4 Reserved 0 NA NA R Reserved

3 BUCK_PFM_

DIS 0 N Y R/W 0 : Enable PFM (default) 1 : Disable PFM

2 UUG_FULLON 0 N Y R/W 0 : Q1 turn on by condition (default)

1 : Force Q1 full on

1 OTG_EN 0 Y Y RWSC

0 : Disable OTG (default) 1 : Enable OTG (Notice : Clear by HZ = 1 or OTP or OTG_LBP or VBUS_OV or QON reset or BATFET_DIS = 1 or auto 7 times hiccup for soft-start fail or overload)

0 CHG_EN 1 Y Y R/W 0 : Disable charge

1 : Enable charge (default) Register Address : 0x03, Register Name : IBUS Bit Bit Name Default WDT RST REG RST Type Description

7 AICC_EN 0 Y Y RWSC

0 : Disable AICC function (default) 1 : Enable AICC function (Notice : Auto clear after AICC function done)

6 AUTO_AICR 1 Y Y R/W

0 : No action 1 : Auto set IAICR by BC1.2 done or PSEL change (default) 5:0 IAICR 001010 N Y RWSC Average input current regulation 000000 : 50mA 000001 : 50mA 000010 : 100mA 001010 : 500mA (default) 111101 : 3050mA 111110 : 3100mA 111111 : 3200mA (Notice : Auto set by BC1.2 done or PSEL change if AUTO_AICR = 1)

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Register Address : 0x04, Register Name : VBUS Bit Bit Name Default WDT RST REG RST Type Description 7:6 VAC_OVP 01 N Y R/W VAC OVP threshold 00 : 5.8V 01 : 6.5V (default) 10 : 10.9V (6.5V while OTG) 11 : 14V (6.5V while OTG) 5:4 VMIVR_BAT_ TRACK 00 N Y R/W 00 : VMIVR by 0x04[3:0] (default) 01 : VMIVR = VBAT + 200mV 10 : VMIVR = VBAT + 250mV 11 : VMIVR = VBAT + 300mV 3:0 VMIVR 0110 N Y R/W Minimum input voltage regulation 0000 : 3900mV 0001 : 4000mV 0110 : 4500mV (default) ... 1110 : 5300mV 1111 : 5400mV Register Address : 0x05, Register Name : PRECHG Bit Bit Name Default WDT RST REG RST Type Description

7 Reserved 0 NA NA R Reserved

6:4 VPRE_CHG 100 Y Y R/W Pre-charge voltage threshold 000 : 2700mV 001 : 2800mV 010 : 2900mV 011 : 3000mV 100 : 3100mV (default) 101 : 3200mV 110 : 3300mV 111 : 3400mV 3:0 IPRE_CHG 0010 Y Y R/W Pre-charge current 0000 : 50mA 0001 : 100mA 0010 : 150mA (default) ... 1110 : 750mA 1111 : 800mA

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Register Address : 0x06, Register Name : REGU Bit Bit Name Default WDT RST REG RST Type Description

6 THREG 1 Y Y R/W

Junction thermal regulation threshold 0 : 100°C 1 : 120°C (default) 5:4 Reserved 00 NA NA R Reserved 3:0 VSYS_MIN 1001 N Y R/W System minimum voltage 0000 : 2600mV 0001 : 2700mV 1001 : 3500mV (default) ... 1110 : 4000mV 1111 : 4100mV Register Address : 0x07, Register Name : VCHG Bit Bit Name Default WDT RST REG RST Type Description

7 VRE_CHG 0 Y Y R/W

Re-charge voltage threshold 0 : 100mV (default) 1 : 200mV 6:0 VBAT_REG 0011110 Y Y R/W Charge voltage 0000000 : 3900mV 0000001 : 3910mV 0011110 : 4200mV (default) 1010000 : 4700mV 1010000 to 1111111 : 4700mV Register Address : 0x08, Register Name : ICHG Bit Bit Name Default WDT RST REG RST Type Description 7:6 Reserved 00 NA NA R Reserved 5:0 ICHG_REG 101000 Y Y R/W Charge current 000000 : 0mA (disable charge) 000001 : 50mA 000010 : 100mA 000011 : 150mA 101000 : 2000mA (default) 111101 : 3100mA 111111 : 3150mA

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Register Address : 0x09, Register Name : CHG_TIMER Bit Bit Name Default WDT RST REG RST Type Description

7 CHG_SAFE_

TMR_EN 1 Y Y R/W 0 : Disable charge safe timer 1 : Enable charge safe timer (default)

6 CHG_SAFE_

TMR_2XT 1 Y Y R/W Double charge safe timer during MIVR, AICR, thermal regulation, and JEITA reduce ICHG 0 : Disable 2x extended charge safe timer 1 : Enable 2x extended charge safe timer (default) 5:4 CHG_SAFE_ TMR 01 Y Y R/W Charge safe timer 00 : 5hr 01 : 10hr (default) 10 : 15hr 11 : 20hr 3:0 Reserved 0000 NA NA R Reserved Register Address : 0x0A, Register Name : EOC Bit Bit Name Default WDT RST REG RST Type Description 7:4 IEOC_CHG 0011 Y Y R/W End-of-charge current threshold 0000 : 50mA 0001 : 100mA 0010 : 150mA 0011 : 200mA (default) ... 1110 : 750mA 1111 : 800mA 3:2 BG_CHG_ TMR 00 Y Y R/W EOC back-ground charge timer 00 : 0min (default) 01 : 15min 10 : 30min 11 : 45min

1 TE 1 Y Y R/W 0 : Disable charge current termination

1 : Enable charge current termination (default)

0 EOC_RST 0 Y Y RWSC

0 : No action 1 : Reset EOC (Notice : Back to 0 after reset EOC done) Register Address : 0x0B, Register Name : INFO Bit Bit Name Default WDT RST REG RST Type Description

7 REG_RST 0 NA NA RWSC

0 : No action 1 : Reset register (Notice : Back to 0 after register reset) 6:3 DEVICE_ID 1001 NA NA R 1001 : RT9470 (PSEL, PGB) 2:0 DEVICE_RE NA NA NA R Revision

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Register Address : 0x0C, Register Name : JEITA Bit Bit Name Default WDT RST REG RST Type Description

7 JEITA_EN 1 Y Y R/W 0 : JEITA disable

1 : JEITA enable (default)

6 JEITA_COLD 0 Y Y R/W 0 : COLD do NOT charging / OTG (default)

1 : COLD still charging / OTG

5 JEITA_COOL_

ISET 1 Y Y R/W 0 : 50% of ICHG 1 : 25% of ICHG (default)

4 JEITA_COOL_

VSET 1 Y Y R/W 0 : VBAT_REG = 4.1V 1 : VBAT_REG = Register setting (default)

3 JEITA_WARM

_ISET 1 Y Y R/W 0 : 50% of ICHG 1 : ICHG = Register setting (default)

2 JEITA_WARM

_VSET 0 Y Y R/W 0 : VBAT_REG = 4.1V (default) 1 : VBAT_REG = Register setting

1 JEITA_HOT 0 Y Y R/W 0 : HOT do NOT charging / OTG (default)

1 : HOT still charging / OTG

0 Reserved 0 NA NA R Reserved

Register Address : 0x0D, Register Name : PUMP_EXP Bit Bit Name Default WDT RST REG RST Type Description

7 PE_EN 0 Y Y RWSC

0 : Idle (default) 1 : Trigger MTK Pump Express process (Notice : Auto clear while PE done or no VBUS) 6 PE_SEL 0 Y Y R/W 0 : PE 1.0 process select (default) 1 : PE 2.0 process select 5 PE10_INC 0 Y Y R/W 0 : PE 1.0 voltage down (default) 1 : PE 1.0 voltage up 4:0 PE20_CODE 00000 Y Y R/W MTK PE 2.0 voltage request setting 00000 : 5.5V (default) 00001 : 6V 11101 : 20V 11110 : Adapter healthy self-testing 11111 : Disable cable drop compensation

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Register Address : 0x0E, Register Name : DPDM_DET Bit Bit Name Default WDT RST REG RST Type Description

7 BC12_EN 1 Y Y R/W

0 : Disable BC1.2 detection 1 : Enable BC1.2 detection while VBUS > 3.8V (default) (Notice : For RT9470D only) 6:5 DCDT_SEL 01 Y Y R/W 00 : Disable DCD timeout function 01 : Enable 300ms DCD timeout function (default) 10 : Enable 600ms DCD timeout function 11 : Wait data contact

4 SPEC_TA_EN 1 Y Y R/W

0 : Disable Samsung / Apple TA detection 1 : Enable Samsung / Apple TA detection (default) 3:1 Reserved 000 NA NA R Reserved

0 DCP_DP_OPT 0 Y Y R/W

0 : DP = 0V after BC 1.2 done (default) 1 : DP keep 0.6V while DCP port detected

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Register Address : 0x0F, Register Name : IC_STATUS Bit Bit Name Default WDT RST REG RST Type Description 7:4 PORT_STAT 0000 NA NA R 0000 : No information 0001 to 0111 : Reserved 1000 : VBUS = device 1 (2100mA-APPLE-10w) 1001 : VBUS = device 2 (2000mA-SAMSUNG-10w) 1010 : VBUS = device 3 (1000mA-APPLE-5w) 1011 : VBUS = device 4 (2400mA-APPLE-12w) 1100 : VBUS = unknown / NSDP (500mA) 1101 : VBUS = SDP (500mA) / PSEL = High 1110 : VBUS = CDP (1500mA) 1111 : VBUS = DCP (2400mA) / PSEL = Low 3:0 IC_STAT 0000 NA NA R 0000 : HZ/SLEEP 0001 : VBUS ready for charge 0010 : Trickle-charge 0011 : Pre-charge 0100 : Fast-charge 0101 : IEOC-charge (EOC and TE = 0) 0110 : Back-Ground charge (EOC and TE = 1 and before turn off power path) 0111 : Charge done (EOC and TE = 1 and power path off) 1000 : Charge fault (VAC_OV / CHG_BUSUV / CHG_TOUT / CHG_SYSOV / CHG_BATOV / JEITA_HOT / JEITA_COLD / OTP) 1001 to 1110 : Reserved 1111 : OTG

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Register Address : 0x10, Register Name : STAT0 Bit Bit Name Default WDT RST REG RST Type Description

7 ST_VBUS_GD 0 NA NA R

0 : VBUS is not good 1 : VBUS is good (Notice : After current capability of the input source detection, and HZ = 0, VAC_OV = 0, VBUS > 3.8V)

6 ST_CHG_RDY 0 NA NA R

0 : VBUS is not ready for charging 1 : VBUS is ready for charging (Notice : After port detection, and HZ = 0, VAC_OV = 0, VBUS > 3.8V)

5 ST_IEOC 0 NA NA R

0 : Not in EOC state 1 : While in EOC state (Notice : Charge current < IEOC level)

4 ST_BG_CHG 0 NA NA R

0 : Not in EOC state or TE = 0 or BG_CHG_TMR = 00 1 : While in EOC state and TE = 1 and BG_CHG_TMR ≠ 00

3 ST_CHG_

DONE 0 NA NA R 0 : Not in EOC state or BATFET on 1 : While in EOC state and BATFET off 2:1 Reserved 00 NA NA R Reserved

0 ST_BC12_

DONE 0 NA NA R 0 : BC1.2 process not ready 1 : While BC1.2 process done Register Address : 0x11, Register Name : STAT1 Bit Bit Name Default WDT RST REG RST Type Description

7 ST_CHG_

MIVR 0 NA NA R 0 : Not in MIVR loop 1 : While in MIVR loop

6 ST_CHG_

AICR 0 NA NA R 0 : Not in AICR loop 1 : While in AICR loop

5 ST_CHG_

THREG 0 NA NA R 0 : Not in THERMAL loop 1 : While in THERMAL loop

4 ST_CHG_

BUSUV 0 NA NA R 0 : Not VBAT < VBUS < 3.8V 1 : While VBAT < VBUS < 3.8V TOUT 0 NA NA R 0 : Not in charge safety time-out 1 : While in charge safety time-out

2 ST_CHG_

SYSOV 0 NA NA R 0 : Not in SYS OV 1 : While in SYS OV

1 ST_CHG_

BATOV 0 NA NA R 0 : Not in BAT OV 1 : While in BAT OV

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Register Address : 0x12, Register Name : STAT2 Bit Bit Name Default WDT RST REG RST Type Description

7 ST_JEITA_

HOT 0 NA NA R 0 : Not in BAT is hot 1 : While in BAT is hot

6 ST_JEITA_

WARM 0 NA NA R 0 : Not in BAT is warm 1 : While in BAT is warm

5 ST_JEITA_

COOL 0 NA NA R 0 : Not in BAT is cool 1 : While in BAT is cool

4 ST_JEITA_

COLD 0 NA NA R 0 : Not in BAT is cold 1 : While in BAT is cold 3:2 Reserved 00 NA NA R Reserved

1 ST_SYS_MIN 0 NA NA R 0 : Not in VBAT < VSYS_MIN

1 : While in VBAT < VSYS_MIN Register Address : 0x13, Register Name : STAT3 Bit Bit Name Default WDT RST REG RST Type Description

7 ST_OTP 0 NA NA R 0 : Not OTP

1 : OTP

6 ST_VAC_OV 0 NA NA R 0 : Not VAC_OV

1 : VAC_OV (charge or OTG mode)

5 ST_WDT 0 NA NA R 0 : WDT is counting

1 : WDT reset will occur after 500ms 4:3 Reserved 00 NA NA R Reserved

2 ST_OTG_CC 0 NA NA R 0 : Not in OTG_CC

1 : While in OTG_CC 1:0 Reserved 00 NA NA R Reserved

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Register Address : 0x20, Register Name : IRQ0 Bit Bit Name Default WDT RST REG RST Type Description

7 FL_VBUS_GD 0 NA NA R 0 : ST_VBUS_GD not rising

1 : While ST_VBUS_GD rising, read clear

6 FL_CHG_RDY 0 NA NA R 0 : ST_CHG_RDY not rising

1 : While ST_CHG_RDY rising, read clear

5 FL_IEOC 0 NA NA R 0 : ST_IEOC not rising

1 : While ST_IEOC rising, read clear

4 FL_BG_CHG 0 NA NA R 0 : ST_BG_CHG not rising

1 : While ST_BG_CHG rising, read clear

3 FL_CHG_

DONE 0 NA NA R 0 : ST_CHG_DONE not rising 1 : While ST_CHG_DONE rising, read clear

2 FL_RECHG 0 NA NA R

0 : While VBAT > VRECHG after EOC 1 : While VBAT < VRECHG after EOC, read clear

1 FL_DETACH 0 NA NA R

0 : ST_VBUS_GD not rising or in ST_VBUS_GD 1 : While ST_VBUS_GD falling then VBUS < VBAT or VBUS < 3.3V, read clear

0 FL_BC12_DO

NE 0 NA NA R 0 : BC1.2 process not ready 1 : While BC1.2 process done Register Address : 0x21, Register Name : IRQ1 Bit Bit Name Default WDT RST REG RST Type Description

7 FL_CHG_

MIVR 0 NA NA R 0 : ST_CHG_MIVR not rising 1 : While ST_CHG_MIVR rising, read clear

6 FL_CHG_

AICR 0 NA NA R 0 : ST_CHG_AICR not rising 1 : While ST_CHG_AICR rising, read clear

5 FL_CHG_

THREG 0 NA NA R 0 : ST_CHG_THREG not rising 1 : While ST_CHG_THREG rising, read clear

4 FL_CHG_

BUSUV 0 NA NA R 0 : ST_CHG_BUSUV not rising 1 : While ST_CHG_BUSUV rising, read clear TOUT 0 NA NA R 0 : ST_CHG_TOUT not rising 1 : While ST_CHG_TOUT rising, read clear

2 FL_CHG_

SYSOV 0 NA NA R 0 : ST_CHG_SYSOV not rising 1 : While ST_CHG_SYSOV rising, read clear

1 FL_CHG_

BATOV 0 NA NA R 0 : ST_CHG_BATOV not rising 1 : While ST_CHG_BATOV rising, read clear

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Register Address : 0x22, Register Name : IRQ2 Bit Bit Name Default WDT RST REG RST Type Description

7 FL_JEITA_

HOT 0 NA NA R 0 : ST_JEITA_HOT not rising 1 : While ST_JEITA_HOT rising, read clear

6 FL_JEITA_

WARM 0 NA NA R 0 : ST_JEITA_WARM not rising 1 : While ST_JEITA_WARM rising, read clear

5 FL_JEITA_

COOL 0 NA NA R 0 : ST_JEITA_COOL not rising 1 : While ST_JEITA_COOL rising, read clear

4 FL_JEITA_

COLD 0 NA NA R 0 : ST_JEITA_COLD not rising 1 : While ST_JEITA_COLD rising, read clear

3 FL_PE_DONE 0 NA NA R 0 : FL_PE_DONE not rising

1 : While PE processing done, read clear

2 FL_AICC_

DONE 0 NA NA R 0 : FL_AICC_DONE not rising 1 : While AICC processing done, read clear

1 FL_SYS_

MIN 0 NA NA R 0 : ST_SYS_MIN not rising 1 : While ST_SYS_MIN rising, read clear

0 FL_SYS_

SHORT 0 NA NA R 0 : ST_SYS_SHORT not rising 1 : While ST_SYS_SHORT rising, read clear Register Address : 0x23, Register Name : IRQ3 Bit Bit Name Default WDT RST REG RST Type Description

7 FL_OTP 0 NA NA R 0 : ST_OTP not rising

1 : While ST_OTP rising, read clear

6 FL_VAC_OV 0 NA NA R 0 : ST_VAC_OV not rising

1 : While ST_VAC_OV rising, read clear

5 FL_WDT 0 NA NA R 0 : ST_WDT not rising

1 : While ST_WDT rising, read clear 4:3 Reserved 00 NA NA R Reserved

2 FL_OTG_CC 0 NA NA R 0 : ST_OTG_CC not rising

1 : While ST_OTG_CC rising, read clear

1 FL_OTG_LBP 0 NA NA R 0 : ST_OTG_LBP not rising

1 : While ST_OTG_LBP rising, read clear

0 FL_OTG_

FAULT 0 NA NA R 0 : ST_OTG_FAULT not rising 1 : While ST_OTG_FAULT rising, read clear

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Register Address : 0x30, Register Name : MASK0 Bit Bit Name Default WDT RST REG RST Type Description

7 MK_VBUS_

GD 1 N Y R/W 0 : Not mask IRQ of FL_VBUS_GD 1 : Mask IRQ of FL_VBUS_GD (default)

6 MK_CHG_

RDY 1 N Y R/W 0 : Not mask IRQ of FL_CHG_RDY 1 : Mask IRQ of FL_CHG_RDY (default)

5 MK_IEOC 1 N Y R/W 0 : Not mask IRQ of FL_IEOC

1 : Mask IRQ of FL_IEOC (default)

4 MK_BG_CHG 1 N Y R/W 0 : Not mask IRQ of MK_BG_CHG

1 : Mask IRQ of MK_BG_CHG (default)

3 MK_CHG_

DONE 1 N Y R/W 0 : Not mask IRQ of FL_CHG_DONE 1 : Mask IRQ of FL_CHG_DONE (default)

2 MK_RECHG 1 N Y R/W 0 : Not mask IRQ of FL_RECHG

1 : Mask IRQ of FL_RECHG (default)

1 MK_DETACH 1 N Y R/W 0 : Not mask IRQ of FL_DETACH

1 : Mask IRQ of FL_DETACH (default)

0 MK_BC12_DO

NE 1 N Y R/W 0 : Not mask IRQ of FL_BC12_DONE 1 : Mask IRQ of FL_BC12_DONE (default) Register Address : 0x31, Register Name : MASK1 Bit Bit Name Default WDT RST REG RST Type Description

7 MK_CHG_

MIVR 1 N Y R/W 0 : Not mask IRQ of FL_CHG_MIVR 1 : Mask IRQ of FL_CHG_MIVR (default) AICR 1 N Y R/W 0 : Not mask IRQ of FL_CHG_AICR 1 : Mask IRQ of FL_CHG_AICR (default)

5 MK_CHG_

THREG 1 N Y R/W 0 : Not mask IRQ of FL_CHG_THREG 1 : Mask IRQ of FL_CHG_THREG (default)

4 MK_CHG_

BUSUV 1 N Y R/W 0 : Not mask IRQ of FL_CHG_BUSUV 1 : Mask IRQ of FL_CHG_BUSUV (default) TOUT 1 N Y R/W 0 : Not mask IRQ of FL_CHG_TOUT 1 : Mask IRQ of FL_CHG_TOUT (default)

2 MK_CHG_

SYSOV 1 N Y R/W 0 : Not mask IRQ of FL_CHG_SYSOV 1 : Mask IRQ of FL_CHG_SYSOV (default)

1 MK_CHG_

BATOV 1 N Y R/W 0 : Not mask IRQ of FL_CHG_BATOV 1 : Mask IRQ of FL_CHG_BATOV (default)

0 Reserved 1 NA NA R Reserved

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Register Address : 0x32, Register Name : MASK2 Bit Bit Name Default WDT RST REG RST Type Description

7 MK_JEITA_

HOT 1 N Y R/W 0 : Not mask IRQ of FL_JEITA_HOT 1 : Mask IRQ of FL_JEITA_HOT (default)

6 MK_JEITA_

WARM 1 N Y R/W 0 : Not mask IRQ of FL_JEITA_WARM 1 : Mask IRQ of FL_JEITA_WARM (default)

5 MK_JEITA_

COOL 1 N Y R/W 0 : Not mask IRQ of FL_JEITA_COOL 1 : Mask IRQ of FL_JEITA_COOL (default)

4 MK_JEITA_

COLD 1 N Y R/W 0 : Not mask IRQ of FL_JEITA_COLD 1 : Mask IRQ of FL_JEITA_COLD (default)

3 MK_PE_

DONE 1 N Y R/W 0 : Not mask IRQ of FL_PE_DONE 1 : Mask IRQ of FL_PE_DONE (default)

2 MK_AICC_

DONE 1 N Y R/W 0 : Not mask IRQ of FL_AICC_DONE 1 : Mask IRQ of FL_AICC_DONE (default)

1 MK_SYS_MIN 1 N Y R/W 0 : Not mask IRQ of FL_SYS_MIN

1 : Mask IRQ of FL_SYS_MIN (default)

0 MK_SYS_

SHORT 1 N Y R/W 0 : Not mask IRQ of FL_SYS_SHORT 1 : Mask IRQ of FL_SYS_SHORT (default) Register Address : 0x33, Register Name : IRQ3 Bit Bit Name Default WDT RST REG RST Type Description

7 MK_OTP 1 N Y R/W 0 : Not mask IRQ of FL_OTP

1 : Mask IRQ of FL_OTP (default)

6 MK_VAC_OV 1 N Y R/W 0 : Not mask IRQ of FL_VAC_OV

1 : Mask IRQ of FL_VAC_OV (default)

5 MK_WDT 1 N Y R/W 0 : Not mask IRQ of FL_WDT

1 : Mask IRQ of FL_WDT (default) 4:3 Reserved 11 NA NA R Reserved

2 MK_OTG_CC 1 N Y R/W 0 : Not mask IRQ of FL_OTG_CC

1 : Mask IRQ of FL_OTG_CC (default)

1 MK_OTG_LBP 1 N Y R/W 0 : Not mask IRQ of FL_OTG_LBP

1 : Mask IRQ of FL_OTG_LBP (default)

0 MK_OTG_

FAULT 1 N Y R/W 0 : Not mask IRQ of FL_OTG_FAULT 1 : Mask IRQ of FL_OTG_FAULT (default)

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023

Application Information

Richtek’s component specification does not include the following information in the Application Information section. Thereby no warranty is given regarding its validity and accuracy. Customers should take responsibility to verify their own designs and reserve suitable design margin to ensure the functional suitability of their components and systems. Power Up ⚫ Power-On-Reset (POR) The device powers internal bias circuits from the higher voltage of VBUS and VBAT. When VBUS rises above 1.8V or VBAT rises above V BAT_UVLO, I2C interface is ready for communication and all the registers are reset to default value. ⚫ Device Power Up from Battery Only When only Battery is present and VBAT above VBAT_DPL_RISE, the BATFET turns on to connect VBAT to VSYS. The REGN stays off to minimize the quiescent current. The low quiescent current on VBAT and low R DS(ON) of BATFET minimize device power consumption and conduction loss maximum battery run life. The device always monitors the discharg e current through BATFET (Battery Supply Mode). When the system is overloaded or shorted (I BAT > IBATFET_OCP), the device turns off BATFET immediately and sets BATFET_DIS = 1 to enter Shipping Mode until VBUS plugs in again or uses the methods to exit Shipping Mode to re -enable BATFET. ⚫ Device Power Up from VBUS When the VBUS is plugged in, the power up sequence is as listed : 1. Power up REGN LDO. 2. Poor Source Detection. 3. PORT_STAT Detection is based on PSEL or input source type to set d efault Average Input Current Regulation (AICR) register. 4. Minimum Input Voltage Regulation (MIVR) setting. 5. Buck Converter Power-up. ⚫ Power-Up REGN LDO The REGN LDO supplies the High -side and Low-side MOSFET gate drive. The REGN also provides bias to TS exte rnal resistor and pull -up rail of STAT. The REGN is enabled when the below conditions are valid : 1. VAC above VBAT + V SLEEP_RISE in buck mode or enable OTG bit in boost mode. 2. After 220ms delay is completed when V AC above VBAT + VSLEEP_RISE. 3. REGN LDO turn s off when device in HZ mode, sleep mode, VBUS over-voltage or OTG disable. ⚫ Poor Source Detection After REGN powers up, the device checks the current capability of the input source. The input source has to meet following requirements to turn on the buck converter. 1. VBUS below VAC_OVP_RISE. 2. VBUS above VBUS_BAD_ADP then pulling IBADSRC (typical = 40mA). When input source passes above conditions, the ST_VBUS_GD and the FL_VBUS_GD turn to high and INT pin is pulsed for interrupting the host. If ST_VBUS_GD doesn’t turn to high, it repeats poor source detection every 2 seconds. ⚫ VBUS Source Type Detection After ST_VBUS_GD turns to high, the device runs VBUS source type detection (RT9470D) or PSEL pin status (RT 9470). After detection is completed, the ST_CHG_RDY and the FL_CHG_RDY turn to high and INT pin is pulsed for interrupting the host. Then the following registers are changed: 1. Average Inpu t Current Regulation (AICR) register is changed to the result of VBUS source type detection or PSEL pin status automatically if AUTO_AICR = 1.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

1. PORT_STAT bit is updated to indicate VBUS
2. If the bit AUTO_AICR is set to 0, the device can’t
3. The host can over-write AICR register to change
4. The AICR register setting from PSEL in the
5. PSEL value upd ates AICR in real time in
6. D+/D- detect value updates AICR after

Table 1. AICR Setting from PSEL Table 2. AICR Setting from D+/D- Detection supports PFM control to improve light-load efficiency. prevent PFM operation in buck configuration. includes USB OTG 500mA output requirement.

1. VBUS less than VBAT+VSLEEP_FALL
2. Voltage at TS pin is within acceptable range
3. After 30ms delay from OTG_EN is set to high,

maintained when VBAT is above VOTG_LBP.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. WDT_CNT_RST = 1 to return counting. Figure 1. WDT Flow Chart

1. Set REG_RST bit to reset all registers to default.
2. Press QON pin from high to low longer than

The QON pin has two function to control BATFET.

1. BATFET Enable : QON pin transition from high

turns on BATFET to exit shipping mode.

1. SYSTEM Reset : QON pin transition from high to

setting QON_RST_EN bit to 0.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 2. QON Timing voltage drop during battery discharging. completes a charging cycle without host controls. The de vice default parameters refers as Ta ble 2. Table 3. Default Charging Parameters

1. Battery charging is enabled (CE pin is low,

CHG_EN = 1 and ICHG_REG is not 0mA).

1. Without any thermal fault on TS.
2. BATFET is turned on (BATFET_DIS = 0).

and device not in AICR, MIVR or thermal regulation. CE pin or CHG_EN can restart a new charging cycle. voltage and back-ground charge (optional). Table 4. Charging Current Setting

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 3. Charging Profile range is from 50mA to 800mA with 50mA resolution. Table 5. EOC Status Scenario

1. If the device triggers AICR, MIVR, JEITA or

counter clock rate will be half.

1. The back -ground charge can be applied after

turn off after back-ground charge timer expires.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. guidelines were released in 2007. and an INT is asserted to the host. (configured by JEITA_COOL_ISET). as VBAT_REG (configured by JEITA_WARM_VSET). (configured by JEITA_COOL_VSET). (configured by JEITA_WARM_ISET). Figure 6. JEITA Protect for Charging Current and Voltage and RT2 can be calculated with equation (1) and (2). resistance of battery under-temperature threshold. charge fault and an INT is asserted to the host.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 7. Thermal Protect During Boost Mode disable by setting CHG_SAFE_TMR_EN = 0. Table 6. Charging Safety Timer

15 Hours, 20 Hours

counter clock rate will be half. be disabled by setting CHG_SAFE_TMR_2XT = 0.

1. CHG_SAFE_TMR disable/enable

communicate with an MTK-PE+ high voltage adapter. the host to indicate AICC_DONE. Figure 8. AICC Enable

1. VBUS above V BUS_MIN_RISE, and I BADSRC is
2. VBUS above VBAT (not in sleep mode)
3. VBUS below VAC_OVP threshold setting
4. The charger thermal is under THREG threshold
5. Completed VBUS Source Type Detection

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 7. STAT Pin State Table 8. STATUS, FLAG and MASK Register Map

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Name STAT IRQ MASK SYS_MIN Y Y Y SYS_SHORT N Y Y OTP Y Y Y VAC_OV Y Y Y WDT Y Y Y OTG_CC Y Y Y OTG_LBP N Y Y OTG_FAULT N Y Y Protections ⚫ VBUS Over-Voltage Protection in Buck Mode If VBUS voltage over V AC_OVP setting (programmable by VAC_OVP bits), the device stops switching immediately and an INT pulse is asserted to the host. When VBUS overvoltage, the status ST_VAC_OV = 1 and the IC_STAT = 1000 for charge fault. The device resume to normal operation when VB US voltage drops below the V AC_OVP threshold. ⚫ VBUS Over-Voltage Protection in Boost Mode When boost mode, VAC_OVP setting is locked at 6.5V even if VAC_OVP threshold is set at 10.5V or 14V. When the output voltage (VBUS) exceeds VAC_OVP threshold, the dev ice stops switching immediately, clear OTG_EN bit to 0 and exit boost mode. The fault (OTG_FAULT) is set to high and an INT pulse is asserted to the host to indicate in boost mode. When the output voltage falling V AC_OVP_HYS below VAC_OVP threshold, the OT G_EN bit can be set to 1 by the host. ⚫ IBUS Overload Protection in Boost Mode The device monitors boost output voltage and current to provide VBUS short circuit protection. The device also build s in constant current regulation to allow OTG to ada ptive to va rious types of load. If short circuit is detected on VBUS, the boost will hiccup 7 times. If boost retries are not successful, OTG_EN bit will set to 0 to disable boost mode and INT pulse is asserted to the host to indicate OTG_FAULT. ⚫ VBUS Soft-Start When the boost function is enabled, the device soft-starts on VBUS to avoid inrush current. ⚫ VSYS Over-Voltage Protection SYSOVP threshold is set at 5.2V . Once VSYS is above SYSOVP level, buck stops switching immediately and an INT pulse is asserted to host to indicate CHG_SYSOV fault. The device provides 30mA current sink on VSYS to bring down the VSYS voltage. ⚫ VSYS Over-Current Protection When the system is shorted or overload ed (IBAT > IOCP_BATFET), the device latches off BATFET (forces enter shipping mode) and an INT pulse is asserted to host to indicate SYS_SHORT fault. Exit shipping mode can reset the latch -off condition and turn on BATFET. ⚫ Battery Over-Voltage Protection The BAT_OVP threshold is 4% above the V BAT_REG setting. When battery exceeds overvoltage threshold, the device disables charging immediately and an INT is asserted to the host to indicate CHG_BATOV. ⚫ Battery Over-Discharge Protection When battery is discharged below V BAT_DPL_FALL, the BATFET turns off to protect battery over discharged. When VBUS is plugged in, the BAFET turns on to charge battery.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. threshold, the device decreases the charge current. mode by setting OTG_EN bit to 1. selected register. End with STOP (P) condition. Figure 9. Read and Write Function

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. there are several suggestions provided. placed as close as possible to the RT9470/D. trace is enough for the operating current. placed as close as possible to the RT9470/D. Figure 12. PCB Layout Guide

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.500 0.600 0.020 0.024 A1 0.170 0.230 0.007 0.009 b 0.240 0.300 0.009 0.012 D 2.460 2.540 0.097 0.100 D1 2.000 0.079 0.000 E 2.060 2.140 0.081 0.084 E1 1.600 0.063 0.000 e 0.400 0.016 30B WL-CSP 2.1x2.5 Package (BSC)

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Footprint Information Package Number of Pin Type Footprint Dimension (mm) Tolerance e A B WL-CSP2.1x2.5-30(BSC) 30 NSMD 0.400 0.240 0.340 ±0.025 SMD 0.270 0.240

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Packing Information Tape and Reel Data Package Type Tape Size (W1) (mm) Pocket Pitch (P) (mm) Reel Size (A) Units per Reel Trailer (mm) Leader (mm) Reel Width (W2) Min./Max. (mm) (mm) (in) WL-CSP 2.1x2.5 8 4 180 7 3,000 160 600 8.4/9.9 Tape Size W1 P B F ØJ H C, D and K are determined by component size. The clearance between the components and the cavity is as follows: - For 8mm carrier tape: 0.5mm max.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Tape and Reel Packing Step Photo/Description Step Photo/Description Reel 7” 12 inner boxes per outer box Packing by Anti-Static Bag Outer box Carton A 3 reels per inner box Box A Container Package Reel Box Carton Size Units Item Size(cm) Reels Units Item Size(cm) Boxes Unit WL-CSP 2.1x2.5 7” 3,000 Box E 18.6*18.6*3.5 1 3,000 For Combined or Partial Reel.

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS9470/D-02 October 2023 www.richtek.com Packing Material Anti-ESD Property Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is curre nt and complete. Rich tek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidi aries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its su bsidiaries. Surface Resistance Aluminum Bag Reel Cover tape Carrier tape Tube Protection Band /cm2 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS9470/D-02 October 2023 Datasheet Revision History Version Date Description Item 02 2023/10/19 Modify General Description on P1 Ordering Information on P1 Absolute Maximum Ratings on P6 Application Information on P32 Packing Information on P47, 48, 49