RT9101

RT9101_11 RICHTEK | Alldatasheet

Document overview

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Technical content

Features

zzzzz Wide Operating Voltage : 2.5V to 5.5V zzzzz High Efficiency With an 8ΩΩΩΩΩ Speaker : zzzzz Low Quiescent Current and Shutdown Current zzzzz Optimized PWM Output Stage Eliminates LC Filter zzzzz Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor zzzzz Internally Generated 250kHz Switching Frequency zzzzz Integrated Pop and Click Suppression Circuitry zzzzz RoHS Compliant and Halogen Free

Applications

z Portable multimedia devices WL-CSP-9B 1.45x1.45 (BSC) General Description The RT9101 is a 2.65W, high efficiency Class-D audio amplifier featuring low-resistance internal power MOSFETs and the gain can be set by an external input resistance. The filter free topology eliminates the output filter and reduces the external component count, footprint area, and system costs. Operating from a single 5V supply, the RT9101 is capable of driving 4Ω speaker load at a continuous average output of 2.65W/10% THD+N or 2W/0.5% THD+N. The RT9101 has a higher efficiency with speaker load compared to a typical class AB amplifier. With a 3.6V supply driving an 8Ω speaker, the efficiency for a 400mW power level is 88%. It is very suitable for power sensitive application, such as cellular handsets and battery powered devices. In addition to these features, the RT9101 provides a fast startup time to minimize audible popping during device turn-on and turn- off. Moreover, the RT9101 also integrates thermal and over current protection circuits. The RT9101 is available in WDFN-8L 3x3, and WL-CSP-9B 1.45x1.45 (BSC) packages. INP INN OUTN GND OUTP VDD GND VDD A1 A2 A3 B3B1 C1 C2 C3 SHDN NC INN OUTN GND VDD OUTP INP GND SHDN RT9101 Package Type QW : WDFN-8L 3x3 (W-Type) WSC : WL-CSP-9B 1.45x1.45 (BSC) Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Default : WDFN-8L 3x3 C : WL-CSP-9B 1.45x1.45 (BSC)

DS9101-01 April 2011 www.richtek.com RT9101 Function Block Diagram Gate Driver Gate Driver Protection Circuit INN OUTN GND VDD OUTP INP SHDN VDD Functional Pin Description Pin No. WDFN-8L 3x3 WL-CSP-9B 1.45x1.45 (BSC) Pin Name Pin Function 1 C2 SHDN Shutdown Control (Active Low). 2 -- NC No Internal Connection. 3 A1 INP Positive Input of Differential Audio Signal. 4 C1 INN Negative Input of Differential Audio Signal. 5 C3 OUTP Positive Output. 6 B1, B2 VDD Supply Voltage Input. 9 (Exposed Pad) A2, B3 GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum thermal dissipation. 8 A3 OUTN Negative Output.

DS9101-01 April 2011www.richtek.com RT9101

Electrical Characteristics

(VDD = 5V, TA = 25°C, unless otherwise specified) Absolute Maximum Ratings (Note 1) z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4) Parameter Symbol Test Conditions Min Typ Max Unit Output Offset Voltage V OS V DD = 2.5V to 5.5V -- 1 25 mV Power Supply Rejection Ratio PSRR V DD = 2.5V to 5.5V (Note 5) -- −70 −55 dB High Level Input Current ⎪ IIH ⎪ V DD = 5.5V, VI = 5.8V -- -- 100 μA Low Level Input Current ⎪ IIL ⎪ V DD = 5.5V, VI = −0.3V -- -- 5 μA Logic-High V IH 2 -- -- SHDN Input Threshold Voltage Logic-Low V IL -- -- 0.4 V VDD = 5.5V, No Load -- 3.4 4.9 VDD = 3.6V, No Load -- 2.8 -- Quiescent Current I Q VDD = 2.5V, No Load -- 2.2 3.2 mA Shutdown Current I SHDN V SHDN = 0V, VDD = 2.5V to 5.5V -- -- 1 μA VDD = 3.6V -- 500 -- Static Drain-Source On-State Resistance RDS(ON) VDD = 5V -- 400 -- mΩ Output Impedance in SHDN VSHDN = 0V -- >1 -- k Ω Switching Frequency V DD = 2.5V to 5.5V 200 250 300 kHz Gain V DD = 2.5V to 5.5V 284k/R I 300k/R I 316k/R I V/V Resistance from SHDN to GND -- 200 -- k Ω To be continued

DS9101-01 April 2011 www.richtek.com RT9101 Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θ JA is measured in natural convection at TA = 25°C on a high-effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. Operating Characteristics (Gain = 2V/V,RL= 8Ω, TA = 25°C, unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit VDD = 3.6V -- 1.5 -- THD+N = 10%, f = 1kHz, RL = 4Ω W VDD = 3.6V -- 1.06 -- THD+N = 1%, f = 1kHz, RL = 4Ω W VDD = 3.6V -- 0.73 -- THD+N = 10%, f = 1kHz, RL = 8Ω W Output Power P O THD+N = 1%, f = 1kHz, RL = 8Ω W VDD = 5V, PO = 1W, RL = 8Ω, f = 1kHz -- 0.06 -- VDD = 3.6V, PO = 0.5W, RL = 8Ω, f = 1kHz -- 0.05 -- Total Harmonic Distortion Plus Noise THD+N VDD = 2.5V, PO = 200mW, RL = 8Ω, Supply Ripple Rejection Ratio PSRR VDD = 5V, f = 217Hz, VDD-Ripple = 200mVpp -- −70 -- dB Signal-to-Noise Ratio SNR VDD = 5V, PO = 1W, RL = 8Ω, A Weighting Filter -- 95 -- dB Input Impedance Z I 142 150 158 k Ω Start-Up Time from Shutdown V DD = 3.6V -- 1 -- ms

DS9101-01 April 2011www.richtek.com RT9101 Typical Operating Characteristics Output Power vs. Load Resistance 0.0 0.5 1.0 1.5 2.0 2.5 4 8 12 16 20 24 28 32 Load Resistance (dB) Output Power (W) VDD = 5V Gain = 2V/V, f = 1kHz, THD+N = 10% VDD = 2.5V VDD = 3.6V Output Power vs. Load Resistance 0.0 0.5 1.0 1.5 2.0 2.5 4 8 12 16 20 24 28 32 Load Resistance (dB) Output Power (W) VDD = 5V Gain = 2V/V, f = 1kHz, THD+N = 1% VDD = 2.5V VDD = 3.6V Efficiency vs. Output Power Output Power (W) Efficiency (%) VDD = 5V Gain = 2V/V, f = 1kHz, RL = 4Ω, 33μH VDD = 2.5V VDD = 3.6V Efficiency vs. Output Power 100 Output Power (W) Efficiency (%) VDD = 5V Gain = 2V/V, f = 1kHz, RL = 8Ω, 33μH VDD = 2.5V VDD = 3.6V Supply Current vs. Output Power 100 200 300 400 500 600 700 00 . 511 . 522 . 53 Output Power (W) Supply Current (mA) VDD = 5V Gain = 2V/V, RL = 4Ω, 33μH VDD = 2.5V VDD = 3.6V Supply Current vs. Output Power 100 150 200 250 300 Output Power (W) Supply Current (mA) VDD = 5V Gain = 2V/V, RL = 8Ω, 33μH VDD = 2.5V VDD = 3.6V

DS9101-01 April 2011 www.richtek.com RT9101 RL = 4Ω, f = 1kHz, Gain = 2V/V THD+N vs. Output Power 10m 20m 50m 100m 200m 500m 1 2 5 THD+N (%/Div) Output Power (W/Div) 0.5 0.2 0.1 0.05 0.02 0.01 VDD = 2.5V VDD = 3.6V VDD = 5V THD+N vs. Frequency 20 50 100 200 500 1k 2k 5k 10k 20k THD+N (%/Div) Frequency (Hz/Div) PO = 50mW PO = 250mW PO = 1W VDD = 5V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V10 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 THD+N vs. Frequency 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz/Div) PO = 25mW PO = 125mW PO = 500mW THD+N (%/Div) VDD = 3.6V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V10 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 THD+N vs. Frequency 20 50 100 200 500 1k 2k 5k 10k 20k THD+N (%/Div) Frequency (Hz/Div) PO = 15mW PO = 75mW PO = 200mW VDD = 2.5V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 THD+N vs. Frequency 20 50 100 200 500 1k 2k 5k 10k 20k THD+N (%/Div) Frequency (Hz/Div) VDD = 2.5V VDD = 3.6V VDD = 5V VDD = 4V PO = 250mW, CI = 2.2μF, RL= 4Ω, Gain = 2V/V 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 RL = 8Ω, f = 1kHz, Gain = 2V/V THD+N vs. Output Power 10m 20m 50m 100m 200m 500m 1 2 5 THD+N (%/Div) Output Power (W/Div) 0.5 0.2 0.1 0.05 0.02 0.01 VDD = 2.5V VDD = 3.6V VDD = 5V

DS9101-01 April 2011www.richtek.com RT9101 Power Dissipation vs. Output Power 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 00 . 511 . 522 . 5 Output Power (W) Power Dissipation (W) RL = 8Ω + 33μH VDD = 5V, f = 1kHz, Gain = 2V/V RL = 4Ω + 33μH Power Dissipation vs. Output Power 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Output Power (W) Power Dissipation (W) RL = 8Ω + 33μH VDD = 3.6V, f = 1kHz, Gain = 2V/V RL = 4Ω + 33μH GSM Power Supply Rejection vs. Time Gain = 2V/V, CI = 2.2μF, RL = 8Ω, f = 217Hz, Duty = 12% Time (2.5ms/Div) VDD (1V/Div) VOUT (20mV/Div) VDD = 3.6V, PK -PK = 512mV GSM Power Supply Rejection vs. Frequency 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k (dB/Div) Frequency (Hz/Div) -20 -40 -60 -80 -100 -120 -140 -150 Supply Voltage Output Voltage VDD = 3.6V, CI = 2.2μF, RL= 8Ω, Gain = 2V/V PSRR vs. Frequency 20 50 100 200 500 1k 2k 5k 10k 20k PSRR (dB/Div) Frequency (Hz/Div) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 VDD = 2.5V VDD = 3.6V VDD = 5V VP-P = 200mV, CI = 2.2μF, RL= 4Ω, Gain = 2V/V PSRR vs. Frequency 20 50 100 200 500 1k 2k 5k 10k 20k PSRR (dB/Div) Frequency (Hz/Div) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 VDD = 2.5V VDD = 3.6V VDD = 5V VP-P = 200mV, CI = 2.2μF, RL= 8Ω, Gain = 2V/V

DS9101-01 April 2011 www.richtek.com RT9101

Application information

The RT9101 is a fully differential amplifier with differential inputs and outputs. The RT9101 integrates a differential amplifier and a common mode voltage controller. The differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The RT9101 can support differential input and single ended input applications. Components Selection Input Resistors (R Amplifier can be resistors and the gain can be calculated as the following equation : Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the input resistors. CMRR, PSRR, and the cancellation of the second harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance or better resistors to keep the performance optimized. The input resistors should be placed very close to the RT9101 to limit noise injection on the high impedance nodes. It is recommended to set the gain at 2V/V or lower for better performance. Decoupling Capacitor The RT9101 is a high performance Class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients, spikes, or digital hash on the line, a good low Equivalent-Series-Resistance (ESR) ceramic capacitor, typically 1μF, placed as close as possible to the VDD pin can achieve the best performance. Placing this decoupling capacitor close to the RT9101 is very important for the efficiency of the Class- D amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lower frequency noise signals, it is recommended to use a 10 μF or greater capacitor placed near the audio power amplifier. Input Capacitor In the typical application, an input coupling capacitor (CI) is required to allow the input signal to the proper dc level for optimum operation. However, the RT9101 is a fully differential amplifier with good CMRR so that the RT9101 does not require input coupling capacitors if using a differential input source that is biased from 0.5 V to VDD − 0.8 V. Use 1% tolerance or better gain-setting resistors if input coupling capacitors are not used. In the single-ended input application, a n input capacitor, (CI), is required to allow the amplifier to bias the input signal to the proper dc level. In this case, CI and RI form a high-pass filter with the corner frequency as shown in the following equation : C II 1f 2R Cπ= f (Hz) fC -3dB Gain (dB) The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit. For example, the flat bass response requirement is 10 Hz and R I is 20k Ω, the value of C I can be calculated by the following equation : I IC 1C 2R fπ= In this example, CI is 0.8μF. A capacitance1μF or larger can be used. Under Voltage Lockout The under voltage lock out circuit operates as a voltage detector and alwa ys monitors the supply voltage (VDD) while SHND = 1. While powered on, the chip is kept still in shutdown mode until VDD rises to greater than 2.2V (typ). While powered off, the chip does not leave operation mode until VDD falls to less than 2. 1V (typ). I 2 x 150kGain = R Ω

DS9101-01 April 2011 www.richtek.com RT9101 Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 2.950 3.050 0.116 0.120 D2 2.100 2.350 0.083 0.093 E 2.950 3.050 0.116 0.120 E2 1.350 1.600 0.053 0.063 e 0.650 0.026 L 0.425 0.525 0.017 0.021 W-Type 8L DFN 3x3 Package 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options D E A L be SEE DETAIL A

DS9101-01 April 2011www.richtek.com RT9101 Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property inf ringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications i s assumed by Richtek. Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com 9B WL-CSP 1.45x1.45 Package (BSC) Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.525 0.625 0.021 0.025 A1 0.200 0.260 0.008 0.010 b 0.290 0.350 0.011 0.014 D 1.400 1.500 0.055 0.059 D1 1.000 0.039 E 1.400 1.500 0.055 0.059 E1 1.000 0.039 e 0.500 0.020