RT8884CGQW

Richtek Technology Corp...

Multi-Phase PWM Controller for CPU Core Power Supply

Manufacturer: Richtek Technology Corp...

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Features

 Intel VR12.5 Serial VID Interface Compatible  4/3/2/1 Phase PWM Controller  Differential Remote Voltage Sensing  Built-in ADC for Platform Programming  Accurate Current Balance  System Thermal Compensated AVP  Diode Emulation Mode at Light Load Condition for Single Phase Operation  Fast Transient Response  Current Monitor Output  OVP, UVP, OCP, NVP, UVLO  External No-Load Offset Setting  Small 32-Lead WQFN Package  RoHS Compliant and Halogen Free Simplified Application Circuit VCORE PWM3 PWM2 PWM1 RT8884C PWM4 RT9624A RT9624A RT9624A RT9624A VR_RDY VR_HOT VCLK VDIO ALERT To CPU To PCH

Ordering Information

Note : Richtek products are :  RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering processes. Marking Information 3J= : Product Code YMDNN : Date Code ISEN1P ISEN4N ISEN3N ISEN3P DVD VCLK TONSET VR_RDY VSEN RGND VCC SET1 ISEN2N ISEN2P EN PWM2 IMON ISEN4P VDIO ALERT FB ISEN1N SET2 PWM1 VREF VR_HOT SET3 PWM3 IBIAS PWM4 COMP TSEN 10 11 12 13 31 30 29 28 187 178 GND (TOP VIEW) Package Type QW : WQFN-32L 4x4 (W-Type) RT8884C Lead Plating System G : Green (Halogen Free and Pb Free) 3J=YM DNN

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 1, 30, 2, 5 ISEN [1:4] P Positive Current Sense Inputs of Channel 1, 2, 3 and 4. 32, 31, 3, 4 ISEN [1:4] N Negative Current Sense Inputs of Channel 1, 2, 3 and 4. 6 IMON CPU CORE Current Monitor Output. This pin outputs a voltage proportional to the output current.

7 VREF

Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the output voltage of IMON pin. Connect a 0.47 F decoupling capacitor between this pin and GND. 8 COMP CORE VR Compensation. This pin is an error amplifier output pin. 9 FB Negative Input of the Error Amplifier. This pin is for output voltage feedback to controller. 10 VSEN VR Voltage Sense Input. This pin is connected to the terminal of VR output voltage. 11 RGND Return Ground for VR. This pin is the negative node of the differential remote voltage sensing.

12 VCC

Controller Power Supply. Connect this pin to 5V and place a minimum 2.2 F decoupling capacitor. The decoupling capacitor should be placed to this pin as close as possible. 13 SET1 1st Platform Setting. Platform can use this pin to set DVID time, RSET , DVID width and OCS. 14 SET2 2nd Platform Setting. Platform can use this pin to set ICCMAX, QRTH and QRSET. 15 SET3 3rd Platform Setting. Platform can use this to set output offset voltage.

16 IBIAS

Internal Bias Current Setting. Connect a 100k resistor from this pin to GND for setting the internal current. Don’t connect a bypass capacitor from this pin to GND. 17 TSEN Thermal Sense Input for CORE VR. 18 VR_HOT Thermal Monitor Output. (Active low). 19 VDIO VR and CPU Data Transmission Interface. 20 ALERT SVID Alert. (Active low) 21 VCLK Synchronous Clock from the CPU. 22 TONSET On-time Setting. An on-time setting resistor is connected from this pin to input voltage. 23 VR_RDY VR Ready Indicator. 24 DVD Divided Input Voltage Detection of CORE VR. Connect this pin to a voltage divider from input voltage of power stage to detect input voltage. 27, 28, 26, 25 PWM [1:4] PWM Outputs for Channel 1, 2, 3 and 4. 29 EN VR Enable. (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Function Block Diagram IBIAS FB COMP RGND PWM4 PWM3 PWM2 PWM1 ISEN4N Soft-Start & Slew Rate Control VSET OVP/UVP/NVP ERROR AMP OCP From Control Logic Offset Cancellation ISEN4P ISEN3N ISEN3P ISEN2N ISEN2P ISEN1N ISEN1P Current Balance To Protection Logic DAC TON GEN Current mirror IB1 Current mirror IB2 Current mirror IB3 Current mirror IB4 + -OCS OC VSEN IMON VREF PWM CMP QR_TH QRWIDTH RSET TONSET SET2 Loop Control Protection Logic SVID Interface Configuration Registers Control Logic UVLO TON, QR_TH QRWIDTH ADC SET1 IMONI TSEN EN DVD VCC VR_RDY GNDMUX VCLK VDIO ALERT VR_HOT VSEN To Protection Logic RSETOCS Ai IB4IB3IB1 IB2 IMON Filter IMONI SET3 DVID_TH, DVID_WTHDVID_TH, DVID_WTH

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Operation The RT8884C adopts G-NAVPTM (Green Native AVP) which is Richtek's proprietary topology derived from finite DC gain of EA amplifier with current mode control, making it easy to set the droop to meet all Intel CPU requirements of AVP (Adaptive Voltage Positioning). The RT8884C adopts the G-NAVP TM controller, which is one type of current mode constant on-time control with DC offset cancellation. The approach can not only improve DC offset problem for increasing system accuracy but also provide fast transient response. For the RT8884C, when current feedback signal reaches COMP signal to generate an on-time width to achieve PWM modulation. TON GEN Generate the PWM1 to PWM4 sequentially according to the phase control signal from the Loop Control Protection Logic. SVID Interface/Configuration Registers/Control Logic The interface that receives the SVID signal from CPU and sends the relative signals to Loop Control Protection Logic to execute the action by CPU. The registers save the pin setting data from ADC output. The Control Logic controls the ADC timing and generates the digital code of the VID that is relative to VSEN. Loop Control Protection Logic It controls the power on sequence, the protection behavior, and the operational phase number. Current Balance Each phase current sense signal is sent to the current balance circuit which adjusts the on-time of each phase to optimize current sharing. Offset Cancellation Cancel the current/voltage ripple issue to get the accurate VSEN. UVLO Detect the DVD and VCC voltage and issue POR signal as they are high enough. DAC Generate an analog signal according to the digital code generated by Control Logic. Soft-Start & Slew Rate Control Control the Dynamic VID slew rate of VSET according to the SetVID fast or SetVID slow.

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 0 1 0 1 0 0 0 28 0.890 0 0 1 0 1 0 0 1 29 0.900 0 0 1 0 1 0 1 0 2A 0.910 0 0 1 0 1 0 1 1 2B 0.920 0 0 1 0 1 1 0 0 2C 0.930 0 0 1 0 1 1 0 1 2D 0.940 0 0 1 0 1 1 1 0 2E 0.950 0 0 1 0 1 1 1 1 2F 0.960 0 0 1 1 0 0 0 0 30 0.970 0 0 1 1 0 0 0 1 31 0.980 0 0 1 1 0 0 1 0 32 0.990 0 0 1 1 0 0 1 1 33 1.000 0 0 1 1 0 1 0 0 34 1.010 0 0 1 1 0 1 0 1 35 1.020 0 0 1 1 0 1 1 0 36 1.030 0 0 1 1 0 1 1 1 37 1.040 0 0 1 1 1 0 0 0 38 1.050 0 0 1 1 1 0 0 1 39 1.060 0 0 1 1 1 0 1 0 3A 1.070 0 0 1 1 1 0 1 1 3B 1.080 0 0 1 1 1 1 0 0 3C 1.090 0 0 1 1 1 1 0 1 3D 1.100 0 0 1 1 1 1 1 0 3E 1.110 0 0 1 1 1 1 1 1 3F 1.120 0 1 0 0 0 0 0 0 40 1.130 0 1 0 0 0 0 0 1 41 1.140 0 1 0 0 0 0 1 0 42 1.150 0 1 0 0 0 0 1 1 43 1.160 0 1 0 0 0 1 0 0 44 1.170 0 1 0 0 0 1 0 1 45 1.180 0 1 0 0 0 1 1 0 46 1.190 0 1 0 0 0 1 1 1 47 1.200 0 1 0 0 1 0 0 0 48 1.210 0 1 0 0 1 0 0 1 49 1.220 0 1 0 0 1 0 1 0 4A 1.230 0 1 0 0 1 0 1 1 4B 1.240 0 1 0 0 1 1 0 0 4C 1.250 0 1 0 0 1 1 0 1 4D 1.260 0 1 0 0 1 1 1 0 4E 1.270 0 1 0 0 1 1 1 1 4F 1.280

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 1 0 1 0 0 0 0 50 1.290 0 1 0 1 0 0 0 1 51 1.300 0 1 0 1 0 0 1 0 52 1.310 0 1 0 1 0 0 1 1 53 1.320 0 1 0 1 0 1 0 0 54 1.330 0 1 0 1 0 1 0 1 55 1.340 0 1 0 1 0 1 1 0 56 1.350 0 1 0 1 0 1 1 1 57 1.360 0 1 0 1 1 0 0 0 58 1.370 0 1 0 1 1 0 0 1 59 1.380 0 1 0 1 1 0 1 0 5A 1.390 0 1 0 1 1 0 1 1 5B 1.400 0 1 0 1 1 1 0 0 5C 1.410 0 1 0 1 1 1 0 1 5D 1.420 0 1 0 1 1 1 1 0 5E 1.430 0 1 0 1 1 1 1 1 5F 1.440 0 1 1 0 0 0 0 0 60 1.450 0 1 1 0 0 0 0 1 61 1.460 0 1 1 0 0 0 1 0 62 1.470 0 1 1 0 0 0 1 1 63 1.480 0 1 1 0 0 1 0 0 64 1.490 0 1 1 0 0 1 0 1 65 1.500 0 1 1 0 0 1 1 0 66 1.510 0 1 1 0 0 1 1 1 67 1.520 0 1 1 0 1 0 0 0 68 1.530 0 1 1 0 1 0 0 1 69 1.540 0 1 1 0 1 0 1 0 6A 1.550 0 1 1 0 1 0 1 1 6B 1.560 0 1 1 0 1 1 0 0 6C 1.570 0 1 1 0 1 1 0 1 6D 1.580 0 1 1 0 1 1 1 0 6E 1.590 0 1 1 0 1 1 1 1 6F 1.600 0 1 1 1 0 0 0 0 70 1.610 0 1 1 1 0 0 0 1 71 1.620 0 1 1 1 0 0 1 0 72 1.630 0 1 1 1 0 0 1 1 73 1.640 0 1 1 1 0 1 0 0 74 1.650 0 1 1 1 0 1 0 1 75 1.660 0 1 1 1 0 1 1 0 76 1.670 0 1 1 1 0 1 1 1 77 1.680

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 0 1 1 1 1 0 0 0 78 1.690 0 1 1 1 1 0 0 1 79 1.700 0 1 1 1 1 0 1 0 7A 1.710 0 1 1 1 1 0 1 1 7B 1.720 0 1 1 1 1 1 0 0 7C 1.730 0 1 1 1 1 1 0 1 7D 1.740 0 1 1 1 1 1 1 0 7E 1.750 0 1 1 1 1 1 1 1 7F 1.760 1 0 0 0 0 0 0 0 80 1.770 1 0 0 0 0 0 0 1 81 1.780 1 0 0 0 0 0 1 0 82 1.790 1 0 0 0 0 0 1 1 83 1.800 1 0 0 0 0 1 0 0 84 1.810 1 0 0 0 0 1 0 1 85 1.820 1 0 0 0 0 1 1 0 86 1.830 1 0 0 0 0 1 1 1 87 1.840 1 0 0 0 1 0 0 0 88 1.850 1 0 0 0 1 0 0 1 89 1.860 1 0 0 0 1 0 1 0 8A 1.870 1 0 0 0 1 0 1 1 8B 1.880 1 0 0 0 1 1 0 0 8C 1.890 1 0 0 0 1 1 0 1 8D 1.900 1 0 0 0 1 1 1 0 8E 1.910 1 0 0 0 1 1 1 1 8F 1.920 1 0 0 1 0 0 0 0 90 1.930 1 0 0 1 0 0 0 1 91 1.940 1 0 0 1 0 0 1 0 92 1.950 1 0 0 1 0 0 1 1 93 1.960 1 0 0 1 0 1 0 0 94 1.970 1 0 0 1 0 1 0 1 95 1.980 1 0 0 1 0 1 1 0 96 1.990 1 0 0 1 0 1 1 1 97 2.000 1 0 0 1 1 0 0 0 98 2.010 1 0 0 1 1 0 0 1 99 2.020 1 0 0 1 1 0 1 0 9A 2.030 1 0 0 1 1 0 1 1 9B 2.040 1 0 0 1 1 1 0 0 9C 2.050 1 0 0 1 1 1 0 1 9D 2.060 1 0 0 1 1 1 1 0 9E 2.070 1 0 0 1 1 1 1 1 9F 2.080

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 1 0 1 0 0 0 0 0 A0 2.090 1 0 1 0 0 0 0 1 A1 2.100 1 0 1 0 0 0 1 0 A2 2.110 1 0 1 0 0 0 1 1 A3 2.120 1 0 1 0 0 1 0 0 A4 2.130 1 0 1 0 0 1 0 1 A5 2.140 1 0 1 0 0 1 1 0 A6 2.150 1 0 1 0 0 1 1 1 A7 2.160 1 0 1 0 1 0 0 0 A8 2.170 1 0 1 0 1 0 0 1 A9 2.180 1 0 1 0 1 0 1 0 AA 2.190 1 0 1 0 1 0 1 1 AB 2.200 1 0 1 0 1 1 0 0 AC 2.210 1 0 1 0 1 1 0 1 AD 2.220 1 0 1 0 1 1 1 0 AE 2.230 1 0 1 0 1 1 1 1 AF 2.240 1 0 1 1 0 0 0 0 B0 2.250 1 0 1 1 0 0 0 1 B1 2.260 1 0 1 1 0 0 1 0 B2 2.270 1 0 1 1 0 0 1 1 B3 2.280 1 0 1 1 0 1 0 0 B4 2.290 1 0 1 1 0 1 0 1 B5 2.300 1 0 1 1 0 1 1 0 B6 2.310 1 0 1 1 0 1 1 1 B7 2.320 1 0 1 1 1 0 0 0 B8 2.330 1 0 1 1 1 0 0 1 B9 2.340 1 0 1 1 1 0 1 0 BA 2.350 1 0 1 1 1 0 1 1 BB 2.360 1 0 1 1 1 1 0 0 BC 2.370 1 0 1 1 1 1 0 1 BD 2.380 1 0 1 1 1 1 1 0 BE 2.390 1 0 1 1 1 1 1 1 BF 2.400 1 1 0 0 0 0 0 0 C0 2.410 1 1 0 0 0 0 0 1 C1 2.420 1 1 0 0 0 0 1 0 C2 2.430 1 1 0 0 0 0 1 1 C3 2.440 1 1 0 0 0 1 0 0 C4 2.450 1 1 0 0 0 1 0 1 C5 2.460 1 1 0 0 0 1 1 0 C6 2.470 1 1 0 0 0 1 1 1 C7 2.480

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V) 1 1 0 0 1 0 0 0 C8 2.490 1 1 0 0 1 0 0 1 C9 2.500 1 1 0 0 1 0 1 0 CA 2.510 1 1 0 0 1 0 1 1 CB 2.520 1 1 0 0 1 1 0 0 CC 2.530 1 1 0 0 1 1 0 1 CD 2.540 1 1 0 0 1 1 1 0 CE 2.550 1 1 0 0 1 1 1 1 CF 2.560 1 1 0 1 0 0 0 0 D0 2.570 1 1 0 1 0 0 0 1 D1 2.580 1 1 0 1 0 0 1 0 D2 2.590 1 1 0 1 0 0 1 1 D3 2.600 1 1 0 1 0 1 0 0 D4 2.610 1 1 0 1 0 1 0 1 D5 2.620 1 1 0 1 0 1 1 0 D6 2.630 1 1 0 1 0 1 1 1 D7 2.640 1 1 0 1 1 0 0 0 D8 2.650 1 1 0 1 1 0 0 1 D9 2.660 1 1 0 1 1 0 1 0 DA 2.670 1 1 0 1 1 0 1 1 DB 2.680 1 1 0 1 1 1 0 0 DC 2.690 1 1 0 1 1 1 0 1 DD 2.700 1 1 0 1 1 1 1 0 DE 2.710 1 1 0 1 1 1 1 1 DF 2.720 1 1 1 0 0 0 0 0 E0 2.730 1 1 1 0 0 0 0 1 E1 2.740 1 1 1 0 0 0 1 0 E2 2.750 1 1 1 0 0 0 1 1 E3 2.760 1 1 1 0 0 1 0 0 E4 2.770 1 1 1 0 0 1 0 1 E5 2.780 1 1 1 0 0 1 1 0 E6 2.790 1 1 1 0 0 1 1 1 E7 2.800 1 1 1 0 1 0 0 0 E8 2.810 1 1 1 0 1 0 0 1 E9 2.820 1 1 1 0 1 0 1 0 EA 2.830 1 1 1 0 1 0 1 1 EB 2.840 1 1 1 0 1 1 0 0 EC 2.850 1 1 1 0 1 1 0 1 ED 2.860 1 1 1 0 1 1 1 0 EE 2.870 1 1 1 0 1 1 1 1 EF 2.880

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 2. Standard Serial VID Commands

Description

00h not supported N/A N/A N/A 01h SetVID_Fast VID code N/A 1. Set new target VID code, VR jumps to new VID target with controlled default “fast” slew rate 12.5mV/s. 2. Set VR_Settled when VR reaches target VID voltage. 02h SetVID_Slow VID code N/A 1. Set new target VID code, VR jumps to new VID target with controlled default “slow” slew rate 3.125mV/s. 2. Set VR_Settled when VR reaches target VID voltage. 03h SetVID_Decay VID code N/A 1. Set new target VID code, VR jumps to new VID target, but does not control the slew rate. The output voltage decays at a rate proportional to the load current. 2. Low side MOSFET is not allowed to sync current. 3. ACK 11b when target higher than current VOUT voltage. 4. ACK 10b when target lower than current VOUT voltage. 04h SetPS Byte indicating power states N/A 1. Set power state. 2. ACK 11b when not support. 3. ACK 10b even slave not change configuration. 4. ACK 11b for still running SetVID command. 5. VR remains in lower state when receiving SetVID (decay). 05h SetRegADR Pointer of registers in data table N/A 1. Set the pointer of the data register. 2. ACK 11b for address outside of support. 3. NAK 01b for SetADR (all call). 06h SetReg DAT New data register content N/A 1. Write the contents to the data register. 2. NAK 01b for SetReg (all call). 07h GetReg Specified Register

Slave returns the contents of the specified register as the payload. 2. ACK 11b for non support address. 3. NAK 01b for GetReg (all call). 08h to 1Fh not supported N/A N/A N/A

©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 3. SVID Data and Configuration Register supports. Binary format in A IE 64h = 100A. Binary format in C IE 64h = 100C. 25h SR-slow Data register containing the capability of slow slew rate.

Electrical Characteristics

Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1)  Power Dissipation, PD @ TA = 25°C  Package Thermal Resistance (Note 2)  ESD Susceptibility (Note 3) (VCC = 5V, TA = 25 °C, unless otherwise specified) Parameter Symbol Test Conditions Min T yp Max Unit Supply Input Supply Current I VCC V EN = H, Not switching -- 4.1 -- mA Supply Current at PS3 I VCC_PS3 V EN = H, Not switching -- 2.7 -- mA Shutdown Current I SHDN V EN = 0V -- -- 5 A Reference and DAC VID VDAC = 1V 1.49V 8 0 8 DAC Accuracy V FB VDAC = 0.5V 0.99V 10 0 10 mV Slew Rate Set VID slow 2.5 3.125 3.75 Dynamic VID Slew Rate SR Set VID fast 10 12.5 15 mV/s EA Amplifier DC Gain A DC R L = 47k 70 -- -- dB Gain-Bandwidth Product G BW C LOAD = 5pF 4 5 -- MHz Slew Rate SR EA CLOAD = 10pF (Gain = 4, RF = 47k, VOUT = 0.5V to 3V) 5 -- -- V/ s

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Output Voltage Range V COMP R L = 47k 0.5 -- 3.6 V Maximum Source/Sink Current I OUTEA V COMP = 2V -- 5 -- mA Load-Line Current Gain Amplifier Input Offset Voltage V ILOFS V IMON = 1V 5 -- 5 mV Current Gain A ILGAIN VIMON VVREF = 1V VFB = VCOMP = 1.7V -- 1/2 -- A/A Current Sensing Amplifier Input Offset Voltage V OSCS 0.8 -- 0.8 mV Impedance at Positive Input R ISENxP 1 -- -- M  Current Mirror Gain A MIRROR I IMON / ISENxN 0.97 1 1.03 A/A TON Setting TONSET Pin Voltage V TON I RTON = 80A, VDAC = 1.7V 1.6 1.7 1.8 V On-Time Setting T ON I RTON = 80A, VDAC = 1.7V 450 500 550 ns Input Current Range I RTON V DAC = 1.7V 25 -- 280 A Minimum Off time T OFF V DAC = 1.7V -- 400 -- ns IBIAS IBIAS Pin Voltage V IBIAS R IBIAS = 100k 1.85 2 -- V OFS Setting Impedance R OFS 1 -- -- M  Enable OFS function and offset 600mV 1.95 2.4 2.44 Enable OFS function and offset 300mV 1.76 1.8 1.84 Enable OFS function and offset 0V 1.16 1.2 1.24 Enable OFS function and offset 50mV 1.06 1.1 1.14 Enable OFS function and offset 250mV 0.66 0.7 0.74 Set OFS Voltage V SET3 Disable -- -- 0.55 V Protections VUVLO 4.1 4.3 4.45 V Under Voltage Lockout Threshold VUVLO Falling edge hysteresis -- 200 -- mV VID higher than 1.5V VID + 300 VID + 350 VID + 400 Over Voltage Protection Threshold V OV VID lower than 1.5V 1800 1850 1900 mV Under Voltage Protection Threshold V UV Respect to VID voltage 400 350 300 mV Negative Voltage Protection Threshold VNV 100 70 -- mV EN and VR_RDY Logic-High V IH 0.7 -- -- EN Input Voltage Logic-Low V IL -- -- 0.3 V Leakage Current of EN 1 -- 1 A

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit VR_RDY Delay T VR_RDY V SEN = VBoot to VR_RDY High 3 4.5 6 s VR_RDY Pull Low Voltage V PGOOD I VR_RDY = 10mA -- -- 0.13 V DVD DVD Input V DVD Detect VIN Voltage 2 -- -- V Serial VID and VR_HOT Logic-High V IH Respect to INTEL Spec. with 50mV hysteresis 0.65 -- -- VCLK, VDIO Input Voltage Logic-Low V IL -- -- 0.45 V Leakage Current of VCLK, VDIO, ALERT and VR_HOT ILEAK_IN 1 -- 1 A IVDIO = 10mA IALERT = 10mA VDIO, ALERT and VR_HOT Pull Low Voltage IVR_HOT = 10mA -- -- 0.13 V VREF and VBOOT VREF Voltage V REF 0.55 0.6 0.65 V VBOOT Voltage V BOOT No Load, set V BOOT = 1.7V 1.692 1.7 1.708 V ADC VIMON VIMON_INI = 1.6V 252 255 258 VIMON VIMON_INI = 0.8V 125 128 131 Digital IMON Set V IMON VIMON VIMON_INI = 0V 0 0 3 Decimal Update Period of IMON T IMON 320 400 480 s TSEN Threshold for Tmp_Zone [7] transition VTSEN 100 C -- 1.887 -- V TSEN Threshold for Tmp_Zone [6] transition VTSEN 97 C -- 1.837 -- V TSEN Threshold for Tmp_Zone [5] transition VTSEN 94 C -- 1.784 -- V TSEN Threshold for Tmp_Zone [4] transition VTSEN 91 C -- 1.729 -- V TSEN Threshold for Tmp_Zone [3] transition VTSEN 88 C -- 1.672 -- V TSEN Threshold for Tmp_Zone [2] transition VTSEN 85 C -- 1.612 -- V TSEN Threshold for Tmp_Zone [1] transition VTSEN 82 C -- 1.551 -- V TSEN Threshold for Tmp_Zone [0] transition VTSEN 75 C -- 1.402 -- V Update Period of TSEN t TSEN 40 50 60 s CICCMAX1 V ICCMAX = 0.403V 58 64 70 CICCMAX2 V ICCMAX = 0.806V 122 128 134 Digital Code of ICCMAX CICCMAX3 V ICCMAX = 1.6V 248 256 260 Decimal

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 °C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit PWM Driving Capability PWM Source Resistance R PWM_SRC -- -- 30  PWM Sink R PWM_SNK -- -- 10 

12 VCC5V

24 DVD IBIAS16

V CC_SENSE V SS_SENSE V CORE_OUT ISEN4N ISEN4P PWM4 25 VIN GND 33 (Exposed Pad) VSEN COMP 12V ISEN1P ISEN1N 32 PWM1 27 VCC_SENSE VSS_SENSE RGND VCCIO VR_RDY23

18 VR_HOT

2.2 0.1µF 2.2µF R5R7 1.833k 9.68k R12 6.2k VCC RNTC1 R6 30k R8 75.8k R10 100k R11 5.6k 100k 390pF 90pF R24 10k C7 C8 Optional Optional Optional R19 10k R20 R21 130 R22 130 R23 150 R18 5.43k100k R16 12.6kC4 0.47µF R17 13.9k R15 100k R13 1 0.1µF R49 680 Q8 x 2 R45 0 R44 2.2 C32 0.1µF C33 22µF C34 390µF C36 1µFR47 510 Optional R48 R46 C35 Optional R43 680 Q6 x 2 R39 0 R38 2.2 C26 0.1µF C27 22µF C28 390µF C30 1µFR41 510 Optional R42 R40 C29 Optional R37 680 Q4 x 2 R33 0 R32 2.2 C17 0.1µF C18 22µF C19 390µF C21 1µFR35 510 Optional R36 R34 C20 Optional C25 0.1µF PWM BOOT UGATE PHASE LGATE RT9624A EN5V VCC GND 12V C31 0.1µF PWM BOOT UGATE PHASE LGATE RT9624A EN5V VCC GND 12V C16 0.1µF PWM BOOT UGATE PHASE LGATE RT9624A EN5V VCC GND 12V C10 0.1µF R31 680 Q2 x 2 R27 0 R26 2.2 C11 0.1µF C12 22µF C13 390µF C15 1µFR29 510 Optional R30 R28 C14 Optional R37 R38 C22 Optional C23 560µF/7m C22 22µFx19 Optional for OFS ß = 4485 ß = 4485 R14 130k 360nH / 0.72m  360nH / 0.72m  360nH / 0.72m  360nH / 0.72m  R25 59.2k Enable

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics VIN = 12V, No Load, Boot VID 1.7V Time (200 μs/Div) CORE VR Power On from EN EN (2V/Div) VR_RDY (2V/Div) UGATE1 (20V/Div) VCORE (2V/Div) VIN = 12V, No Load, Boot VID 1.7V Time (200 μs/Div) CORE VR Power Off from EN EN (2V/Div) VR_RDY (2V/Div) UGATE1 (20V/Div) VCORE (2V/Div) VIN = 12V, VID = 1.85V to 1.6V, Slew Rate = Slow Time (20 μs/Div) CORE VR Dynamic VID Down VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VCORE (1V/Div) VIN = 12V, VID = 1.6V to 1.85V, Slew Rate = Slow Time (20 μs/Div) CORE VR Dynamic VID Up VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VCORE (1V/Div) VIN = 12V, Boot VID 1.7V Time (40 μs/Div) CORE VR OVP VR_RDY (1V/Div) UGATE1 (20V/Div) LGATE1 (20V/Div) VCORE (2V/Div) VIN = 12V, Boot VID 1.7V Time (100 μs/Div) CORE VR OCP ILOAD (150A/Div) VR_RDY (2V/Div) UGATE1 (50V/Div) VCORE (2V/Div)

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VIMON vs. Load Current 0.0 0.5 1.0 1.5 2.0 2.5 0 25 50 75 100 125 Load Current (A) VIMON (V) VIN = 12V, TSEN Sweep from 1.7V to 2.1V Time (10ms/Div) CORE VR Thermal Monitoring TSEN (1V/Div) VR_HOT (1V/Div) VIN = 12V, VID = 1.6V to 1.85V, Slew Rate = Fast Time (10 μs/Div) CORE VR Dynamic VID Up VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VCORE (1V/Div) VIN = 12V, VID = 1.85V to 1.6V, Slew Rate = Fast Time (10 μs/Div) CORE VR Dynamic VID Down VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VCORE (1V/Div) VIN = 12V, VID = 1.7V, PS2 to PS0, ILOAD = 0.6A Time (100 μs/Div) CORE VR Mode Transient VCLK (1V/Div) UGATE1 (20V/Div) LGATE1 (10V/Div) VCORE (50mV/Div) VIN = 12V, VID = 1.7V, PS0 to PS2, ILOAD = 0.6A Time (100 μs/Div) CORE VR Mode Transient VCLK (1V/Div) UGATE1 (20V/Div) LGATE1 (10V/Div) VCORE (50mV/Div)

©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. can help reduce output voltage ripple and EMI problem. voltage and VID code to obtain a constant current ripple. like a constant as different input and output voltage change. TONSET pin to set the on-time width. Figure 4. Lossless Current Sense Method in per phase current loop for thermal compensation. and set accurate over current protection. drifting for high accuracy load-line (droop). fSW(MAX) is the maximum switching frequency. VDAC(MAX) is the maximum VDAC of application. VIN(MAX) is the maximum application input voltage. parameters (VIN(MAX), VDAC(MAX)). more power from input terminal to regulate output voltage. related loss increases, vice versa. for allowing high efficiency as illustrated in the Figure 4.

1 DCR R2RAR = = (m ) R2A

Figure 6. Load-Line (Droop) Figure 7. Voltage Loop and Current Loop Figure 5. Total Current Sense Method

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 4 : SET2 Pin Setting for QR Threshold and QR Width QR_SET R1 R2V = 8 0 A R1 R2   Min Typical Max unit QR_TH <2:0> QRWIDTH <2:0> QR Threshold QR Width (%TON) 0.000 10.948 21.896 mV 000 No Use 25.024 35.973 46.921 mV 001 155% 50.049 60.997 71.945 mV 010 133% 75.073 86.022 96.970 mV 011 111% 100.098 11 1.046 121.994 mV 100 89% 125.122 136.070 147.019 mV 101 67% 150.147 161.095 172.043 mV 110 44% 175.171 186.119 197.067 mV 000 111 Disable No Use 200.196 211.144 222.092 mV 000 No Use 225.220 236.168 247.116 mV 001 155% 250.244 261.193 272.141 mV 010 133% 275.269 286.217 297.165 mV 011 111% 300.293 311.241 322.190 mV 100 89% 325.318 336.266 347.214 mV 101 67% 350.342 361.290 372.239 mV 110 44% 375.367 386.315 397.263 mV 001 111 30mV No Use 400.391 411.339 422.287 mV 000 No Use 425.415 436.364 447.312 mV 001 155% 450.440 461.388 472.336 mV 010 133% 475.464 486.413 497.361 mV 011 111% 500.489 511.437 522.385 mV 100 89% 525.513 536.461 547.410 mV 101 67% 550.538 561.486 572.434 mV 110 44% 575.562 586.510 597.458 mV 010 111 35mV No Use 600.587 611.535 622.483 mV 000 No Use 625.611 636.559 647.507 mV 001 155% 650.635 661.584 672.532 mV 010 133% 675.660 686.608 697.556 mV 011 111% 700.684 711.632 722.581 mV 100 89% 725.709 736.657 747.605 mV 101 67% 750.733 761.681 772.630 mV 110 44% 775.758 786.706 797.654 mV 011 111 40mV No Use 800.782 811.730 822.678 mV 000 No Use 825.806 836.755 847.703 mV 001 155% 850.831 861.779 872.727 mV 010 133% 875.855 886.804 897.752 mV 011 111% 900.880 911.828 922.776 mV 100 89% 925.904 936.852 947.801 mV 101 67% 950.929 961.877 972.825 mV 110 44% 975.953 986.901 997.849 mV 100 111 45mV No Use

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Dynamic VID (DVID) Compensation When VID transition event occurs, a charge current will be generated in the loop to cause that DVID performance is deteriorated by this induced charge current, the phenomenon is called droop effect. The droop effect is shown in Figure 13. When VID up transition occurs, the output capacitor will be charged by inductor current. Since current signal is sensed in inductor, an induced charge current will appear in control loop. The induced charge current will produce a voltage drop in R1 to cause output voltage to have a droop effect. Due to this, VID transition performance will be deteriorated. The RT8884C provides a DVID compensation function. A virtual charge current signal can be established by the SET1 pin to cancel the real induced charge current signal and the virtual charge current signal is defined in Figure 15. Figure 14 shows the operation of cancelling droop effect. A virtual charge current signal is established first and then VID signal plus virtual charge current signal is generated in FB pin. Hence, an induced charge current signal flows to R1 and is cancelled to reduce droop effect. QR_SET R1 R2V = 8 0 A R1 R2   Min Typical Max unit QR_TH <2:0> QRWIDTH <2:0> QR Threshold QR Width (%TON) 1000.978 1011.926 1022.874 mV 000 No Use 1026.002 1036.950 1047.898 mV 001 155% 1051.026 1061.975 1072.923 mV 010 133% 1076.051 1086.999 1097.947 mV 011 11 1% 1101.075 1112.023 1122.972 mV 100 89% 1 126.100 1137.048 1147.996 mV 101 67% 1 151.124 1162.072 1173.021 mV 110 44% 1 176.149 1187.097 1198.045 mV 101 111 50mV No Use 1201.173 1212.121 1223.069 mV 000 No Use 1226.197 1237.146 1248.094 mV 001 155% 1251.222 1262.170 1273.118 mV 010 133% 1276.246 1287.195 1298.143 mV 011 11 1% 1301.271 1312.219 1323.167 mV 100 89% 1326.295 1337.243 1348.192 mV 101 67% 1351.320 1362.268 1373.216 mV 110 44% 1376.344 1387.292 1398.240 mV 110 111 55mV No Use 1401.369 1412.317 1423.265 mV 000 No Use 1426.393 1437.341 1448.289 mV 001 155% 1451.417 1462.366 1473.314 mV 010 133% 1476.442 1487.390 1498.338 mV 011 11 1% 1501.466 1512.414 1523.363 mV 100 89% 1526.491 1537.439 1548.387 mV 101 67% 1551.515 1562.463 1573.412 mV 110 44% 1576.540 1587.488 1598.436 mV 111 111 60mV No Use

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 5 : SET1 Pin Setting for DVID_Threshold DVID_Threshold R1 R2V = 8 0 A R1 R2   Min Typical Max unit DVID_TH <2:0> OCS <2:0> DVID_Threshold OCP = %ICCMAX 0.000 10.948 21.896 mV 000 No Use 25.024 35.973 46.921 mV 001 100% 50.049 60.997 71.945 mV 010 110% 75.073 86.022 96.970 mV 011 120% 100.098 111.046 121.994 mV 100 130% 125.122 136.070 147.019 mV 101 140% 150.147 161.095 172.043 mV 110 150% 175.171 186.119 197.067 mV 000 111 15mV No Use 200.196 21 1.144 222.092 mV 000 No Use 225.220 236.168 247.116 mV 001 100% 250.244 261.193 272.141 mV 010 110% 275.269 286.217 297.165 mV 011 120% 300.293 31 1.241 322.190 mV 100 130% 325.318 336.266 347.214 mV 101 140% 350.342 361.290 372.239 mV 110 150% 375.367 386.315 397.263 mV 001 111 25mV No Use 400.391 41 1.339 422.287 mV 000 No Use 425.415 436.364 447.312 mV 001 100% 450.440 461.388 472.336 mV 010 110% 475.464 486.413 497.361 mV 011 120% 500.489 51 1.437 522.385 mV 100 130% 525.513 536.461 547.410 mV 101 140% 550.538 561.486 572.434 mV 110 150% 575.562 586.510 597.458 mV 010 111 35mV No Use 600.587 61 1.535 622.483 mV 000 No Use 625.611 636.559 647.507 mV 001 100% 650.635 661.584 672.532 mV 010 110% 675.660 686.608 697.556 mV 011 120% 700.684 71 1.632 722.581 mV 100 130% 725.709 736.657 747.605 mV 101 140% 750.733 761.681 772.630 mV 110 150% 775.758 786.706 797.654 mV 01 1 111 45mV No Use 800.782 81 1.730 822.678 mV 000 No Use 825.806 836.755 847.703 mV 001 100% 850.831 861.779 872.727 mV 010 110% 875.855 886.804 897.752 mV 011 120% 900.880 91 1.828 922.776 mV 100 130% 925.904 936.852 947.801 mV 101 140% 950.929 961.877 972.825 mV 110 150% 975.953 986.901 997.849 mV 100 111 55mV No Use

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. DVID_Thr eshold R1 R2V = 8 0 A R1 R2   Min Typical Max unit DVID_TH <2:0> OCS <2:0> DVID_Threshold OCP = %ICCMAX 1000.978 1011.926 1022.874 mV 000 No Use 1026.002 1036.950 1047.898 mV 001 100% 1051.026 1061.975 1072.923 mV 010 110% 1076.051 1086.999 1097.947 mV 011 120% 1 101.075 11 12.023 1122.972 mV 100 130% 1 126.100 1137.048 1147.996 mV 101 140% 1 151.124 1162.072 1173.021 mV 1 10 150% 1 176.149 1187.097 1198.045 mV 101 111 65mV No Use 1201.173 1212.121 1223.069 mV 000 No Use 1226.197 1237.146 1248.094 mV 001 100% 1251.222 1262.170 1273.1 18 mV 010 110% 1276.246 1287.195 1298.143 mV 011 120% 1301.271 1312.219 1323.167 mV 100 130% 1326.295 1337.243 1348.192 mV 101 140% 1351.320 1362.268 1373.216 mV 1 10 150% 1376.344 1387.292 1398.240 mV 110 111 75mV No Use 1401.369 1412.317 1423.265 mV 000 No Use 1426.393 1437.341 1448.289 mV 001 100% 1451.417 1462.366 1473.314 mV 010 110% 1476.442 1487.390 1498.338 mV 011 120% 1501.466 1512.414 1523.363 mV 100 130% 1526.491 1537.439 1548.387 mV 101 140% 1551.515 1562.463 1573.412 mV 1 10 150% 1576.540 1587.488 1598.436 mV 111 111 85mV No Use

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 6 : SET1 Pin Setting for DVID_Width DVID_Width CC R2V = V R1 R2  Min Typical Max unit DVID_WTH <2:0> RSET <2:0> DVID_Width RSET % 130k R TON 0.000 10.948 21.896 mV 000 No Use 25.024 35.973 46.921 mV 001 75% 50.049 60.997 71.945 mV 010 87.5% 75.073 86.022 96.970 mV 011 100% 100.098 111.046 121.994 mV 100 112.5% 125.122 136.070 147.019 mV 101 125% 150.147 161.095 172.043 mV 110 137.5% 175.171 186.119 197.067 mV 000 111 48s No Use 200.196 211.144 222.092 mV 000 No Use 225.220 236.168 247.116 mV 001 75% 250.244 261.193 272.141 mV 010 87.5% 275.269 286.217 297.165 mV 011 100% 300.293 311.241 322.190 mV 100 112.5% 325.318 336.266 347.214 mV 101 125% 350.342 361.290 372.239 mV 110 137.5% 375.367 386.315 397.263 mV 001 111 72s No Use 400.391 411.339 422.287 mV 000 No Use 425.415 436.364 447.312 mV 001 75% 450.440 461.388 472.336 mV 010 87.50% 475.464 486.413 497.361 mV 011 100% 500.489 511.437 522.385 mV 100 112.5% 525.513 536.461 547.410 mV 101 125% 550.538 561.486 572.434 mV 110 137.5% 575.562 586.510 597.458 mV 010 111 96s No Use 600.587 611.535 622.483 mV 000 No Use 625.611 636.559 647.507 mV 001 75% 650.635 661.584 672.532 mV 010 87.50% 675.660 686.608 697.556 mV 011 100% 700.684 711.632 722.581 mV 100 112.50% 725.709 736.657 747.605 mV 101 125% 750.733 761.681 772.630 mV 110 137.5% 775.758 786.706 797.654 mV 011 111 120s No Use 800.782 811.730 822.678 mV 000 No Use 825.806 836.755 847.703 mV 001 75% 850.831 861.779 872.727 mV 010 87.5% 875.855 886.804 897.752 mV 011 100% 900.880 911.828 922.776 mV 100 112.50% 925.904 936.852 947.801 mV 101 125% 950.929 961.877 972.825 mV 110 137.5% 975.953 986.901 997.849 mV 100 111 144s No Use

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. DVID_Width CC R2V = V R1 R2  Min Typical Max unit DVID_WTH <2:0> RSET <2:0> DVID_Width RSET % 130k R TON 1000.978 1011.926 1022.874 mV 000 No Use 1026.002 1036.950 1047.898 mV 001 75% 1051.026 1061.975 1072.923 mV 010 87.5% 1076.051 1086.999 1097.947 mV 011 100% 1101.075 1112.023 1 122.972 mV 100 112.5% 1126.100 1 137.048 1 147.996 mV 101 125% 1151.124 1 162.072 1 173.021 mV 110 137.5% 1176.149 1 187.097 1 198.045 mV 101 111 168s No Use 1201.173 1212.121 1223.069 mV 000 No Use 1226.197 1237.146 1248.094 mV 001 75% 1251.222 1262.170 1273.1 18 mV 010 87.5% 1276.246 1287.195 1298.143 mV 011 100% 1301.271 1312.219 1323.167 mV 100 112.5% 1326.295 1337.243 1348.192 mV 101 125% 1351.320 1362.268 1373.216 mV 110 137.5% 1376.344 1387.292 1398.240 mV 110 111 192s No Use 1401.369 1412.317 1423.265 mV 000 No Use 1426.393 1437.341 1448.289 mV 001 75% 1451.417 1462.366 1473.314 mV 010 87.50% 1476.442 1487.390 1498.338 mV 011 100% 1501.466 1512.414 1523.363 mV 100 112.5% 1526.491 1537.439 1548.387 mV 101 125% 1551.515 1562.463 1573.412 mV 110 137.5% 1576.540 1587.488 1598.436 mV 111 111 216s No Use

©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 16. Ramp Compensation be considered during mode transition from PS0/1 to PS2. RTON is 100kΩ, the RAMP is set as . definitions of DCR, RCS and REQ can refer to Figure 6. signal will be pulled to low level if VIMON − VREF = 1.6V.

DS8884C-00 July 2015www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 7 : SET2 Pin Setting for ICCMAX ICCMAX CC R2V = V R1 R2  Min Typical Max Unit ICCMAX Unit 0.000 3.128 6.256 mV 0 A 12.512 15.640 18.768 mV 2 A 25.024 28.152 31.281 mV 4 A 37.537 40.665 43.793 mV 6 A 50.049 53.177 56.305 mV 8 A 62.561 65.689 68.817 mV 10 A 75.073 78.201 81.329 mV 12 A 87.586 90.714 93.842 mV 14 A 100.098 103.226 106.354 mV 16 A 1 12.610 115.738 118.866 mV 18 A 125.122 128.250 131.378 mV 20 A 137.634 140.762 143.891 mV 22 A 150.147 153.275 156.403 mV 24 A 162.659 165.787 168.915 mV 26 A 175.171 178.299 181.427 mV 28 A 187.683 190.811 193.939 mV 30 A 200.196 203.324 206.452 mV 32 A 212.708 215.836 218.964 mV 34 A 225.220 228.348 231.476 mV 36 A 237.732 240.860 243.988 mV 38 A 250.244 253.372 256.500 mV 40 A 262.757 265.885 269.013 mV 42 A 275.269 278.397 281.525 mV 44 A 287.781 290.909 294.037 mV 46 A 300.293 303.421 306.549 mV 48 A 312.805 315.934 319.062 mV 50 A 325.318 328.446 331.574 mV 52 A 337.830 340.958 344.086 mV 54 A 350.342 353.470 356.598 mV 56 A 362.854 365.982 369.110 mV 58 A 375.367 378.495 381.623 mV 60 A 387.879 391.007 394.135 mV 62 A 400.391 403.519 406.647 mV 64 A 412.903 416.031 419.159 mV 66 A 425.415 428.543 431.672 mV 68 A 437.928 441.056 444.184 mV 70 A 450.440 453.568 456.696 mV 72 A 462.952 466.080 469.208 mV 74 A 475.464 478.592 481.720 mV 76 A 487.977 491.105 494.233 mV 78 A 500.489 503.617 506.745 mV 80 A ICCMAX CC R2V = V R1 R2  Min Typical Max Unit ICCMAX Unit 513.001 516.129 519.257 mV 82 A 525.513 528.641 531.769 mV 84 A 538.025 541.153 544.282 mV 86 A 550.538 553.666 556.794 mV 88 A 563.050 566.178 569.306 mV 90 A 575.562 578.690 581.818 mV 92 A 588.074 591.202 594.330 mV 94 A 600.587 603.715 606.843 mV 96 A 613.099 616.227 619.355 mV 98 A 625.611 628.739 631.867 mV 100 A 638.123 641.251 644.379 mV 102 A 650.635 653.763 656.891 mV 104 A 663.148 666.276 669.404 mV 106 A 675.660 678.788 681.916 mV 108 A 688.172 691.300 694.428 mV 1 10 A 700.684 703.812 706.940 mV 1 12 A 713.196 716.325 719.453 mV 1 14 A 725.709 728.837 731.965 mV 1 16 A 738.221 741.349 744.477 mV 1 18 A 750.733 753.861 756.989 mV 120 A 763.245 766.373 769.501 mV 122 A 775.758 778.886 782.014 mV 124 A 788.270 791.398 794.526 mV 126 A 800.782 803.910 807.038 mV 128 A 813.294 816.422 819.550 mV 130 A 825.806 828.935 832.063 mV 132 A 838.319 841.447 844.575 mV 134 A 850.831 853.959 857.087 mV 136 A 863.343 866.471 869.599 mV 138 A 875.855 878.983 882.111 mV 140 A 888.368 891.496 894.624 mV 142 A 900.880 904.008 907.136 mV 144 A 913.392 916.520 919.648 mV 146 A 925.904 929.032 932.160 mV 148 A 938.416 941.544 944.673 mV 150 A 950.929 954.057 957.185 mV 152 A 963.441 966.569 969.697 mV 154 A 975.953 979.081 982.209 mV 156 A 988.465 991.593 994.721 mV 158 A 1000.978 1004.106 1007.234 mV 160 A 1013.490 1016.618 1019.746 mV 162 A

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. ICCMAX CC R2V = V R1 R2  Min Typical Max Unit ICCMAX Unit 1026.002 1029.13 1032.258 mV 164 A 1038.514 1041.642 1044.770 mV 166 A 1051.026 1054.154 1057.283 mV 168 A 1063.539 1066.667 1069.795 mV 170 A 1076.051 1079.179 1082.307 mV 172 A 1088.563 1091.691 1094.819 mV 174 A 1101.075 1104.203 1107.331 mV 176 A 1 113.587 11 16.716 1119.844 mV 178 A 1126.100 1129.228 1132.356 mV 180 A 1138.612 1141.740 1144.868 mV 182 A 1151.124 1154.252 1157.380 mV 184 A 1163.636 1166.764 1169.892 mV 186 A 1176.149 1179.277 1182.405 mV 188 A 1188.661 1191.789 1194.917 mV 190 A 1201.173 1204.301 1207.429 mV 192 A 1213.685 1216.813 1219.941 mV 194 A 1226.197 1229.326 1232.454 mV 196 A 1238.710 1241.838 1244.966 mV 198 A 1251.222 1254.350 1257.478 mV 200 A 1263.734 1266.862 1269.990 mV 202 A 1276.246 1279.374 1282.502 mV 204 A 1288.759 1291.887 1295.015 mV 206 A 1301.271 1304.399 1307.527 mV 208 A ICCMAX CC R2V = V R1 R2  Min Typical Max Unit ICCMAX Unit 1313.783 1316.911 1320.039 mV 210 A 1326.295 1329.423 1332.551 mV 212 A 1338.807 1341.935 1345.064 mV 214 A 1351.320 1354.448 1357.576 mV 216 A 1363.832 1366.960 1370.088 mV 218 A 1376.344 1379.472 1382.600 mV 220 A 1388.856 1391.984 1395.112 mV 222 A 1401.369 1404.497 1407.625 mV 224 A 1413.881 1417.009 1420.137 mV 226 A 1426.393 1429.521 1432.649 mV 228 A 1438.905 1442.033 1445.161 mV 230 A 1451.417 1454.545 1457.674 mV 232 A 1463.930 1467.058 1470.186 mV 234 A 1476.442 1479.570 1482.698 mV 236 A 1488.954 1492.082 1495.210 mV 238 A 1501.466 1504.594 1507.722 mV 240 A 1513.978 1517.107 1520.235 mV 242 A 1526.491 1529.619 1532.747 mV 244 A 1539.003 1542.131 1545.259 mV 246 A 1551.515 1554.643 1557.771 mV 248 A 1564.027 1567.155 1570.283 mV 250 A 1576.540 1579.668 1582.796 mV 252 A 1589.052 1592.180 1595.308 mV 254 A

©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 24. All Kind of RxCx Constants load condition then DCR value goes large simultaneously. TH, at which are compensated. β is in the NTC thermistor datasheet. RIMON2 and RIMON3 can be found out unique solution.

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Design Step : RT8884C Excel based design tool is available. Users can contact your Richtek representative to get the spreadsheet. Three main design procedures for RT8884C design, first step is initial settings, second step is loop design and the last step is protection settings. The following design example is to explain RT8884C design procedure : VCORE Specification Input Voltage 12V No. of Phases 3 Vboot 1.7V VDAC(MAX) 1.85V ICCMAX 90A ICC-DY 60A ICC-TDC 55A Load-Line 1.5m  Fast Slew Rate 12.5mV/ s Max Switching Frequency 300kHz In Shark Bay VRTB Guideline, the output filter requirements of VRTB specification for desktop platform are as follows : Output Inductor : 360nH/0.72mΩ Output Bulk Capacitor : 560μF/2.5V/5mΩ (max) 4 to 5pcs Output Ceramic Capacitor : 22μF/0805 (18pcs max sites on top side) (1)Initial Settings : RT8884C initial voltage is 1.7V IBIASE needs to connect a 100kΩ resistor to ground.  A voltage divider for setting DVD can choose RDVD_U = 510kΩ and RDVD_L = 125kΩ to set VDVD > 2V, RT8884C enabled. (2)Loop Design : On time setting : Using the specification, TON is  Current sensor adopts lossless RC filter to sense current signal in DCR. For getting an expected load transient waveform, RxCx time constant needs to match Lx/DCRx per phase. Cx = 1μF is set, then F  X X X LR= = 5 0 01 DCR  IMON resistor network design : T L = 25°C, TR = 50°C and TH = 100°C are decided, NTC thermistor = 100kΩ @25°C, β = 4485 and ICCMAX = 90A. According to the sub-section “ Current Loop Design in Details ” , RIMON1 = 5.43kΩ, RIMON2 = 12.6kΩ and RIMON3 = 13.9kΩ can be decided. The REQ (25°C) = 16.8kΩ.  Load-line design : 1.5mΩ droop is required, because REQ (25°C) is decided, the voltage loop Av gain is also decided by the following equation : EQ CSV LL I

1 DCR R2RAR= = ( m ) R2A

Where DCR(25 °C) = 0.72m Ω, R CS = 680 Ω and REQ (25°C) = 16.8kΩ. Hence the AV = R2 / R1 = 5.92 can be obtained. R1 = 10kΩ usually is decided, so R2 = 59.2kΩ.  Typical compensator design can use the following equations to design the C1 and C2 values 1 1S W 1C = 106pFRf  OUT CE S RC = 79pFR For Intel platform, in order to induce the band width to enhance transient performance to meet Intel's criterion, the compensator of Zero can be designed close to 1/10 of switching frequency.  SET1 resistor network design : First the DVID compensation parameters need to be decided. The DVID_TH can be calculated as the following equation : DVID_TH OUT dVIDV= L L C dt Where LL is load-line, C OUT is total output capacitance and dVID/dt is DVID fast slew rate. Thus VDVID_TH = 45mV is needed in this case. And DVID_Width is chosen as 72μs typically. Next, OCP threshold is designed as 1.4 x ICCMAX. Last, RAMP = R TON / 130kΩ = 100%, 100% is The on time setting resistor RTON = 130kΩ  DAC(MAX) ON SW(MAX) IN V1t = = 514n(s)fV

©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. resistor from SET3 pin to ground. to calculate related resistances for VR_HOT setting. on the maximum power dissipation. Figure 25. Derating Curve of Maximum Power

DS8884C-00 July 2015 www.richtek.com ©Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Layout Considerations Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flushed against one another. Follow these guidelines for optimum PC board layout :  Keep the high current paths short, especially at the ground terminals.  Keep the power traces and load connections short. This is essential for high efficiency.  When trade-offs in trace lengths must be made, it 's preferable to let the inductor charging path be longer than the discharging path.  Place the current sense component close to the controller. ISENxP and ISENxN connections for current limit and voltage positioning must be made using Kelvin sense connections to guarantee current sense accuracy. The PCB trace from the sense nodes should be paralleled back to the controller.  Route high speed switching nodes away from sensitive analog areas (COMP, FB, ISENxP, ISENxN, etc...)  User need to connect exposed pad to the ground plane through low impedance path. Recommend use of at least 5 vias to connect to ground planes in PCB internal layers.

DS8884C-00 July 2015www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 3.900 4.100 0.154 0.161 D2 2.650 2.750 0.104 0.108 E 3.900 4.100 0.154 0.161 E2 2.650 2.750 0.104 0.108 e 0.400 0.016 L 0.300 0.400 0.012 0.016 W-Type 32L QFN 4x4 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2

Product Information

RT8884CGQW specifications and overview.

Summary

Multi-Phase PWM Controller for CPU Core Power Supply

Description

Multi-Phase PWM Controller for CPU Core Power Supply

Source title RT8884CGQW Datasheet(PDF) - Richtek Technology Corporation

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7 VREF

12 VCC

16 IBIAS

Contents

Description

Electrical Characteristics

12 VCC5V

24 DVD IBIAS16

18 VR_HOT

1 DCR R2RAR = = (m ) R2A

1 DCR R2RAR= = ( m ) R2A

RT8884CGQW specifications and overview.

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