RT8859M

RT8859M_14 RICHTEK | Alldatasheet

Document overview

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Technical content

Features

zzzzz 4/3/2/1 + 1 Phase PWM Controller zzzzz G-NAVPTM Topology zzzzz Serial VID Interface zzzzz 0.5% DAC Accuracy zzzzz Differential Remote Voltage Sensing zzzzz Built-in ADC for Platform Programming zzzzz Accurate Current Balance zzzzz System Thermal Compensated AVP zzzzz Diode Emulation Mode at Light Load Condition for Multiple and Single Phase zzzzz Fast Transient Response zzzzz VR12 / IMVP7 Compatible Power Management States zzzzz VR Ready Indicator zzzzz Thermal Throttling zzzzz Current Monitor Output zzzzz Switching Frequency up to 1MHz per Phase zzzzz OVP, UVP, OCP, NVP, UVLO zzzzz Slew Rate Setting/Address Flip Function zzzzz External No-Load Offset Setting for both Rails zzzzz DVID Improvement zzzzz Small 56-Lead WQFN Package zzzzz RoHS Compliant and Halogen Free

Applications

zzzzz VR12 / IMVP7 Intel Core Supply zzzzz Notebook/ Desktop Computer/ Servers Multi-phase CPU Core Supply zzzzz AVP Step-Down Converter Package Type QW : WQFN-56L 7x7 (W-Type) RT8859M Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free)

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin Configurations WQFN-56L 7x7 (TOP VIEW) Marking Information RT8859MZQW : Product Number YMDNN : Date Code ISEN2P ISEN1P ISEN1N RGND FB COMP RSET ISEN4P ISEN4N ISEN3P ISEN3N ISEN2N IMON IMONFB ADD VCLK VDIO ICCMAXA IBIAS SETINI SETINIA TMPMAX ICCMAX OCSETA VRA_RDY VR_RDY FBA COMPA ISENAN ISENAP QRSETA EN PWMA VCC QRSET PWM2 PWM1 PWM3 PWM4 TSEN TONSET TONSETA DVD DVDA 262524232221201918171615 454647484950515253545556 RGNDA31 OFSA30 SR_ADDF29 IMONFBA IMONA DVID 13 OFS 14 TSENA OCSET GND DVIDA VRHOT ALERT RT8859M ZQW YMDNN RT8859MGQW : Product Number YMDNN : Date Code RT8859MGQW RT8859MZQW RT8859M GQW YMDNN

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Application Circuit Thermal Compensation at Voltage Loop RT8859M 12V 12V RT9612 VCC PWM BOOT UGATE PHASE LGATE 12V PGND VCC PWM BOOT UGATE PHASE LGATE 12V PGND RT9612 12V 12V RT9612 VCC PWM BOOT UGATE PHASE LGATE 12V PGND VCC PWM BOOT UGATE PHASE LGATE 12V PGND RT9612 12V RT9612 VCC PWM BOOT UGATE PHASE LGATE 12V PGND ISEN4P ISEN4N ISEN3N ISEN3P ISEN2P VCC ISEN2N ISEN1N ISEN1P TSEN TSENA ADD ISENAN PWM4 PWM3 PWM2 PWM1 ISENAP PWMA EN FB COMP IMONFB IMONFBA V SS_SENSE 12V 12V TONSETA TONSET50 VCCIO DVD48 OFSA QRSETA ICCMAXA 26 IBIAS 21 VRHOT IMON 15 ICCMAX TMPMAX 24 VSSAXG_SENSE GND 57 (Exposed Pad) RSET9 IMONA28 DVID13 VCC_SENSE R NTC VCCAXG_SENSE 12V RNTC COMPA33 FBA32 LOAD LOAD R NTC OCSETA 42 R NTC OCSET 43 R NTC SR_ADDF 30 Chip Enable QRSET RNTC RGNDA31 RGND 12 SETINIA 23SETINI 22 OFS 14 DVDA47 12V VIN VIN DVIDA56 VR_RDY VRA_RDY 39 VDIO VCLK ALERT VR_RDY VRA_RDY VDIO VCLK ALERT VCCIO

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Thermal Compensation at Current Loop RT8859M 12V 12V RT9612 VCC PWM BOOT UGATE PHASE LGATE 12V PGND VCC PWM BOOT UGATE PHASE LGATE 12V PGND RT9612 12V 12V RT9612 VCC PWM BOOT UGATE PHASE LGATE 12V PGND VCC PWM BOOT UGATE PHASE LGATE 12V PGND RT9612 12V RT9612 VCC PWM BOOT UGATE PHASE LGATE 12V PGND ISEN4P ISEN4N ISEN3N ISEN3P ISEN2P VCC ISEN2N ISEN1N ISEN1P TSEN TSENA ADD ISENAN PWM4 PWM3 PWM2 PWM1 ISENAP PWMA EN FB COMP IMONFB IMONFBA V SS_SENSE 12V 12V TONSETA TONSET50 VCCIO DVDA47 OFSA QRSETA ICCMAXA 26 IBIAS 21 VRHOT IMON 15 ICCMAX TMPMAX 24 V CCAXG_SENSE GND 57 (Exposed Pad) RSET9 IMONA28 OFS14 V CC_SENSE R NTC V SSAXG_SENSE 12V RNTC COMPA33 FBA32 LOAD LOAD R NTC OCSETA R NTC SR_ADDF OCSET Chip Enable R NTC 55QRSET RGNDA31 RGND 12 SETINIA 23 SETINI 22 OFS 14 VIN VIN DVD48 12V DVIDA56 VR_RDY VRA_RDY 39 VDIO VCLK ALERT VR_RDY VRA_RDY VDIO VCLK ALERT VCCIO

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. AXG VR Disabled RT8859M 12V 12V RT9619 VCC PWM BOOT UGATE PHASE LGATE 12V PGND VCC PWM BOOT UGATE PHASE LGATE 12V PGND RT9619 12V 12V RT9619 VCC PWM BOOT UGATE PHASE LGATE 12V PGND VCC PWM BOOT UGATE PHASE LGATE 12V PGND RT9619 ISEN4P ISEN4N ISEN3N ISEN3P ISEN2P VCC ISEN2N ISEN1N ISEN1P TSEN TSENA ADD ISENAN PWM4 PWM3 PWM2 PWM1 ISENAP PWMA EN FB COMP IMONFB IMONFBA V SS_SENSE 12V TONSETA TONSET50 DVDA47 VTTVR_RDY 40 VTT VDIO VCLK ALERT 12V48DVD QRSET TMPMAX 24 IBIAS 21 VRHOT IMON 15 SETINI 22 RSET9 IMONA28 V CC_SENSE R NTC COMPA33 FBA32 LOAD R NTC ICCMAX 25 Chip Enable RGNDA31 RGND 12 * * * * * : Optional ICCMAXA SETINIA23 OCSETA42 QRSETA OCSET43 R NTC GND 57 (Exposed Pad) Floating OFS SR_ADDF OFSA30 VRA_RDY39 DVID DVIDA56

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 4, 1, 5, 8 ISEN [1:4] P Positive Current Sense Pin of Phase 1, 2, 3 and 4. 3, 2, 6, 7 ISEN [1:4] N Negative Current Sense Pin of Phase 1, 2, 3 and 4. 9 RSET Multi-Phase CORE VR Ramp Setting. This is used to set the multi-phase CORE VR loop external ramp slope. 10 COMP Multi-Phase CORE VR Compensation. This pin is the output node of the error amplifier. 11 FB Multi-Phase CORE VR Feedback. This is the negative input node of the error amplifier. 12 RGND Return Ground for Multi-Phase CORE VR. This pin is the negative node of the differential remote voltage sensing.

13 DVID Connect a resistor and a capacitor from this pin to GND to improve DVID

performance. Short this pin to GND if this function is not needed. 14 OFS Output Voltage Offset Setting. 15 IMON Current Monitor Output. This pin outputs a voltage proportional to the output current.

16 IMONFB

Current Monitor Output Gain External Setting. Connect this pin with one resistor to CPU V CC_SENSE, while the IMON pin is connected to ground with another resistor. The current monitor output gain can be set by the ratio of these two resistors. 17 ADD VR Address Setting Pin. 18 VCLK Synchronous Clock from CPU. 19 VDIO Controller and CPU Data Transmission Interface. 20 ALERT SVID Alert Pin (Active Low). 21 IBIAS Internal Bias Current Setting. Connect this pin to GND via a resistor to set the internal current. 22 SETINI CORE VR V INITIAL Setting. 23 SETINIA AXG VR V INITIALA Setting. 24 TMPMAX ADC Input for Multi-Phase CORE VR Maximum Temperature Setting. This pin is also used for AXG VR’s offset selection. 25 ICCMAX ADC Input for Multi-Phase CORE VR Maximum Current Setting. This pin is also used for CORE VR’s offset selection. 26 ICCMAXA ADC Input for Single-Phase AXG VR Maximum Current Setting.

27 IMONFBA

Single-Phase AXG VR Current Monitor Output Gain External Setting. Connect this pin with one resistor to AXG rail V CCAXG_SENSE, while IMONA pin is connected to ground with another resistor. The current monitor output gain can be set by the ratio of these two resistors. 28 IMONA Single-Phase AXG VR Current Monitor Output. This pin outputs a voltage proportional to the output current. 29 SR_ADDF Address Flip and DVID Slew Rate Setting. Set the pin to GND if fast slew rate= 10mV/μs and slow slew rate = 2.5mV/μs is used. 30 OFSA AXG VR Output Voltage Offset Setting. 31 RGNDA Return Ground for Single-Phase AXG VR. This pin is the negative node of the differential remote voltage sensing.

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin No. Pin Name Pin Function 32 FBA Single-Phase AXG VR Feedback. This is the negative input node of the error amplifier. 33 COMPA Single-Phase AXG VR Compensation. This pin is the output node of the error amplifier. 34 ISENAN Negative Current Sense Pin of Single-Phase AXG VR. 35 ISENAP Positive Current Sense Pin of Single-Phase AXG VR. 36 QRSETA Single-Phase AXG VR Quick Response Time Setting. 37 PWMA PWM Output for Single-Phase AXG VR.

38 EN Chip Enable (Active High)

39 VRA_RDY VR Ready Indicator of Single-Phase AXG VR. 40 VR_RDY VR Ready Indicator of Multi-Phase CORE VR. 41 VCC Chip Power. Connect this pin to 5V via an RC filter.

42 OCSETA

Single-Phase AXG VR Over Current Protection Setting. Place a resistive voltage divider between VCC and ground and connect the joint of the voltage divider to the OCSETA pin. The voltage at the OCSET pin determines the over current threshold, ILIMITA.

43 OCSET

Multi-Phase CORE VR Over Current Protection Setting. Place a resistive voltage divider between VCC and ground and connect the joint of the voltage divider to the OCSET pin. The voltage at the OCSET pin determines the over current threshold, I LIMIT. 44 TSENA Thermal Monitor Sense Point of AXG VR. 45 TSEN Thermal Monitor Sense Point of CORE VR. 46 VRHOT Thermal Monitor Output (Active Low).

47 DVDA

Divided Voltage Detection of AXG VR. Connect this pin to a voltage divider from the single-phase power stage input power for input voltage detection.

48 DVD

Divided Voltage Detection of CORE VR. Connect this pin to a voltage divider from the multi-phase power stage input power for input voltage detection. 49 TONSETA Single-Phase AXG VR On-Time Setting. Connect this pin to V IN with one resistor to set ripple size in PWM mode. 50 TONSET Multi-Phase CORE VR On-Time Setting. Connect this pin to V IN with one resistor to set ripple size in PWM mode. 51, 52, 54, 53 PWM [4 :1] PWM Output for CH1, 2, 3 and 4. 55 QRSET Multi-Phase CORE VR Quick Response Time Setting.

56 DVIDA Connect a resistor and a capacitor from this pin to GND to improve

DVID performance. Short this pin to GND if this function is not needed. 57 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Function Block Diagram Control & Protection Logic UVLO SVID XCVR ADC MUX TON Gen+ PWM CMP Soft-Start & Slew Rate Control VSETA ERROR AMP DAC From Control Logic To Protection Logic OCPOVP/UVP/NVP 20 TON Gen PWM CMP+ Soft-Start & Slew Rate Control VSET DAC PHASE Selector VQR_TRIP QR CMP From Control Logic To Protection Logic OCPOVP/UVP/NVP Current Balance OCSET ISEN4P ISEN4N ISEN3N ISEN3P ISEN2P DVD ISEN2N ISEN1N ISEN1P VRHOT ICCMAX COMPA GND VRA_RDY SETINIA VDIO SETINI TMPMAX VCLK ADD ISENAN OCSETA PWM4 PWM3 PWM2 PWM1 QRSETA QRSET ISENAP PWMA EN RGNDA FB COMP DVDA TONSETA RSET TONSET RGND FBA ALERT Current Monitor VSET IMONFB IMON Current Monitor IMONA VSETA IMONFBA Offset GeneratorOFS ICCMAXA TSENA TSEN VCC VR_RDY SUM IBIAS Offset Cancellation Offset Cancellation Offset Generator OFSA 1/20DVIDA 1/20DVID SR_ADDF Set VIDA Fast & Slow Set VID Fast & Slow

©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 1. VR12 VID Code Table

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex Voltage 0 0 1 0 1 0 0 1 2 9 0.450 0 0 1 0 1 0 1 0 2 A 0.455 0 0 1 0 1 0 1 1 2 B 0.460 0 0 1 0 1 1 0 0 2 C 0.465 0 0 1 0 1 1 0 1 2 D 0.470 0 0 1 0 1 1 1 0 2 E 0.475 0 0 1 0 1 1 1 1 2 F 0.480 0 0 1 1 0 0 0 0 3 0 0.485 0 0 1 1 0 0 0 1 3 1 0.490 0 0 1 1 0 0 1 0 3 2 0.495 0 0 1 1 0 0 1 1 3 3 0.500 0 0 1 1 0 1 0 0 3 4 0.505 0 0 1 1 0 1 0 1 3 5 0.510 0 0 1 1 0 1 1 0 3 6 0.515 0 0 1 1 0 1 1 1 3 7 0.520 0 0 1 1 1 0 0 0 3 8 0.525 0 0 1 1 1 0 0 1 3 9 0.530 0 0 1 1 1 0 1 0 3 A 0.535 0 0 1 1 1 0 1 1 3 B 0.540 0 0 1 1 1 1 0 0 3 C 0.545 0 0 1 1 1 1 0 1 3 D 0.550 0 0 1 1 1 1 1 0 3 E 0.555 0 0 1 1 1 1 1 1 3 F 0.560 0 1 0 0 0 0 0 0 4 0 0.565 0 1 0 0 0 0 0 1 4 1 0.570 0 1 0 0 0 0 1 0 4 2 0.575 0 1 0 0 0 0 1 1 4 3 0.580 0 1 0 0 0 1 0 0 4 4 0.585 0 1 0 0 0 1 0 1 4 5 0.590 0 1 0 0 0 1 1 0 4 6 0.595 0 1 0 0 0 1 1 1 4 7 0.600 0 1 0 0 1 0 0 0 4 8 0.605 0 1 0 0 1 0 0 1 4 9 0.610 0 1 0 0 1 0 1 0 4 A 0.615 0 1 0 0 1 0 1 1 4 B 0.620 0 1 0 0 1 1 0 0 4 C 0.625 0 1 0 0 1 1 0 1 4 D 0.630 0 1 0 0 1 1 1 0 4 E 0.635 0 1 0 0 1 1 1 1 4 F 0.640 0 1 0 1 0 0 0 0 5 0 0.645 0 1 0 1 0 0 0 1 5 1 0.650 0 1 0 1 0 0 1 0 5 2 0.655

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex Voltage 0 1 0 1 0 0 1 1 5 3 0.660 0 1 0 1 0 1 0 0 5 4 0.665 0 1 0 1 0 1 0 1 5 5 0.670 0 1 0 1 0 1 1 0 5 6 0.675 0 1 0 1 0 1 1 1 5 7 0.680 0 1 0 1 1 0 0 0 5 8 0.685 0 1 0 1 1 0 0 1 5 9 0.690 0 1 0 1 1 0 1 0 5 A 0.695 0 1 0 1 1 0 1 1 5 B 0.700 0 1 0 1 1 1 0 0 5 C 0.705 0 1 0 1 1 1 0 1 5 D 0.710 0 1 0 1 1 1 1 0 5 E 0.715 0 1 0 1 1 1 1 1 5 F 0.720 0 1 1 0 0 0 0 0 6 0 0.725 0 1 1 0 0 0 0 1 6 1 0.730 0 1 1 0 0 0 1 0 6 2 0.735 0 1 1 0 0 0 1 1 6 3 0.740 0 1 1 0 0 1 0 0 6 4 0.745 0 1 1 0 0 1 0 1 6 5 0.750 0 1 1 0 0 1 1 0 6 6 0.755 0 1 1 0 0 1 1 1 6 7 0.760 0 1 1 0 1 0 0 0 6 8 0.765 0 1 1 0 1 0 0 1 6 9 0.770 0 1 1 0 1 0 1 0 6 A 0.775 0 1 1 0 1 0 1 1 6 B 0.780 0 1 1 0 1 1 0 0 6 C 0.785 0 1 1 0 1 1 0 1 6 D 0.790 0 1 1 0 1 1 1 0 6 E 0.795 0 1 1 0 1 1 1 1 6 F 0.800 0 1 1 1 0 0 0 0 7 0 0.805 0 1 1 1 0 0 0 1 7 1 0.810 0 1 1 1 0 0 1 0 7 2 0.815 0 1 1 1 0 0 1 1 7 3 0.820 0 1 1 1 0 1 0 0 7 4 0.825 0 1 1 1 0 1 0 1 7 5 0.830 0 1 1 1 0 1 1 0 7 6 0.835 0 1 1 1 0 1 1 1 7 7 0.840 0 1 1 1 1 0 0 0 7 8 0.845 0 1 1 1 1 0 0 1 7 9 0.850 0 1 1 1 1 0 1 0 7 A 0.855 0 1 1 1 1 0 1 1 7 B 0.860

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex Voltage 0 1 1 1 1 1 0 0 7 C 0.865 0 1 1 1 1 1 0 1 7 D 0.870 0 1 1 1 1 1 1 0 7 E 0.875 0 1 1 1 1 1 1 1 7 F 0.880 1 0 0 0 0 0 0 0 8 0 0.885 1 0 0 0 0 0 0 1 8 1 0.890 1 0 0 0 0 0 1 0 8 2 0.895 1 0 0 0 0 0 1 1 8 3 0.900 1 0 0 0 0 1 0 0 8 4 0.905 1 0 0 0 0 1 0 1 8 5 0.910 1 0 0 0 0 1 1 0 8 6 0.915 1 0 0 0 0 1 1 1 8 7 0.920 1 0 0 0 1 0 0 0 8 8 0.925 1 0 0 0 1 0 0 1 8 9 0.930 1 0 0 0 1 0 1 0 8 A 0.935 1 0 0 0 1 0 1 1 8 B 0.940 1 0 0 0 1 1 0 0 8 C 0.945 1 0 0 0 1 1 0 1 8 D 0.950 1 0 0 0 1 1 1 0 8 E 0.955 1 0 0 0 1 1 1 1 8 F 0.960 1 0 0 1 0 0 0 0 9 0 0.965 1 0 0 1 0 0 0 1 9 1 0.970 1 0 0 1 0 0 1 0 9 2 0.975 1 0 0 1 0 0 1 1 9 3 0.980 1 0 0 1 0 1 0 0 9 4 0.985 1 0 0 1 0 1 0 1 9 5 0.990 1 0 0 1 0 1 1 0 9 6 0.995 1 0 0 1 0 1 1 1 9 7 1.000 1 0 0 1 1 0 0 0 9 8 1.005 1 0 0 1 1 0 0 1 9 9 1.010 1 0 0 1 1 0 1 0 9 A 1.015 1 0 0 1 1 0 1 1 9 B 1.020 1 0 0 1 1 1 0 0 9 C 1.025 1 0 0 1 1 1 0 1 9 D 1.030 1 0 0 1 1 1 1 0 9 E 1.035 1 0 0 1 1 1 1 1 9 F 1.040 1 0 1 0 0 0 0 0 A 0 1.045 1 0 1 0 0 0 0 1 A 1 1.050 1 0 1 0 0 0 1 0 A 2 1.055 1 0 1 0 0 0 1 1 A 3 1.060 1 0 1 0 0 1 0 0 A 4 1.065

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex Voltage 1 0 1 0 0 1 0 1 A 5 1.070 1 0 1 0 0 1 1 0 A 6 1.075 1 0 1 0 0 1 1 1 A 7 1.080 1 0 1 0 1 0 0 0 A 8 1.085 1 0 1 0 1 0 0 1 A 9 1.090 1 0 1 0 1 0 1 0 A A 1.095 1 0 1 0 1 0 1 1 A B 1.100 1 0 1 0 1 1 0 0 A C 1.105 1 0 1 0 1 1 0 1 A D 1.110 1 0 1 0 1 1 1 0 A E 1.115 1 0 1 0 1 1 1 1 A F 1.120 1 0 1 1 0 0 0 0 B 0 1.125 1 0 1 1 0 0 0 1 B 1 1.130 1 0 1 1 0 0 1 0 B 2 1.135 1 0 1 1 0 0 1 1 B 3 1.140 1 0 1 1 0 1 0 0 B 4 1.145 1 0 1 1 0 1 0 1 B 5 1.150 1 0 1 1 0 1 1 0 B 6 1.155 1 0 1 1 0 1 1 1 B 7 1.160 1 0 1 1 1 0 0 0 B 8 1.165 1 0 1 1 1 0 0 1 B 9 1.170 1 0 1 1 1 0 1 0 B A 1.175 1 0 1 1 1 0 1 1 B B 1.180 1 0 1 1 1 1 0 0 B C 1.185 1 0 1 1 1 1 0 1 B D 1.190 1 0 1 1 1 1 1 0 B E 1.195 1 0 1 1 1 1 1 1 B F 1.200 1 1 0 0 0 0 0 0 C 0 1.205 1 1 0 0 0 0 0 1 C 1 1.210 1 1 0 0 0 0 1 0 C 2 1.215 1 1 0 0 0 0 1 1 C 3 1.220 1 1 0 0 0 1 0 0 C 4 1.225 1 1 0 0 0 1 0 1 C 5 1.230 1 1 0 0 0 1 1 0 C 6 1.235 1 1 0 0 0 1 1 1 C 7 1.240 1 1 0 0 1 0 0 0 C 8 1.245 1 1 0 0 1 0 0 1 C 9 1.250 1 1 0 0 1 0 1 0 C A 1.255 1 1 0 0 1 0 1 1 C B 1.260 1 1 0 0 1 1 0 0 C C 1.265 1 1 0 0 1 1 0 1 C D 1.270

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex Voltage 1 1 0 0 1 1 1 0 C E 1.275 1 1 0 0 1 1 1 1 C F 1.280 1 1 0 1 0 0 0 0 D 0 1.285 1 1 0 1 0 0 0 1 D 1 1.290 1 1 0 1 0 0 1 0 D 2 1.295 1 1 0 1 0 0 1 1 D 3 1.300 1 1 0 1 0 1 0 0 D 4 1.305 1 1 0 1 0 1 0 1 D 5 1.310 1 1 0 1 0 1 1 0 D 6 1.315 1 1 0 1 0 1 1 1 D 7 1.320 1 1 0 1 1 0 0 0 D 8 1.325 1 1 0 1 1 0 0 1 D 9 1.330 1 1 0 1 1 0 1 0 D A 1.335 1 1 0 1 1 0 1 1 D B 1.340 1 1 0 1 1 1 0 0 D C 1.345 1 1 0 1 1 1 0 1 D D 1.350 1 1 0 1 1 1 1 0 D E 1.355 1 1 0 1 1 1 1 1 D F 1.360 1 1 1 0 0 0 0 0 E 0 1.365 1 1 1 0 0 0 0 1 E 1 1.370 1 1 1 0 0 0 1 0 E 2 1.375 1 1 1 0 0 0 1 1 E 3 1.380 1 1 1 0 0 1 0 0 E 4 1.385 1 1 1 0 0 1 0 1 E 5 1.390 1 1 1 0 0 1 1 0 E 6 1.395 1 1 1 0 0 1 1 1 E 7 1.400 1 1 1 0 1 0 0 0 E 8 1.405 1 1 1 0 1 0 0 1 E 9 1.410 1 1 1 0 1 0 1 0 E A 1.415 1 1 1 0 1 0 1 1 E B 1.420 1 1 1 0 1 1 0 0 E C 1.425 1 1 1 0 1 1 0 1 E D 1.430 1 1 1 0 1 1 1 0 E E 1.435 1 1 1 0 1 1 1 1 E F 1.440 1 1 1 1 0 0 0 0 F 0 1.445 1 1 1 1 0 0 0 1 F 1 1.450 1 1 1 1 0 0 1 0 F 2 1.455 1 1 1 1 0 0 1 1 F 3 1.460 1 1 1 1 0 1 0 0 F 4 1.465 1 1 1 1 0 1 0 1 F 5 1.470 1 1 1 1 0 1 1 0 F 6 1.475

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex Voltage 1 1 1 1 0 1 1 1 F 7 1.480 1 1 1 1 1 0 0 0 F 8 1.485 1 1 1 1 1 0 0 1 F 9 1.490 1 1 1 1 1 0 1 0 F A 1.495 1 1 1 1 1 0 1 1 F B 1.500 1 1 1 1 1 1 0 0 F C 1.505 1 1 1 1 1 1 0 1 F D 1.510 1 1 1 1 1 1 1 0 F E 1.515 1 1 1 1 1 1 1 1 F F 1.520

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 2. Serial VID Command

Contents

00h Not Supported N/A N/A N/A 01h SetVID_Fast VID code N/A Set new target VID code, VR jumps to new VID target with controlled default “fast” slew rate 12.5mV/μs. 02h SetVID_Slow VID code N/A Set new target VID code, VR jumps to new VID target with controlled default “slow” slew rate 3.125mV/μs. 03h SetVID_Decay VID code N/A Set new target VID code, VR jumps to new VID target, but doest not control the slew rate. The output voltage decays at a rate proportional to the load current 04h SetPS Byte indicating power states N/A Set power state 05h SetRegADR Pointer of registers in data table N/A Set the pointer of the data register 06h SetRegDAT New data register content N/A Write the contents to the data register 07h GetReg Pointer of registers in data table Specified register Slave returns the contents of the specified register as the payload. 08h 1Fh Not Supported N/A N/A N/A

©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 3. SVID Data and Configuration Register output current, scaled to ICC_MAX = ADC full range.

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1) z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3)

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit Supply Input Supply Current I VCC V EN = 1.05V, Not Switching -- 12 20 mA Shutdown Current I SHDN V EN = 0V -- -- 5 μA Reference and DAC VDAC = 1.000 to 1.520 (No Load, Active Mode) −0.5 0 0.5 %VID VDAC = 0.800 to 1.000 −5 0 5 mV VDAC = 0.500 to 0.800 −8 0 8 mV DAC Accuracy V FB VDAC = 0.250 to 0.500 −8 0 8 mV RGND Current RGND Current IRGND V EN = 1.05V, Not Switching -- -- 500 μA Slew Rate Set VID Slow, SR_ADDF pin = 0V 2.5 3.125 3.75 Dynamic VID Slew Rate SR Set VID Fast, SR_ADDF pin = 0V 10 12.5 15 mV/μs Error Amplifier DC Gain A DC R LOAD = 47kΩ -- 80 -- dB Gain-Bandwidth Product GBW C LOAD = 5pF -- 10 -- MHz Slew Rate SR CLOAD = 10pF (Gain = −4 , RLOAD = 47kΩ, VOUT = 0.5V to −3V) -- 5 -- V/ μs (VCC = 5V, TA = 25 °C, unless otherwise specified)

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Output Voltage Range V COMP R LO AD = 47kΩ 0.3 -- 3.6 V MAX Source/Sink Current I OUTEA V CO MP = 2V -- 250 -- μA Current Sense Amplifier Input Offset Voltage V OSCS −0.75 -- 0.75 mV Impedance at Negative Input R ISENxN 1 -- -- M Ω Impedance at Positive Input R ISENxP 1 -- -- M Ω CORE VR -- 10 -- DC Gain AXG VR -- 20 -- V/V Input Range V ISEN_IN −50 -- 100 mV VISEN Linearity V ISEN_ACC −30mV < VISEN_IN < 50mV −1 -- 1 % tON Setting TONSETx Pin Voltage V TON I RTON = 80μA, VDAC = 0.75V -- 1.07 -- V CCM On-Time Setting t ON I RTON = 80μA, PS0, PS1 275 305 335 ns TONSETx Input Current Range IRTON 25 -- 280 μA On-Time in PS2 (Core only) t ON_PS2 With Respect to PS0 t ON -- 85 -- % Minimum Off-Time t OFF -- 250 -- ns IBIAS IBIAS Pin Voltage V IBIAS R IBIAS = 53.6kΩ 2.09 2.14 2.19 V QRSET Quick Response On-Time Setting tONx_QR VDAC = 0.75V, VQRSET = 1.2V, IRTON = 80μA -- 305 -- ns QRSET Source Current I QRSET Before UVLO -- 80 -- μA VIH V CC − 0.5 -- -- V No Load Line Setting Threshold VIL QRSET Voltage before UVLO, Relative to VCC -- -- V CC − 1.8 V OFS Function OFS Enable/Disable Threshold Voltage VEN_OFS VOFS > VEN_OFS before EN rising 0.7 1.2 -- V VID = 1V , VOFS = 1.83V 1.62 1.63 1.64 VID = 1V , VOFS = 0.9V 0.69 0.7 0.71 Offset Voltage V OUT VID = 1V , VOFS = 1.2V 0.9 1 1.01 V Impedance R OFS 1 -- -- M Ω RSET Setting RSET Voltage V RSET RSET Voltage, V DAC = 1V 0.97 1 1.03 V Zero Current Detection Zero Current Detection Threshold VZCD ISEN1P (AP) − ISEN1N (AN) -- 1 -- mV Protection VUVLO Falling Edge, 100mV Hysteresis 4.04 4.24 4.44 V Under Voltage Lock-out (UVLO)Threshold ΔVUVLO Falling Edge Hysteresis -- 100 -- mV Absolute Over Voltage (OVP) Protection Threshold VOV ABS With respect to VOUT_Max 100 150 200 mV

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol T est Conditions Min Typ Max Unit VDVDx VDVDx Threshold 1.01 1.06 1.11 V Divided Input Voltage Detection (DVDx) Threshold VDVDHYS Falling Edge Hysteresis -- 25 -- mV Delay of UVLO, DVDx t UVLO Rising Above Threshold -- 3 -- μs Delay of OVP t OV VISENx N Rising Above Threshold, Pin OFS Disable -- 1 -- μs Under Voltage Protection (UVP) Threshold VUV Measured at ISEN1N/ISENAN with respect to unloaded output voltage (UOV) (for 0.8 < UOV < 1.52) −350 −300 −250 mV Delay of UVP t UVP VISENxN Falling below Threshold -- 3 -- μs Negative Voltage Protection Threshold VNVP After OVP, Falling Edge −100 −50 -- mV Delay of NVP t NVP VISENxN Falling below Threshold -- 1 -- μs GILIMIT = VOCSET / (VISENxP − VISENxN), VOCSET = 2.400V, (VISENxP − VISENxN) = 50mV 43.2 48 52.8 Current Limit Gain Setting (per phase) GILIMIT GILIMITA = VOCSETA / (VISENAP − VISENAN), VOCSETA = 2.4V, (VISENAP − VISENAN) = 50mV 43.2 48 52.8 V/V Current Limit Latch Counter (per phase) NILIM Times of UGATE Rising -- 15 -- Times Logic-High V IH 0.7 -- -- EN Input Threshold Voltage Logic-Low V IL -- -- 0.3 V Logic Inputs EN Hysteresis V ENHYS -- 30 -- mV Leakage Current of EN I EN −1 -- 1 μA Logic-High V IH 0.665 -- -- VCLK, VDIO Input Threshold Voltage Logic-Low V IL -- -- 0.367 V VCLK,VDIO Hysteresis V HYS -- 70 -- mV Leakage Current of ADD,VCLK,VDIO ILEAK_IN −1 -- 1 μA ALERT ALERT Low Voltage V ALERT IALERT = 10mA -- -- 0.13 V Power On Sequence SVID Ready Delay Time t A From EN = high until VR Controller is ready to accept SVID command -- -- 2 ms VR_RDY Trip Threshold V TH_VR_RDY V ISENxN − 1st VDAC -- −100 -- mV VR_RDY Low Voltage V VR_RDY I VR_RDY = 4mA -- -- 0.4 V VR_RDY Delay t VR_RDY VISENxN = VINITIAL to VR_RDY High -- 100 -- μs

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Thermal Throttling VRHOT Output Voltage V VRHOT I VRHOT = 10mA -- -- 0.13 V Current Monitor Current Monitor Maximum Output Voltage in Operating Range VIMON VDAC = 1V, VFB − VCC_SENSE = 100mV, RIMONFB = 10kΩ, RIMON = 330kΩ 3.2 3.3 3.4 V High Impedance Output PWMx, ALERT, VRx_RDY , VRHOT ILEAK_OUT −1 -- 1 μA PWM Driving Capability PWM Source Resistor R PWM_SOURCE -- 30 -- Ω PWM Sink Resistor R PWM_SINK -- 15 -- Ω DVID, DVIDA, ICCMAX, ICCMAXA, and TMPMAX Pin Current Current Sourcing Out from DVIDx Pin to GND IDVIDx During dynamic VID fast event 6 8 10 μA Current Sinking In from 5V to ICCMAX Pin IICCMAX After VR_RDY -- 16 -- μA Current Sourcing Out from ICCMAXA Pin to GND IICCMAXA After VRA_RDY -- 128 -- μA Current Sinking In from 5V to TMPMAX Pin ITMPMAX After VR_RDY -- 16 -- μA DVID and DVIDA Maximum Voltage Maximum Allowable Voltage at DVIDx Pin VDVIDx_MAX During Dynamic VID Event -- -- 2 V SVID SVID Frequency fSVID 5 25 26.25 MHz SVID Clock to Data Delay tCO 4 -- 8.3 ns Setup Time of VDIO tSU 7 -- -- ns Hold Time of VDIO tHLD 14 -- -- ns VINITIAL Setting VSETINI0 For VINITIAL = 0V 0 -- 8 VSETINI0_9 For VINITIAL = 0.9V 17 -- 20 VSETINI1_0 For VINITIAL = 1V 32.5 -- 42.5 VSETINI1_1 For VINITIAL = 1.1V 57.5 -- 67.5 SETINIx Threshold Voltage VSETINI1_5 For VINITIAL = 1.5V 82.5 -- 100 %VCC ADD Threshold Logic-Low V IL Set SVID address 0000 0001 -- -- 0.35 Logic-Medium V IM Set SVID address 0010 001 1 0.7 -- 3 ADD Input Threshold Voltage Logic-High V IH Set SVID address 0100 0101 V CC − 0.2 -- -- V

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 °C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit ADC CICCMAX1 V ICCMAX = 12.74%VCC 29 32 35 CICCMAX2 V ICCMAX = 25.284%VCC 61 64 67 Digital Code of ICCMAX CICCMAX3 V ICCMAX = 50.372%VCC 125 128 131 decimal CICCMAXA1 V ICCMAX = 3.332%VCC 5 8 1 1 CICCMAXA2 V ICCMAX = 6.468%VCC 13 16 19 Digital Code of ICCMAXA CICCMAXA3 V ICCMAX = 12.74%VCC 29 32 35 decimal CTMPMAX1 V ICCMAX = 33.516%VCC 82 85 88 CTMPMAX2 V ICCMAX = 39.396%VCC 97 100 103 Digital Code of TMPMAX CTMPMAX3 V ICCMAX = 49.196%VCC 122 125 128 decimal COCR1 V IM ON(A) = 3.3V 252 255 255 COCR2 V IM ON(A) = 2.208V 167 170 173 Digital Code of Output Current Report COCR3 V IM ON(A) = 1.107V 82 85 88 decimal Updating Period of Output Current Report tOCR -- -- 500 μs Tolerance Band of Temperature_Zone Trip Points b7, b6, b5 V TSEN 20 -- 20 mV Updating Period of Temperature_Zone tTZ -- -- 4 ms

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics CORE VR Power On Time (100 μs/Div) VCORE (1V/Div) VCORE = 1.1V, ILOAD = 5A VR_RDY (2V/Div) VDIO (1V/Div) ALERT (2V/Div) CORE VR Power Off from EN Time (1ms/Div) VCORE (1V/Div) VR_RDY (2V/Div) EN (2V/Div) PWM1 (5V/Div) VCORE = 1.1V, ILOAD = 5A CORE VR Dynamic VID Up Time (40 μs/Div) VCORE (500mV/Div) VCLK (1V/Div) ALERT (2V/Div) VDIO (2V/Div) VCORE = 0.7V up to 1.2V, ILOAD = 20A Fast Slew Rate CORE VR Dynamic VID Down Time (100 μs/Div) VCLK (1V/Div) ALERT (2V/Div) VDIO (2V/Div) Slow Slew Rate, VCORE (500mV/Div) VCORE = 1.2V down to 0.7V, ILOAD = 20A CORE VR Dynamic VID Down Time (40 μs/Div) VCLK (1V/Div) ALERT (2V/Div) VDIO (2V/Div) VCORE = 1.2V down to 0.7V, ILOAD = 20A Fast Slew Rate, VCORE (500mV/Div) CORE VR Dynamic VID Up Time (100 μs/Div) VCLK (1V/Div) ALERT (2V/Div) VDIO (2V/Div) VCORE = 0.7V up to 1.2V, ILOAD = 20A Slow Slew Rate, VCORE (500mV/Div)

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VIMON vs. Load Current 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 0 1 02 03 04 05 06 07 08 09 0 1 0 0 Load Current (A) VIMON (V) CORE VR Load Transient Response Time (100 μs/Div) VCORE (50mV/Div) VCORE = 1.1V, fLOAD = 300Hz, ILOAD = 5A to 70A 70A ILOAD CORE VR Load Transient Response Time (100 μs/Div) VCORE = 1.1V, fLOAD = 300Hz, ILOAD = 70A to 5A 70A ILOAD VCORE (50mV/Div) CORE VR OCP Time (100 μs/Div) VCORE = 1.1V VCORE (2V/Div) VR_RDY (2V/Div) PWM1 (5V/Div) ILOAD (100A/Div) CORE VR OVP & NVP Time (40 μs/Div) VCORE (1V/Div) VR_RDY (1V/Div) PWM1 (5V/Div) VCORE = 1.1V CORE VR UVP Time (1ms/Div) VCORE = 1.1V, ILOAD = 1A VCORE (1V/Div) VR_RDY (1V/Div) PWM1 (5V/Div)

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. AXG VR Dynamic VID Down Time (100 μs/Div) VAXG = 1.2V down to 0.7V, ILOAD = 20A VAXG (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) Slow Slew Rate, AXG VR Dynamic VID Down Time (40 μs/Div) VAXG = 1.2V down to 0.7V, ILOAD = 20A VAXG (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) Fast Slew Rate, AXG VR Dynamic VID Up Time (100 μs/Div) VAXG = 0.7V up to 1.2V, ILOAD = 20A VAXG (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) Slow Slew Rate AXG VR Dynamic VID Up Time (40 μs/Div) VAXG (500mV/Div) VCLK (2V/Div) VDIO (2V/Div) ALERT (2V/Div) VAXG = 0.7V up to 1.2V, ILOAD = 20A Fast Slew Rate AXG VR Power Off from EN VAXG (1V/Div) VRA_RDY (1V/Div) EN (1V/Div) PWMA (10V/Div) VAXG = 1.1V, ILOAD = 5A Time (1ms/Div) AXG VR Power On VAXG = 1.1V, ILOAD = 5A VAXG (1V/Div) VDIO (1V/Div) ALERT (1V/Div) VRA_RDY (2V/Div) Time (100 μs/Div)

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VIMONA vs. Load Current 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 0 3 6 9 12 15 18 21 24 27 30 Load Current (A) VIMONA (V) AXG VR Load Transient Response Time (100 μs/Div) VAXG (50mV/Div) VAXG = 1.1V, fLOAD = 300Hz, ILOAD = 2A to 22A 22A ILOAD AXG VR Load Transient Response Time (100 μs/Div) VAXG (50mV/Div) 22A ILOAD VAXG = 1.1V, fLOAD = 300Hz, ILOAD = 22A to 2A AXG VR OCP Time (100 μs/Div) VAXG = 1.1V VAXG (2V/Div) VRA_RDY (2V/Div) PWMA (10V/Div) ILOAD (50A/Div) AXG VR OVP & NVP Time (100 μs/Div) VAXG (1V/Div) VRA_RDY (1V/Div) PWMA (5V/Div) VAXG = 1.1V AXG VR UVP Time (1ms/Div) VAXG = 1.1V, ILOAD = 1A VAXG (1V/Div) VRA_RDY (1V/Div) PWMA (5V/Div)

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Thermal Monitoring Time (400 μs/Div) TSEN from 1.7V Sweep to 1.9V, ILOAD = 0A TSEN (100mV/Div) VRHOT (1V/Div)

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.

Application Information

The RT8859M is a CPU power controller which includes two voltage rails : a 4/3/2/1 phase synchronous buck controller, the CORE VR, and a single phase buck controller, the AXG VR. The RT8859M is compliant with Intel VR12/IMVP7 voltage regulator specification to fulfill Intel's CPU power supply requirements of both CORE and AXG voltage rails. A Serial VID (SVID) interface is built-in in the RT8859M to communicate with Intel VR12/IMVP7 compliant CPU. The RT8859M adopts G-NAVP TM (Green Native AVP), which is Richtek's proprietary topology derived from finite DC gain compensator with current mode control, making it an easy setting PWM controller, meeting all Intel CPU requirements of AVP (Active Voltage Positioning). The load line can be easily programmed by setting the DC gain of the error amplifier. The RT8859M has fast transient response due to the G-NAVP TM commanding variable switching frequency. Based on the G-NAVPTM topology, the RT8859M also features a quick response mechanism for optimized AVP performance during load transient. The G-NAVP TM topology also represents a high efficiency system with green power concept. With the G-NAVP TM topology, the RT8859M becomes a green power controller with high efficiency under heavy load, light load, and very light load conditions. The RT8859M supports mode transition function with various operating states, including multi-phase, single phase and diode emulation modes. These different operating states allow the overall power control system to have the lowest power loss. By utilizing the G-NAVP TM topology, the operating frequency of the RT8859M varies with VID, load, and input voltage to further enhance the efficiency even in CCM. The built-in high accuracy DAC converts the SVID code ranging from 0.25V to 1.52V with 5mV per step. The RT8859M supports VID on-the-fly function with three different slew rates : Fast, Slow and Decay. The RT8859M also builds in a high accuracy ADC for some platform setting functions, such as no-load offset or over-current level. The controller supports both DCR and sense resistor current sensing. The RT8859M provides power VR ready signals for both CORE VR and AXG VR. It also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and under voltage lockout. The RT8859M is available in a WQFN- 56L 7x7 small footprint package. General Loop Functions VR Rail Addressing and Slew rate Setting The voltage level at the ADD pin defines the VR addresses of the RT8859M. User can also flip the VR address by properly setting the voltage on SR_ADDF pin. There are three valid voltage levels for ADD pin : VCC (5V), floating, and GND. Connecting the ADD pin to one of these three voltage levels can set the addresses of both CORE VR and AXG VR according to the following table. The All Call address, 1111, 1110, can only be used with SetVID or SetPS commands. Address Flip AD D Level VR1 (CORE) Address VR1 (AXG) Address VCC 0100 0101 Floating 0010 0011 No GND 0000 0001 VCC 0101 0100 Floating 0011 0010 Yes GND 0001 0000 The RT8859M can also program the dynamic VID slew rate by setting the SR_ADDF pin. After POR, the RT8859M will detect the voltage level on the SR_ADDF pin and latch the status of the address and the dynamic VID slew rate. Below is the setting table of SR_ADDF. The recommended voltage tolerance i s (recommended voltage ±25mV). Make sure the voltage divider at SR_ADDF pin uses the same VCC as pin 41 (VCC).

DS8859M-07 January 2014 www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Recommended SR_ADDF Voltage (if VCC = 5V) Address Flipped VR0 Fast Slew Rate (mV/μs) VR0 Slow Slew Rate (mV/μs) VR1 Fast Slew Rate (mV/μs) VR1 Slow Slew Rate (mV/μs) 5 Y es 10 2.5 10 2.5 4.766 Y es 10 2.5 10 5 4.609 Y es 10 5 10 2.5

4.453 Y es 10 5 10 5

4.297 Y es 15 3.75 10 2.5 4.141 Y es 15 3.75 10 5 3.984 Y es 15 7.5 10 2.5 3.828 Y es 15 7.5 10 5 3.672 Y es 20 5 10 2.5

1.797 No 20 10 10 5

1.641 No 20 10 10 2.5

1.484 No 20 5 10 5

1.328 No 20 5 10 2.5 1.172 No 15 7.5 10 5 1.016 No 15 7.5 10 2.5 0.859 No 15 3.75 10 5 0.703 No 15 3.75 10 2.5

0.547 No 10 5 10 5

0.391 No 10 5 10 2.5 0.234 No 10 2.5 10 5 0 No 10 2.5 10 2.5

©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. messages will only be utilized by the CPU. platform users through the SETINI and the SETINIA pins.

1. Recommended voltage setting at the SETINIA pin is

zero) immediately after both POR = high and EN= high. Table 4. SETINI (SETINIA) Pin Setting

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 4 (a). Power Sequence for the RT8859M (VINITIAL = VINITIALA = 0V) Figure 4 (b). Power Sequence for the RT8859M (VINITIAL ≠ 0V, VINITIALA ≠ 0V) EN DVD SVID Valid xxXX VR_RDY 100µs POR 0.2V PWM MAX Phases MAX PhasesHi-Z 0.2V SVID defined

1 Phase CCM

100µs VRA_RDY (DVDA) VOUT, CORE VOUT, AXG EN DVD SVID Valid xxXX VOUT, CORE VR_RDY POR 0.2V PWM MAX Phases 0.2V SVID defined SVID definedPWMA VRA_RDY 100µs 100µs VOUT, AXG VINITIALA

©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. 80μA x 1kΩ/2) before POR and 2.5V (5V/2) after POR. resistive feedback components for the error amplifier gain. Next, C1 and C2 must be calculated for the compensation. over the widest possible frequency range. Figure 7. CORE VR : Loop Setting with Temperature where 0.00393 is the temperature coefficient of copper.

11 T+273 298

thermistor placed in the feedback path.

©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. switching frequency to filter the switching related noise. of the CORE VR, and VDAC is the DAC voltage. inductor DCR, and RDROOP is the load line setting. Figure 8. CORE VR : On-Time Setting with RC Filter On-time translates only roughly to switching frequencies. are influenced by switching delays in external HS-FET. period equal to the HS-FET rising dead time.

©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 9. CORE VR : Lossless Inductor Sensing to be tuned on board by examining the transient voltage. dip and the recovery is too fast causing a ring back. can have better accuracy, but the efficiency is a trade-off. inductor DCR sensing method. operation) and PS2 (single phase DEM operation). compatibility with PS1 operation mode. current sense amplifier of any phase.

©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. monitors the output voltage via the ISEN1N pin after POR. exceeds “V(MAX) + 150mV”, OVP is triggered and latched. 0.9V before power up, OVP will trigger at “VMAX +850mV”. CORE VR while the high side MOSFETs still remains off. the OVP latch will restart to turn on all low side MOSFETs. Figure 15. OCP Setting with Temperature Compensation continuous cycles, the OCP latch counter will be reset. will also enter soft shut down sequence. OCP setting with temperature compensation.

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. where C is the capacitance of output capacitor, and RC is the ESR of output capacitor. C2 can be calculated as below : The zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. Such that, = πP C 1f 2 x x C x R (46) = CC x RC2 R2 (47) (48)() ° +π NTC, 25 C SW 1C1 R1 b R1 a / /R x x f SENSE, HOT NTC, HOT NTC, COLD SENSE, COLD SENSE, HOT SENSE, COLD R1b R x (R1 a / /R ) (R1 a / /R )R R1 R (45) The standard formula for the resistance of NTC thermistor as a function of temperature is given by : ( ) ( ){ } NTC, T C 25 CRR e (42) where R25°C is the thermistor's nominal resistance at room temperature, β is the thermistor's material constant in Kelvins, and T is the thermistor actual temperature in Celsius. To calculate DCR value at different temperatures, use the equation below : DCR where 0.00393 is the temperature coefficient of copper. For a given NTC thermistor, solving equation (41) at room temperature ( 25°C) yields R2 = AV, 25°C x (R1b + R1a // RNTC, 25°C) (44) where AV, 25°C is the error amplifier gain at room temperature and can be obtained from equation (39). R 1b can be obtained by substituting (44) to (40), Droop Disable The AXG VR's droop function can be enabled or disabled with different connections of the QRSETA pin. The connection of the QRSETA pin is usually a voltage divider TON Setting High frequency operation optimizes the application by allowing smaller component size, but with the trade-off of efficiency due to higher switching losses. This may be acceptable in ultra portable devices where the load currents Usually, R1a is set to equal RNTC (25°C) and R1b is selected to linearize the NTC's temperature characteristic. For a given NTC, the design procedure is to get R 1b and R2 first, and then C1 and C2 next. According to equation (39), to compensate the temperature variations of the sense resistor, the error amplifier gain (A V) should have the same temperature coefficient as RSENSE. Hence : From (37), Av can be obtained at any temperature (T°C) as : V, HOT SENSE, HOT V, COLD SENSE, COLD AR AR = (40) V, T C NTC, T C R2A R1a // R R1b° = + (41) circuit which is described later in the Quick Response section. Before POR, the RT8859M will source 80 μA current from the QRSETA pin to the external voltage divider to determine the voltage level while the RT8859M is still not powered on. Before POR, if the voltage at the QRSETA pin is higher than 4.5V, the AXG VR will operate in droop- enabled mode. If the voltage is lower than 3.2V, the AXG VR will operate without droop function, which means at the DC level of DAC voltage. For example, a 5V voltage divided by two 1kΩ resistors connected to the QRSETA pin generates 2.54V (5V/2 + 80μA x 1kΩ/2) before POR and 2.5V (5V/2) after POR. Loop Compensation Optimized compensation of the AXG VR allows for best possible load step response of the regulator's output. A type-I compensator with one pole and one zero is adequate for a proper compensation. Figure 17 shows the compensation circuit. Prior design procedure shows how to select the resistive feedback components for the error amplifier gain. Next, C1 and C2 must be calculated for the compensation. The target is to achieve constant resistive output impedance over the widest possible frequency range. The pole frequency of the compensator must be set to compensate the output capacitor ESR zero :

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Considering the inductance tolerance, the resistor RX has to be tuned on board by examining the transient voltage. If the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, R X is chosen too small. Vice versa, if the resistance is too large the output voltage transient has only a small initial dip and the recovery becomes too fast, causing a ring back to occur. Using current sense resistor in series with the inductor can have better accuracy, but at the expense of efficiency. Considering the equivalent inductance (LESL) of the current sense resistor, an RC filter is recommended. The RC filter calculation method is similar to the above mentioned inductor DCR sensing method. No Load Offset (SVID & Platform) The AXG VR features no load offset function which provides the possibility of wide range positive offset of output voltage. The no load offset function can be implemented through the SVID interface or OFSA pin. Users can disable pin offset function by simply connecting OFSA pin to GND. The RT8859M will latch the OFSA status after POR. If pin offset function is enabled, users can decide either to disable SVID OFS or not by selecting proper resistor values of TMPMAX pin. After receiving a valid VID, the RT8859M sinks in 16μA from TMPMAX pin. The voltage on TMPMAX is For example, supplying 1.3V at OFSA pin will achieve 100mV offset at the out put. Connecting a filter capacitor =− μTMPMAX CC R2V x V 16 A (R1 // R2)R1 + R2 If VTMPMAX <1V, then the output voltage is OUT DAC LOAD DROOP PIN OFSVV I x R + V −=− If VTMPMAX >1V, then the output voltage is =−OUT DAC LOAD DROOP PIN OFS SVID OFS VV I x R + V + V The pin offset voltage is set by supplying a voltage into OFSA pin. The linear range of offset pin voltage is from 0.9V to 1.83V. The pin offset voltage can be calculated as below : − −PIN OFSA OFSAV = V 1.2V between the OFSA pin and GND is necessary. Designers can design the offset slew rate by properly setting the filter bandwidth. Operation Mode Transition The RT8859M supports operation mode transition function at AXG VR for the SetPS command of Intel VR12/IMVP7 CPU. The default operation mode of the AXG VR is PS0, which is CCM operation. Other operation mode includes PS2 (single phase DEM operation). After receiving SetPS command, the AXG VR will immediately change to the new operation state. When the AXG VR receives SetPS command of PS2 operation mode, the AXG VR operates as a single phase DCM controller and diode emulation operation is activated. Therefore, an external driver which supports tri-state shutdown is required for compatibility with PS2 operation state. If the AXG VR receives dynamic VID change command (SetVID), the AXG VR will automatically enter PS0 operation mode. After V OUT, AXG reaches target voltage, the AXG VR will stay at PS0 state and ignore former SetPS command. Only by resending SetPS command after SetVID command will the AXG VR be forced into PS2 operation state again. Dynamic VID Enhancement During a dynamic VID event, the charging (dynamic VID up) or discharging (dynamic VID down) current causes unwanted load-line effect which degrades the settling time performance. The DVIDA pin can be used to compensate the load-line effect, so that the output voltage can settle to the target value more quickly. During a dynamic VID up event, the RT8859M sources out a current (I DVIDA) to DVIDA pin. The voltage on DVIDA pin is added to DAC during DVID rising to enhance the dynamic VID performance. Connecting a capacitor in parallel with a resistor to DVIDA pin is recommended. I DVIDA is 8 μA during a SetVID_Fast event. If it is a SetVID_Slow event, IDVIDA automatically shrinks to 2μA (if slow slew rate is 0.25x fast slew rate) or 4 μA(if slow slew rate is 0.5x fast slew rate). This function is null during a dynamic VID down event. (54) (55) (56) (57)

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. (72)−=× IN OUTMIN ON Ripple(MAX) VVLT I where tON is the UGATE turn-on period. Higher inductance yields in less ripple current and hence higher efficiency. The downside is a slower transient response of the power stage to load transients. This might increase the need for more output capacitors, thus driving up the cost. Select a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must be large enough not to be saturated at the peak inductor current. Output Capacitor Selection Output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output capacitors are typically used : bulk capacitors closely located next to the inductors, and ceramic output capacitors in close proximity to the load. Latter ones are for mid-frequency decoupling with especially small ESR and ESL values, while the bulk capacitors have to provide enough stored energy to overcome the low frequency bandwidth gap between the regulator and the CPU. (69) OC1 b OC2 EQU, HOT EQU, COLD R (1 ) R R R (1 ) α− × +α× − where SENSE, HOT 25 C HOT SENSE, COLD 25 C COLD R DCR [1 0.00393 (T 25)] R DCR [1 0.00393 (T 25)] (70) REQU, T°C = ROC1a // RNTC, T°C (71) Over Voltage Protection (OVP) The over voltage protection circuit of the AXG VR monitors the output voltage via the ISENAN pin after POR. The supported maximum operating VID of the VR (V (MAX) ) is stored in the VOUT_Max register. Once VISENAN exceeds “V (MAX) + 150mV”, OVP is triggered and latched. The AXG VR will try to turn on low side MOSFETs and turn off high side MOSFETs of the AXG VR to protect the CPU. When OVP is triggered by the AXG VR, the CORE VR will also enter shut down sequence. A 1μs delay is used in OVP detection circuit to prevent false trigger. Note that if OFSA pin is higher than 0.9V before power up, OVP would trigger when “V MAX + 850mV”. Negative Voltage Protection (NVP) During OVP latch state, the AXG VR also monitors the ISENAN pin for negative voltage protection. Since the OVP latch will continuously turn on all low side MOSFETs of the AXG VR, the AXG VR may suffer negative output voltage. As a consequence, when the ISENAN voltage drops below −0.05V after triggering OVP, the AXG VR will trigger NVP to turn off all low side MOSFETs of the AXG VR while the high side MOSFETs still remaining off. After triggering NVP, if the output voltage rises above 0V, the OVP latch will restart to turn on all low side MOSFETs. Therefore, the output voltage may bounce between 0V and −0.05V due to OVP latch and NVP triggering. The NVP function will be active only after OVP is triggered. A 1μs delay is used in NVP detection circuit to prevent false trigger. Under Voltage Protection (UVP) The AXG VR implements under voltage protection of VOUT, AXG. If VFBA is less than the internal reference by 300mV, the AXG VR will trigger UVP latch. The UVP latch will turn off both high side and low side MOSFETs. When UVP is triggered by the AXG VR, the CORE V R will also enter soft shut down sequence. A 3 μs delay is used in UVP detection circuit to prevent false trigger. If platform OFSA function is enabled (OFSA pin not connected to GND), the UVP function will be disabled. Under Voltage Lock Out (UVLO) During normal operation, if the voltage at the VCC or DVD pin drops below POR threshold, the AXG VR will trigger UVLO. The UVLO protection forces all high side MOSFETs and low side MOSFETs off by shutting down internal PWM logic driver. A 3μs delay is used in UVLO detection circuit to prevent false trigger. Inductor Selection The switching frequency and ripple current determine the inductor value as follows :

©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. with their ground terminals flushed against one another. is essential for high efficiency. sense connections to guarantee current sense accuracy. paralleled back to the controller. Figure 26. Derating Curve of Maximum Power on the maximum power dissipation.

DS8859M-07 January 2014www.richtek.com ©Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 6.900 7.100 0.272 0.280 D2 5.150 5.250 0.203 0.207 E 6.900 7.100 0.272 0.280 E2 5.150 5.250 0.203 0.207 e 0.400 0.016 L 0.350 0.450 0.014 0.018 W-Type 56L QFN 7x7 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2

DS8859M-07 January 2014 www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries.