RT8816A RICHTEK | Alldatasheet
Document overview
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Technical content
Features
Dual-Phase PWM Controller Power State Indicator 1P-CCM/2P-CCM/1P-DEM/2P-DEM Two Embedded MOSFET Drivers and Embedded Switching Boot Diode Support 1.8V PWM-VID Interface External Reference Input Control PWM-VID Dynamic Voltage Control Dynamic Phase Number Control Lossless RDS(ON) Current Sensing for Current Balance Internal/External Soft-Start Adjustable Current Limit Threshold Adjustable Switching Frequency Shoot Through Protection and Short Pulse Free Technology Support an Ultra-Low Output Voltage as Standby Voltage Power Good Indicator (EN to PG high = 500μμμμμs)
Applications
CPU/GPU Core Power Supply Desktop PC Memory, VTT Power Chipset/RAM Power Supply Generic DC-DC Power Regulator
Ordering Information
Note : Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Package Type QW : WQFN-20L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) RT8816A Marking Information 7J=YM DNN 7J= : Product Code YMDNN : Date Code Pin Configuration (TOP VIEW) WQFN-20L 3x3 PSI EN BOOT1 UGATE1 BOOT2 UGATE2 OCSET/SS PGOOD REFADJ REFIN TON PHASE1 LGATE1 LGATE2 PVCC 17181920 9876 GND 115 PHASE2 VID VSNS RGND VREF
DS8816A-07 March 2022www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 1 BOOT1 Bootstrap supply for PWM1. This pin powers the high-side MOSFET driver. 2 UGATE1 High-side gate driver of PWM1. This pin provides the gate drive for the converter's high-side MOSFET. Connect this pin to the gate of high-side MOSFET. 3 EN Enable control input. Active high input. When PVCC POR, the input voltage must not be over PVCC.
4 PSI
Power saving interface. When the voltage is pulled below 0.4V, the device operates into 1 phase DEM. When the voltage is between 0.7V to 0.88V, the device operates into 1 phase forced CCM. When the voltage is between 1.08V to 1.35V, the device operates into 2 phase DEM. When the voltage is between 1.6V to 5.5V, the device operates into 2 phase forced CCM. 5 VID Programming output voltage control input. Refer to PWM-VID Dynamic Voltage Control. 6 REFADJ Reference adjustment output. Refer to PWM-VID Dynamic Voltage Control. 7 REFIN External reference input. 8 VREF Reference voltage output. This is a high precision voltage reference (2V) from the VREF pin to RGND pin. 9 TON On-time/switching frequency adjustment input. Connecting a 100pF ceramic capacitor between CTON and ground is optional for noise immunity enhancement. 10 RGND Negative remote sense input. Connect this pin to the ground of output load. 11 VSNS Positive remote sense input. Connect this pin to the positive terminal of output load.
12 OCSET/SS
Current limit setting. Connect a resistor from OCSET/SS to GND to set the current limit threshold. The external soft start time also can be set through by connecting a capacitor from OCSET/SS pin to GND. 13 PGOOD Power good indicator output. Active high open-drain output. 14 UGATE2 High-side gate driver of PWM2. This pin provides the gate drive for the converter's high-side MOSFET. Connect this pin to the gate of high-side MOSFET. 15 BOOT2 Bootstrap supply for PWM2. This pin powers the high-side MOSFET driver.
16 PHASE2
Switch node for PWM2. This pin is return node of the high-side driver of PWM 2. Connect this pin to the source of high-side MOSFET together with the drain of low-side MOSFET and the inductor. 17 LGATE2 Low-side gate driver of PWM2. This pin provides the gate drive for the converter's low-side MOSFET. Connect this pin to the gate of low-side MOSFET. 18 PVCC Supply voltage input. Connect this pin to a 5V bias supply. Place a high quality bypass capacitor from this pin to GND. 19 LGATE1 Low-side gate driver of PWM1. This pin provides the gate drive for the converter's low-side MOSFET. Connect this pin to the gate of low-side MOSFET.
20 PHASE1
Switch node for PWM1. This pin is return node of the high-side driver of PWM 1. Connect this pin to the Source of high-side MOSFET together with the drain of low-side MOSFET and the inductor. (Exposed Pad) GND Ground. The Exposed pad should be soldered to a large PCB and connected to GND for maximum thermal dissipation.
DS8816A-07 March 2022 www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram LGATE2 PHASE2 UGATE2 BOOT2 LGATE1 PVCC PHASE1 UGATE1 BOOT1 VSNS TON REFIN VREF EN Driver Logic Boot-Phase Detection 2 Boot-Phase Detection 1 S/H S/H Current Balance Control & Protection Logic TON Gen 1 TON Gen 2 PWM1 PWM2 To Power On Reset VIN Detection To Protection Logic PWM CMP To Driver Logic To Power On Reset Enable Logic 40% REFIN Power On Reset & Central Logic Reference Output Gen. Soft-Start & Slew Rate Control UV 150% REFIN or 2V Current Limit VB VB PGOOD VID PSI REFADJ Mode Select GM GM RGND OCSET/SS OV X(-1/12) ICS 10µ ICS 40µ To SSOK
DS8816A-07 March 2022www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Operation The RT8816A is a dual-phase synchronous Buck PWM controller with integrated drivers which are optimized for high performance graphic microprocessor and computer applications. The IC integrates a COT (Constant-On-Time) PWM controller with two MOSFET drivers, as well as output current monitoring and protection functions. Referring to the function block diagram of TON Genx, the synchronous UGATE driver is turned on at the beginning of each cycle. After the internal one-shot timer expires, the UGATE driver is turned off. The pulse width of this one-shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range and output voltage. Another one-shot sets a minimum off-time. The RT8816A also features a PWM-VID dynamic voltage control circuit driven by the pulse width modulation method. This circuit reduces the device pin count and enables a wide dynamic voltage range. Soft-Start (SS) For soft-start function, an internal current source charges an internal capacitor to build the soft-start ramp voltage. The output voltage will track the internal ramp voltage during soft-start interval. PGOOD The power good output is an open-drain architecture. When the soft-start is finished, the PGOOD open-drain output is high impedance. Current Balance The RT8816A implements internal current balance mechanism in the current loop. The RT8816A senses per phase current and compares it with the average current. If the sensed current of any particular phase is higher than average current, the on-time of this phase is adjusted to be shorter. Current Limit The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle. Thus, the current to the load exceeds average output inductor current, the output voltage falls and eventually crosses the under-voltage protection threshold, inducing IC shutdown. Over-Voltage Protection (OVP) & Under-Voltage Protection (UVP) The output voltage is continuously monitored for over- voltage and under-voltage protection. When the output voltage exceeds its set voltage threshold (If V REFIN ≤ 1.33V, OV = 2V, or VREFIN > 1.33V, OV = 1.5 x VREFIN), UGATE goes low and LGATE is forced high; when it is less than 40% of its set voltage, under voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. The controller is latched until PVCC is re-supplied and exceeds the POR rising threshold voltage or EN is reset.
DS8816A-07 March 2022 www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Absolute Maximum Ratings (Note 1) BOOTx to PHASEx BOOTx to GND PHASEx to GND UGATEx to GND UGATEx to PHASEx LGATEx to GND Power Dissipation, PD @ TA = 25°C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)
DS8816A-07 March 2022www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit PWM Controller PVCC Supply Voltage V PVCC 4.5 -- 5.5 V PVCC Supply Current I SUPPLY VEN = 3.3V, 1phase DEM mode, not switching, VREF external R = 40k -- 0.4 -- mA PVCC Shutdown Current I SHDN V EN = 0V -- -- 10 A PVCC POR Threshold 3.8 4.1 4.4 V POR Hysteresis -- 0.3 -- V Switching Frequency f SW R TON = 500k (Note 5) 270 300 330 kHz Minimum On-Time t ON(MIN) -- 70 -- ns Minimum Off-Time t OFF(MIN) -- 300 -- ns EN Input Voltage EN Input Voltage Logic-High V EN_H 1.2 -- 5.5 V Logic-Low V EN_L -- -- 0.55 Mode Decision 2 Phase CCM V PSI 1.6 1.8 5.5 V 2 Phase DEM V PSI 1.08 1.2 1.35 V 1 Phase CCM V PSI 0.7 0.8 0.88 V 1 Phase DEM V PSI -- 0 0.4 V PWM-VID Input Voltage for 1.8V GPIO Setting PWM-VID Input Voltage Logic H VPWM-VID_H 1.2 -- -- V PWM-VID Input Voltage Logic L VPWM-VID_L -- -- 0.6 V PWM-VID Tri-state Voltage V PWM-VID_Tri 0.8 -- 1 V Protection Function Zero Current Crossing Threshold 8 -- 8 mV Current Limit Setting Current I OCSET T A = TJ = 25C 9 10 11 A Current Limit Setting Current Temperature Coefficient IOCSET_TC -- 4700 -- ppm/ C Current Limit Threshold R OCSET = 120k -- 100 -- mV Absolute Over-Voltage Protection Threshold VOVP, Absolute VREFIN 1.33V 1.9 2 2.1 V Relative Over-Voltage Protection Threshold VOVP, Relative V REFIN > 1.33V 145 150 155 % OV Fault Delay FB forced above OV threshold -- 5 -- s Relative Under-Voltage Protection Threshold VUVP UVP 35 40 45 % UV Fault Delay FB forced above UV threshold -- 3 -- s
Electrical Characteristics
(VPVCC = 5V, typical values are referenced to TA = TJ = 25°C, Min and Max values are referenced to TA = TJ from −10°C to 105°C, unless other noted)
DS8816A-07 March 2022 www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precautions are recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Not production tested. Test condition is V IN = 8V, VOUT = 1V, IOUT = 20A using application circuit. Parameter Symbol Test Conditions Min Typ Max Unit Thermal Shutdown Threshold T SD -- 150 -- C VOUT Soft-Start (PGOOD Blanking Time) From VEN = high to VOUT regulation point, VREFIN = 1V -- 0.5 -- ms Error Amplifier VSNS Error Comparator Threshold (Valley) V REFIN = 1V 11 6 1 mV Reference Reference Voltage V VREF Sourcing current = 1mA, VID no switching 1.98 2 2.02 V Driver On-Resistance UGATE Driver Source R UGATEsr BOOTx PHASEx forced to 5V -- 2 4 UGATE Driver Sink R UGATEsk BOOTx PHASEx forced to 5V -- 1 2 LGATE Driver Source R LGATEsr LGATEx, high state -- 1.5 3 LGATE Driver Sink R LGATEsk LGATEx, low state -- 0.7 1.5 Dead-Time From LGATE falling to UGATE rising -- 30 -- ns From UGATE falling to LGATE rising -- 20 -- Internal Boost Diode Resistance RBOOT PVCC to BOOTx, I BOOT = 10mA -- 80 --
©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 1. 2 Active Phase Configuration Figure 2. 1 Active Phase Configuration
18 PVCC
13 PGOODPGOOD
4 PSIPSI
5 VIDVID
3 ENEnable
9 TONVIN
DS8816A-07 March 2022 www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Inductor Valley Current vs. Load Current 0 1 02 03 04 05 06 0 Load Current (A) Inductor Valley Current (A) IL1 IL2 VIN = 19V, VPVCC = 5V Current Limit Setting Current vs. Temperature -50 -25 0 25 50 75 100 125 Temperature (°C) Current Limit Setting Current (μA) VPVCC = 5V, No load Reference Voltage vs. Temperature 1.980 1.985 1.990 1.995 2.000 2.005 2.010 - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 Temperature (°C) Reference Voltage (V) VPVCC = 5V, No load Power On from EN Time (200 μs/Div) UGATE2 (20V/Div) VIN = 12V, VPVCC = 5V, IOUT = 40A VEN (5V/Div) UGATE1 (20V/Div) VOUT (1V/Div) Efficiency vs. Load Current 0.01 0.1 1 10 100 Load Current (A) Efficiency (%) VPSI = 1.2V, VOUT = 1V VIN = 12V VIN = 19V VIN = 5V Power Off from EN Time (200 μs/Div) UGATE1 (20V/Div) VIN = 12V, VPVCC = 5V, IOUT = 40A VEN (5V/Div) UGATE2 (20V/Div) VOUT (1V/Div)
DS8816A-07 March 2022www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Dynamic Output Voltage Control Time (50 μs/Div) UGATE1 (20V/Div) VREFIN = 0.6V to 1.2V, IOUT = 40A UGATE2 (20V/Div) VOUT (600mV/Div) VREFIN (600mV/Div) Dynamic Output Voltage Control Time (50 μs/Div) UGATE1 (20V/Div) UGATE2 (20V/Div) VOUT (600mV/Div) VREFIN (600mV/Div) VREFIN = 1.2V to 0.6V, IOUT = 40A VREFIN VOUT VREFIN VOUT Power On from PVCC Time (1ms/Div) UGATE2 (20V/Div) VPVCC (5V/Div) UGATE1 (20V/Div) VOUT (1V/Div) VIN = 12V, VPVCC = 5V, IOUT = 40A Power Off from VCC Time (20ms/Div) VOUT PVCC UGATE2 (20V/Div) VPVCC (5V/Div) UGATE1 (20V/Div) VOUT (1V/Div) VIN = 12V, VPVCC = 5V, IOUT = 40A Load Transient Response UGATE1 (20V/Div) IOUT (20A/Div) UGATE2 (20V/Div) VOUT (40mV/Div) VIN = 12V, VOUT = 1V Time (10 μs/Div) Load Transient Response UGATE1 (20V/Div) IOUT (20A/Div) UGATE2 (20V/Div) VOUT (40mV/Div) VIN = 12V, VOUT = 1V Time (10 μs/Div)
DS8816A-07 March 2022 www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Current Limit and UVP Time (100 μs/Div) UGATE1 (20V/Div) VIN = 12V, VPVCC = 5V LGATE1 (5V/Div) VOUT (500mV/Div) IL1 (10A/Div) OVP Time (100 μs/Div) UGATE1 (20V/Div) VSNS (500mV/Div) LGATE1 (5V/Div) VIN = 12V, VPVCC = 5V, No Load
©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. operation threshold. Refer to Table 1 for detail. Figure 5. Boundary Condition of CCM/DEM be the complement of the high-side gate drive waveform.
©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. average current, the on-time of this phase is decreased. the current balance accuracy. Figure 12. “Valley” Current Limit normally, below setting limitation must be followed. current limit threshold is internally preset to 200mV. protection threshold, inducing IC shutdown. The RT8816A adopts per-phase current limiting protection. VOCSET. The threshold range of VOCSET is 30mV to 200mV.
DS8816A-07 March 2022www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. can only be released by PVCC or EN power on reset. A 5μs delay is used in OVP detection circuit to prevent false trigger. Output Under-Voltage Protection (UVP) The output voltage can be continuously monitored for under- voltage protection. When the output voltage is less than 40% of its set voltage, under voltage protection is triggered and then all UGATE and LGATE gate drivers are forced low. There is a 3μs delay built in the UVP circuit to prevent false transitions. During soft-start, the UVP blanking time is equal to PGOOD blanking time. MOSFET Gate Driver The RT8816A integrates high current gate drivers for the MOSFETs to obtain high efficiency power conversion in synchronous Buck topology. A dead-time is used to prevent the cross conduction for high-side and low-side MOSFETs. Because both the two gate signals are off during the dead- time, the inductor current freewheels through the body diode of the low-side MOSFET. The freewheeling current and the forward voltage of the body diode contribute power losses to the converter. The RT8816A employs adaptive dead time control scheme to ensure safe operation without sacrificing efficiency. Furthermore, elaborate logic circuit is implemented to prevent cross conduction. For high output current applications, two power MOSFETs are usually paralleled to reduce R DS(ON). The gate driver needs to provide more current to switch on/off these paralleled MOSFETs. Gate driver with lower source/sink current capability results in longer rising/falling time in gate signals and higher switching loss. The RT8816A embeds high current gate drivers to obtain high efficiency power conversion. MOSFET Selection The majority of power loss in the step-down power conversion is due to the loss in the power MOSFETs. For low voltage high current applications, the duty cycle of the high-side MOSFET is small. Therefore, the switching loss of the high-side MOSFET is of concern. Power MOSFETs with lower total gate charge are preferred in such kind of application. However, the small duty cycle means the low-side MOSFET is on for most of the switching cycle. Therefore, the conduction loss tends to dominate the total power loss of the converter. To improve the overall efficiency, the MOSFETs with low R DS(ON) are preferred in the circuit design. In some cases, more than one MOSFET are connected in parallel to further decrease the on-state resistance. However, this depends on the low-side MOSFET driver capability and the budget. Inductor Selection Inductor plays an importance role in step-down converters because the energy from the input power rail is stored in it and then released to the load. From the viewpoint of efficiency, the DC Resistance (DCR) of inductor should be as small as possible to minimize the copper loss. In addition, the inductor occupies most of the board space so the size of it is important. Low profile inductors can save board space especially when the height is limited. However, low DCR and low profile inductors are usually not cost effective. Additionally, higher inductance results in lower ripple current, which means the lower power loss. However, the inductor current rising time increases with inductance value. This means the transient response will be slower. Therefore, the inductor design is a trade-off between performance, size and cost. In general, inductance is designed to let the ripple current ranges between 20% to 40% of full load current. The inductance can be calculated using the following equation : IN OUT OUTmin SW OUT_rated IN VV VL = fk I V where k is the ratio between inductor ripple current and rated output current. Input Capacitor Selection Voltage rating and current rating are the key parameters in selecting input capacitor. Generally, input capacitor voltage rating should be 1.5 times greater than the maximum input voltage for a conservatively safe design. The input capacitor is used to supply the input RMS current, which can be approximately calculated using the
©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. reducing the input voltage ripple at heavy load. polymer capacitor(s) are recommended. Figure 13. Derating Curve of Maximum Power on the maximum power dissipation.
DS8816A-07 March 2022www.richtek.com ©Copyright 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Layout Considerations Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. Following layout guidelines must be considered before starting a layout for the RT8816A. Place the RC filter as close as possible to the PVCC pin. Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high voltage switching node. Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. All sensitive analog traces and components such as VSNS, RGND, EN, PSI, VID, PGOOD, VREF, TON REFADJ and REFIN should be placed away from high voltage switching nodes such as PHASE, LGATE, UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. Power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses.
DS8816A-07 March 2022 www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than ci rcuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no respon sibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 2.900 3.100 0.1 14 0.122 D2 1.650 1.750 0.065 0.069 E 2.900 3.100 0.1 14 0.122 E2 1.650 1.750 0.065 0.069 e 0.400 0.016 L 0.350 0.450 0.014 0.018 W-Type 20L QFN 3x3 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2