RT8801 RICHTEK | Alldatasheet
Document overview
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Technical content
Features
zzzzz Multi-Phase Power Conversion with Automatic Phase Selection zzzzz 6-bits VRD10.x DAC Output with Active Droop Compensation for Fast Load Transient zzzzz Smooth VCORE Transition at VID Jump zzzzz Power Stage Thermal Balance by DCR Current Sense zzzzz Hiccup Mode Over-Current Protection zzzzz Adjustable Switching Frequency (50kHz to 400kHz per Phase) zzzzz Under-Voltage Lockout and Soft-Start zzzzz High Ripple Frequency Times Channel Number zzzzz 2-wires programming interface zzzzz Software Programmable VID zzzzz 32-Lead VQFN Package zzzzz RoHS Compliant and 100% Lead (Pb)-Free
Applications
z Intel® VR10.x-compliant Processors Voltage Regulator z Low Output Voltage, High power density DC-DC Converters z Voltage Regulator Modules
Ordering Information
Note : Richtek Pb-free and Green products are : \RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. \Suitable for use in SnPb or Pb-free soldering processes. \`100% matte tin (Sn) plating. Package Type QV : VQFN-32L 5x5 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commer- cial Standard) RT8801
DS8801-04 August 2007www.richtek.com All brandname or trademark belong to their owner respectively Registers 0x00 Hi-I setting registers; Default 0x00 Bit4-0 : Pin Configurations (TOP VIEW) VQFN-32L 5x5 Bit4 Bit3 Bit2 Bit1 Bit0 VID Offset (mV) 0 0 0 0 0 0 0 0 0 0 1 12.5 0 0 0 1 0 25 0 0 0 1 1 37.5 0 0 1 0 0 50 0 0 1 0 1 62.5 0 0 1 1 0 75 0 0 1 1 1 87.5 0 1 0 0 0 100 0 1 0 0 1 112.5 0 1 0 1 0 125 0 1 0 1 1 137.5 0 1 1 0 0 150 0 1 1 0 1 162.5 0 1 1 1 0 175 0 1 1 1 1 187.5 Bit4 Bit3 Bit2 Bit1 Bit0 VID Offset (mV) 1 0 0 0 0 200 1 0 0 0 1 212.5 1 0 0 1 0 225 1 0 0 1 1 237.5 1 0 1 0 0 250 1 0 1 0 1 262.5 1 0 1 1 0 275 1 0 1 1 1 287.5 1 1 0 0 0 300 1 1 0 0 1 312.5 1 1 0 1 0 325 1 1 0 1 1 337.5 1 1 1 0 0 350 1 1 1 0 1 362.5 1 1 1 1 0 375 1 1 1 1 1 400 SLOT_OCC PWM3 AD_SEL GND IC_OUT FB CLK DATA CSP2 ADJ CSP4 CSP3 CSP1 PWM1 PWM2 1615 91 0 1 1 1 2 1 4 13 28 27 26 25 32 31 30 29 GND PWM4 VID1 VID125 VID0 VID2 VID3 VID4 VDD CSN VOSS COMP SGND DVD SS PGOOD RT RST
DS8801-04 August 2007 www.richtek.com All brandname or trademark belong to their owner respectively 0x01 Core Current. Default 0x00 (read only). The core current full scale is over current trigger point. Bit6-0 : Show core voltage current. 0x03 MISC. Default 0x04. Bit2 : Slot_OCC Detection. This bit be written clear and only can be written 0. 0 : Normal 1 : Slot_OCC ever be pulled high Bit1 : The reset pin ever be pull low when bit0 = 1 and only can be written 0. 0 : Never issue reset 1 : Ever issue reset Bit0 : Reset control. When this bit be write 1, the Watching Dog timer (Reset pin) will repeat counter 1400ms then pull low 200ms.Reset pin be pull low, if this bit = 1 will reset all registers to default exception MISC(Index 0x03). 0 : Disable 1 : Enable Note : If SLOT_OCC pin = 1 reset all registers value to default. Product information registers (Read Only) 0x13 Revision_ID 0x00 RST enable 0x03 bit 0 7 x Tdelay Tdelay WD Timer RST
DS8801-04 August 2007www.richtek.com All brandname or trademark belong to their owner respectively Typical Application Circuit GND SLOT_OCC AD_SEL GND IC_OUT FB RST CLK DATA PWM3 CSP2 ADJ CSP4 CSP3 CSP1 PWM1 PWM2 CSN VOSS COMP SGND DVD SS PGOOD RT PWM4 VID1 VID125 VID0 VID2 VID3 VID4 VDD VCORE 680uF x 10 10uF x 18 161591 0 1 1 1 2 1 413 28 27 26 25 32 31 30 29 SLOT_OCC 5VSB VID4 VID3 VID2 VID1 VID0 VID12.5 0.1uF CLK DATA 10nF 15k 33pF 10nF 100k 0.1uF 12k 27k27k VCC 12V 330 NC NC NC NC NC 0 0 VCOREIN4148 55VSB 4.7k NC 6 VCC 3V 4.7k VCC 5V 4.7k BOOT1 UGATE1 PHASE1 LGATE1 VCC RT9607PQV 1114 UGATE2 PHASE2 LGATE2 BOOT2 PWM2 PWM1 PVCC GND PGND4 1uF 12V 1uF IPD09N03 0.6uH PVCC12V IPD06N03 2.2 0.01uF 1uF 1500uF IPD09N03 0.6uH IPD06N03 2.2 0.01uF 1uF 1500uF 1uF NC 3 BOOT1 UGATE1 PHASE1 LGATE1 VCC RT9607PQV 1114 UGATE2 PHASE2 LGATE2 BOOT2 PWM2 PWM1 PVCC GND PGND4 1uF 12V 1uF10 IPD09N03 0.6uH PVCC12V IPD06N03 2.2 0.01uF 1uF 1500uF IPD09N03 0.6uH IPD06N03 2.2 0.01uF 1uF 1500uF 1uF NC 3 RT8801 200 NC NTC
DS8801-04 August 2007 www.richtek.com All brandname or trademark belong to their owner respectively Functional Pin Description SLOT_OCC (Pin 1) CPU socket occupied; the signal is defined to indicate if the CPU has been changed/ removed and it will reset all chip. There is one register implemented for the status indication. The register will be reset when the V DD power removed or CPU changed/removed. The pin is implemented as an input, TTL level, and active-low signal. DATA (Pin 2), CLK (Pin 3) 2-wires programming interface. RST (Pin 4) This pin be pull low (the Watching Dog = Low), it will reset some register, when 0x03 bit 0 be setting. AD_SEL (Pin 5) The pin select series bus address. Pin =1,Address = 0x5E & Pin = 0, Address = 0x5C. GND (Pin 6, Bottom Pad) Chip power ground. IC_OUT (Pin 7) The pin is defined as a reference current output. A capacitor is attached to set the de fault Watching Dog low pluse time. Write the index 0x03 bit0 = 1 delay 7 times T delay time then issue Tdelay low pluse. FB (Pin 8) The pin is defined as an inverting input of internal error amplifier. COMP (Pin 9) The pin is defined as an output of the error amplifier and an input of the PWM comparator. SGND (Pin 10) Difference ground sense of VCORE. VOSS (Pin 11) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. C_OUT C_OUT OUT delay x VI C T where = DVD (Pin 12) Hardware adjustable system power UVLO detection; input pin; the internal trip threshold = 0.9V at VDVD rising. SS (Pin 13) The pin is defined to set soft-start ramp rate; a capacitor is attached to set the start time interval. Pull this pin lower than 1.0V (ramp valley of saw-tooth wave in pulse width modulator) will shut the converter down. PGOOD (Pin 14) Power Good Indication. PGOOD is an open drain output. PGOOD will go high impedance when SS voltage greater than 3.7V and no fault occurs. RT (Pin 15) Default operation switching frequency setting. A resistor is attached to set the default operation frequency. CSN (Pin 16) The pin is defined to sense load current of CPU. The pin should be connected to the output node of choke. ADJ (Pin 17) Pin for active droop adjustment. An external resistor is attached to GND for load droop setting. CSP1 (Pin 21), CSP2 (Pin 20), CSP3 (Pin 19), CSP4 (Pin 18) Current sense inputs from the individual converter channels. PWM1 (Pin 22), PWM2 (Pin 23), PWM3 (Pin 24), PWM4 (Pin 25) PWM outputs for each phase switching drive. VDD (Pin 26) Chip powers supply. Connect this pin to a 5VSB or VCC5 supply.
DS8801-04 August 2007www.richtek.com All brandname or trademark belong to their owner respectively Function Block Diagram Oscillator Ramp Generator ++ SUM/M PWM1 PWM2 PWM3 Droop Tune Current Correction DAC VID1 VID3 VID4 VID125 VID0 VID2 SLOT_OCC SGND AD_SEL PGOOD DVD RT RST GND VDD Soft Start & PGOOD - CSN CSP1 CSP2 CSP3 PWM Logic PWMCP PWM Logic PWMCP PWM Logic PWMCP PWM Logic PWMCP - PWM4 M u x CSP4 Mux Digital Logic Power On Reset SS FB EA GM CLK COMP IC_OUT VOSS DATA OVP Trip PointOffset Current Source/Sink ADJ WD Timer OCP DetectionOCP OCP INH VID4 (Pin 27), VID3 (Pin 28), VID2 (Pin 29), VID1 (Pin 30), VID0 (Pin 31), VID125 (Pin 32) DAC voltage identification; Input; The VID0~4 is implemented for VRM9.0 (5-bits) DAC identification; The VID0~4, VID125 is implemented for VRM10.X (6-bits) DAC identification. The pins are internally pulled to 1.2V (pull high 50μA) if left open. GND [Exposed Pad (33)] The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.
Table 1. Output Voltage Program
DS8801-04 August 2007 www.richtek.com All brandname or trademark belong to their owner respectively Absolute Maximum Ratings (Note 1) z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 4) z ESD Susceptibility (Note 2)
Electrical Characteristics
Recommended Operating Conditions (Note 3) To be continued Parameter Symbol Test Conditions Min Typ Max Units VDD Supply Current Nominal Supply Current IDD PWM 1,2,3,4 Open -- 12 16 mA Power-On Reset POR Threshold VDDRTH V DD Rising 4.0 4.2 4.5 V Hysteresis VDDHYS 0.2 0.5 -- V Trip (Low to High) VDVDTP Enable 0.8 0.9 1.0 V VDVD Threshold Hysteresis VDVDHYS -- 70 -- mV Oscillator Free Running Frequency fOSC R RT = 22.5kΩ 250 300 350 kHz Frequency Adjustable Range fOSC_ADJ 50 -- 400 kHz Ramp Amplitude ΔVOSC R RT = 22.5kΩ -- 1.9 -- V Ramp Valley VRV 0.7 1.0 -- V Maximum On-Time of Each Channel 62 66 75 % RT Pin Voltage VRT R RT = 22.5kΩ 1.7 1.8 1.9 V Reference and DAC VDAC ≥ 1V −1 -- +1 % DACOUT Voltage Accuracy ΔVDAC VDAC < 1V −10 -- +10 mV DAC (VID0-VID125) Input Low VILDAC -- -- 0.3 V DAC (VID0-VID125) Input High VIHDAC 0.8 -- -- V (VDD = 5V, TA = 25°C, unless otherwise specified)
DS8801-04 August 2007www.richtek.com All brandname or trademark belong to their owner respectively Parameter Symbol Test Conditions Min Typ Max Units Offset Voltage −3 -- 3 % VOSS Pin Voltage VVOSS R VOSS = 100kΩ 1.6 1.7 1.8 V Error Amplifier DC Gain -- 85 -- dB Gain-Bandwidth Product GBW -- 10 -- MHz Slew Rate SR COMP = 10pF -- 3 -- V/μs Current Sense GM Amplifier CSN Full Scale Source Current IISPFSS 150 -- -- μA CSN Current for OCP -- 150 -- μA Protection SS Current ISS VSS = 1V 8 13 18 μA Over-Voltage Trip SEN DACOUT OFFSET V V + V ΔOVT 130 140 150 % Delay Time WD Timer, TDL (CL = 100nF) -- 200 -- ms WD Timer, TDH (CL = 100nF) -- 1400 -- ms Power Good Output Low Voltage VPGOODL I PGOOD = 4mA -- -- 0.2 V Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard.
DS8801-04 August 2007 www.richtek.com All brandname or trademark belong to their owner respectively Typical Operating Characteristics Adjustable Frequency 100 150 200 250 300 350 400 450 0 20 40 60 80 100 120 RRT (k) FOSC (kHz) (kΩ) Linearity of each PWM 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8 0 500 1000 1500 2000 2500 3000 3500 Pulse Width (ns) VCOMP (V) PWM2 PWM3 PWM1 PWM4 fOSC = 200k Load Transient Response Time (5 μs/Div) VCORE Phase IOUT VADJ CH1: (500mV/Div) CH2: (10V/Div) CH3: (50A/Div) CH4: (100mV/Div) Load Transient Response Time (5 μs/Div) VCORE Phase1 Phase2 Phase3 CH1: (500mV/Div), CH2: (10V/Div) CH3: (10V/Div), CH4: (10V/Div) CH3:(10V/Div) CH4:(1V/Div) Power-Off @ IOUT = 60A Time (10 μs/Div) VCOMP PWM UGATE LGATE CH1:(5V/Div) CH2:(20V/Div) Power-On @ IOUT = 60A Time (10ms/Div) UGATE LGATE VSS PWM CH3:(20V/Div) CH4:(10V/Div) CH1:(5V/Div) CH2:(5V/Div)
DS8801-04 August 2007www.richtek.com All brandname or trademark belong to their owner respectively CH1:(5V/Div) CH2:(5V/Div) Relationship Between Inductor Current and V ADJ Time (25ms/Div) VSS PWM VADJ IL CH3:(50mV/Div) CH4:(20A/Div)
Place the high-power switching components first, and separate them from sensitive nodes.
- Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
- Switching ripple current path:
a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
- MOSFET driver should be closed to MOSFET.
- The compensation, bypass and other function setting components should be near the IC and away from the noisy
Figure 26. Power Stage Ripple Current Path
DS8801-04 August 2007 www.richtek.com Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com Outline Dimension E D L be A SEE DETAIL A Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 4.950 5.050 0.195 0.199 D2 3.400 3.750 0.134 0.148 E 4.950 5.050 0.195 0.199 E2 3.400 3.750 0.134 0.148 e 0.500 0.020 L 0.350 0.450 0.014 0.018 V-Type 32L QFN 5x5 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2