RT8207P RICHTEK | Alldatasheet
Document overview
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Technical content
Features
Resistor Programmable Current Limit by Low Side RDS(ON) Sense Quick Load Step Response within 100ns 1% VVDDQ Accuracy Over Line and Load Fixed 1.8V (DDRII), 1.5V (DDRIII) or Adjustable 0.75V to 3.3V Output Range for 1.35V (Low-Power DDRIII), 1.2V (DDRIV) and 1.1V (Low-Power DDRIV) 4.5V to 26V Battery Input Range Resistor Programmable Frequency Over/Under Voltage Protection Internal Current Limit Ramp Soft-Start Drives Large Synchronous-Rectifier FETs Power Good Indicator 1.5A LDO (VTT), Buffered Reference (VTTREF) Capable to Sink and Source 1.5A External Input Available to Minimize Power Losses Integrated Divider Tracks 1/2 VDDQ for Both VTT and VTTREF Buffered Low Noise 10mA VTTREF Output Remote Sensing (VTTSNS) Supports High-Z in S3 and Soft-Off in S4/S5 RoHS Compliant and Halogen Free
Applications
DDRI/II/III/Low-Power DDRIII/DDRIV/Low-Power DDRIV Memory Power Supplies Notebook Computers SSTL18, SSTL15 and HSTL Bus Termination
Ordering Information
Note : Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. RT8207P Package Type QW : WQFN-20L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free)
DS8207P-03 September 2016www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin Configuration (TOP VIEW) WQFN-20L 3x3 VTTREF GND VTTGND VTTSNS LGATE PGND VDDP CS FB TON VTT VLDOIN UGATE BOOT 17181920 9876 GND 115 PHASE VDDQ VDD PGOOD Marking Information 4B=YM DNN 4B= : Product Code YMDNN : Date Code Functional Pin Description Pin No. Pin Name Pin Function 1 VTTGND Power ground output for VTT LDO. 2 VTTSNS Voltage sense input for VTT LDO. Connect to the terminal of the VTT LDO output capacitor. 21 (Exposed Pad) GND Analog ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum thermal dissipation. 4 VTTREF Buffered reference output.
5 VDDQ
Reference input for VTT and VTTREF. Discharge current sinking terminal for VDDQ non-tracking discharge. Output voltage feedback input for VDDQ output if the FB pin is connected to VDD or GND. 6 FB VDDQ output setting. Connect to GND for DDR3 (VVDDQ = 1.5V) power supply. Connect to VDD for DDR2 (V VDDQ = 1.8V) power supply. Or connect to a resistive voltage divider from VDDQ to GND to adjust the output of PWM from 0.75V to 3.3V. 7 S3 S3 signal input.
8 S5 S5 signal input
9 TON Set the UGATE on time through a pull-up resistor connecting to V IN. 10 PGOOD Power good open drain output. In High state when VDDQ output voltage is within the target range. 11 VDD Supply input for analog supply. 12 VDDP Supply input for LGATE gate driver. 13 CS Current limit threshold setting input. Connect to VDD through the voltage setting resistor. 14 PGND Power ground for low side MOSFET. 15 LGATE Low side gate driver output for VDDQ. 16 PHASE Switch node. External inductor connection for VDDQ and behave as the current sense comparator input for Low Side MOSFET RDS(ON) sensing. 17 UGATE High side gate driver output for VDDQ. 18 BOOT Boost flying capacitor connection for VDDQ. 19 VLDOIN Power supply for VTT LDO. 20 VTT Power output for VTT LDO.
DS8207P-03 September 2016www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Buck Controller R QS Min. TOFF QT R I G 1-SHOT 0.75V VREF S1 Q Latch S1 Q Latch OV UV 116%VREF 70% VREF 90% VREF SS Timer Thermal Shutdown Diode Emulation DRV DRV On-time Compute 1-SHOT CS FB VDDQ VDD UGATE PHASE VDDP PGOOD PGND LGATE TON BOOT TRIG PWM GM - Comp SS Int. + 10µA VTT LDO VTTSNS S3 VTTREF VTT VLDOIN VTTGND Tracking Discharge Thermal Shutdown 110% VVTTREF 90% VVTTREF GND VDDQ
DS8207P-03 September 2016 www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Absolute Maximum Ratings (Note 1) BOOT to GND BOOT to PHASE VDD, VDDP, CS, S3, S5, VTTSNS, VDDQ, VTTREF, VTT, VLDOIN, PHASE to GND UGATE to GND LGATE to GND UGATE to PHASE Power Dissipation, PD @ TA = 25°C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)
DS8207P-03 September 2016www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit PWM Controller Quiescent Supply Current (VDD + VDDP) FB forced above the regulation point, VS5 = 5V, VS3 = 0V -- 470 1000 A TON Operating Current R TON = 1M -- 15 -- A IVLDOIN BIAS Current V S5 = VS3 = 5V, VTT = No Load -- 1 -- A IVLDOIN Standby Current V S5 = 5V, VS3 = 0V, VTT = No Load -- 0.1 10 A Shutdown Current (VS5 = VS3 = 0V) ISHDN VDD + VVDDP -- 1 10 A TON -- 0.1 5 S5/S3 = 0V 1 0.1 1 IVLDOIN -- 0.1 1 Fixed VDDQ Output Voltage FB = GND -- 1.5 -- V FB = VDD -- 1.8 -- FB Input Bias Current FB = 0.75V 1 0.1 1 A VDDQ Voltage Range 0.75 -- 3.3 V On-Time R TON = 1M, VVDDQ = 1.25V 267 334 401 ns Minimum Off-Time 250 400 550 ns VDDQ Input Resistance -- 100 -- k VDDQ Shutdown Discharge Resistance V S5 = GND -- 15 -- Current Sensing CS Sink Current V CS > 4.5V 9 10 11 A Current Limit Comparator Offset (VVDDCS – VGNDPHASE), RCS = 10k 15 -- 15 mV Zero Crossing Threshold GND PHASE 5 -- 10 mV Current Limit Threshold Setting Range V DD – VCS 50 -- 200 mV Fault Protection Under Voltage Protection Threshold VUVP 60 70 80 % Over Voltage Protection Threshold VOVP With respect to error comparator threshold 113 116 120 % Over Voltage Fault Delay FB forced above over voltage threshold -- 20 -- s VDD POR Threshold Rising edge, hysteresis = 120mV, PWM disabled below this level 3.9 4.2 4.5 V Under Voltage Blank Time From S5 signal going high -- 5 -- ms Thermal Shutdown T SD -- 165 -- °C Thermal Shutdown Hysteresis TSD -- 10 -- °C
Electrical Characteristics
(VIN = 15V, VDD = VVDDP = 5V, RTON = 1MΩ, TA = 25°C, unless otherwise specified)
DS8207P-03 September 2016 www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Driver On-Resistance UGATE Driver Source R UGATEsr BOOT PHASE Forced to 5V -- 2.5 5 UGATE Driver Sink R UGATEsk BOOT PHASE Forced to 5V -- 1.5 3 LGATE Driver Source R LGATEsr DL, High State -- 2.5 5 LGATE Driver Sink R LGATEsk DL, Low State -- 0.8 1.6 Dead Time LGATE Rising (PHASE = 1.5V) -- 40 -- ns UGATE Rising -- 40 -- Internal Boost Charging Switch On Resistance VDDP to BOOT, 10mA -- -- 80 Logic I/O Logic Input Low Voltage S3, S5 Low -- -- 0.8 V Logic Input High Voltage S3, S5 High 2 -- -- V Logic Input Current S3, S5 = VDD/GND 1 0 1 A PGOOD (upper side threshold decide by Over Voltage threshold) Trip Threshold (Falling) Measured at FB, with respect to reference, no load 13 10 7 % Trip Threshold (Hysteresis) -- 3 -- % Fault Propagation Delay Falling edge, FB forced below PGOOD trip threshold -- 2.5 -- s Output Low Voltage I SINK = 1mA -- -- 0.4 V Leakage Current I LEAK High state, forced to 5V -- -- 1 A VTT LDO VTT Output Tolerance V VTTTOL VVDDQ = VLDOIN = 1.2V/1.35/1.5V/1.8V, mV VVDDQ = VLDOIN = 1.2V/1.35/1.5V/1.8V, VVDDQ = VLDOIN = 1.2V/1.35, VVDDQ = VLDOIN = 1.5V/1.8V, VTT Source Current Limit I VTTOCLSRC VDDQTT VV0 . 9 5 2 PGOOD = High 1.6 2.6 3.6 A VTT = 0V -- 1.3 -- VTT Sink Current Limit I VTTOCLSNK VDDQTT VV1 . 0 5 2 PGOOD = High 1.6 2.6 3.6 A VTT = VVDDQ -- 1.3 -- VTT Leakage Current I VTTLK S5 = 5V, S3 = 0V, VDDQTT VV 2 10 -- 10 A
DS8207P-03 September 2016www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit VTTSNS Leakage Current I VTTSNSLK I SINK = 1mA 1 -- 1 A VTT Discharge Current I DSCHRG V VDDQ = 0V, VTT = 0.5V, S5 = S3 =0V 10 30 -- mA VTTREF Output Voltage V VTTREF VDDQVTTREF VV 2 -- 0.9 / 0.75 -- V VDDQSNS/2, VTTREF Output Voltage Tolerance VVTTREFTOL VLDOIN = VVDDQ = 1.5V, IVTTREF <10mA 15 -- 15 mV VLDOIN = VVDDQ = 1.8V, IVTTREF <10mA 18 -- 18 VTTREF Source Current Limit IVTTREFOCL V VTTREF = 0V 10 40 80 mA Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.
DS8207P-03 September 2016 www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics VDDQ Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) 1 VIN = 8V, VDDQ = 1.8V, S3 = GND, S5 = 5V DDRII VDDQ Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) 1 VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V DDRIII VDDQ Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) 1 VIN = 20V, VDDQ = 1.5V, S3 = GND, S5 = 5V DDRIII VDDQ Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) 1 VIN = 20V, VDDQ = 1.8V, S3 = GND, S5 = 5V DDRII VDDQ Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) 1 VIN = 8V, VDDQ = 1.5V, S3 = GND, S5 = 5V DDRIII VDDQ Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) 1 VIN = 12V, VDDQ = 1.8V, S3 = GND, S5 = 5V DDRII
DS8207P-03 September 2016www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Switching Frequency vs. Output Current 100 150 200 250 300 350 400 450 500 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) 1 DDRIII, VIN = 20V, VVDDQ = 1.5V, S3 = GND, S5 = 5V Switching Frequency vs. Output Current 100 150 200 250 300 350 400 450 500 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) 1 DDRIII, VIN = 12V, VVDDQ = 1.5V, S3 = GND, S5 = 5V Switching Frequency vs. Output Current 100 150 200 250 300 350 400 450 500 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) 1 DDRII, VIN = 20V, VDDQ = 1.8V, S3 = GND, S5 = 5V Switching Frequency vs. Output Current 100 150 200 250 300 350 400 450 500 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) 1 DDRIII, VIN = 8V, VVDDQ = 1.5V, S3 = GND, S5 = 5V Switching Frequency vs. Output Current 100 150 200 250 300 350 400 450 500 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) 1 DDRII, VIN = 12V, VDDQ = 1.8V, S3 = GND, S5 = 5V Switching Frequency vs. Output Current 100 150 200 250 300 350 400 450 500 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) 1 DDRII, VIN = 8V, VDDQ = 1.8V, S3 = GND, S5 = 5V
DS8207P-03 September 2016 www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VDDQ Output Voltage vs. Output Current 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0.001 0.01 0.1 1 10 Output Current (A) Output Voltage (V) 1 DDRII VIN = 12V, VDDQ = 1.8V, S3 = GND, S5 = 5V VDDQ Output Voltage vs. Output Current 1.480 1.485 1.490 1.495 1.500 1.505 1.510 1.515 0.001 0.01 0.1 1 10 Output Current (A) Output Voltage (V) 1 DDRIII VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V VTT Output Voltage vs. Output Current 0.8970 0.8975 0.8980 0.8985 0.8990 0.8995 0.9000 Output Current (A) Output Voltage (V) 1 VIN = 12V, VDDQ = 1.8V, S3 = S5 = 5V DDRII VTTREF Output Voltage vs. Output Current 0.898 0.900 0.902 0.904 0.906 0.908 0.910 0.912 - 1 0 - 8- 6- 4- 2 0 2 4 6 81 0 Output Current (mA) Output Voltage (V) 1 VIN = 12V, VDDQ = 1.8V, S3 = S5 = 5V DDRII VTTREF Output Voltage vs. Output Current 0.746 0.748 0.750 0.752 0.754 0.756 0.758 0.760 - 1 0 - 8- 6- 4- 2 0 2 4 6 81 0 Output Current (mA) Output Voltage (V) 1 DDRIII VIN = 12V, VDDQ = 1.5V, S3 = S5 = 5V VTT Output Voltage vs. Output Current 0.7450 0.7455 0.7460 0.7465 0.7470 0.7475 0.7480 Output Current (A) Output Voltage (V) 1 DDRIII VIN = 12V, VDDQ = 1.5V, S3 = S5 = 5V
DS8207P-03 September 2016www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (1ms/Div) VDDQ (1V/Div) VTT (500mV/Div) (5V/Div) PGOOD (5V/Div) No Load VDDQ and VTT Start Up VIN = 12V, VDDQ = 1.5V, S3 = S5 = 5V VDDQ Start Up Time (400 μs/Div) VDDQ (1V/Div) VIN = 12V, VDDQ = 1.5V S3 = GND, S5 = 5V, ILOAD = 10A UGATE (20V/Div) LGATE (5V/Div) IL (10A/Div) VDDQ Voltage vs. Temperature 1.474 1.478 1.482 1.486 1.490 1.494 1.498 1.502 -50 -25 0 25 50 75 100 125 Temperature (C) VDDQ Voltage (V) 1 DDRIII VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V VDDQ Voltage vs. Temperature 1.77400 1.77725 1.78050 1.78375 1.78700 1.79025 1.79350 1.79675 1.80000 -50 -25 0 25 50 75 100 125 Temperature (C) VDDQ Voltage (V) 1 VIN = 12V, VDDQ = 1.8V, S3 = S5 = 5V DDRII Shutdown Current vs. Input Voltage 0.00 0.50 1.00 1.50 2.00 2.50 3.00 5 8 11 14 17 20 23 26 Input Voltage (V) Shutdown Current (µA) 1 No Load, S3 = S5 = GND Standby Current vs. Input Voltage 480 500 520 540 560 580 600 5 8 11 14 17 20 23 26 Input Voltage (V) Standby Current (µA) 1 No Load, S3 = GND, S5 = 5V
DS8207P-03 September 2016 www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (20 μs/Div) IL (10A/Div) VDDQ (50mV/Div) LGATE (10V/Div) DDRIII, VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V ILOAD = 0.1A to 10A UGATE (20V/Div) VDDQ Load Transient Response VTT Load Transient Response Time (200 μs/Div) VTT - VTTREF (20mV/Div) DDRIII, VIN = 12V, VDDQ = 1.5V, S3 = S5 = 5V, IVTT = −1.5A to 1.5A VTT (20mV/Div) IVTT (2A/Div) VTTREF (20mV/Div) VTT Load Transient Response Time (200 μs/Div) DDRII, VIN = 12V, VDDQ = 1.8V, S3 = S5 = 5V, IVTT = −1.5A to 1.5A VTT (20mV/Div) IVTT (2A/Div) VTTREF (20mV/Div) VTT - VTTREF (20mV/Div) OVP Time (40 μs/Div) VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V No Load PGOOD (5V/Div) VDDQ (1V/Div) LGATE (5V/Div) Shutdown Time (400 μs/Div) VDDQ (1V/Div) VDDQ = 1.5V, S3 = S5 = 5V VTT (1V/Div) VTTREF (500mV/Div) (5V/Div) No Load Tracking Mode VIN = 12V VDDQ Load Transient Response Time (20 μs/Div) VDDQ (50mV/Div) LGATE (10V/Div) UGATE (20V/Div) IL (10A/Div) DDRII, VIN = 12V, VDDQ = 1.8V, S3 = GND, S5 = 5V, ILOAD = 0.1A to 10A
DS8207P-03 September 2016www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. PGOOD (5V/Div) VDDQ (2V/Div) LGATE (5V/Div) UGATE (20V/Div) UVP Time (40 μs/Div) VIN = 12V, VDDQ = 1.5V, S3 = GND, S5 = 5V
DS8207P-03 September 2016 www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Application Information
The RT8207P PWM controller provides the high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low voltage chipset RAM supplies in notebook computers. Richtek's Mach Response TM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology circumvents the poor load transient timing problems of fixed-frequency current mode PWMs, while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant- off-time PWM schemes. The DRV TM mode PWM modulator is specifically designed to have better noise immunity for such a single output application. The 1.5A sink/source LDO maintains fast transient response, only requiring 20 μF of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The RT8207P supports all of the sleep state controls, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5. PWM Operation The Mach ResponseTM DRVTM mode controller relies on the output filter capacitor's Effective Series Resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. Referring to the function diagrams of the RT8207P, the synchronous high side MOSFET is turned on at the beginning of each cycle. After the internal one-shot timer expires, the MOSFET will be turned off. The pulse width of this one- shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the entire input voltage range. Another one-shot sets a minimum off-time (400ns typ.). On-Time Control The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to V VDDQ, thereby making the on-time of the high side switch directly proportional to the output voltage and inversely proportional to the input voltage. This implementation results in a nearly constant switching frequency without the need of a clock generator, as shown below : ON TON VDDQ INt 3.85p x R x V / (V 0.5) And then the switching frequency is : VDDQ IN ONf V / (V x t ) where RTON is the resistor connected from VIN to the TON pin. Diode-Emulation Mode In diode-emulation mode, the RT8207P automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly without increasing VDDQ ripples or load regulation. As the output current decreases from heavy load condition, the inductor current will also be reduced and eventually come to the point where its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial negative current to flow when the inductor freewheeling current reaches negative. As the load current is further decreased, it takes longer and longer time to discharge the output capacitor to the level that requires the next “ON” cycle. The on-time is kept the same as that in the heavy load condition. In contrast, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. The transition load point to the light load operation is shown in below figure and can be calculated as follows : IN VDDQ LOAD(SKIP) ON VVI x t 2L where tON is the on-time.
©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. flying capacitor between VDDP and PGND. the turn-off time (Figure 5). Figure 5. Increasing the UGATE Rise Time is over and the output reaches 93% of its set voltage. 4.2V (typ.), VDDQ, VTT and VTTREF will be activated. This is a non-latch protection. smoothly and safely under enough source/sink ability. diode across the output to act as a reverse polarity clamp. soft-start, the UVP has a blanking time around 5ms.
©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. and can only be released by VDD power on reset or S5. FB pin according to Table 1. Table 1. FB and output voltage setting Figure 6. Setting VDDQ with a Resistive Voltage Divider Where RVDD is the resistor between VDDP and VDD pin. time for VDDQ at the no load condition.
©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. when S5 is low or in the S4/S5 state. the maximum average inductor current. performance, especially at low VIN − VVDDQ differences. where minimum off-time, tOFF(MIN), is 400ns typically. have high enough ESR to satisfy stability requirements. without tripping the OVP circuit. Table 2. S3 and S5 truth table
DS8207P-03 September 2016www.richtek.com RT8207P ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. where VP−P is the peak-to-peak output voltage ripple. Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. For low input-to-output voltage differentials (VIN/VVDDQ < 2), additional output capacitance is required to maintain stability and good efficiency in ultrasonic mode. The amount of overshoot due to stored inductor energy can be calculated as : PEAK SOAR OUT VDDQ (I ) x LV 2 x C x V where IPEAK is the peak inductor current. Output Capacitor Stability Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation : SW ESR OUT f1f 2 x x ESR x C 4 Do not put high value ceramic capacitors directly across the outputs without taking precautions to ensure stability. Large ceramic capacitors can have a high ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting VDDQ or the FB voltage divider close to the inductor. Unstable operation manifests itself in two related and distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it may indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillations at the output in the form of line or load perturbations, which can trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It helps to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under- or over-shoot. Thermal Considerations The junction temperature should never exceed the absolute maximum junction temperature T J(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula : P D(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125 °C. The junction-to-ambient thermal resistance, θ JA, is highly package dependent. For a WQFN-20L 3x3 package, the thermal resistance, θJA, is 68°C/W on a standard JEDEC 51-7 high effective-thermal- conductivity four-layer test board. The maximum power dissipation at T A = 25°C can be calculated as below : PD(MAX) = (125 °C − 25 °C) / (68 °C/W) = 1.471W for a WQFN-20L 3x3 package. The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, θJA. The derating curves in Figure 7 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. starting a layout for the RT8207P. to high voltage switching node. short as possible to reduce stray inductance. close as possible to the pin with short and wide trace. additional ESR and/or ESL of the trace. trace between the GND pin and the output capacitor(s). the current limit resistor located at the device. handling (including the chip power ground connections). as possible to minimize loops and reduce losses. Figure 7. Derating Curve of Maximum Power Dissipation
DS8207P-03 September 2016www.richtek.com RT8207P Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 2.900 3.100 0.114 0.122 D2 1.650 1.750 0.065 0.069 E 2.900 3.100 0.114 0.122 E2 1.650 1.750 0.065 0.069 e 0.400 0.016 L 0.350 0.450 0.014 0.018 W-Type 20L QFN 3x3 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2 Outline Dimension