RT8167A

RT8167A RICHTEK | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 40

Technical content

Features

zzzzz G-NAVPTM (Green Native Active Voltage Positioning) Topology zzzzz Dual Output Controller with Two Built-in Gate Drivers zzzzz Serial VID Interface zzzzz 0.5% DAC Accuracy zzzzz Differential Remote Output Voltage Sensing zzzzz Built-in ADC for Platform Programming zzzzz Diode Emulation Mode (DEM) at Light Load Condition zzzzz Droop Enable/Disable zzzzz Fast Transient Response zzzzz VR12/IMVP7 Compatible Power Management States zzzzz VR Ready Indicator zzzzz Thermal Throttling Indicator zzzzz Current Monitor Output zzzzz Switching Frequency up to 1MHz per Phase zzzzz Protection : OVP, UVP, NVP, OCP, UVLO zzzzz Small 48-Lead WQFN Package zzzzz RoHS Compliant and Halogen Free

Applications

z VR12 / IMVP7 Intel CPU Core Supply z AVP Step-down Converter z Notebook/ Netbook/ Desktop Computer CPU Core Supply

Ordering Information

Note : Richtek products are : \ RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. \ Suitable for use in SnPb or Pb-free soldering processes. General Description The RT8167A is a dual single-phase synchronous Buck PWM controller with integrated gate drivers, compliant with Intel VR12/IMVP7 specification. A serial VID (SVID) interface is built-in in the RT8167A to communicate with Intel VR12/IMVP7 compliant CPU. The integrated differential remote output voltage sensing function and built-in high accuracy DAC achieve accurate output voltage regulation. The RT8167A supports VR12/ IMVP7 compatible power management states and VID on-the-fly function. The RT8167A operates in two power management states including DEM in PS2 and Forced-CCM in PS1/PS0. Richtek 's proprietary G-NAVPTM (Green Native AVP) makes AVP (Active Voltage Positioning) design easier and more robust. By utilizing the G-NAVP TM topology, DEM and CCM efficiency can be improved. The RT8167A integrates high accuracy ADC for platform setting functions, such as no-load offset or over current level. Individual VR ready output signals are provided for both CORE VR and GFX VR. The IC also features complete fault protection functions, including over voltage, under voltage, negative voltage, over current and under voltage lockout. The RT8167A is available in a WQFN-48L 6x6 small foot print package. Marking Information RT8167AGQW : Product Number YMDNN : Date Code Package Type QW : WQFN-48L 6x6 (W-Type) RT8167A Lead Plating System G : Green (Halogen Free and Pb Free) RT8167A GQW YMDNN

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function

1 ISEN1P Positive Current Sense Input of CORE VR

2 ISEN1N Negative Current Sense Input of CORE VR

3 COMP CORE VR Compensation. This pin is the output node of the error amplifier. 4 FB CORE VR Feedback. This is the negative input node of the error amplifier. 5 RGND Return Ground for CORE VR. This pin is the negative input for differential remote voltage sensing.

6 IMON

Current Monitor Output of CORE VR. The output voltage V IMON of this pin is proportional to the output current. For digital output current reporting, detailed VIMON is generated by built-in ADC.

7 IMONFB

This pin is used to externally set the current monitor output gain of CORE VR. Connect this pin with one resistor R IMONFB to CORE VCC_SENSE while IMON pin is connected to ground with another resistor, R IMON. The current monitor output gain can be set by the ratio of these two resistors.

8 DRPEN

Droop Enable Mode Setting of CORE VR. An internal 80 μA current source is connected to the DRPEN pin and flows out of this pin for 10 μs. Connect this pin to VCC to enable droop function. Connect this pin to GND to disable droop function.

9 OFS

Output Voltage No-Load Offset Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage V OFS for offset setting. Connect this pin to GND for no offset setting.

10 OFSA

Output Voltage No-Load Offset Setting of GFX VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage VOFSA for offset setting. Connect this pin to GND for no offset setting. Pin Configurations WQFN-48L 6x6 (TOP VIEW) ISEN1P FB COMP VCC GFXPS2 OFSA OFS DRPEN IMONFB RGND IMON ISEN1N SETINIA SETINI TMPMAX ICCMAX ICCMAXA TSEN VR_READY OCSET TSENA OCSETA IBIAS ISENAP FBA COMPA VRA_READY DRPENA VDIO VCLK IMONFBA RGNDA IMONA ISENAN TONSET BOOT UGATE PHASE LGATE PVCC TONSETA LGATEA PHASEA UGATEA BOOTA EN GND 242322212019181716151413 373839404142434445464748 VRHOT ALERT

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin No. Pin Name Pin Function 11 GFXPS2 Forced DEM Enable Setting of GFX VR. Connect to V CC for forced-DEM setting and connect to GND for following SVID power state command. 12 VCC 5V Power Supply Input of Controller. Bypass this pin to GND with a 1 μF or greater ceramic capacitor.

13 SETINIA

Initial Startup Voltage V INI_GFX Setting of GFX VR. Connect to a resistive voltage divider from V CC to GND to set the pin voltage V SETINIA for GFX VR initial startup voltage VINI_GFX setting. Connect this pin to GND for 0V VINI_GFX setting.

14 SETINI

Initial Startup Voltage V INI_CORE Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage V SETINI for CORE VR initial startup voltage VINI_CORE setting. Connect this pin to GND for 0V VINI_CORE setting. 15 TMPMAX Maximum Temperature Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage VTM PM AX for TMPMAX setting. 16 ICCMAX Maximum Current Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage VICCMAX for ICCMAX setting. 17 ICCMAXA Maximum Current Setting of GFX VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage VICCMAXA for ICCMAXA setting. 18 TSEN Thermal Monitor Sense Pin of CORE VR.

19 OCSET

Over Current Protection Setting of CORE VR. Connect to a resistive voltage divider from VCC to GND to set the pin voltage V OCSET from 0 to 3.3V for CORE VR over current protection threshold. 20 TSENA Thermal Monitor Sense Pin of GFX VR.

21 OCSETA

Over Current Protection Setting of GFX VR. Connect to a resistive voltage divider from VCC to GND to adjust the pin voltage VOCSETA from 0 to 3.3V for GFX VR over current protection threshold. 22 IBIAS Internal bias current setting. Connect a 53.6k Ω resistor from IBIAS pin to GND. 23 VRHOT Thermal Monitor Output (Active Low). Connect a pull high resistor from VRHOT pin to 1.05V. 24 VR_READY Voltage Ready Indicator of CORE VR. Connect a pull high resistor from VR_READY pin to 1.05V. 25 VRA_READY Voltage Ready Indicator GFX VR. Connect a pull high resistor from VRA_READY pin to 1.05V.

26 DRPENA

Droop Enable Mode Setting of GFX VR. An internal 80 μA current source is connected to DRPENA pin and flows out of this pin for 10 μs. Connect this pin to VCC to enable droop function. Connect this pin to GND to disable droop function. 27 ALERT SVID Alert Pin (Active Low). Connect a 75Ω resistor from ALERT pin to 1.05V. 28 VDIO Controller and CPU Data Transmission Interface. Connecting a 64.9 Ω resistor between VDIO pin to 1.05V. 29 VCLK Synchronous Clock from the CPU. Connect a 64.9 Ω resistor from VCLK pin to 1.05V.

30 IMONFBA

This pin is used to externally set the current monitor output gain of GFX VR. Connect this pin with one resistor R IMONFBA to GFX VCC_SENSE while IMON pin is connected to ground with another resistor R IMONA. The current monitor output gain can be set by the ratio of these two resistors.

31 IMONA

Current Monitor Output of GFX VR. The output voltage VIMONA of this pin is proportional to the output current. For digital output current reporting, detailed VIMONA is generated by built-in ADC.

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin No. Pin Name Pin Function 32 RGNDA Return Ground for GFX VR. This pin is the negative input for differential remote voltage sensing. 33 FBA GFX VR Feedback. This is the negative input node of the error amplifier. 34 COMPA GFX VR Compensation. This pin is the output node of the error amplifier. 35 ISENAN Negative Current Sense Input of GFX VR. 36 ISENAP Positive Current Sense Input of GFX VR. 37 TONSETA On-Time Setting of GFX VR. Connect this pin to VIN with one resistor. 38 EN Chip Enable (Active High).

39 BOOTA

Bootstrap Flying Capacitor Connection for GFX VR. This pin powers the high side MOSFET drivers. Connect this pin to PHASEA with an external ceramic capacitor. 40 UGATEA High Side MOSFET Floating Gate Driver Output for GFX VR. Connect this pin to the gate of high side MOSFET.

41 PHASEA

Switching Node Connection for GFX VR. PHASEA is also the zero cross detect input for GFX VR. Connect this pin to the high side MOSFET sources together with the low side MOSFET drains and the inductor. 42 LGATEA Synchronous-Rectifier Gate Driver Output of GFX VR. Connect this pin to the gate of low side MOSFET. 43 PVCC 5V Power Supply of Driver. Bypass this pin to GND with a 1 μF or greater ceramic capacitor. 44 LGATE Synchronous-Rectifier Gate Driver Output of CORE VR. Connect this pin to the gate of low side MOSFET.

45 PHASE

Switching Node Connection for CORE VR. PHASE is the internal lower supply rail for the UGATE. PHASE is also the zero cross detect input for CORE VR. Connect this pin to the high side MOSFET sources together with the low side MOSFET drains and the inductor. 46 UGATE High Side MOSFET Floating Gate Driver Output for CORE VR. Connect this pin to the gate of high side MOSFET.

47 BOOT

Bootstrap Flying Capacitor Connection for CORE VR. This pin powers the high side MOSFET drivers. Connect this pin to PHASE with an external ceramic capacitor. 48 TONSET On-Time Setting of CORE VR. Connect this pin to VIN with one resistor. 49 (Exposed pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 1. Dual Output Application Circuit

38 ENEN

11 GFXPS2

16 ICCMAX

26 DRPENA8 DRPEN

29 VCLK28 VDIO27

25 VRA_READY24 VR_READY

©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 2. Single Output Application Circuit

29 VCLKVCLK 28 VDIOVDIO 27ALERT

24 VR_READYVR_READY

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Function Block Diagram ICCMAXA FB COMP RGND TSEN ISEN1N ISEN1P OCSET FBA COMPA ERROR AMP GFX VR OCP GFX VR Protection Signal ISENAN ICCMAX TMPMAX Control & Protection Logic MUX ADC SVID XCVR VDIO VCLK TONSETA EN ISENAP OCSETA VR_READY VRA_READY RGNDA PWM CMP GFX VR VID/OFS control Slew Rate Control VREFA VREF VCC VREF IMONFB UVLO GFX VR OV/UV/NV IBIAS TONSET GFX VR Current Monitor VREFA IMONFBA IMONA BOOT UGATE PHASE LGATE PVCC GFX VR CCRCOT PWM Generator BOOTA UGATEA PHASEA LGATEA OFS SETINIA SETINI TSENA DRPENA DRPEN IMON OFSA Droop EnablerGFX 0LL EN GFX 0LL EN CORE 0LL EN CORE VR Current Monitor GND CORE VR CCRCOT PWM Generator Droop EnablerCORE 0LL EN PVDD Driver logic control DAC OFS Control Offset Cancellation GFX VR Slew Rate control ERROR AMP CORE VR VID/OFS Control Slew Rate Control DAC OFS Control Offset Cancellation CORE VR Slew Rate control Driver logic control GFX VR Slew Rate control CORE VR Slew Rate control GFX VR VID/OFS Control CORE VR VID/OFS Control GFX 0LL EN CORE 0LL VCS GFX 0LL VCS CORE 0LL VCS CORE 0LL EN GFX 0LL VCS CORE VR Protection Signal GFX VR Protection Signal CORE VR OCP CORE VR Protection Signal CORE VR OV/UV/NV 2.14V PWM CMP VREFA VREF GM Current Sense AMP Current Sense AMP GM GFX VR Operation Mode CORE VR Operation Mode GFX VR Operation Mode CORE VR Operation Mode GFXPS2 VRHOT ALERT 10+ X4.8 X4.8

©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 1. IMVP7/VR12 Compliant VID Table

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 0 1 0 0 0 1 1 2 3 0.420 0 0 1 0 0 1 0 0 2 4 0.425 0 0 1 0 0 1 0 1 2 5 0.430 0 0 1 0 0 1 1 0 2 6 0.435 0 0 1 0 0 1 1 1 2 7 0.440 0 0 1 0 1 0 0 0 2 8 0.445 0 0 1 0 1 0 0 1 2 9 0.450 0 0 1 0 1 0 1 0 2 A 0.455 0 0 1 0 1 0 1 1 2 B 0.460 0 0 1 0 1 1 0 0 2 C 0.465 0 0 1 0 1 1 0 1 2 D 0.470 0 0 1 0 1 1 1 0 2 E 0.475 0 0 1 0 1 1 1 1 2 F 0.480 0 0 1 1 0 0 0 0 3 0 0.485 0 0 1 1 0 0 0 1 3 1 0.490 0 0 1 1 0 0 1 0 3 2 0.495 0 0 1 1 0 0 1 1 3 3 0.500 0 0 1 1 0 1 0 0 3 4 0.505 0 0 1 1 0 1 0 1 3 5 0.510 0 0 1 1 0 1 1 0 3 6 0.515 0 0 1 1 0 1 1 1 3 7 0.520 0 0 1 1 1 0 0 0 3 8 0.525 0 0 1 1 1 0 0 1 3 9 0.530 0 0 1 1 1 0 1 0 3 A 0.535 0 0 1 1 1 0 1 1 3 B 0.540 0 0 1 1 1 1 0 0 3 C 0.545 0 0 1 1 1 1 0 1 3 D 0.550 0 0 1 1 1 1 1 0 3 E 0.555 0 0 1 1 1 1 1 1 3 F 0.560 0 1 0 0 0 0 0 0 4 0 0.565 0 1 0 0 0 0 0 1 4 1 0.570 0 1 0 0 0 0 1 0 4 2 0.575 0 1 0 0 0 0 1 1 4 3 0.580 0 1 0 0 0 1 0 0 4 4 0.585 0 1 0 0 0 1 0 1 4 5 0.590

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 1 0 0 0 1 1 0 4 6 0.595 0 1 0 0 0 1 1 1 4 7 0.600 0 1 0 0 1 0 0 0 4 8 0.605 0 1 0 0 1 0 0 1 4 9 0.610 0 1 0 0 1 0 1 0 4 A 0.615 0 1 0 0 1 0 1 1 4 B 0.620 0 1 0 0 1 1 0 0 4 C 0.625 0 1 0 0 1 1 0 1 4 D 0.630 0 1 0 0 1 1 1 0 4 E 0.635 0 1 0 0 1 1 1 1 4 F 0.640 0 1 0 1 0 0 0 0 5 0 0.645 0 1 0 1 0 0 0 1 5 1 0.650 0 1 0 1 0 0 1 0 5 2 0.655 0 1 0 1 0 0 1 1 5 3 0.660 0 1 0 1 0 1 0 0 5 4 0.665 0 1 0 1 0 1 0 1 5 5 0.670 0 1 0 1 0 1 1 0 5 6 0.675 0 1 0 1 0 1 1 1 5 7 0.680 0 1 0 1 1 0 0 0 5 8 0.685 0 1 0 1 1 0 0 1 5 9 0.690 0 1 0 1 1 0 1 0 5 A 0.695 0 1 0 1 1 0 1 1 5 B 0.700 0 1 0 1 1 1 0 0 5 C 0.705 0 1 0 1 1 1 0 1 5 D 0.710 0 1 0 1 1 1 1 0 5 E 0.715 0 1 0 1 1 1 1 1 5 F 0.720 0 1 1 0 0 0 0 0 6 0 0.725 0 1 1 0 0 0 0 1 6 1 0.730 0 1 1 0 0 0 1 0 6 2 0.735 0 1 1 0 0 0 1 1 6 3 0.740 0 1 1 0 0 1 0 0 6 4 0.745 0 1 1 0 0 1 0 1 6 5 0.750 0 1 1 0 0 1 1 0 6 6 0.755 0 1 1 0 0 1 1 1 6 7 0.760 0 1 1 0 1 0 0 0 6 8 0.765 0 1 1 0 1 0 0 1 6 9 0.770

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 0 1 1 0 1 0 1 0 6 A 0.775 0 1 1 0 1 0 1 1 6 B 0.780 0 1 1 0 1 1 0 0 6 C 0.785 0 1 1 0 1 1 0 1 6 D 0.790 0 1 1 0 1 1 1 0 6 E 0.795 0 1 1 0 1 1 1 1 6 F 0.800 0 1 1 1 0 0 0 0 7 0 0.805 0 1 1 1 0 0 0 1 7 1 0.810 0 1 1 1 0 0 1 0 7 2 0.815 0 1 1 1 0 0 1 1 7 3 0.820 0 1 1 1 0 1 0 0 7 4 0.825 0 1 1 1 0 1 0 1 7 5 0.830 0 1 1 1 0 1 1 0 7 6 0.835 0 1 1 1 0 1 1 1 7 7 0.840 0 1 1 1 1 0 0 0 7 8 0.845 0 1 1 1 1 0 0 1 7 9 0.850 0 1 1 1 1 0 1 0 7 A 0.855 0 1 1 1 1 0 1 1 7 B 0.860 0 1 1 1 1 1 0 0 7 C 0.865 0 1 1 1 1 1 0 1 7 D 0.870 0 1 1 1 1 1 1 0 7 E 0.875 0 1 1 1 1 1 1 1 7 F 0.880 1 0 0 0 0 0 0 0 8 0 0.885 1 0 0 0 0 0 0 1 8 1 0.890 1 0 0 0 0 0 1 0 8 2 0.895 1 0 0 0 0 0 1 1 8 3 0.900 1 0 0 0 0 1 0 0 8 4 0.905 1 0 0 0 0 1 0 1 8 5 0.910 1 0 0 0 0 1 1 0 8 6 0.915 1 0 0 0 0 1 1 1 8 7 0.920 1 0 0 0 1 0 0 0 8 8 0.925 1 0 0 0 1 0 0 1 8 9 0.930 1 0 0 0 1 0 1 0 8 A 0.935 1 0 0 0 1 0 1 1 8 B 0.940 1 0 0 0 1 1 0 0 8 C 0.945 1 0 0 0 1 1 0 1 8 D 0.950

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC V oltage 1 0 0 0 1 1 1 0 8 E 0.955 1 0 0 0 1 1 1 1 8 F 0.960 1 0 0 1 0 0 0 0 9 0 0.965 1 0 0 1 0 0 0 1 9 1 0.970 1 0 0 1 0 0 1 0 9 2 0.975 1 0 0 1 0 0 1 1 9 3 0.980 1 0 0 1 0 1 0 0 9 4 0.985 1 0 0 1 0 1 0 1 9 5 0.990 1 0 0 1 0 1 1 0 9 6 0.995 1 0 0 1 0 1 1 1 9 7 1.000 1 0 0 1 1 0 0 0 9 8 1.005 1 0 0 1 1 0 0 1 9 9 1.010 1 0 0 1 1 0 1 0 9 A 1.015 1 0 0 1 1 0 1 1 9 B 1.020 1 0 0 1 1 1 0 0 9 C 1.025 1 0 0 1 1 1 0 1 9 D 1.030 1 0 0 1 1 1 1 0 9 E 1.035 1 0 0 1 1 1 1 1 9 F 1.040 1 0 1 0 0 0 0 0 A 0 1.045 1 0 1 0 0 0 0 1 A 1 1.050 1 0 1 0 0 0 1 0 A 2 1.055 1 0 1 0 0 0 1 1 A 3 1.060 1 0 1 0 0 1 0 0 A 4 1.065 1 0 1 0 0 1 0 1 A 5 1.070 1 0 1 0 0 1 1 0 A 6 1.075 1 0 1 0 0 1 1 1 A 7 1.080 1 0 1 0 1 0 0 0 A 8 1.085 1 0 1 0 1 0 0 1 A 9 1.090 1 0 1 0 1 0 1 0 A A 1.095 1 0 1 0 1 0 1 1 A B 1.100 1 0 1 0 1 1 0 0 A C 1.105 1 0 1 0 1 1 0 1 A D 1.110 1 0 1 0 1 1 1 0 A E 1.115 1 0 1 0 1 1 1 1 A F 1.120 1 0 1 1 0 0 0 0 B 0 1.125 1 0 1 1 0 0 0 1 B 1 1.130

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 0 1 1 0 0 1 0 B 2 1.135 1 0 1 1 0 0 1 1 B 3 1.140 1 0 1 1 0 1 0 0 B 4 1.145 1 0 1 1 0 1 0 1 B 5 1.150 1 0 1 1 0 1 1 0 B 6 1.155 1 0 1 1 0 1 1 1 B 7 1.160 1 0 1 1 1 0 0 0 B 8 1.165 1 0 1 1 1 0 0 1 B 9 1.170 1 0 1 1 1 0 1 0 B A 1.175 1 0 1 1 1 0 1 1 B B 1.180 1 0 1 1 1 1 0 0 B C 1.185 1 0 1 1 1 1 0 1 B D 1.190 1 0 1 1 1 1 1 0 B E 1.195 1 0 1 1 1 1 1 1 B F 1.200 1 1 0 0 0 0 0 0 C 0 1.205 1 1 0 0 0 0 0 1 C 1 1.210 1 1 0 0 0 0 1 0 C 2 1.215 1 1 0 0 0 0 1 1 C 3 1.220 1 1 0 0 0 1 0 0 C 4 1.225 1 1 0 0 0 1 0 1 C 5 1.230 1 1 0 0 0 1 1 0 C 6 1.235 1 1 0 0 0 1 1 1 C 7 1.240 1 1 0 0 1 0 0 0 C 8 1.245 1 1 0 0 1 0 0 1 C 9 1.250 1 1 0 0 1 0 1 0 C A 1.255 1 1 0 0 1 0 1 1 C B 1.260 1 1 0 0 1 1 0 0 C C 1.265 1 1 0 0 1 1 0 1 C D 1.270 1 1 0 0 1 1 1 0 C E 1.275 1 1 0 0 1 1 1 1 C F 1.280 1 1 0 1 0 0 0 0 D 0 1.285 1 1 0 1 0 0 0 1 D 1 1.290 1 1 0 1 0 0 1 0 D 2 1.295 1 1 0 1 0 0 1 1 D 3 1.300 1 1 0 1 0 1 0 0 D 4 1.305 1 1 0 1 0 1 0 1 D 5 1.310

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 1 0 1 0 1 1 0 D 6 1.315 1 1 0 1 0 1 1 1 D 7 1.320 1 1 0 1 1 0 0 0 D 8 1.325 1 1 0 1 1 0 0 1 D 9 1.330 1 1 0 1 1 0 1 0 D A 1.335 1 1 0 1 1 0 1 1 D B 1.340 1 1 0 1 1 1 0 0 D C 1.345 1 1 0 1 1 1 0 1 D D 1.350 1 1 0 1 1 1 1 0 D E 1.355 1 1 0 1 1 1 1 1 D F 1.360 1 1 1 0 0 0 0 0 E 0 1.365 1 1 1 0 0 0 0 1 E 1 1.370 1 1 1 0 0 0 1 0 E 2 1.375 1 1 1 0 0 0 1 1 E 3 1.380 1 1 1 0 0 1 0 0 E 4 1.385 1 1 1 0 0 1 0 1 E 5 1.390 1 1 1 0 0 1 1 0 E 6 1.395 1 1 1 0 0 1 1 1 E 7 1.400 1 1 1 0 1 0 0 0 E 8 1.405 1 1 1 0 1 0 0 1 E 9 1.410 1 1 1 0 1 0 1 0 E A 1.415 1 1 1 0 1 0 1 1 E B 1.420 1 1 1 0 1 1 0 0 E C 1.425 1 1 1 0 1 1 0 1 E D 1.430 1 1 1 0 1 1 1 0 E E 1.435 1 1 1 0 1 1 1 1 E F 1.440 1 1 1 1 0 0 0 0 F 0 1.445 1 1 1 1 0 0 0 1 F 1 1.450 1 1 1 1 0 0 1 0 F 2 1.455 1 1 1 1 0 0 1 1 F 3 1.460 1 1 1 1 0 1 0 0 F 4 1.465 1 1 1 1 0 1 0 1 F 5 1.470 1 1 1 1 0 1 1 0 F 6 1.475 1 1 1 1 0 1 1 1 F 7 1.480 1 1 1 1 1 0 0 0 F 8 1.485

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage 1 1 1 1 1 0 0 1 F 9 1.490 1 1 1 1 1 0 1 0 F A 1.495 1 1 1 1 1 0 1 1 F B 1.500 1 1 1 1 1 1 0 0 F C 1.505 1 1 1 1 1 1 0 1 F D 1.510 1 1 1 1 1 1 1 0 F E 1.515 1 1 1 1 1 1 1 1 F F 1.520

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1) z PHASEx to GND z UGATEx to PHASEx z LGATEx to GND z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3)

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit Supply Input VCC/VPVCC V EN = 1.05V, Not Switching 4.5 5 5.5 V Input Voltage Range VIN Battery Input Voltage 5 -- 25 V Supply Current (VCC + PVCC) IVCC + IPVCC V EN = 1.05V, Not Switching -- 12 20 mA Supply Current (TONSETx) ITONSETx V FB =1V, VIN = 12V, RTON = 100kΩ -- 1 10 -- μA (VCC = 5V, TA = 25 °C, unless otherwise specified)

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Current (PVCC + VCC) IVCC_SHDN + IPVCC_SHDN VEN = 0V -- -- 5 μA Shutdown Current (TONSETx) ITONSETx_SHDN V EN = 0V -- -- 5 μA TON Setting TONSETx Voltage V TONSETx I RTON = 80μA, VFBx = 1V 0.95 1.075 1.2 0V On-Time t ON I RTON = 80μA, VFBx = 1V 315 350 385 ns TONSETx Input Current Range IRTON V FBx = 1.1V 25 -- 280 μA Minimum Off-Time T OFF_MIN -- 350 -- ns Droop Enable / Disable DRPENx Internal Current Source IDRPENx EN goes high within 10 μs -- 80 -- μA Droop Enable Threshold V DRPENx Detect VDRPENx, EN goes high within 10μs 4.5 -- -- Droop Disable Threshold VDRPENx Detect VDRPENx, EN goes high within 10μs -- -- 2 V GFX VR Forced DEM GFXPS2x Enable Threshold VGFXPS 4.3 -- -- V GFXPS2x Disable Threshold VGFXPS -- -- 0.7 V References and System Output Voltage VIDSVID Setting = 1.000V~1.520V OFSSVID Setting = 0V −0.5 0 0.5 %VID VIDSVID Setting = 0.800V~1.000V OFSSVID Setting = 0V −5 0 5 VIDSVID Setting = 0.500V~0.800V OFSSVID Setting = 0V −8 0 8 VIDSVID Setting = 0.250V~0.500V OFSSVID Setting = 0V −8 0 8 DAC Accuracy (PS0/PS1) VFBx VIDSVID Setting = 1.100V OFSSVID Setting = −0.640V~0.635V −10 0 10 mV VINI_CORE = 0V , VINI_GFX = 0V 0 0.3125 0.5125 VINI_CORE = 1V , VINI_GFX = 1V 1.3625 1.5625 1.7625 SETINIx Voltage V SETINIx VINI_CORE = 1.1V, VINI_GFX = 1.1V 2.6125 -- 5 V Offset = 100mV 68 72 -- Offset = 50mV 52 56 60 Offset = −50mV 36 40 44 Offset = −100mV 20 24 28 External OFSx Voltage V OFSx No Offset Voltage 0 8 12 %VCC Impedance of OFSx Pin R OFSx 1 -- -- M Ω

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit IBIAS Pin Voltage V IBIAS R IBIAS = 53.6kΩ 2.09 2.14 2.19 V SetVID Slow 2.5 3.125 3.75 Dynamic VID Slew Rate SR DVID SetVID Fast 10 12.5 15 mV/μs Error Amplifier DC Gain A DC R L = 47kΩ (Note5) 70 80 -- dB Gain-Bandwidth Product GBW C LOAD = 5pF (Note5) -- 10 -- MHz Slew Rate SR COMP CLOAD = 10pF (Gain = −4, RLOAD_COMP = 47kΩ, VCOMPx = 0.5V to 3V) -- 5 -- V/ μs Output Voltage Range V COMP R L = 47kΩ 0.5 -- 3.6 V MAX Source/Sink Current ICOMP V COMP = 2V -- 250 -- μA Impedance of FBx R FBx 1 -- -- M Ω Current Sense Amplifier Input Offset Voltage V OFS_CSA −1 -- 1 mV Impedance of Neg. Input R ISENxN 1 -- -- M Ω Impedance of Pos. Input R ISENxP 1 -- -- M Ω Current Sense Differential Input Range VCSDIx VFBx = 1.1V, VCSDIx = VISENxP − VISENxN −50 -- 100 mV Current Sense DC Gain (Loop) AI V FBx = 1.1V, −30mV < VCSDIx < 50mV -- 10 -- V/V VISEN Linearity V ISEN_ACC V DAC = 1.1V −30mV < VISEN_IN < 50mV −1 -- 1 % Digital Current Monitor Current Monitor Output Voltage (Droop Enabled) VIMONx_ENLL VFBx = 1V , VISENxN = 0.9V, VRIMONFBx = 10k, RIMONx = 160k -- 1.6 -- V Current Monitor Output Voltage (Droop Disabled) VIMONx_DISLL VCSDIx = VISENxP − VISENxN = 100mV VFBx = 1V , VRIMONFBx = 10k, RIMONx = 80k -- 1.6 -- V IMON Voltage Range V IMON 0 -- 3.3 V Digital IMON LSB 3.3V / 255 = 12.94mV -- 12.94 -- mV VIMONx = 388.3mV, DIOUT [7 : 0] = 30 27 30 33 Decimal VIMONx = 776.5mV, DIOUT [7 : 0] = 60 57 60 63 Decimal Digital Code of IMON C DIMON VIMONx = 1164.7mV, DIOUT [7 : 0] = 90 87 90 93 Decimal Update Period of Digital Current Monitor tIMON -- 1600 -- μs Gate Driver Upper Driver Source R UGATEx_sr VBOOTx − VPHASEx = 5V VBOOTx − VUGATEx = 0.1V -- 1 -- Ω Upper Driver Sink R UGATEx_sk V UGATEx = 0.1V -- 1 -- Ω Lower Driver Source R LGATEx_sr PVCC = 5V, PVCC − VLGATEx = 0.1V -- 1 -- Ω Lower Driver Sink R LGATEx_sk V LGATEx = 0.1V -- 0.5 -- Ω Internal Boot Charging Switch On-Resistance RBOOTx PVCC to BOOTx -- 30 -- Ω

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Zero Current Detection Threshold VZCD_TH V ZCD_TH = GND − VPHASEx -- 10 -- mV Protection Under Voltage Lock-out Threshold VUVLO VCC Falling edge 4.04 4.24 -- V Under Voltage Lock-out Hysteresis ΔVUVLO -- 100 -- mV Over Voltage Protection Threshold VOVP Respect to VOUT_MAX SVID, with 1μs filter time 100 150 200 mV Under Voltage Protection Threshold VUVP VUVP = V ISENxN − V REFx, 0.8V < VREFx <1.52V, with 3μs filter time −350 −300 −250 mV Negative V oltage Protection Threshold VNVP V NVP = VISENxN − GND −100 −50 -- mV Current Sense Gain for Over Current Protection AOC VOCSET = 2.4V VISENxP − VISENxN = 50mV -- 48 -- V/V Logic Inputs Logic-High V IH With respect to 1V, 70% 0.7 -- -- V EN Input Threshold Voltage Logic-Low V IL With respect to 1V, 30% -- -- 0.3 V Leakage Current of EN −1 -- 1 μA VIH With respect to Intel Spec. 0.65 -- -- V VCLK,VDIO Input Threshold Voltage VIL With respect to Intel Spec. -- -- 0.45 V Leakage Current of VCLK, VDIO ILEAK_IN −1 -- 1 μA ALERT ALERT Low Voltage VALERT IALER T_ SINK = 4mA -- -- 0.4 V VR Ready VRx_READY Low Voltage V VRx_READY I VRx_READY_ SINK = 4mA -- -- 0.4 V VRx_READY Delay t VRx_READY V ISENxN = VBOOT to VVRx_READY high 70 100 160 μs Thermal Throttling VRHOT Output Voltage VVRHOT IVRHOT_SINK = 40mA -- 0.4 -- V High Impedance Output ALERT, VRx_READY, VRHOT ILEAK_OUT −1 -- 1 μA Temperature Zone TSEN Threshold for Tmp_Zone [7] transition 100°C -- 1.8725 -- V TSEN Threshold for Tmp_Zone [6] transition 97°C -- 1.8175 -- V TSEN Threshold for Tmp_Zone [5] transition 94°C -- 1.7625 -- V TSEN Threshold for Tmp_Zone [4] transition 91°C -- 1.7075 -- V TSEN Threshold for Tmp_Zone [3] transition VTSENx

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 °C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Parameter Symbol Test Conditions Min Typ Max Unit TSEN Threshold for Tmp_Zone [2] transition 85°C -- 1.5975 -- V TSEN Threshold for Tmp_Zone [1] transition 82°C -- 1.5425 -- V TSEN Threshold for Tmp_Zone [0] transition VTSENx Update Period t TSEN -- 1600 -- μs ADC Latency t LA T -- -- 400 μs CICCMAX1 V ICCMAX = 0.637V 29 32 35 decimal CICCMAX2 V ICCMAX = 1.2642V 61 64 67 decimal Digital Code of ICCMAX CICCMAX3 V ICCMAX = 2.5186V 125 128 131 decimal CICCMAXA1 V ICCMAXA = 0.1666V 5 8 11 decimal CICCMAXA2 V ICCMAXA = 0.3234V 13 16 19 decimal Digital Code of ICCMAXA CICCMAXA3 V ICCMAXA = 0.637V 29 32 35 decimal CTMPMAX1 V TMPMAX = 1.6758V 82 85 88 decimal CTMPMAX2 V TMPMAX = 1.9698V 97 100 103 decimal Digital Code of TMPMAX CTMPMAX3 V TMPMAX = 2.4598V 122 125 128 decimal

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Boot VID = 1V Time (100 μs/Div) CORE VR Power On from EN EN (2V/Div) VCORE (500mV/Div) VR_READY (2V/Div) UGATE (20V/Div) Time (100 μs/Div) CORE VR Power Off from EN Boot VID = 1V EN (2V/Div) VCORE (500mV/Div) VR_READY (2V/Div) UGATE (20V/Div) VID = 1.1V Time (100 μs/Div) CORE VR OCP ILOAD (10A/Div) VCORE (1V/Div) VR_READY (1V/Div) UGATE (20V/Div) Time (40 μs/Div) CORE VR OVP and NVP VID = 1.1V LGATE (10V/Div) VCORE (1V/Div) VR_READY (1V/Div) UGATE (20V/Div) 0.7V to 1.2V, Slew Rate = Slow, ILOAD = 4A Time (40 μs/Div) CORE VR Dynamic VID Up VDIO (2V/Div) VCLK (2V/Div) VCORE (500mV/Div) ALERT (2V/Div) Time (40 μs/Div) CORE VR Dynamic VID Down 1.2V to 0.7V, Slew Rate = Slow, ILOAD = 4A ALERT (2V/Div) VCORE (500mV/Div) VDIO (2V/Div) VCLK (2V/Div)

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (10 μs/Div) CORE VR Dynamic VID Up 0.7V to 1.2V, Slew Rate = Fast, ILOAD = 4A VDIO (2V/Div) VCLK (2V/Div) VCORE (500mV/Div) ALERT (2V/Div) Time (10 μs/Div) CORE VR Dynamic VID Down 1.2V to 0.7V, Slew Rate = Fast, ILOAD = 4A VCORE (500mV/Div) ALERT (2V/Div) VDIO (2V/Div) VCLK (2V/Div) VID = 1.1V, ILOAD = 1A to 8A, Slew Time = 150ns Time (100 μs/Div) CORE VR Load Transient VCORE (20mV/Div) ILOAD (A/Div) Time (100 μs/Div) CORE VR Load Transient VID = 1.1V, ILOAD = 8A to 1A, Slew Time = 150ns VCORE (20mV/Div) ILOAD (A/Div) VID = 1.1V, PS0 to PS2, ILOAD = 0.2A Time (100 μs/Div) CORE VR Mode Transition UGATE (20V/Div) VCLK (1V/Div) LGATE (10V/Div) VCORE (20mV/Div) Time (100 μs/Div) CORE VR Mode Transition VID = 1.1V, PS2 to PS0, ILOAD = 0.2A UGATE (20V/Div) VCORE (20mV/Div) VCLK (1V/Div) LGATE (10V/Div)

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (100 μs/Div) GFX VR OCP ILOAD (5A/Div) VGFX (1V/Div) VRA_READY (1V/Div) UGATEA (20V/Div) Time (40 μs/Div) GFX VR OVP and NVP VID = 1.1V LGATEA (10V/Div) VGFX (1V/Div) VRA_READY (1V/Div) UGATEA (20V/Div) Time (100 μs/Div) GFX VR Power On from EN Boot VID = 1V EN (2V/Div) VGFX (500mV/Div) VRA_READY (2V/Div) UGATEA (20V/Div) Time (100 μs/Div) GFX VR Power Off from EN Boot VID = 1V UGATEA (20V/Div) EN (2V/Div) VGFX (500mV/Div) VRA_READY (2V/Div) TSEN Sweep from 1.7V to 1.9V Time (10ms/Div) CORE VR Thermal Monitoring VRHOT (500mV/Div) TSEN (V/Div) 1.9 1.7 CORE VR VREF vs. Temperature 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 -50 -25 0 25 50 75 100 125 Temperature (°C) VREF (V)

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (40 μs/Div) GFX VR Dynamic VID 0.7V to 1.2V, Slew Rate = Slow, I LOAD = 1.25A VDIO (2V/Div) VCLK (2V/Div) VGFX (500mV/Div) ALERT (2V/Div) Time (40 μs/Div) GFX VR Dynamic VID ALERT (2V/Div) VGFX (500mV/Div) 1.2V to 0.7V, Slew Rate = Slow, I LOAD = 1.25A VDIO (2V/Div) VCLK (2V/Div) Time (10 μs/Div) GFX VR Dynamic VID 0.7V to 1.2V, Slew Rate = Fast, ILOAD = 1.25A VDIO (2V/Div) VCLK (2V/Div) VGFX (500mV/Div) ALERT (2V/Div) Time (10 μs/Div) GFX VR Dynamic VID ALERT (2V/Div) 1.2V to 0.7V, Slew Rate = Fast, ILOAD = 1.25A VDIO (2V/Div) VCLK (2V/Div) VGFX (500mV/Div) Time (100 μs/Div) GFX VR Load Transient VID = 1.1V, ILOAD = 1A to 4A, Slew Time = 150ns VGFX (20mV/Div) ILOAD (A/Div) Time (100 μs/Div) GFX VR Load Transient VID = 1.1V, ILOAD = 4A to 1A, Slew Time = 150ns VGFX (20mV/Div) ILOAD (A/Div)

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (100 μs/Div) GFX VR Mode Transition VID = 1.1V, PS2 to PS0, ILOAD = 0.1A UGATEA (20V/Div) VGFX (20mV/Div) VCLK (1V/Div) LGATEA (10V/Div) Time (100 μs/Div) GFX VR Mode Transition VID = 1.1V, PS0 to PS2, ILOAD = 0.1A UGATEA (20V/Div) VCLK (1V/Div) LGATEA (10V/Div) VGFX (20mV/Div) Time (10ms/Div) GFX VR Thermal Monitoring TSENA Sweep from 1.7V to 1.9V 1.9 1.7 TSENA (V/Div) VRHOT (500mV/Div) GFX VR VREF vs. Temperature 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 - 5 0 - 2 50 2 55 07 5 1 0 0 1 2 5 Temperature (°C) VREF (V)

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. management states and VID on-the-fly function. The power management states include DEM in PS2/PS3 and Forced- CCM in PS1/PS0. The VID on-the-fly function has three different slew rates : Fast, Slow and Decay. The RT8167A integrates a high accuracy ADC for platform setting functions, such as no-load offset and over current level. The controller supports both DCR and sense-resistor current sensing. The RT8167A provides VR ready output signals of both CORE VR and GFX VR. It also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and under voltage lockout. The RT8167A is available in a WQFN- 48L 6x6 small foot print package. Design Tool To help users reduce efforts and errors caused by manual calculations, a user-friendly design tool is now available on request. This design tool calculates all necessary design parameters by entering user's requirements. Please contact Richtek's representatives for details. Serial VID (SVID) Interface SVID is a three-wire serial synchronous interface defined by Intel. The three wire bus includes VDIO, VCLK and ALERT signals. The master (Intel's VR12/IMVP7 CPU) initiates and terminates SVID transactions and drives the VDIO, VCLK, and ALERT during a transaction. The slave (RT8167A) receives the SVID transactions and acts accordingly.

Application Information

The RT8167A is a VR12/IMVP7 compliant, dual single- phase synchronous Buck PWM controller for the CPU CORE VR and GFX VR. The gate drivers are embedded to facilitate PCB design and reduce the total BOM cost. A serial VID (SVID) interface is built-in in the RT8167A to communicate with Intel VR12/IMVP7 compliant CPU. The RT8167A adopts G-NAVP TM (Green Native AVP), which is Richtek's proprietary topology derived from finite DC gain compensator, making it an easy setting PWM controller to meet AVP requirements. The load line can be easily programmed by setting the DC gain of the error amplifier. The RT8167A has fast transient response due to the G-NAVP TM commanding variable switching frequency. G-NAVPTM topology also represents a high efficiency system with green power concept. With G-NAVP TM topology, the RT8167A becomes a green power controller with high efficiency under heavy load, light load, and very light load conditions. The RT8167A supports mode transition function between CCM and DEM. These different operating states allow the overall power system to have low power loss. By utilizing the G-NAVP TM topology, the operating frequency of RT8167A varies with output voltage, load and VIN to further enhance the efficiency even in CCM. The built-in high accuracy DAC converts the SVID code ranging from 0.25V to 1.52V with 5mV per step. The differential remote output voltage sense and high accuracy DAC allow the system to have high output voltage accuracy. The RT8167A supports VR12/IMVP7 compatible power

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Standard Serial VID Command Code Commands Master Payload

Contents

00h not supported N/A N/A N/A 01h SetVID_Fast VID code N/A Set new target VID code, VR jumps to new VID target with controlled default “fast” slew rate 12.5mV/μs. 02h SetVID_Slow VID code N/A Set new target VID code, VR jumps to new VID target with controlled default “slow” slew rate 3.125mV/μs. 03h SetVID_Decay VID code N/A Set new target VID code, VR jumps to new VID target, but does not control the slew rate. The output voltage decays at a rate proportional to the load current 04h SetPS Byte indicating power states N/A Set power state 05h SetRegADR Pointer of registers in data table N/A Set the pointer of the data register 06h SetReg DAT New data register content N/A Write the contents to the data register 07h GetReg Pointer of registers in data table Specified Register Slave returns the contents of the specified register as the payload 08h 1Fh not supported N/A N/A N/A

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Data and Configuration Register Index Register Name Description Access Default 00h Vendor ID Vendor ID, default 1Eh. RO, Vendor 1Eh 01h Product ID Product ID. RO, Vendor 65h 02h Product Revision Product Revision. RO, Vendor 01h 05h Protocol ID SVID Protocol ID. RO, Vendor 01h 06h VR_Capability Bit mapped register, identifies the SVID VR capabilities and which of the optional telemetry register are supported. RO, Vendor 81h 10h Status_1 Data register containing the status of VR. R-M, W-PWM 00h 11h Status-2 Data register containing the status of transmission. R-M, W-PWM 00h 12h Temperature Zone Data register showing temperature zone that have been entered. R-M, W-PWM 00h 15h Output_Current Data register showing direct ADC conversion of averaged output current. R-M, W-PWM 00h 1Ch Status_2_lastread The register contains a copy of the status_2. R-M, W-PWM 00h 21h ICC_Max Data register containing the maximum ICC of platform supports. Binary format in Amp, IE 64h = 100A. RO, Platform -- 22h Temp_Max Data register containing the temperature max the platform supports. Binary format in °C, IE 64h = 100°C Only for CORE VR RO, Platform -- 24h SR-Fast Data register containing the capability of fast slew rate the platform can sustains. Binary format in mV/μs, IE 0Ah = 10mV/μs. RO 0Ah 25h SR-Slow Data register containing the capability of slow slew rate. Binary format in mV/μs IE 02h = 2.5mV/μs. RO 02h 30h VOUT_Max The register is programmed by the master and sets the maximum VID. RW, Master BFh 31h VID Setting Data register containing currently programmed VID. RW, Master 00h 32h Power State Register containing the current programmed power state. RW, Master 00h 33h Offset Set offset in VID steps. RW, Master 00h 34h Multi VR Config Bit mapped data register which configures multiple VRs behavior on the same bus. RW, Master 00h 35h Pointer Scratch pad register for temporary storage of the SetRegADR pointer register. RW, Master 30h Notes : RO = Read Only RW = Read/Write R-M = Read by Master W-PWM = Write by PWM only Vendor = hard coded by VR vendor Platform = programmed by platform Master = programmed by the master PWM = programmed by the VR control IC

©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. switching frequency to filter the switching-related noise. affects the output accuracy in high temperature conditions. thermistor placed in the feedback path. Figure 10. Loop Setting with Temperature Compensation selected to linearize the NTC's temperature characteristic. where 0.00393 is the temperature coefficient of copper.

©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. to be tuned on board by examining the transient voltage. and the recovery will be too fast, causing a ring-back. can have better accuracy, but the efficiency is a trade-off. inductor DCR sensing method. four-level offsets of output voltage for the CORE/GFX VR. the OFSx pin voltage setting is shown in Figure 13. are also shown in Figure 13.

0.16 VCC

0.32 VCC

0.48 VCC

0.64 VCC

Figure 13. OFS and OFSA Pins Voltage Setting operation mode is PS2 (DEM operation). Figure 14. Thermal Monitoring Circuit variation of VR from 75% to 100% VR max temperature. versus temperature variation is shown in Table 2. the VR operates as a DEM controller. VR be forced into PS2 operation state again.

©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 2. Temperature Zone Register sensed from IMONFBx pin and mirrored to IMONx pin. of VR temperature), the VRHOT signal will be set to low. Temperature_Zone register content of the GFX VR. Figure 15. Current Monitor Setting Principle RIMONFB are the current monitor current setting resistors. meet the maximum voltage of IMON at full load.

DS8167A-00 January 2012www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Solving (26) and (27) yields ROC1b and ROC2 (28) OC2 EQU, HOT EQU, COLD EQU, 25 CC OCSET, 25 R RR ( 1 ) R V (1 )V α× − + −α × ×− α (29) OC1 b EQU, HOT EQU, COLD R (1 ) R 2 R R (1 ) α− × +α× − where SENSE, HOT 25 HOT SENSE, COLD 25 COLD R DCR [1 0.00393 (T 25)] R DCR [1 0.00393 (T 25)] (30) REQU, T = ROC1a // RNTC, T (31) Over Voltage Protection (OVP) The over voltage protection circuit of CORE/GFX VR monitors the output voltage via the ISENxN pin. The supported maximum operating VID of VR (V (MAX)) is stored in the VOUT(MAX) register. Once VISENxN exceeds “V(MAX) + 200mV”, OVP is triggered and latched. VR will try to turn on low side MOSFETs and turn off high side MOSFETs to protect CPU. When OVP is triggered by the one of the VRs, the other VR will enter soft shutdown sequence. A 10μs delay is used in OVP detection circuit to prevent false trigger. Negative Voltage Protection (NVP) During OVP latch state, both CORE/GFX VRs also monitor ISENxN pin for negative voltage protection. Since the OVP latch will continuously turn on low side MOSFET of VR, VR may suffer negative output voltage. Therefore, when the voltage of ISENxN drops below −0.05V after triggering OVP, VR will turn off low side MOSFETs while high side MOSFETs remain off. The NVP function will be active only after OVP is triggered. Under Voltage Protection (UVP) Both CORE/GFX VR implement Under Voltage Protection (UVP). If ISENxN is less than V REFx by 300mV + VOFFSET, VR will trigger UVP latch. The UVP latch will turn off both high side and low side MOSFETs. When UVP is triggered by one of the VRs, the other VR will enter into soft shutdown sequence. The UVP mechanism is masked when VRx_READY = low. (32) IN OUTMIN ON Ripple(MAX) VVLt I −=× where tON is the UGATE turn on period. Higher inductance induces less ripple current and hence higher efficiency. However, the tradeoff is a slower transient response of the power stage to load transients. This might increase the need for more output capacitors, thus driving up the cost. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must be large enough not to be saturated at the peak inductor current. Output Capacitor Selection Output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output capacitors can be found, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. Latter ones are for mid-frequency decoupling with very small ESR and ESL values while the bulk capacitors have to provide enough stored energy to overcome the low-frequency bandwidth gap between the regulator and the CPU. Layout Considerations Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flushed against one another. Follow these guidelines for optimum PC board layout : Under Voltage Lock Out (UVLO) During normal operation, if the voltage at the VCC pin drops below UVLO falling edge threshold, both VR will trigger UVLO. The UVLO protection forces all high side MOSFETs and low side MOSFETs off to turn off. Inductor Selection The switching frequency and ripple current determine the inductor value as follows :

DS8167A-00 January 2012 www.richtek.com ©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. \ Keep the high current paths short, especially at the ground terminals. \ Keep the power traces and load connections short. This is essential for high efficiency. \ When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharging path. \ Place the current sense component close to the controller. ISENxP and ISENxN connections for current limit and voltage positioning must be made using Kelvin sense connections to guarantee the current sense accuracy. The PCB trace from the sense nodes should be parallel to the controller. \ Route high-speed switching nodes away from sensitive analog areas (COMPx, FBx, ISENxP, ISENxN, etc...) \ Special attention should be paid in placing the DCR current sensing components. The DCR current sensing capacitor and resistors must be placed close to the controller. \ The capacitor connected to the ISEN1N/ISENAN for noise decoupling is optional and it should also be placed close to the ISEN1N/ISENAN pin. \ The NTC thermistor should be placed physically close to the inductor for better DCR thermal compensation.

DS8167A-00 January 2012www.richtek.com Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 5.950 6.050 0.234 0.238 D2 4.250 4.350 0.167 0.171 E 5.950 6.050 0.234 0.238 E2 4.250 4.350 0.167 0.171 e 0.400 0.016 L 0.350 0.450 0.014 0.018 W-Type 48L QFN 6x6 Package 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options