RT8152C

RT8152C RICHTEK | Alldatasheet

Document overview

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Technical content

Features

zzzzz Single Phase PWM Controller with Integrated MOSFET Driver. zzzzz Low-Gain Compensator with CCRCOT Topology (Constant Current Ripple Constant On Time) zzzzz 7-bit DAC zzzzz 0.8% DAC Accuracy zzzzz 1.5% or 11.5mV System Accuracy zzzzz Fixed VBOOT (For CPU Core Only) zzzzz Differential Remote Voltage Sensing zzzzz G-NAVP Topology (Green-Native AVP) zzzzz Programmable Output Transition Slew Rate Control zzzzz System Thermal Compensated AVP zzzzz Ringing Free Mode at Light Load Condition zzzzz Fast Transient Response zzzzz IMVP6.5 Compatible Power Management States zzzzz Power Good zzzzz Clock Enable Output (For CPU Core Only) zzzzz Thermal Throttling zzzzz Current Monitor Output zzzzz Switching Frequency Up to 1MHz zzzzz OVP, UVP, OCP, OTP, UVLO, NVP zzzzz 32-Lead WQFN Package zzzzz RoHS Compliant and Halogen Free

Applications

z IMVP6.5 CPU / Render Core Voltage Regulator z AVP Step-Down Converter z Notebook / Desktop Computer / Servers Note : Richtek products are : \ RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. \ Suitable for use in SnPb or Pb-free soldering processes.

Ordering Information

QW : WQFN-32L 5x5 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) RT8152 VRON Power C : 1.05V D : 3.3V

Figure 1. CPU Core Voltage Regulator

26 VID5

1 NTC

from VCC using NTC on the top to set the thermal management threshold level.

2 OCSET

3 DPRSLPVR Deeper Sleep Mode Signal. 4 VRON Voltage Regulator Enabler. 5 PGOOD Power Good Indicator.

6 CLKEN

open-drain pin is an output indicating the start of the PLL locking of the clock chip. Connect to GND for Render application.

8 SOFT

capacitance of the slew rate control capacitor is restricted to be larger than 10nF. Figure 2. Render Core Voltage Regulator

DS8152C/D-04 April 2011www.richtek.com Pin No. Pin Name Pin Function 10 CM Current Monitor Output. This pin outputs a voltage proportional to the output current.

11 C MS ET

Current Monitor Output Gain Externally Setting. Connect this pin with one resistor to VSEN while CM pin is connected to ground with one another resistor. In such way, current monitor output gain can be set by the ratio of these two resistors. 12 VSEN Positive Voltage Sensing Pin. This pin is the positive node of the differential voltage sensing. 13 FB Feedback. This is the negative input node of the error amplifier. 14 COMP Compensation. This pin is the output node of the error amplifier. 15 ISEN_N Negative input of the current sense. 16 ISEN Positive input of the current sense. 17 TON Connect this pin to VIN with one resistor. 18, 33 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 19 PVDD Driver Power. 20 LGATE Lower Gate Drive. This pin drives the gate of the low side MOSFETs. 21 PGND Driver Ground.

22 PHASE

This pin is return node of the high side MOSFET driver. Connect this pin to the high side MOSFET sources together with the low side MOSFET drains and the inductor. 23 UGATE Upper Gate Drive. This pin drives the gate of the high side MOSFETs. 24 BOOT Bootstrap Power Input. This pin powers the high side MOSFET drivers. Connect this pin to bootstrap capacitor. 25 to 31 VID6 to VID0 Voltage ID. DAC voltage identification inputs for IMVP6.5. The logic threshold is 30% of the VCCP as the maximum value for low state and 70% of the VCCP as the minimum value for the high state.

32 VRTT

Voltage Regulator Thermal Throttling. This open-drain output pin will be pulled low when the preset temperature level is exceeded.

Table 1. IMVP6.5 VID Code Table

DS8152C/D-04 April 2011www.richtek.com VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output 1 0 0 0 0 1 0 0.6750V 1 0 0 0 0 1 1 0.6625V 1 0 0 0 1 0 0 0.6500V 1 0 0 0 1 0 1 0.6375V 1 0 0 0 1 1 0 0.6250V 1 0 0 0 1 1 1 0.6125V 1 0 0 1 0 0 0 0.6000V 1 0 0 1 0 0 1 0.5875V 1 0 0 1 0 1 0 0.5750V 1 0 0 1 0 1 1 0.5625V 1 0 0 1 1 0 0 0.5500V 1 0 0 1 1 0 1 0.5375V 1 0 0 1 1 1 0 0.5250V 1 0 0 1 1 1 1 0.5125V 1 0 1 0 0 0 0 0.5000V 1 0 1 0 0 0 1 0.4875V 1 0 1 0 0 1 0 0.4750V 1 0 1 0 0 1 1 0.4625V 1 0 1 0 1 0 0 0.4500V 1 0 1 0 1 0 1 0.4375V 1 0 1 0 1 1 0 0.4250V 1 0 1 0 1 1 1 0.4125V 1 0 1 1 0 0 0 0.4000V 1 0 1 1 0 0 1 0.3875V 1 0 1 1 0 1 0 0.3750V 1 0 1 1 0 1 1 0.3625V 1 0 1 1 1 0 0 0.3500V 1 0 1 1 1 0 1 0.3375V 1 0 1 1 1 1 0 0.3250V 1 0 1 1 1 1 1 0.3125V 1 1 0 0 0 0 0 0.3000V VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output 1 1 0 0 0 0 1 0.2875V 1 1 0 0 0 1 0 0.2750V 1 1 0 0 0 1 1 0.2625V 1 1 0 0 1 0 0 0.2500V 1 1 0 0 1 0 1 0.2375V 1 1 0 0 1 1 0 0.2250V 1 1 0 0 1 1 1 0.2125V 1 1 0 1 0 0 0 0.2000V 1 1 0 1 0 0 1 0.1875V 1 1 0 1 0 1 0 0.1750V 1 1 0 1 0 1 1 0.1625V 1 1 0 1 1 0 0 0.1500V 1 1 0 1 1 0 1 0.1375V 1 1 0 1 1 1 0 0.1250V 1 1 0 1 1 1 1 0.1125V 1 1 1 0 0 0 0 0.1000V 1 1 1 0 0 0 1 0.0875V 1 1 1 0 0 1 0 0.0750V 1 1 1 0 0 1 1 0.0625V 1 1 1 0 1 0 0 0.0500V 1 1 1 0 1 0 1 0.0375V 1 1 1 0 1 1 0 0.0250V 1 1 1 0 1 1 1 0.0125V 1 1 1 1 0 0 0 0.0000V 1 1 1 1 0 0 1 0.0000V 1 1 1 1 0 1 0 0.0000V 1 1 1 1 0 1 1 0.0000V 1 1 1 1 1 0 0 0.0000V 1 1 1 1 1 0 1 0.0000V 1 1 1 1 1 1 0 0.0000V 1 1 1 1 1 1 1 0.0000V

DS8152C/D-04 April 2011 www.richtek.com Function Block Diagram COMP RGND SOFT OVP Trip PointVID1 VID3 VID4 VID5 VID0 VID2 FB PGOOD VCC GND ERROR AMP OCP Setting Soft Start NVP Trip Point Power On Reset Central Logic VSEN VRON OCSETNTC VID6 Mode Selection DPRSLPVR VBOOT UVP Trip Point OTP VCC MUX DAC ISEN_N PWMCP Driver Logic Control PGND LGATE PVDD PHASE UGATE BOOT ISEN CM CLKEN VRTT CM CMSET CCRCOT On-Time Generator TON FB Mode Selection VDAC Offset Cancellation

DS8152C/D-04 April 2011www.richtek.com Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1) z LGATE to PGND z PHASE to PGND z UGATE to PHASE z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3)

DS8152C/D-04 April 2011 www.richtek.com To be continued Parameter Symbol Test Conditions Min Typ Max Unit Supply Input Supply Current I VCC + IPVDD RTON = 130k, VRON = 3.3V, No Loading Current -- -- 10 mA Shutdown Current I VCC + IPVDD V RON = 0V -- -- 5 μA Soft-Start/Slew Rate Control (based on 10nF CSS) Soft-Start / Soft-Shutdown I SS1 SOFT = 1.5V -- 20 -- μA Normal VID Change Slew Current ISS2 SOFT = 1.5V 40 50 60 μA Deeper Sleep Exit/VID Change Slew Current ISS3 For Render Mode Only, SOFT = 1.5V 80 100 120 μA Reference and DAC VDAC = 0.7500 − 1.5000 (No Load, Active Mode ) −0.8 0 0.8 %VID DC Accuracy V FB VDAC = 0.5000 − 0.7500 −7.5 0 7.5 mV RT8152C 1.089 1.1 1.111 Boot Voltage V BOOT RT8152D 1.188 1.2 1.212 V Error Amplifier DC Gain R L = 47kΩ (Note 5) 70 80 -- dB Gain-Bandwidth Product GBW C LOAD = 5pF (Note 5) -- 10 -- MHz Slew Rate SR COMP CLOAD = 10pF (Gain = −4, Rf = 47kΩ, VOUT = 0.5V − 3V) -- 5 -- V/ μs Output Voltage Range V COMP R L = 47kΩ 0.5 -- 3.6 V Maximum Source Current V COMP = 2V 200 250 -- μA Maximum Sink Current IOUTEA_COMP VCOMP = 2V -- 20 -- mA Current Sense Amplifier Input Offset Voltage V OSCS I SEN = ISEN_N = 1.5V −1 -- 1 mV Impedance at Neg. Input R ISEN_N I SEN_N = 1.5V 1 -- -- M Ω Impedance at Pos. Input R ISEN I SEN = 1.5V 1 -- -- M Ω DC Gain -- 10 -- V/V Input Range V ISEN_IN V DAC = 1.1V, VISEN_IN = ISEN − ISEN_N −50 -- 80 mV TON Setting TON Pin Output Voltage V TON R TON = 80kΩ, VTON = VDAC = VBOOT −5 0 5 % ON-Time Setting T ON I RTON = 80μA, VTON = VDAC = VBOOT -- 350 -- ns RTON Current Range I RTON V TON = VDAC = VBOOT 25 -- 280 μA Minimum Off Time T Off I RTON = 80μA, VDAC = VBOOT 250 -- 500 ns Protection Under Voltage Lock-out Threshold VUVLO Falling edge, 80mV Hysteresis 3.9 4.1 4.3 V

Electrical Characteristics

(VCC = 5V, T A = 25°C, unless otherwise specified)

DS8152C/D-04 April 2011www.richtek.com To be continued Parameter Symbol Test Conditions Min Typ Max Unit Protection Absolute Over Voltage Protection Threshold VOVABS (Respect to 1.5V, ±50mV) 1.45 1.5 1.55 V Relative Over Voltage Protection Threshold VOV (Respect to V DAC, ±50mV) 250 300 350 mV Under Voltage Protection Threshold VUV Measured at VSEN respect to unloaded output voltage (UOV) (for 0.8 < UOV < 1.5) −450 −400 −350 mV Negative Voltage Protection Threshold VNV Measured at VSEN respect to GND −100 -- -- mV Current Limit Threshold Voltage VILIM VISEN − VISEN_N = VILIM, VOC SET = 2V, 40 x VILIM = VOCSET 46.5 50 53.5 mV Thermal Shutdown Threshold T SD Typical hysteresis is 10°C -- 160 -- °C Logic Inputs RT8152E Respect to 1.05V, 70% 0.735 -- -- VIH RT8152F Respect to 3.3V, 70% 2.31 -- -- RT8152E Respect to 1.05V, 30% -- -- 0.315 VRON Threshold VIL RT8152F Respect to 3.3V, 30% -- -- 0.99 V Leakage Current of VRON −1 -- 1 μA VIH Respect to 1.05V, 70% 0.77 -- -- V DAC (VID0 − VID6) and DPRSLPVR VIL Respect to 1.05V, 30% -- -- 0.33 V Leakage Current of DAC (VID0 − VID6) and DPRSLPVR −1 -- 1 μA Power Good CPU Core : VSEN − VBOOT -- −100 -- PGOOD Threshold V TH_PGOOD Render : VSEN − VDAC -- −100 -- mV PGOOD Low Voltage V PGOOD I PGOOD = 4mA -- -- 0.4 V CPU Core, CLKEN Low to PGOOD High 3 -- 20 ms PGOOD Delay T PGOOD Render Mode VRON High to PGOOD High 3 -- 20 ms Clock Enable CLKEN Low Voltage V CLKEN For CPU Core Only, I CLKEN = 4mA -- -- 0.4 V Thermal Throttling Thermal Throttling Threshold V OT Measure at NTC respect to V CC -- 80 -- %VDD Thermal Throttling Threshold Hysteresis VOT_HY At V CC = 5V -- 230 -- mV VRTT Output Voltage V VRTT I VRTT = 40mA -- -- 0.4 V Current Monitor Current Monitor Output Voltage in Operating Range VDAC = 0.9V, VRCMSET = 0.82V, RCM = 7.5kΩ, RCMSET = 1.5kΩ 770 800 830 mV Current Monitor Maximum Output Voltage -- -- 1.15 V

DS8152C/D-04 April 2011 www.richtek.com Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θ JA is measured in the natural convection at T A = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Parameter Symbol Test Conditions Min T yp Max Unit Gate Driver Upper Driver Source R UGATEsr VBOOT − VPHASE = 5V VBOOT − VUGATE = 1V -- 0.7 -- Ω Upper Driver Sink R UGATEsk V UGATE = 1V -- 0.6 -- Ω Lower Driver Source R LGATEsr V PVDD = 5V, VPVDD − VLGATE = 1V -- 0.75 -- Ω Lower Driver Sink R LGATEsk V LGATE = 1V -- 0.5 -- Ω Upper Driver Source/Sink Current IUGATE VBOOT −VPHASE = 5V VUGATE = 2.5V -- 3 -- A Lower Driver Source Current ILGATEsr V LGATE = 2.5V -- 3 -- A Lower Driver Sink Current I LGATEsk V LGATE = 2.5V -- 5 -- A Internal Boot Charging Switch On-Resistance RBOOT PVDD to BOOT -- 30 -- Ω

DS8152C/D-04 April 2011www.richtek.com Typical Operating Characteristics VIN = 12.6V, RTON = 150ΩΩΩΩΩ, L = 0.36μμμμμH, COUT = 330μμμμμF, No Load, TA = 25°°°°°C, unless otherwise specified. CCM Efficiency vs. Load Current 100 0 3 6 9 12 15 18 21 24 27 30 Load Current (A) Efficiency (%) VID = 1.15V, DPRSLPVR = Low VIN = 8V VIN = 12V VIN = 19V CCM VCC_SENSE vs. Load Current 1.04 1.06 1.08 1.10 1.12 1.14 1.16 0 3 6 9 12 15 18 21 24 27 30 Load Current (A) VCC_SENSE (V) VID = 1.15V, DPRSLPVR = Low VIN = 8V VIN = 12V VIN = 19V VCM vs. Load Current 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 5 10 15 20 25 30 Load Current (A) VCM (V) VID = 0.9375V, DPRSLPVR = Low VIN = 8V VIN = 12V VIN = 19V RFM Efficiency vs. Load Current 100 Load Current (A) Efficiency (%) VID = 0.85V, DPRSLPVR = High VIN = 8V VIN = 12V VIN = 19V CCM VCC_SENSE vs. Load Current 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 0 3 6 9 12 15 18 21 24 27 30 Load Current (A) VCC_SENSE (V) VID = 0.9375V, DPRSLPVR = Low VIN = 8V VIN = 12V VIN = 19V CCM Efficiency vs. Load Current 100 0 3 6 9 12 15 18 21 24 27 30 Load Current (A) Efficiency (%) VID = 0.9375V, DPRSLPVR = Low VIN = 8V VIN = 12V VIN = 19V

DS8152C/D-04 April 2011 www.richtek.com CPU Mode Power On VCC_SENSE (1V/Div) Time (1ms/Div) PGOOD (5V/Div) VRON (5V/Div) VID = 0.9375V, CLKEN Pull High to 3.3V CLKEN (5V/Div) Render Mode Power On VCC_SENSE (1V/Div) Time (1ms/Div) PGOOD (5V/Div) VRON (5V/Div) CLKEN (5V/Div) VID = 0.9375V, CLKEN Pull low to GND CPU Mode Power Down VCC_SENSE (1V/Div) Time (100 μs/Div) PGOOD (5V/Div) VRON (5V/Div) VID = 0.9375V, CLKEN Pull High to 3.3V CLKEN (5V/Div) CCM VID Change Down VCC_SENSE (100mV/Div) Time (20 μs/Div) UGATE (20V/Div) LGATE (5V/Div) VID change from 0.9375V to 0.85V VID0 (5V/Div) CLKEN Pull High to 3.3V CCM VID Change Up VCC_SENSE (100mV/Div) Time (20 μs/Div) UGATE (20V/Div) LGATE (5V/Div) VID change from 0.85V to 0.9375V VID0 (5V/Div) CLKEN Pull High to 3.3V CPU-RFM VID Change Down VCC_SENSE (100mV/Div) Time (20 μs/Div) UGATE (20V/Div) LGATE (5V/Div) VID change from 0.9375V to 0.85V CLKEN Pull High to 3.3V VID0 (5V/Div)

DS8152C/D-04 April 2011www.richtek.com CCM Load Transient Response VCC_SENSE (50mV/Div) Time (10 μs/Div) UGATE (20V/Div) LGATE (5V/Div) VID = 0.9375V, ILOAD = 28A to 5A CLKEN Pull High to 3.3V (CPU) DPSLPVR = High CCM Load Transient Response VCC_SENSE (50mV/Div) Time (10 μs/Div) UGATE (20V/Div) LGATE (5V/Div) VID = 0.9375V, ILOAD = 5A to 28A CLKEN Pull High to 3.3V (CPU) DPSLPVR = Low C4 ENTRY / EXIT with VID Change VCC_SENSE (100mV/Div) Time (40 μs/Div) VID0 (5V/Div) DPRSLPVR (5V/Div) DPSLPVR = High ILOAD-DPRSLPVR = 1A, I LOAD-CCM = 21A VID = 0.9375V and 0.85V, CLKEN Pull High to 3.3V ILOAD (40A/Div) Over Current Protection VCC_SENSE (1V/Div) Time (10 μs/Div) PHASE (10V/Div) PWRGD (2V/Div) ILOAD (20A/Div) CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low Over Voltage Protection VCC_SENSE (1V/Div) Time (10 μs/Div) LGATE (10V/Div) PWRGD (2V/Div) CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low UGATE (20V/Div) Under Voltage Protection VCC_SENSE (1V/Div) Time (10 μs/Div) LGATE (10V/Div) PWRGD (2V/Div) CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low UGATE (20V/Div)

DS8152C/D-04 April 2011 www.richtek.com

Application Information

The RT8152C/D is a single-phase PWM controller with embedded gate driver. It is compliant with Intel IMVP6.5 Voltage Regulator Specification to fulfill its mobile CPU and Render voltage regulator power supply requirement. Inductor current are continuously sensed for loop control, droop tuning, and over current protection. The 7-bit VID DAC and a low offset differential amplifier allow the controller to maintain high regulating accuracy to meet Intel’s IMVP6.5 specification. Design Tool To help users to reduce the efforts and errors caused by manual calculations using the design concept below, a user friendly design tool is now available on request. This design tool calculates all necessary design parameters by entering user's requirements. Please contact Richtek's representatives for details. Operation Modes Table 2 shows the RT8152C/D operation modes. When VRON is enable (=1), and within 10μs the RT8152C/D will detect the CLKEN to determine which operation mode is applied. If the CLKEN is low, the RT8152C/D will operate in Render core voltage regulator mode. If the CLKEN is high, the IC will operate in CPU core voltage regulator mode. DPRSLPVR determines the operation mode of the controller operation in CCM or RFM. The controller enters RFM (Ring Free Mode) when DPRSLPVR = 1 and enters CCM when DPRSLPVR = 0. Table 2. Control signal truth table for operation

0 Render CCM 0

0 CPU CCM 1

RGND for accurate remote sensing. Figure 3. Lossless Inductor Current Sensing

it affects the output accuracy at hot conditions. thermistor placed in the feedback path. Figure 6. Loop Setting with Temperature Compensation over the widest possible frequency range. switching frequency to filter the switching related noise.

of converter, VDAC is DAC voltage. On-time translate only roughly to switching frequencies. are influenced by switching delays in external HS-FET. on-time by a period equal to the HS-FET rising dead time. Figure 7. On-Time setting with RC Filter and is, therefore, the commanded system voltage. SOFT during soft-start, and soft-shutdown. Render mode power-up sequence. CLKEN goes low, VSEN starts ramping to first VDAC value.

Figure 12. Thermal Throttling Setting Principle \` Condition 1 : When VVSEN exceeds 1.52V. the processor to prevent catastrophic thermal damage.

gap between the regulator and the CPU. and temperature difference between junction to ambient. the junction to ambient thermal resistance. RT8152C/D, The maximum junction temperature is 125°C. with their ground terminals flush against one another. is essential for high efficiency. longer than the discharging path. connections to guarantee the current sense accuracy. Figure 15. Derating Curve for RT8152C/D Package

DS8152C/D-04 April 2011www.richtek.com Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property inf ringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications i s assumed by Richtek. Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com Outline Dimension E D L be A SEE DETAIL A Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2 Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 4.950 5.050 0.195 0.199 D2 3.400 3.750 0.134 0.148 E 4.950 5.050 0.195 0.199 E2 3.400 3.750 0.134 0.148 e 0.500 0.020 L 0.350 0.450 0.014 0.018 W-Type 32L QFN 5x5 Package